Interleaved modulation type bidirectional blocking device and manufacturing method thereof

Abstract

The present invention discloses an interleaved modulation bidirectional blocking device, which primarily addresses the problems of existing devices that only block in one direction and have a high turn-on voltage. From bottom to top, the device comprises: a substrate, a transition layer, a barrier layer, and a passivation layer. A source is provided on the left side of the passivation layer; a recessed anode is provided on the right side of the barrier layer and the passivation layer; an interconnect metal is provided on the upper surface of the passivation layer and the recessed anode; N left array blocks and M right array blocks are provided below the interconnect metal, the lower portions of these array blocks all being located within the transition layer; a window is provided within the passivation layer between the source and the left array block, within which a P-type block, an i-GaN block, and a gate are sequentially provided. The gate, source, array block, and recessed anode form a HEMT structure, which is combined with a diode composed of the array block, recessed anode, and the semiconductor material in contact therewith to form a bidirectional blocking device. The present invention can reduce the turn-on voltage, achieve bidirectional blocking, and increase the threshold voltage, and can be used in power electronics systems.

Description

Technical Field

[0001] The invention belongs to the field of microelectronic technology, and in particular relates to a bidirectional blocking device which can be used in power electronic systems. Technical Background

[0002] In applications such as wireless charging, aerospace, radio frequency, and medical equipment, devices are often required to have bidirectional voltage resistance to maintain high power conversion efficiency and improve device reliability. Thanks to the superior material properties of GaN, such as high breakdown field strength, good thermal properties, and high electron mobility, GaN-based enhancement-mode high electron mobility transistors have attracted great attention from researchers in high-power and high-frequency applications. However, traditional GaN-based enhancement-mode high electron mobility transistors can often only achieve unidirectional blocking, that is, the drain voltage can only be higher than the source voltage, and forward blocking is achieved by turning off the gate, which severely limits the application of such devices.

[0003] The traditional enhancement mode high electron mobility transistor includes from bottom to top: substrate 1, transition layer 2, barrier layer 3, source 6 and drain 5 on the left and right sides of the upper part of the barrier layer 3 respectively, a P-type block 4 is provided on the upper part of the barrier layer 3 close to the source 6, and a gate 7 is provided on the upper part of the P-type block 4. When using the traditional structure to form a bidirectional blocking device, only Schottky diodes can be connected in series externally, which will bring about a large parasitic effect, increase power consumption, and occupy a large area, making it difficult to achieve monolithic integration. In order to improve the problems existing in the above-mentioned traditional structure, the Ferdinand Braun Institute in Germany first proposed a groove SBD drain structure in 2009. The groove SBD drain structure is embedded in the traditional enhancement mode high electron mobility transistor to form Figure 1 The conventional enhancement-mode high electron mobility transistor shown in the figure consists of a substrate, a transition layer, a barrier layer, a P-type block, and a gate. An ohmic contact is located on the left side of the upper barrier layer, with a source electrode located above it. A Schottky contact is located on the right side of the barrier layer and the transition layer, with a drain electrode located above it. A passivation layer covers the entire upper portion of the device, except for the source, gate, and drain electrodes. The device fabrication process is compatible with conventional GaN-based HEMT devices and can achieve bidirectional withstand voltage. However, this device structure suffers from high forward turn-on voltage and low forward output current, making it difficult to meet practical application requirements. Summary of the Invention

[0004] The purpose of the present invention is to address the deficiencies of the above-mentioned prior art and provide an interleaved modulation bidirectional blocking device and a manufacturing method thereof, so as to achieve bidirectional blocking characteristics, improve the threshold voltage of the device, reduce the gate leakage of the device, lower the forward turn-on voltage, increase the forward output current, and improve the reliability of the device.

[0005] To achieve the above object, the technical solution of the present invention is as follows:

[0006] 1. A staggered modulation bidirectional blocking device, comprising, from bottom to top: a substrate 1, a transition layer 2, a barrier layer 3, and a passivation layer 4, characterized in that:

[0007] A source groove 5 is provided on the left side of the passivation layer 4 on the barrier layer 3, and a source electrode 6 is provided inside the source groove;

[0008] A groove anode 12 is provided on the right side of the barrier layer 3 and the passivation layer 4, and the bottom of the groove anode is located in the transition layer 2;

[0009] The upper surface of the groove anode 12 and the passivation layer 4 is provided with an interconnection metal 13;

[0010] N left array blocks 10 are provided below the left portion of the interconnection metal 13, and M right array blocks 11 are provided below the middle portion of the interconnection metal 13. The lower portions of the left array blocks 10 and the right array blocks 11 are located in the transition layer 2.

[0011] A window 14 is provided inside the passivation layer 4 between the source 6 and the left array block 10, and a P-type block 15, an i-GaN block 16, and a gate 17 are provided inside the passivation layer 4 from bottom to top.

[0012] The source 6, gate 17, array block and recessed anode 12 on the right side form a HEMT structure. A diode structure is formed between the array block and recessed anode 12 and the barrier layer 3 and passivation layer 4 in contact therewith. The HEMT and diode are combined to form a bidirectional blocking device.

[0013] Furthermore, the substrate 1 is made of silicon carbide, silicon or sapphire.

[0014] Furthermore, the thickness a of the barrier layer 3 is 3 nm to 100 nm; the thickness b of the passivation layer 4 is 5 nm to 1000 nm.

[0015] Furthermore, the N left array blocks 10 and the M right array blocks 11 are staggered; the spacing d between the left array block 10 and the right array block 11 is greater than 0, and the spacing e between the right array block 11 and the groove anode 12 is greater than 0.

[0016] Furthermore, the N left array blocks 10 , the M right array blocks 11 and the groove anode 12 have the same height, which is c, where c>a+b.

[0017] Furthermore, the left array block 10 is composed of N equally spaced metal rectangular blocks, and the distance f between two adjacent rectangular blocks is greater than 0, where N≥1; the right array block 11 is composed of M equally spaced metal rectangular blocks, and the distance g between two adjacent rectangular blocks is greater than 0, where M≥2.

[0018] Furthermore, the P-type block 15 is made of P-GaN, CuO or NiO material, with a thickness of 10 nm to 500 nm and a doping concentration of 5×10 15 cm -3 ~1×10 22 cm -3 ; The thickness of the i-GaN block 16 is 10nm to 500nm.

[0019] 2. The method of the present invention for manufacturing an interleaved modulation type bidirectional blocking device comprises the following steps:

[0020] §1. Epitaxially grow GaN semiconductor material on substrate 1 to form transition layer 2;

[0021] §2. Epitaxially grow GaN-based wide bandgap semiconductor material on the transition layer 2 to form a barrier layer 3;

[0022] §3. Depositing an insulating material on the barrier layer 3 to form a passivation layer 4;

[0023] §4. Making Source 6:

[0024] 4.1) A mask is made on the passivation layer 4 for the first time, and the mask is used to etch the left side of the passivation layer 4 until the upper surface of the barrier layer 3 is reached, thereby forming the source trench 5;

[0025] 4.2) Using the mask produced initially, deposit multiple layers of metal inside the source trench 5 and perform rapid thermal annealing to form the source electrode 6;

[0026] §5. A second mask is formed on the passivation layer 4 and source electrode 6. The mask is used to sequentially etch the right-side passivation layer 4, barrier layer 3, and transition layer 2 until the transition layer 2 is etched, forming N left array block grooves 7, M right array block grooves 8, and anode grooves 9.

[0027] §6. A third mask is formed on the passivation layer 4, source electrode 6, left array block groove 7, right array block groove 8, and anode groove 9. Using this mask, metal is deposited inside the left array block groove 7, right array block groove 8, and anode groove 9 to form N left array blocks 10, M right array blocks 11, groove anodes 12, and interconnect metal 13, respectively.

[0028] §7. A fourth mask is formed on the passivation layer 4, source electrode 6, and interconnect metal 13. The mask is used to etch the passivation layer 4 between the source electrode 6 and the left array block 10 until the upper surface of the barrier layer 3 is reached, forming a window 14.

[0029] §8. A fifth mask is made on the passivation layer 4, source electrode 6, interconnect metal 13 and window 14. Using this mask, a layer with a thickness of 10 nm to 500 nm is deposited in the window 14, with a doping concentration of 5×10 15 cm-3 ~1×10 22 cm -3 P-type block 15;

[0030] §9. Using the fifth mask, deposit an i-GaN block 16 with a thickness of 10 nm to 500 nm on top of the P-type block 15;

[0031] §10. A sixth mask is made on the passivation layer 4, source 6, interconnect metal 13, and i-GaN block 16. The mask is used to deposit metal on top of the i-GaN block 16 to form the gate 17, completing the fabrication of the entire device.

[0032] Compared with the existing enhanced high electron mobility transistor, the device of the present invention has the following advantages:

[0033] 1. Reduce the turn-on voltage and increase the output current.

[0034] Since the device of the present invention adopts the left array block 10 and the right array block 11, when a positive voltage is applied to the groove anode 12 of the device, carriers can flow through the edges of the array block and the groove anode 12, which is equivalent to increasing the contact area between the groove anode 12 and the electrons in the channel, improving the efficiency of carrier tunneling through the Schottky barrier, thereby reducing the turn-on voltage and increasing the conduction current; in addition, due to the use of a distributed array structure, the anode end metal blocks are connected in parallel, which reduces the voltage drop at the anode end when conducting, thereby further reducing the turn-on voltage.

[0035] 2. Increase threshold voltage and enhance device reliability.

[0036] Since the present invention adds an i-GaN block 16 to the P-type block 15, the threshold voltage of the device is regulated. The original high threshold voltage no longer requires a higher P-type block 15 concentration and a lower work function contact metal. Since the i-GaN block 16 is added, the gate 17 can directly contact the i-GaN block 16, increasing the contact barrier height and width, thereby increasing the gate voltage shared by the barrier region and reducing the requirements for the gate metal work function. That is, the gate only needs ordinary metal, thereby improving the threshold voltage of the device and enhancing the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 It is a structural diagram of an existing device;

[0038] Figure 2 is a top view of the interleaved modulation type bidirectional blocking device of the present invention;

[0039] Figure 3 It is along Figure 2 AB line cross-sectional view;

[0040] Figure 4 It is along Figure 2 CD line cross-sectional view;

[0041] Figure 5 It is along Figure 2 EF line cross-sectional view;

[0042] Figure 6 This is a schematic diagram of the process for preparing an interleaved modulation type bidirectional blocking device according to the present invention;

[0043] Figure 7 It is a graph of the output characteristic of the device of the present invention. DETAILED DESCRIPTION

[0044] The embodiments and effects of the present invention are further described in detail below with reference to the accompanying drawings.

[0045] Reference Figure 2 、 Figure 3 、 Figure 4 and Figure 5 The staggered modulation bidirectional blocking device provided in this embodiment includes: a substrate 1, a transition layer 2, a barrier layer 3, a passivation layer 4, a source groove 5, a source 6, a left array block groove 7, a right array block groove 8, an anode groove 9, a left array block 10, a right array block 11, a groove anode 12, an interconnect metal 13, a window 14, a P-type block 15, an i-GaN block 16, and a gate 17. Among them:

[0046] The substrate 1 is made of silicon carbide, silicon or sapphire;

[0047] The transition layer 2 is located on the upper part of the substrate 1 and has a thickness of 3 μm to 100 μm and a doping concentration of 1×10 15 ~1×10 18 cm -3 ;

[0048] The barrier layer 3 is located on the upper part of the transition layer 2 and is composed of several layers of the same or different GaN-based wide bandgap semiconductor materials, with a thickness a of 3nm to 100nm;

[0049] The passivation layer 4 is located on the upper portion of the barrier layer 3 and is made of any one of SiO2, Al2O3, HfO2, TiO2 or other insulating dielectric materials, with a thickness b of 5nm to 1000nm;

[0050] The source trench 5 is located on the left side of the passivation layer 4, and its lower surface is in contact with the barrier layer 3;

[0051] The source electrode 6 is located inside the source groove 5, and the source electrode 6 forms a good ohmic contact with the semiconductor below;

[0052] The left array block groove 7, the right array block groove 8, and the anode groove 9 are sequentially distributed on the right side of the passivation layer 4 and the barrier layer 3 from left to right. The lower parts of the left array block groove 7, the right array block groove 8, and the anode groove 9 are located in the transition layer 2. The heights c thereof are the same, and c>a+b;

[0053] The left array block 10 is located inside the left array block groove 7, the right array block 11 is located inside the right array block groove 8, and the groove anode 12 is located inside the anode tank 9. The left array block 10, the right array block 11, the groove anode 12 form Schottky contacts with the surrounding semiconductors. The spacing d between the left array block 10 and the right array block 11 is greater than 0, and the spacing e between the right array block 11 and the groove anode 12 is greater than 0. The left array block 10 is composed of N equally spaced metal rectangular blocks, and the spacing f is greater than 0, N ≥ 1; the right array block 11 is composed of M equally spaced metal rectangular blocks, and the spacing g is greater than 0, M ≥ 2.

[0054] The interconnection metal 13 is located on the upper surfaces of the left array block 10, the right array block 11 and the groove anode 12;

[0055] The window 14 is located inside the passivation layer 4 between the source 6 and the left array block 10, and its lower surface is in contact with the barrier layer 3;

[0056] The P-type block 15 is located inside the window 14, and its thickness is 10nm to 500nm, and its doping concentration is 5×10 15 cm -3 ~1×10 22 cm -3 , choose P-GaN or CuO or NiO materials;

[0057] The i-GaN block 16 is located inside the window 14 and on top of the P-type block 15, and has a thickness of 10 nm to 500 nm;

[0058] The gate 17 is located on the upper portion of the i-GaN block 16 , has a length smaller than that of the i-GaN block 16 , and forms a Schottky contact with the i-GaN block 16 ;

[0059] The source 6, gate 17, array block and recessed anode 12 on the right side form a HEMT structure. A diode structure is formed between the array block and recessed anode 12 and the barrier layer 3 and passivation layer 4 in contact therewith. The HEMT and diode are combined to form a bidirectional blocking device.

[0060] Reference Figure 6 The present invention provides a method for preparing an interleaved modulation type bidirectional blocking device, and provides the following three embodiments.

[0061] Example 1: A barrier layer 3 with a thickness a of 3 nm is fabricated on a silicon carbide substrate. The passivation layer 4 is made of Al2O3 material with a thickness b of 20 nm. The height c of the array block and the groove anode 12 is 30 nm. The P-type block 15 is made of GaN material, and an interleaved modulation bidirectional blocking device with N=3 and M=4 is fabricated.

[0062] Step 1. Make transition layer 2, such as Figure 6 a.

[0063] Using metal organic chemical vapor deposition technology under the process conditions of temperature of 1000°C, pressure of 45 Torr, hydrogen flow rate of 4600 sccm, ammonia flow rate of 4600 sccm, and gallium source flow rate of 120 μmol / min, GaN material with a thickness of 4.9 μm was epitaxially grown on the silicon carbide substrate 1 to complete the production of the transition layer 2.

[0064] Step 2. Epitaxial Al 0.4 Ga 0.6 N, make barrier layer 3, such as Figure 6 b.

[0065] Using molecular beam epitaxy technology, in a vacuum degree of less than or equal to 1.0×10 -11 mbar, RF power 420W, reactants using N2, high-purity Ga source, high-purity Al source process conditions, epitaxial thickness of 3nm Al on the GaN transition layer 2 0.4 Ga 0.6 N material, forming the barrier layer 3.

[0066] Step 3. Deposit Al2O3 material to form a passivation layer 4, such as Figure 6 c.

[0067] Using atomic layer deposition technology, under the process conditions that the reaction sources are trimethylaluminum (TMA) and deionized water, the reaction temperature is 300°C, the reaction chamber pressure is 5 Torr, and a single reaction cycle includes 1.5 seconds of trimethylaluminum gas introduction, 3 seconds of nitrogen purge, 1 second of deionized water vapor introduction, and 3 seconds of nitrogen purge, an Al2O3 material with a thickness of 20 nm is deposited on the barrier layer 3 to form a passivation layer 4.

[0068] Step 4. Make source 6:

[0069] 4.1) A mask is first formed on the upper portion of the passivation layer 4. Using this mask, reactive ion etching is performed on the left side of the passivation layer 4 under the process conditions of a CF4 flow rate of 20 sccm, an O2 flow rate of 2 sccm, a pressure of 20 mT, and a bias voltage of 100 V. Etching is performed until the upper surface of the barrier layer 3 is reached, thereby forming a source trench 5. Figure 6 d;

[0070] 4.2) Using the mask, electron beam evaporation technology was used to obtain a film with a vacuum degree of less than 1.8×10 -3 Pa, the power is 400W, and the evaporation rate is Under the process conditions, a Ti / Al / Ni / Au metal combination is deposited inside the source groove 5 with thicknesses of 0.02 μm, 0.14 μm, 0.055 μm, and 0.045 μm, respectively; then, a rapid thermal annealing is performed under the process conditions of a temperature of 860° C. and a time of 30 s to complete the production of the source 6, as shown in FIG. Figure 6 e.

[0071] Step 5. Make the left array block groove 7, the right array block groove 8 and the anode groove 9, as shown Figure 6 f.

[0072] A second mask is made on the upper part of the passivation layer 4 and the source electrode 6. Using reactive ion etching technology, under the process conditions of a Cl2 flow rate of 15 sccm, a pressure of 10 mTorr, and a power of 130 W, the mask is used to etch the right side of the passivation layer 4 to a depth of 30 nm, etching into the interior of the transition layer 2 to form three left array block grooves 7, four right array block grooves 8, and an anode groove 9.

[0073] Step 6. Make the left array block 10, the right array block 11, the groove anode 12 and the interconnection metal 13, as shown Figure 6 g.

[0074] The third mask is made on the passivation layer 4, source 6, three left array block grooves 7, four right array block grooves 8 and the upper part of the anode groove 9 by electron beam evaporation technology in a vacuum degree of 1.6×10 -3 Pa, the power is 350W, and the evaporation rate is Under the process conditions, on the right side of the upper part of the passivation layer 4, metal W is deposited inside the three left array block grooves 7, the four right array block grooves 8 and the anode groove 9 to make Schottky contacts, forming three left array blocks 10, four right array blocks 11, groove anodes 12 and interconnection metal 13; a diode structure is formed between the array blocks, the groove anodes 12 and the barrier layer 3 and the passivation layer 4 in contact with them.

[0075] Step 7. Etching to form window 14, such as Figure 6 h.

[0076] A fourth mask is formed on the passivation layer 4, source 6, and interconnect metal 13. Using this mask, reactive ion etching technology is used to etch the passivation layer 4 between the source 6 and the left array block 10, under process conditions of a Cl2 flow rate of 18 sccm, a pressure of 14 mTorr, and a power of 120 W, until the etching reaches the upper surface of the barrier layer 3, forming a window 14.

[0077] Step 8. Make P-type block 15, such as Figure 6 i.

[0078] A fifth mask was made on the passivation layer 4, source 6, interconnect metal 13 and window 14. Using this mask, metal organic chemical vapor deposition technology was used. Under the process conditions of temperature of 950°C, pressure of 42 Torr, hydrogen flow rate of 4100 sccm, high purity Mg source as dopant, ammonia flow rate of 4100 sccm, and gallium source flow rate of 100 μmol / min, a 10 nm thick and doping concentration of 1×10 22 cm -3 P-type GaN is formed to form a P-type block 15.

[0079] Step 9. Make i-GaN block 16, such as Figure 6 j.

[0080] The fifth mask was used again, and metal organic chemical vapor deposition technology was used on the upper part of the P-type block 15. Under the process conditions of temperature of 500°C, pressure of 46 Torr, hydrogen flow rate of 4300 sccm, ammonia flow rate of 4300 sccm, and gallium source flow rate of 21 μmol / min, a 10 nm thick undoped GaN material was deposited to form an i-GaN block 16.

[0081] Step 10. Deposit multiple layers of metal to form a gate 17, such as Figure 6 k.

[0082] A sixth mask was fabricated on the passivation layer 4, source 6, interconnect metal 13, and i-GaN block 16. Using this mask, a metal combination of Ta and Au with thicknesses of 0.025 μm and 0.45 μm, respectively, was sputtered onto the i-GaN block 16 under the following process conditions: a sputtering pressure of 0.1 Pa, an Ar flow rate of 8 sccm, a substrate temperature of 200°C, and a target RF power of 150 W. This formed the gate 17. The source 6, gate 17, array block on the right, and recessed anode 12 formed a HEMT structure. The HEMT structure and the diode structure were combined through the connection of the array block to form a bidirectional blocking device, completing the fabrication of the entire device.

[0083] Example 2: A barrier layer 3 with a thickness a of 24 nm is fabricated on a silicon substrate. The passivation layer 4 is made of SiO2 material with a thickness b of 450 nm. The height c of the array block and the groove anode 12 is 520 nm. The P-type block 15 is made of CuO material, and an interleaved modulation bidirectional blocking device with N=4 and M=5 is fabricated.

[0084] Step A. Make transition layer 2, such as Figure 6 a.

[0085] The process conditions are set to 950℃, 40Torr, SiH4 as doping source, 4000sccm hydrogen flow rate, 4000sccm ammonia flow rate, and 100μmol / min gallium source flow rate. On silicon substrate 1, a metal organic chemical vapor deposition technique is used to deposit an epitaxial layer with a thickness of 4μm and a doping concentration of 2×10 19 cm -3 n - Type GaN transition layer 2.

[0086] Step B. Epitaxial Al 0.25 Ga 0.75 N, make barrier layer 3, such as Figure 6 b.

[0087] Set the vacuum degree to be less than or equal to 1.0×10 -10 mbar, RF power of 400W, the reactants used N2, high-purity Ga source, and high-purity Al source process conditions, using molecular beam epitaxy technology, an Al layer with a thickness of 24nm was grown on the GaN transition layer 2. 0.25 Ga 0.75 N material, forming the barrier layer 3.

[0088] Step C. Deposit SiO2 to make a passivation layer 4, such as Figure 6 c.

[0089] The process conditions are set to 250°C, RF power to 25W, pressure to 1100mTorr, N2O flow rate to 850sccm, and SiH4 flow rate to 200sccm. SiO2 is deposited on the barrier layer 3 using plasma enhanced chemical vapor deposition technology to form a passivation layer 4 with a thickness of 450nm.

[0090] Step D. Making source 6:

[0091] D1) Set the process conditions of CF4 flow rate to 20 sccm, O2 flow rate to 2 sccm, pressure to 20 mT, and bias voltage to 100 V, make a mask on the upper part of the passivation layer 4 for the first time, and use the mask to etch the left side of the passivation layer 4 using reactive ion etching technology until the upper surface of the barrier layer 3 is reached, forming the source groove 5. Figure 6 d;

[0092] D2) Set the vacuum degree to less than 1.8×10 -3 Pa, the power is 400W, and the evaporation rate is Under the process conditions of , the mask is used again to deposit Ti / Al / Mo / Au metal combination inside the source groove 5 using electron beam evaporation technology, with thicknesses of 0.320μm, 0.108μm, 0.150μm, and 0.242μm respectively; then, rapid thermal annealing is performed under the process conditions of temperature of 850℃ and time of 35s to complete the production of source 6, as shown in FIG. Figure 6 e.

[0093] Step E. Make the left array block groove 7, the right array block groove 8 and the anode groove 9, as shown in FIG. Figure 6 f.

[0094] The process conditions are set to 28 sccm for CF4 flow, 3 sccm for O2 flow, 25 mT for pressure, and 110 V for bias voltage. A mask is formed a second time on the upper part of the passivation layer 4 and the source electrode 6. The mask is used to use reactive ion etching technology to etch the right side of the passivation layer 4 to a depth of 520 nm until it reaches the inside of the transition layer 2, forming four left array block grooves 7, five right array block grooves 8, and an anode groove 9.

[0095] Step F. Make the left array block groove 7, the right array block groove 8 and the anode groove 9, as shown in FIG. Figure 6 g.

[0096] The vacuum degree was set to 1.6×10 -3 Pa, the power is 350W, and the evaporation rate is Under the process conditions, a mask is formed for the third time on the upper part of the passivation layer 4, the source 6, the four left array block grooves 7, the five right array block grooves 8, and the anode groove 9. Using the mask and electron beam evaporation technology, metal Mo is deposited on the right side of the upper part of the passivation layer 4, inside the four left array block grooves 7, the five right array block grooves 8, and the anode groove 9 to form Schottky contacts, forming four left array blocks 10, five right array blocks 11, groove anodes 12, and interconnection metal 13; a diode structure is formed between the array blocks, the groove anodes 12, and the barrier layer 3 and the passivation layer 4 with which they contact.

[0097] Step G. Etching to form window 14, such as Figure 6 h.

[0098] The process conditions are set to 28 sccm for CF4 flow, 3 sccm for O2 flow, 25 mT for pressure, and 110 V for bias voltage. A mask is formed on the passivation layer 4, the source 6, and the interconnect metal 13 for the fourth time. The passivation layer 4 between the source 6 and the left array block 10 is etched using reactive ion etching technology using the mask until the upper surface of the barrier layer 3 is reached, forming a window 14.

[0099] Step H. Make a P-type block 15, such as Figure 6 i.

[0100] The target material is copper with a purity of 99.999%, the sputtering gas is high-purity argon, and the high-purity oxygen with the same purity is used as the reaction gas. The vacuum degree of the reaction chamber before sputtering is set to 2.0×10 -4 Pa, the argon flow rate is maintained at 20 sccm, the oxygen flow rate is 10 sccm, the pressure of the deposition chamber is 0.5 Pa, the RF power is 35 W, and the substrate temperature is 200 ° C. The fifth mask is made on the passivation layer 4, the source 6, the interconnection metal 13 and the window 14. The mask is used to deposit a 170 nm thick and doping concentration of 3×10 20 cm -3 CuO forms a P-type block 15.

[0101] Step I. Make i-GaN block 16, such as Figure 6 j.

[0102] The process conditions are set to 500°C, 46 Torr, 4300 sccm hydrogen flow rate, 4300 sccm ammonia flow rate, and 21 μmol / min gallium source flow rate. The fifth mask is used again to deposit 230 nm thick undoped GaN material on the top of the P-type block 15 using metal organic chemical vapor deposition technology to form an i-GaN block 16.

[0103] Step J. Deposit multiple layers of metal to form a gate 17, such as Figure 6 k.

[0104] Set the vacuum degree to less than 1.8×10 -3 Pa, power is 500W, evaporation rate is less than Under the process conditions, a mask is formed for the sixth time on the passivation layer 4, source 6, interconnect metal 13 and i-GaN block 16. Using this mask, a metal combination Ni / Au with thicknesses of 0.020μm / 0.32μm respectively is deposited on the i-GaN block 16 using electron beam evaporation technology to form a gate 17. The source 6, gate 17, array block on the right and recessed anode 12 form a HEMT structure. The HEMT structure and the diode structure are combined to form a bidirectional blocking device through the connection of the array block, completing the fabrication of the entire device.

[0105] Example 3: A barrier layer with a thickness a of 100 nm is fabricated on a sapphire substrate, the passivation layer 4 is made of HfO2 material with a thickness b of 1000 nm, the array block and the groove anode 12 have a height c of 1300 nm, the P-type block 15 is made of NiO material, and an interleaved modulation bidirectional blocking device with N=1 and M=2 is fabricated.

[0106] Step 1. Make transition layer 2, such as Figure 6 a.

[0107] Using metal organic chemical vapor deposition technology, an epitaxial layer with a thickness of 5.3 μm and a doping concentration of 1×10 15 cm -3 n - Type GaN transition layer 2.

[0108] The deposition process conditions are: temperature of 950°C, pressure of 40 Torr, SiH4 as the doping source, hydrogen flow rate of 4000 sccm, ammonia flow rate of 4000 sccm, and gallium source flow rate of 100 μmol / min.

[0109] Step 2. Epitaxial Al 0.1 Ga 0.9 N, make barrier layer 3, such as Figure 6 b.

[0110] Using molecular beam epitaxy technology, Al with a thickness of 100 nm is grown on the GaN transition layer 2. 0.1 Ga 0.9 N material, forming a barrier layer 3;

[0111] The process conditions of molecular beam epitaxy technology are: vacuum degree is less than or equal to 1.0×10 -10 mbar, the RF power is 400W, and the reactants are N2, high-purity Ga source, and high-purity Al source.

[0112] Step 3. Deposit HfO2 material to make a passivation layer 4, such as Figure 6 c.

[0113] Using radio frequency magnetron reactive sputtering technology, HfO2 material with a thickness of 1000 nm is deposited on the barrier layer 3 to form a passivation layer 4;

[0114] The process conditions of RF magnetron reactive sputtering technology are: the sputtering gas pressure in the reaction chamber is maintained at about 0.1 Pa, the flow rates of O2 and Ar are 1 sccm and 8 sccm respectively, the substrate temperature is fixed at 200°C, and the Hf target RF power is 150W.

[0115] Step 4. Make source 6:

[0116] 4a) A mask is made on the upper portion of the passivation layer 4 for the first time, and the left side of the passivation layer 4 is etched using the reactive ion etching technique using the mask until the upper surface of the barrier layer 3 is reached, thereby forming a source trench 5. Figure 6 d.

[0117] The process conditions of reactive ion etching technology are: CF4 flow rate of 45sccm, O2 flow rate of 5sccm, pressure of 15mT, and power of 250W;

[0118] 4b) Using the mask again, electron beam evaporation technology is used to deposit Ti / Au / Ni metal combinations with thicknesses of 0.350 μm, 0.44 μm, and 0.27 μm, respectively; then rapid thermal annealing is performed to complete the production of the source electrode 6, as shown in FIG. Figure 6 e;

[0119] The process conditions of electron beam evaporation technology are: vacuum degree less than 1.8×10 -3 Pa, the power is 400W, and the evaporation rate is

[0120] The process conditions of rapid thermal annealing are: temperature of 860°C and time of 35s.

[0121] Step 5. Make the left array block groove 7, the right array block groove 8 and the anode groove 9, as shown in FIG. Figure 6 f.

[0122] A second mask is made on the passivation layer 4 and the source electrode 6. The right side of the passivation layer 4 is etched with the mask to a depth of 1300 nm. After etching, a left array block groove 7, two right array block grooves 8, and an anode groove 9 are formed.

[0123] The etching process conditions are: CF4 flow rate is 48 sccm, O2 flow rate is 6 sccm, pressure is 18 mT, and power is 270 W.

[0124] Step 6. Make a left array block 10, two right array blocks 11, groove anode 12 and interconnect metal 13, as shown in FIG. Figure 6 g.

[0125] A third mask is formed on the upper portion of the passivation layer 4, the source electrode 6, the left array block groove 7, the right array block groove 8, and the anode groove 9. Using this mask, electron beam evaporation is used to deposit Ni metal to a thickness of 1000 nm on the right side of the upper portion of the passivation layer 4, inside the left array block groove 7, the right array block groove 8, and the anode groove 9, forming a left array block 10, two right array blocks 11, a groove anode 12, and interconnecting metal 13. A diode structure is formed between the array blocks, the groove anode 12, and the barrier layer 3 and the passivation layer 4 in contact therewith.

[0126] The process conditions of electron beam evaporation technology are: vacuum degree is less than or equal to 1.6×10 -3 Pa, the power is set to 350W, and the evaporation rate is

[0127] Step 7. Etching to form window 14, as shown Figure 6 h.

[0128] A fourth mask is made on the passivation layer 4, the source electrode 6 and the interconnect metal 13. The passivation layer 4 between the source electrode 6 and the left array block 10 is etched using the mask using reactive ion etching technology until the upper surface of the barrier layer 3 is reached, forming a window 14.

[0129] The etching process conditions are: CF4 flow rate is 48 sccm, O2 flow rate is 6 sccm, pressure is 18 mT, and power is 270 W.

[0130] Step 8. Make P-type block 15, such as Figure 6 i.

[0131] A fifth mask is made on the passivation layer 4, the source 6, the interconnection metal 13 and the window 14. The mask is used to sputter a 500 nm thick and 5×10 15 cm -3 P-type NiO forms a P-type block 15;

[0132] The process conditions of magnetron sputtering technology are: sputtering power of 110W, temperature of 300℃, Ar flow rate of 20sccm, and O2 flow rate of 30sccm.

[0133] Step 9. Make i-GaN block 16, such as Figure 6 j.

[0134] Using the mask made in the fifth step, a 500 nm thick undoped GaN material is deposited on the upper portion of the P-type block 15 using metal organic chemical vapor deposition technology to form an i-GaN block 16.

[0135] The deposition process conditions are: temperature of 500°C, pressure of 46 Torr, hydrogen flow rate of 4300 sccm, ammonia flow rate of 4300 sccm, and gallium source flow rate of 21 μmol / min.

[0136] Step 10. Deposit multiple layers of metal to form a gate 17, such as Figure 6 k.

[0137] A sixth mask was fabricated on the passivation layer 4, source 6, interconnect metal 13, and i-GaN block 16. Process conditions were set: a sputtering pressure of approximately 0.1 Pa, an Ar flow rate of 8 sccm, a substrate temperature fixed at 200°C, and a target RF power of 150 W. Using this mask, a metal combination of Gd and Au with a thickness of 0.035 μm / 0.35 μm, respectively, was sputtered onto the i-GaN block 16 to form a gate 17. The source 6, gate 17, array block on the right, and recessed anode 12 formed a HEMT structure. The HEMT structure and the diode structure were combined through the connection of the array block to form a bidirectional blocking device, completing the fabrication of the entire device.

[0138] The effects of the present invention can be further illustrated by the following simulation.

[0139] Simulation content: The output characteristics of the device of Example 2 of the present invention are simulated, and the results are as follows Figure 7 .

[0140] Depend on Figure 7 It can be seen that the turn-on voltage of the device of the present invention is about 0.36V and the output current is relatively large, indicating that the device of the present invention has good conduction characteristics.

[0141] The above descriptions are only three specific embodiments of the present invention and do not constitute a limitation of the present invention. Obviously, for professionals in this field, after understanding the content and principles of the present invention, they can make various modifications and changes in form and details according to the method of the present invention without departing from the principles and scope of the present invention. For example, the substrate uses other materials such as graphene, and the passivation layer uses SiN and Sc2O3 materials. However, these modifications and changes based on the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. An interleaved modulation bidirectional blocking device, comprising, from bottom to top: A substrate (1), a transition layer (2), a barrier layer (3) and a passivation layer (4), characterized in that: A source groove (5) is provided on the left side of the passivation layer (4) on the upper portion of the barrier layer (3), and a source electrode (6) is provided inside the source groove; A groove anode (12) is provided on the right side of the barrier layer (3) and the passivation layer (4), and the bottom of the groove anode is located in the transition layer (2); Interconnection metal (13) is provided on the upper surfaces of the groove anode (12) and the passivation layer (4); N left array blocks (10) are provided below the left portion of the interconnection metal (13), and M right array blocks (11) are provided below the middle portion of the interconnection metal (13), with the lower portions of the left array blocks (10) and the right array blocks (11) being located in the transition layer (2); A window (14) is provided inside the passivation layer (4) between the source electrode (6) and the left array block (10), and a P-type block (15), an i-GaN block (16), and a gate (17) are provided inside the passivation layer (4) in order from bottom to top; The source (6), gate (17), array block on the right and recessed anode (12) form a HEMT structure; a diode structure is formed between the array block, recessed anode (12) and the barrier layer (3) and passivation layer (4) in contact therewith; the HEMT and diode are combined to form a bidirectional blocking device.

2. The device according to claim 1, characterized in that The substrate (1) is made of silicon carbide, silicon or sapphire.

3. The device according to claim 1, wherein: The thickness a of the barrier layer (3) is 3 nm to 100 nm; The thickness b of the passivation layer (4) is 5 nm to 1000 nm; The N left array blocks (10), the M right array blocks (11) and the groove anode (12) have the same height, which is c, where c>a+b.

4. The device according to claim 1, characterized in that The N left array blocks (10) and the M right array blocks (11) are staggered.

5. The device according to claim 1, wherein: The distance d between the left array block (10) and the right array block (11) is greater than 0; The distance e between the right array block (11) and the groove anode (12) is greater than 0.

6. The device according to claim 1, wherein: The left array block (10) is composed of N equally spaced metal cuboid blocks, and the distance f between two adjacent cuboid blocks is greater than 0, wherein N≥1; The right array block (11) is composed of M metal cuboid blocks with equal spacing, and the distance g between two adjacent cuboid blocks is greater than 0, wherein M≥2.

7. The device according to claim 1, characterized in that: The P-type block (15) is made of P-GaN, CuO or NiO material, with a thickness of 10nm to 500nm and a doping concentration of 5×10 15 cm -3 ~1×10 22 cm -3 ; The thickness of the i-GaN block (16) is 10 nm to 500 nm.

8. A method for manufacturing an interleaved modulation bidirectional blocking device, characterized in that: The steps include: §1. Epitaxially growing GaN semiconductor material on a substrate (1) to form a transition layer (2); §2. Epitaxially growing a GaN-based wide bandgap semiconductor material on the transition layer (2) to form a barrier layer (3); §3. Depositing an insulating material on the barrier layer (3) to form a passivation layer (4); §4. Making the Source (6): 4.1) Making a mask on the passivation layer (4) for the first time, and using the mask to etch the left side of the passivation layer (4) until the upper surface of the barrier layer (3) is reached, thereby forming a source trench (5); 4.2) Using the mask produced for the first time, deposit multiple layers of metal inside the source trench (5), and perform rapid thermal annealing to form a source electrode (6); §5. A second mask is made on the passivation layer (4) and the source electrode (6). The mask is used to sequentially etch the right passivation layer (4), the barrier layer (3), and the transition layer (2), until the transition layer (2) is etched inside, forming N left array block grooves (7), M right array block grooves (8), and an anode groove (9); §6. A mask is formed for the third time on the passivation layer (4), the source electrode (6), the left array block groove (7), the right array block groove (8), and the anode groove (9). The mask is used to deposit metal inside the left array block groove (7), the right array block groove (8), and the anode groove (9), thereby forming N left array blocks (10), M right array blocks (11), groove anodes (12), and interconnection metal (13). §7. A fourth mask is made on the passivation layer (4), the source electrode (6), and the interconnect metal (13). The mask is used to etch the passivation layer (4) between the source electrode (6) and the left array block (10) until the upper surface of the barrier layer (3) is reached, forming a window (14). §8. A fifth mask is made on the passivation layer (4), source (6), interconnect metal (13) and window (14). Using this mask, a layer with a thickness of 10 nm to 500 nm is deposited in the window (14), with a doping concentration of 5×10 15 cm -3 ~1×10 22 cm -3 P-type block (15); §9. Using the fifth mask, deposit an i-GaN block (16) with a thickness of 10 nm to 500 nm on the top of the P-type block (15); §10. A sixth mask is made on the passivation layer (4), source electrode (6), interconnect metal (13) and i-GaN block (16). The mask is used to deposit metal on the top of the i-GaN block (16) to form a gate electrode (17), completing the fabrication of the entire device.

9. The method according to claim 8, characterized in that: The epitaxial or deposition techniques used in steps §1, §2, §3, §8, and §9 include: metal organic chemical vapor deposition method, plasma enhanced chemical vapor deposition method, molecular beam epitaxy method, and magnetron sputtering method.

10. The method according to claim 8, characterized in that: The metal deposition process used in steps §4, §6, and §10 includes: electron beam evaporation process and sputtering process; The process conditions of the rapid thermal annealing used in step §4 are: the temperature is set to 800° C. to 900° C., and the time is set to 30 seconds to 40 seconds.

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