An adaptive wide range voltage input circuit

Abstract

The application belongs to the field of integrated circuit design, and particularly relates to a self-adaptive wide-width voltage input circuit; the circuit comprises a first module circuit and a second module circuit, and the first module circuit module output end is connected with the second module circuit; the first module circuit comprises a first current source, a first transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first resistor, a second resistor, a third resistor and a fourth resistor; the second module circuit comprises a second current source, a second transistor, a third transistor, a fourth transistor and a fifth transistor; the first module circuit module output end connected with the second module circuit comprises that the output end of the first current source is connected with the emitter of the third transistor, and the base of the first transistor is connected with the base of the second transistor and the collector of the second transistor; the application can provide a wide-width input voltage range and has a low drift characteristic of transconductance, and simultaneously meets the requirement of high integration of a single-chip operational amplifier.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design, specifically relating to an adaptive wide-range voltage input circuit. Background Technology

[0002] In the field of operational amplifiers, the ability to operate with a single supply and low supply voltage is typically required, but this limits the usable range of voltage signals. Therefore, full-swing input / output op-amps have emerged, with their common-mode input range and output voltage swing becoming key consideration parameters. Typically, full-swing input op-amps employ... Figure 1 The double differential pair structure shown is used to implement this. However, a major drawback of this structure is that its transconductance varies by nearly double across the entire common-mode input range. If applied to an op-amp with a feedback loop, this can lead to output waveform distortion. Large variations in input stage transconductance reduce the op-amp's phase margin, resulting in decreased stability. Therefore, an input structure that provides a wide input voltage range and low transconductance drift is particularly important. Summary of the Invention

[0003] To address the shortcomings of existing technologies, this invention proposes an adaptive wide-range voltage input circuit, which includes:

[0004] The first module circuit (100) and the second module circuit (200) are connected to the output terminal of the second module circuit (200). The first module circuit (100) includes a first current source (I1), a first transistor (Q1), a fifth transistor (Q5), a sixth transistor (Q6), a seventh transistor (Q7), an eighth transistor (Q8), a first resistor (R1), a second resistor (R2), a third resistor (R3), and a fourth resistor (R4). The second module circuit (200) includes a second current source (I2), a second transistor (Q2), a third transistor (Q3), a fourth transistor (Q4), and a fifth resistor (R5).

[0005] The output terminal of the first module circuit (100) is connected to the second module circuit (200), including the output terminal of the first current source (I1) connected to the emitter of the third transistor (Q3), and the base of the first transistor (Q1) connected to the base of the second transistor (Q2) and the collector of the second transistor (Q2).

[0006] Preferably, the output terminal of the first current source (I1) is connected with the emitter of the fifth transistor (Q5) and the emitter of the eighth transistor (Q8), the input terminal of the first current source (I1) is connected with the positive electrode of the power supply (VCC); the collector of the first transistor (Q1) is connected with the emitter of the sixth transistor (Q6) and the emitter of the seventh transistor (Q7), the emitter of the first transistor (Q1) is connected with the negative electrode of the power supply (VEE); the emitter of the fifth transistor (Q5) is connected with the emitter of the eighth transistor (Q8), the base of the fifth transistor (Q5) is connected with the negative signal input terminal (IN-), the collector of the fifth transistor (Q5) is connected with the positive terminal of the third resistor (R3); the emitter of the sixth transistor (Q6) is connected with the emitter of the seventh transistor (Q7), the base of the sixth transistor (Q6) is connected with the negative signal input terminal (IN-), the collector of the sixth transistor (Q6) is connected with the negative terminal of the first resistor (R1); the base of the seventh transistor (Q7) is connected with the positive signal input terminal (IN+), the collector of the seventh transistor (Q7) is connected with the negative terminal of the second resistor (R2); the base of the eighth transistor (Q8) is connected with the positive signal input terminal (IN+), the collector of the eighth transistor (Q8) is connected with the positive terminal of the fourth resistor (R4); the positive terminals of the first resistor (R1) and the second resistor (R2) are both connected with the positive electrode of the power supply (VCC), the negative terminals of the third resistor (R3) and the fourth resistor (R4) are both connected with the negative electrode of the power supply (VEE).

[0007] Preferably, the input terminal of the second current source (I2) is connected with the base of the third transistor (Q3) and the negative terminal of the fifth resistor (R5), the output terminal of the second current source (I2) is connected with the negative electrode of the power supply (VEE); the base of the second transistor (Q2) is connected with the collector of the second transistor (Q2) and the collector of the third transistor (Q3), the emitter of the second transistor (Q2) is connected with the negative electrode of the power supply (VEE); the base of the third transistor (Q3) is connected with the negative terminal of the fifth resistor (R5), the collector of the third transistor (Q3) is connected with the collector of the second transistor (Q2); the base of the fourth transistor (Q4) is connected with the collector of the fourth transistor (Q4) and the positive terminal of the fifth resistor (R5), the emitter of the fourth transistor (Q4) is connected with the positive electrode of the power supply (VCC).

[0008] Preferably, the first transistor (Q1), the second transistor (Q2), the sixth transistor (Q6) and the seventh transistor (Q7) are NPN tubes, the third transistor (Q3), the fourth transistor (Q4), the fifth transistor (Q5) and the eighth transistor (Q8) are PNP tubes.

[0009] The beneficial effects of the present application are: the adaptive wide voltage input circuit designed in the present application adopts a new structure, generates a constant voltage through an on-chip mode, and then through a current compensation circuit, can significantly reduce the influence of input common mode voltage change on the working current of the input transistor; compared with the traditional double differential input structure, the present application has higher stability, can make the input transistor have smaller working current offset dispersion in the full input voltage range, at the same time meets the requirement of single chip operational amplifier for high integration, and has wide application prospect. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 is a schematic diagram of a traditional full-swing input double differential pair circuit structure;

[0011] Figure 2 is a schematic diagram of an adaptive wide voltage input circuit structure of a preferred embodiment in the present application;

[0012] Figure 3 is a schematic diagram of an adaptive wide voltage input circuit structure of another preferred embodiment in the present application. DETAILED DESCRIPTION

[0013] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the present application.

[0014] The present application provides an adaptive wide voltage input circuit, as shown in the drawings, Figure 2 In a preferred embodiment of the present application, the first module circuit 100 and the second module circuit 200 are connected at the output end of the first module circuit 100; the first module circuit 100 comprises a first current source I1, a first transistor Q1, a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7, an eighth transistor Q8, a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4; the second module circuit 200 comprises a second current source I2, a second transistor Q2, a third transistor Q3, a fourth transistor Q4 and a fifth resistor R5.

[0015] The output end of the first current source I1 of the first module circuit 100 is connected with the emitter of the third transistor Q3, and the base of the first transistor Q1 is connected with the base and the collector of the second transistor Q2.

[0016] In this embodiment, the first transistor Q1, the second transistor Q2, the sixth transistor Q6 and the seventh transistor Q7 are NPN tubes, and the third transistor Q3, the fourth transistor Q4, the fifth transistor Q5 and the eighth transistor Q8 are PNP tubes.

[0017] The circuit structure of the first module circuit 100 is as follows:

[0018] The output end of the first current source I1 is connected with the emitter of the fifth transistor Q5 and the emitter of the eighth transistor Q8, and the input end of the first current source I1 is connected with the positive electrode VCC of the power supply; the collector of the first transistor Q1 is connected with the emitter of the sixth transistor Q6 and the emitter of the seventh transistor Q7, and the emitter of the first transistor Q1 is connected with the negative electrode VEE of the power supply; the emitter of the fifth transistor Q5 is connected with the emitter of the eighth transistor Q8, the base of the fifth transistor Q5 is connected with the negative input end IN-, the collector of the fifth transistor Q5 is connected with the positive end of the third resistor R3; the emitter of the sixth transistor Q6 is connected with the emitter of the seventh transistor Q7, the base of the sixth transistor Q6 is connected with the negative input end IN-, the collector of the sixth transistor Q6 is connected with the negative end of the first resistor R1; the base of the seventh transistor Q7 is connected with the positive input end IN+, the collector of the seventh transistor Q7 is connected with the negative end of the second resistor R2; the base of the eighth transistor Q8 is connected with the positive input end IN+, the collector of the eighth transistor Q8 is connected with the positive end of the fourth resistor R4; the positive ends of the first resistor R1 and the second resistor R2 are connected with the positive electrode VCC of the power supply, and the negative ends of the third resistor R3 and the fourth resistor R4 are connected with the negative electrode VEE of the power supply.

[0019] The circuit structure of the second module circuit 200 is as follows:

[0020] The input end of the second current source I2 is connected with the base of the third transistor Q3 and the negative end of the fifth resistor R5, and the output end of the second current source I2 is connected with the negative electrode VEE of the power supply; the base of the second transistor Q2 is connected with the collector of the second transistor Q2 and the collector of the third transistor Q3, and the emitter of the second transistor Q2 is connected with the negative electrode VEE of the power supply; the base of the third transistor Q3 is connected with the negative end of the fifth resistor R5, and the collector of the third transistor Q3 is connected with the collector of the second transistor Q2; the base of the fourth transistor Q4 is connected with the collector of the fourth transistor Q4 and the positive end of the fifth resistor R5, and the emitter of the fourth transistor Q4 is connected with the positive electrode VCC of the power supply.

[0021] In this embodiment, the working principle of the circuit is as follows:

[0022] The current source inside the circuit unit is used as an active load to provide constant current. The difference is that, due to the effect of the current mirror structure, the current mapping relationship is formed inside the unit circuit itself. The third transistor Q3 can dynamically adjust the working current of the differential input, i.e. the fifth transistor Q5, the eighth transistor Q8 and the sixth transistor Q6, the seventh transistor Q7, according to the different input common-mode voltage. The second current source I2, the fourth transistor Q4 and the fifth resistor R5 form a circuit to provide a reference voltage, and the base of the third transistor Q3 is provided with a bias voltage, which is approximately equal to the middle value of the power supply voltage. When the input common-mode voltage is the middle value of the power supply voltage, the current of the first current source I1 is approximately twice the collector current of the first transistor Q1, and the collector current of the first transistor Q1 is approximately equal to the working current of the third transistor Q3. At the same time, the current of the second current source I2 needs to be consistent with the working current of the third transistor Q3, so that the be junction voltage drop temperature drift of the fourth transistor Q4 can compensate for the be junction voltage drop temperature drift of the third transistor Q3, thereby reducing the influence of the bias voltage drift caused by temperature change.

[0023] When the input common-mode voltage rises, the working current of the third transistor Q3 becomes larger, and the current of the first current source I1 flowing into the differential pair of the fifth transistor Q5 and the eighth transistor Q8 becomes smaller. According to the formula transconductance gm = IC / (kT / q), the transconductance of the differential pair of the fifth transistor Q5 and the eighth transistor Q8 also decreases, where IC is the working current of the transistor, and kT / q is a constant of 26mV. The working current of the differential pair of the sixth transistor Q6 and the seventh transistor Q7 is mapped from the working current of the third transistor Q3 by the first transistor Q1 and the second transistor Q2, so the working current of the sixth transistor Q6 and the seventh transistor Q7 becomes larger, thereby realizing the increase of the transconductance of the differential pair of the sixth transistor Q6 and the seventh transistor Q7. Conversely, when the working current of the third transistor Q3 becomes smaller as the input common-mode voltage rises, the working current of the differential pair of the fifth transistor Q5 and the eighth transistor Q8 becomes larger, and the working current of the differential pair of the sixth transistor Q6 and the seventh transistor Q7 becomes smaller. With the change of the input common-mode voltage, when one differential pair transistor is turned off, the working current of the other differential pair transistor is doubled, thereby adapting to the requirement of full swing input under low power supply voltage, and ensuring that the transconductance of the operational amplifier is basically stable in the entire input common-mode range.

[0024] In another preferred embodiment of the present application, the first transistor Q1 and the second transistor Q2, the fifth transistor Q5 and the eighth transistor Q8 are PNP transistors, and the third transistor Q3, the fourth transistor Q4, the sixth transistor Q6 and the seventh transistor Q7 are NPN transistors.

[0025] As Figure 3As shown, the embodiment differs from the previous embodiment in that the input end of the first current source I1 is connected with the emitter of the third transistor Q3, the emitter of the sixth transistor Q6 and the emitter of the seventh transistor Q7, and the output end of the first current source I1 is connected with the negative electrode VEE of the power supply.

[0026] The collector of the first transistor Q1 is connected with the emitter of the fifth transistor Q5 and the emitter of the eighth transistor Q8.

[0027] The input end of the second current source I2, the emitter of the first transistor Q1 and the emitter of the second transistor Q2 are all connected with the positive electrode VCC of the power supply, and the output end of the second current source I2 is connected with the base of the third transistor Q3 and the positive end of the fifth resistor R5.

[0028] The collector of the fourth transistor Q4 is connected with the base of the fourth transistor Q4 and then connected with the negative end of the fifth resistor R5, and the emitter of the fourth transistor Q4 is connected with the negative electrode VEE of the power supply.

[0029] The adaptive wide voltage input circuit designed in the present application is designed to consider more application adaptability from the circuit design, avoid the influence of process manufacturing deviation, introduce the structure of current source and differential pair tube, current mirror combination, generate a constant voltage through the on-chip mode, and then through the current compensation circuit, the working current of the input transistor can be significantly reduced. Compared with the traditional double differential input structure, the present application has higher stability, can make the input transistor have smaller working current offset dispersion in the full input voltage range, and at the same time meet the requirement of single chip operational amplifier for high integration.

[0030] The above embodiments further illustrate the purpose, technical solutions and advantages of the present application. It should be understood that the above embodiments are only preferred embodiments of the present application and are not used to limit the present application. Any modification, equivalent replacement, improvement, etc. made to the present application within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. An adaptive wide voltage input circuit, comprising: The first module circuit (100) and the second module circuit (200), the first module circuit (100) module output end is connected with the second module circuit (200), characterized by, the first module circuit (100) includes first current source (I1), first transistor (Q1), fifth transistor (Q5), sixth transistor (Q6), seventh transistor (Q7), eighth transistor (Q8), first resistance (R1), second resistance (R2), third resistance (R3) and fourth resistance (R4);The second module circuit (200) includes second current source (I2), second transistor (Q2), third transistor (Q3), fourth transistor (Q4) and fifth resistance (R5); The first module circuit (100) module output end connected with the second module circuit (200) includes the output end of first current source (I1) is connected with the emitter of third transistor (Q3), the base of first transistor (Q1) is connected with the base of second transistor (Q2) and the collector of second transistor (Q2); The output end of first current source (I1) is connected with the emitter of fifth transistor (Q5) and the emitter of eighth transistor (Q8), the input end of first current source (I1) is connected with power supply positive (VCC);The collector of first transistor (Q1) is connected with the emitter of sixth transistor (Q6) and the emitter of seventh transistor (Q7), the emitter of first transistor (Q1) is connected with power supply negative (VEE);The emitter of fifth transistor (Q5) is connected with the emitter of eighth transistor (Q8), the base of fifth transistor (Q5) is connected with signal negative input end (IN-), the collector of fifth transistor (Q5) is connected with the positive end of third resistance (R3);The emitter of sixth transistor (Q6) is connected with the emitter of seventh transistor (Q7), the base of sixth transistor (Q6) is connected with signal negative input end (IN-), the collector of sixth transistor (Q6) is connected with the negative end of first resistance (R1);The base of seventh transistor (Q7) is connected with signal positive input end (IN+), the collector of seventh transistor (Q7) is connected with the negative end of second resistance (R2);The base of eighth transistor (Q8) is connected with signal positive input end (IN+), the collector of eighth transistor (Q8) is connected with the positive end of fourth resistance (R4);The positive end of first resistance (R1) and second resistance (R2) is connected with power supply positive (VCC), the negative end of third resistance (R3) and fourth resistance (R4) is connected with power supply negative (VEE); An input end of the second current source (I2) is connected with the base of the third transistor (Q3) and the negative end of the fifth resistor (R5), and an output end of the second current source (I2) is connected with the negative electrode (VEE) of the power supply; the base of the second transistor (Q2) is connected with the collector of the second transistor (Q2) and the collector of the third transistor (Q3), and the emitter of the second transistor (Q2) is connected with the negative electrode (VEE) of the power supply; the base of the third transistor (Q3) is connected with the negative end of the fifth resistor (R5), and the collector of the third transistor (Q3) is connected with the collector of the second transistor (Q2); the base of the fourth transistor (Q4) is connected with the collector of the fourth transistor (Q4) and the positive end of the fifth resistor (R5), and the emitter of the fourth transistor (Q4) is connected with the positive electrode (VCC) of the power supply.

2. An adaptive wide voltage input circuit according to claim 1, wherein, The first transistor (Q1), the second transistor (Q2), the sixth transistor (Q6) and the seventh transistor (Q7) are NPN tubes, and the third transistor (Q3), the fourth transistor (Q4), the fifth transistor (Q5) and the eighth transistor (Q8) are PNP tubes.

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