Correlated double sampling front-end readout circuit, capacitance-to-digital converter, and sensor

Abstract

The application provides a correlated double sampling front-end readout circuit, a capacitance digital converter and a sensor, and relates to the technical field of analog-to-digital conversion. The application comprises a pre-charging unit, a sampling conversion unit and an operational amplifier unit; in a first pre-charging stage, the pre-charging unit receives an external voltage for pre-charging, and a first capacitor array in the sampling conversion unit is discharged; in a first sampling stage, the operational amplifier unit transfers the charge obtained in the pre-charging stage to the sampling conversion unit for sampling; in a quantization stage, the sampling conversion unit is converted to obtain a quantization result. The application discards the traditional mode of two pre-charging stages and two sampling stages, and the proposed new correlated double sampling front-end readout circuit only needs one pre-charging and one sampling operation, so that the required time of the pre-charging stage is reduced to 1 / 3 of the original time, thereby greatly reducing the working time of the operational amplifier and indirectly reducing the overall power consumption of the capacitance digital converter.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of analog-to-digital conversion, in particular to a correlated double sampling front-end readout circuit, a capacitance-to-digital converter and a sensor. BACKGROUND

[0002] Capacitance sensors have been widely used in the measurement of environmental signals such as pressure, humidity, acceleration, position and flow due to their good temperature characteristics, simple structure, good dynamic response, high sensitivity and no static power consumption.

[0003] However, the booming development of implantable medical devices and smart medical care has put forward new requirements for capacitance-to-digital converters. The pressure sensor microsystem in implantable medical devices usually requires a system volume of a few cubic millimeters, so the battery volume is small, resulting in very limited battery capacity, and the wireless charging efficiency is low and the technology is complex. SENS The goal of a capacitance-to-digital converter (CDC) is to convert C into a digital code value, so the CDC requires high precision while meeting ultra-low power consumption (nW-level power consumption).

[0004] However, the current front-end readout circuit based on correlated double sampling and SAR quantization capacitance-to-digital converter requires two pre-charging stages and two sampling stages, and the operational amplifier needs to work normally during the pre-charging and sampling stages. The time of two pre-charging stages and two sampling stages is very long, resulting in a large static power consumption of the entire circuit due to the normal operation of the operational amplifier, which cannot meet the requirements of high precision while meeting ultra-low power consumption. SUMMARY

[0005] The present application provides a correlated double sampling front-end readout circuit, a capacitance-to-digital converter and a sensor, which proposes a technical solution that can meet the requirements of high precision while meeting ultra-low power consumption.

[0006] The first aspect of the embodiment of the present application provides a correlated double sampling front-end readout circuit, which comprises a pre-charging unit, a sampling conversion unit and an operational amplifier unit.

[0007] In a pre-charging stage, the pre-charging unit receives an external voltage for pre-charging, and at the same time, the first capacitance array in the sampling conversion unit discharges;

[0008] In a sampling stage, the operational amplifier unit transfers the charge obtained in the pre-charging stage to the sampling conversion unit for sampling;

[0009] In a quantization stage, the sampling conversion unit converts to obtain a quantization result.

[0010] Optionally, the pre-charging unit comprises a reference capacitor and a sensor capacitor.

[0011] The lower plate of the reference capacitor is connected with the first end of a first multi-way selection switch, and the second end of the first multi-way selection switch is grounded or receives the external voltage.

[0012] The upper plate of the reference capacitor is connected with the upper plate of the sensor capacitor, the sampling conversion unit and the operational amplifier unit respectively.

[0013] The lower plate of the sensor capacitor is connected with the first end of a second multi-way selection switch, and the second end of the second multi-way selection switch is grounded or receives the external voltage.

[0014] Optionally, the sampling conversion unit comprises the first capacitor array, a second capacitor array, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch and a seventh switch.

[0015] The upper plate of the first capacitor array is connected with the first end of the second switch, and the second end of the second switch is connected with the second end of the fifth switch, the second end of the reference capacitor and the operational amplifier unit respectively.

[0016] The lower plate of the first capacitor array is connected with the first end of the first switch and the first end of the third switch respectively, the second end of the first switch receives a bias voltage, the second end of the third switch is connected with the first end of the fourth switch, the second end of the sixth switch and the operational amplifier unit respectively, and the second end of the fourth switch receives the bias voltage.

[0017] The upper plate of the second capacitor array is connected with the first end of the sixth switch.

[0018] The lower plate of the second capacitor array is connected with the first end of the fifth switch and the first end of the seventh switch respectively, and the second end of the seventh switch receives the bias voltage.

[0019] Optionally, the operational amplifier unit comprises an operational amplifier, a de-noising capacitor, an eighth switch, a ninth switch and a tenth switch.

[0020] The inverting terminal of the operational amplifier is connected with the lower plate of the de-noising capacitor and the first end of the ninth switch respectively.

[0021] The non-inverting terminal of the operational amplifier is connected with the second end of the tenth switch and receives the bias voltage.

[0022] The output terminal of the operational amplifier is connected with the first end of the eighth switch and the second end of the ninth switch respectively.

[0023] The second end of the eighth switch is connected with the second end of the third switch;

[0024] The upper plate of the de-noising capacitor is connected with the second end of the second switch, the first end of the tenth switch and the upper plate of the sensor capacitor respectively.

[0025] Optionally, during the pre-charging phase, the reference capacitor and the sensor capacitor are charged at the same time, and the offset voltage and the low frequency noise are stored on the de-noising capacitor.

[0026] Optionally, during the pre-charging phase and the sampling phase, the output voltage V OUT is obtained at the output end of the operational amplifier:

[0027]

[0028] In the above formula, C SENS represents the capacitance of the sensor capacitor, C REF represents the capacitance of the reference capacitor, C DACP represents the capacitance of the first capacitor array, C DACN represents the capacitance of the second capacitor array, V DD represents the external voltage.

[0029] Optionally, during the pre-charging phase, the second end of the first multi-selection switch is grounded, the second end of the second multi-selection switch receives the external voltage, the reference capacitor and the sensor capacitor are charged at the same time, the first switch, the seventh switch, the eighth switch are opened, and the remaining switches are closed, and the first capacitor array is discharged.

[0030] During the sampling phase, the second end of the first multi-selection switch receives the external voltage, the second end of the second multi-selection switch is grounded, at the same time, the first switch, the fourth switch, the seventh switch, the ninth switch, the tenth switch are opened, and the remaining switches are closed, and the upper plate of the first capacitor array and the lower plate of the second capacitor array are sampled at the same time.

[0031] During the quantization phase, the second end of the first multi-selection switch receives the external voltage, the second end of the second multi-selection switch is grounded, at the same time, the second switch, the third switch, the fourth switch, the fifth switch, the sixth switch, the tenth switch are opened, and the remaining switches are closed.

[0032] Optionally, in the quantization stage, the lower plate of each of the first and second capacitor arrays receives the bias voltage, and the upper plate of the first capacitor array receives the output voltage V OUT , and the upper plate of the second capacitor array receives a differential voltage: 2V CM -V OUT .

[0033] The second aspect of the embodiment of the present application provides a capacitance digital converter, which comprises the front-end readout circuit according to any one of the first aspect.

[0034] The third aspect of the embodiment of the present application provides a sensor, which comprises the front-end readout circuit according to any one of the first aspect.

[0035] The front-end readout circuit provided by the present application, in a first pre-charging stage, the pre-charging unit receives an external voltage for pre-charging, and the first capacitor array in the sampling conversion unit is discharged; in a first sampling stage, the operational amplifier unit transfers the charge obtained in the pre-charging stage to the sampling conversion unit for sampling; in a quantization stage, the sampling conversion unit is converted to obtain a quantization result. The traditional two pre-charging stages and two sampling stages are abandoned, and the proposed new front-end readout circuit of correlated double sampling only needs one pre-charging and one sampling operation, so the required time of the pre-charging stage is reduced to 1 / 3 of the original, thereby greatly reducing the working time of the operational amplifier, and indirectly reducing the overall power consumption of the capacitance digital converter. BRIEF DESCRIPTION OF DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments of the present application will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0037] Figure 1 is a schematic diagram of a current front-end readout circuit of correlated double sampling;

[0038] Figure 2 is a structural schematic diagram of a preferred front-end readout circuit of the embodiment of the present application;

[0039] Figure 3 is a circuit structure schematic diagram of a first pre-charging stage in the embodiment of the present application;

[0040] Figure 4 is a circuit structure schematic diagram of a first sampling stage in the embodiment of the present application;

[0041] Figure 5This is a schematic diagram of the circuit structure during the quantization stage in an embodiment of the present invention. Detailed Implementation

[0042] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0043] The inventors discovered that the current working principle of the front-end readout circuit based on correlation double sampling and the capacitor-to-digital converter based on SAR quantization, combined with... Figure 1 The schematic diagram of the current relevant double sampling front-end readout circuit is shown below for explanation. Figure 1 C REF For reference capacitor, C SENS For sensor capacitance, C SAMPLE To use capacitors, V OS These are noise reduction capacitors and operational amplifiers. <PRE-CHARGE1> represents the first pre-charge stage, <PRE-CHARGE2> represents the second pre-charge stage, and <SAMPLE2> represents the second sampling stage. The principle of the front-end readout circuit is as follows:

[0044] PRE-CHARGE1 stage: For C REF With C SENS Charging, and for C SAMPLE Discharge is performed.

[0045] SAMPLE1 stage: The charge is Q SAMPLE1 =(C SENS -C REF The charge of VDD is transferred through an operational amplifier to C. SAMPLE The voltage V of the first sample output can be obtained using the following formula. OUT1 for:

[0046]

[0047] In the above formula, C SENS C represents the capacitance of the sensor capacitor. REF This indicates the capacitance of the reference capacitor, C. AMPLE VDD represents the capacitance of the sampling capacitor, and VDD represents the external voltage. REF Indicates reference voltage, V OS This represents the voltage across the noise reduction capacitor.

[0048] After the PRE-CHARGE2 stage: the charge amount Q REF is transferred to C SENS , and C SAMPLE is discharged.

[0049] The SAMPLE2 stage: the charge amount Q SAMPLE2 = (C SENS -C REF )*VDD is transferred to C SAMPLE through the operation of the operational amplifier, and the voltage V OUT2 of the second sampling output can be obtained through the following formula:

[0050]

[0051] The input voltage V OUT quantized by the SAR ADC is:

[0052]

[0053] The charge amount Q SAMPLE transferred to the lower and upper capacitor arrays of the SAR ADC is:

[0054] Q SAMPLE = Q SAMPLE1 -Q SAMPLE2 = 2(C REF -C SENS )*VDD

[0055] The main purpose of the entire front-end readout circuit is to transfer the charge amount Q SAMPLE shown in the above formula to the capacitor array of the SAR ADC.

[0056] Since it can be known that the entire front-end readout circuit needs to perform two pre-charge stages and two sampling stages, the pre-charge and sampling stages need the operational amplifier to work normally, and the time of two pre-charge stages plus two sampling stages is long, which leads to a large static power consumption of the entire circuit due to the need for the operational amplifier to work normally, and cannot well meet the requirement of simultaneously realizing medium-to-high-precision analog quantization while satisfying ultra-low power consumption.

[0057] In view of the above problems, the inventor creatively proposes the front-end readout circuit of the present application, discards the traditional two pre-charge stages and two sampling stages, and only needs one pre-charge and one sampling operation for the proposed new front-end readout circuit of correlated double sampling, which will be described in detail below.

[0058] The front-end readout circuit of the related dual sampling in this embodiment of the invention includes: a pre-charge unit, a sampling conversion unit, and an operational amplifier unit; in the first pre-charge stage, the pre-charge unit receives an external voltage VDD for pre-charge, while the first capacitor array in the sampling conversion unit discharges; in the first sampling stage, the operational amplifier unit transfers the charge obtained in the pre-charge stage to the sampling conversion unit for sampling; finally, in the quantization stage, the sampling conversion unit uses a bias voltage for conversion to obtain the final quantization result.

[0059] Specifically, refer to Figure 2 The diagram shows a preferred front-end readout circuit according to an embodiment of the present invention. Figure 2 In the pre-charge unit, there is a reference capacitor C. REF and sensor capacitance C SENS Reference capacitor C REF The lower electrode plate is connected to the first terminal of the first multiplexer S200, and the second terminal of the first multiplexer S200 is grounded or receives an external voltage V. DD .

[0060] Reference capacitor C REF The upper electrode and the sensor capacitor C SENS Upper electrode connection; sensor capacitor C SENS The lower electrode plate is connected to the first terminal of the second multiplexer S300, and the second terminal of the second multiplexer S300 is grounded or receives an external voltage V. DD In essence, both the first multiplexer S200 and the second multiplexer S300 are two-to-one switches, and their second terminals are either grounded or receive an external voltage V. DD .

[0061] The sampling conversion unit includes: a first capacitor array C DACP Second capacitor array C DACN The switches are: first switch S1, second switch S2, third switch S3, fourth switch S4, fifth switch S5, sixth switch S6, and seventh switch S7. It should be noted that the first capacitor array C... DACP Second capacitor array C DACN Both are arrays formed by multiple capacitors connected in parallel. Figure 2 For the sake of simplicity in the illustration, a single capacitor is used as an example to represent a capacitor array.

[0062] First capacitor array C DACP The upper plate is connected to the first terminal of the second switch S2, and the second terminal of the second switch S2 is connected to the second terminal of the fifth switch S5, the second terminal of the reference capacitor CREF, and the operational amplifier unit, respectively; the first capacitor array C DACPThe lower electrode plate is connected to the first terminal of the first switch S1 and the first terminal of the third switch S3, respectively. The second terminal of the first switch S1 receives the bias voltage V. CM The second terminal of the third switch S3 is connected to the first terminal of the fourth switch S4, the second terminal of the sixth switch S6, and the operational amplifier unit, respectively. The second terminal of the fourth switch S4 receives the bias voltage V. CM .

[0063] Second capacitor array C DACN The upper plate is connected to the first terminal of the sixth switch S6; the second capacitor array C DACN The lower electrode plate is connected to the first terminal of the fifth switch S5 and the first terminal of the seventh switch S7, respectively. The second terminal of the seventh switch S7 receives the bias voltage V. CM .

[0064] The operational amplifier unit includes: operational amplifier CMP, noise reduction capacitor C OS Eighth switch S8, Ninth switch S9, Tenth switch S10;

[0065] The inverting input of the operational amplifier CMP and the noise reduction capacitor C OS The lower plate of the circuit is connected to the first terminal of the ninth switch S9; the non-inverting input of the operational amplifier CMP is connected to the second terminal of the tenth switch S10 and receives the bias voltage V. CM .

[0066] The output terminal of the operational amplifier CMP is connected to the first terminal of the eighth switch S8 and the second terminal of the ninth switch S9, respectively; the second terminal of the eighth switch S8 is connected to the second terminal of the third switch S3; it can be understood that the second terminal of the eighth switch S8 is also connected to the first terminal of the fourth switch S4 and the second terminal of the sixth switch S6, respectively.

[0067] Denoising capacitor C OS The upper electrode plate is connected to the second terminal of the second switch S2, the first terminal of the tenth switch S10, and the sensor capacitor C. SENS The upper plates are connected respectively. It is understandable that the noise reduction capacitor C... OS The upper plate is also connected to the second terminal of the fifth switch S5 and the reference capacitor C. REF The upper electrode plate is connected.

[0068] The principle of the front-end readout circuit in this embodiment of the invention is as follows:

[0069] During a pre-charge phase, the second terminal of the first multiplexer S200 is grounded, and the second terminal of the second multiplexer S300 receives an external voltage V. DD For the reference capacitor C REF and sensor capacitance C SENSDuring charging, the first switch S1, the seventh switch S7, and the eighth switch S8 are open, while the remaining switches are closed, and the first capacitor array C... DACP Discharge occurs, and simultaneously, the offset voltage and low-frequency noise are stored in the noise reduction capacitor C. OS Above. The circuit structure diagram for this stage is shown below. Figure 3 As shown, it should be noted that since the first switch S1 and the seventh switch S7 are open, it is equivalent to the first capacitor array C being deactivated. DACP The lower plate receives a bias voltage V through the closed fourth switch S4. CM However, the bias voltage V was not received through the first switch S1. CM The second capacitor array C DACN The lower electrode plate did not receive the bias voltage V through the seventh switch S7. CM And through the tenth switch S10 and the bias voltage V CM Connection, therefore Figure 3 The first switch S1, the seventh switch S7, and their respective received bias voltage V are not shown. CM For the sake of simplicity in the diagram, the remaining closed switches are represented by lines to indicate that the circuit is open.

[0070] After a pre-charge phase ends, during a sampling phase, the second terminal of the first multiplexer S200 receives the external voltage V. DD The second terminal of the second multiplexer switch S300 is grounded. Simultaneously, the first switch S1, the fourth switch S4, the seventh switch S7, the ninth switch S9, and the tenth switch S10 are open, while the remaining switches are closed. The first capacitor array C... DACP The upper electrode and the second capacitor array C DACN The lower plate is sampled simultaneously. The circuit structure diagram for this stage is shown below. Figure 4 As shown, it should be noted that, and Figure 3 Similarly, since the first switch S1 and the seventh switch S7 are open, it is equivalent to the first capacitor array C being open. DACP The lower electrode plate does not receive the bias voltage V through the first switch S1. CM The second capacitor array C DACN The lower electrode is not connected to the bias voltage V CM Connection, therefore Figure 4 The first switch S1, the seventh switch S7, and their respective received bias voltage V are not shown. CM For the sake of simplicity in the diagram, the remaining closed switches are represented by lines to indicate that the circuit is open.

[0071] Based on the charge conservation during the pre-charging and sampling phases, the following equation can be obtained:

[0072] (V CM -0)C REF+(V CM -V DD )C SENS =(V CM -V DD )C REF +(V CM -0)C SENS +(V CM -V OUT )(C DACN +C DACP )

[0073] Therefore, in the pre-charge stage and the sampling stage, the output voltage V OUT at the output terminal of the operational amplifier is:

[0074]

[0075] In the above formula, C SENS represents the capacitance of the sensor capacitor C SENS , C REF represents the capacitance of the reference capacitor C REF , C DACP represents the capacitance of the first capacitor array C DACP , C DACN represents the capacitance of the second capacitor array C DACN , V DD represents the external voltage, V CM represents the bias voltage.

[0076] After the pre-charge stage and the sampling stage, the quantization stage is entered. In the quantization stage, the second end of the first multiplexer switch S200 receives the external voltage V DD , the second end of the second multiplexer switch S300 is grounded, and at the same time, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, the sixth switch S6, and the tenth switch S10 are opened, and the remaining switches are closed. The circuit structure diagram of this stage is shown in Figure 5 , and it should be noted that, similar to Figure 3 , since the first switch S1 and the seventh switch S7 are closed, it is equivalent that the lower plate of the first capacitor array C DACP receives the bias voltage V CM through the first switch S1, and the lower plate of the second capacitor array C DACN receives the bias voltage V CM through the seventh switch S7, so the loop conduction is directly represented in the form of a line, and the first switch S1 and the seventh switch S7 are not shown. The remaining closed switches are directly represented in the form of a loop conduction for the sake of simplicity of the diagram.

[0077] Therefore, in the quantization stage, it is equivalent that the first capacitor array CDACP and a second capacitor array C DACN Each of the lower plates receives a bias voltage V CM , the first capacitor array C DACP The upper plate obtains an output voltage V OUT , the second capacitor array C DACN The upper plate obtains a differential voltage: 2V CM -V OUT Thus, the single conversion difference of ADC quantization is realized, and the entire work flow of the capacitive digital converter is ultimately completed, and the entire front-end readout circuit only performs a pre-charge stage and a sampling stage to obtain the quantization result.

[0078] Based on the above-mentioned front-end readout circuit of correlated double sampling, the embodiment of the present application further provides a capacitive digital converter, which comprises the front-end readout circuit according to any one of the above.

[0079] Based on the above-mentioned front-end readout circuit of correlated double sampling, the embodiment of the present application further provides a sensor, which comprises the front-end readout circuit according to any one of the above.

[0080] Through the above example, the present application discards the traditional two pre-charge stages and two sampling stages, and the proposed new front-end readout circuit of correlated double sampling only needs one pre-charge and one sampling operation, so that the required time of the pre-charge stage is reduced to 1 / 3 of the original, thereby greatly reducing the working time of the operational amplifier and indirectly reducing the overall power consumption of the capacitive digital converter.

[0081] It should be noted that in this document, the terms "comprising", "containing", or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or apparatus that includes a series of elements not only includes those elements, but also includes other elements not explicitly listed, or inherent to such a process, method, article or apparatus. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article or apparatus that includes the element.

[0082] The embodiments of the present application are described above in combination with the drawings, but the present application is not limited to the above-mentioned specific embodiments, and the above-mentioned specific embodiments are only illustrative and not limiting, and those skilled in the art can make many forms under the inspiration of the present application without departing from the purpose of the present application and the scope protected by the claims, which are all within the protection of the present application.

Claims

1. A correlated double sampling front-end readout circuit, characterized by The front-end readout circuit comprises a pre-charging unit, a sampling conversion unit and an operational amplifier unit; In a pre-charging stage, the pre-charging unit receives an external voltage for pre-charging, and a first capacitor array in the sampling conversion unit is discharged; in a sampling stage, the operational amplifier unit transfers the charge obtained in the pre-charging stage to the sampling conversion unit for sampling; in a quantization stage, the sampling conversion unit is converted to obtain a quantization result; The pre-charging unit comprises a reference capacitor and a sensor capacitor; a lower plate of the reference capacitor is connected with a first end of a first multi-way selection switch, a second end of the first multi-way selection switch is grounded or receives the external voltage; an upper plate of the reference capacitor is connected with an upper plate of the sensor capacitor, and the sampling conversion unit and the operational amplifier unit are connected respectively; a lower plate of the sensor capacitor is connected with a first end of a second multi-way selection switch, a second end of the second multi-way selection switch is grounded or receives the external voltage; The sampling conversion unit comprises the first capacitor array, a second capacitor array, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch and a seventh switch; an upper plate of the first capacitor array is connected with a first end of the second switch, a second end of the second switch is connected with a second end of the fifth switch, a second end of the reference capacitor and the operational amplifier unit respectively; a lower plate of the first capacitor array is connected with a first end of the first switch and a first end of the third switch respectively, a second end of the first switch receives a bias voltage, a second end of the third switch is connected with a first end of the fourth switch, a second end of the sixth switch and the operational amplifier unit respectively, and a second end of the fourth switch receives the bias voltage; an upper plate of the second capacitor array is connected with a first end of the sixth switch; a lower plate of the second capacitor array is connected with a first end of the fifth switch and a first end of the seventh switch respectively, and a second end of the seventh switch receives the bias voltage; The operational amplifier unit comprises an operational amplifier, a de-noising capacitor, an eighth switch, a ninth switch and a tenth switch; an inverting terminal of the operational amplifier is connected with a lower plate of the de-noising capacitor and a first end of the ninth switch respectively; a non-inverting terminal of the operational amplifier is connected with a second end of the tenth switch and receives the bias voltage; an output terminal of the operational amplifier is connected with a first end of the eighth switch and a second end of the ninth switch respectively; a second end of the eighth switch is connected with a second end of the third switch; an upper plate of the de-noising capacitor is connected with a second end of the second switch, a first end of the tenth switch and an upper plate of the sensor capacitor respectively.

2. The front-end sense circuit of claim 1, wherein, In the pre-charging stage, the reference capacitor and the sensor capacitor are charged, and the offset voltage and the low-frequency noise are stored on the de-noising capacitor.

3. The front-end sense circuit of claim 1, wherein, At one of the pre-charge phase and the sampling phase, the output terminal of the operational amplifier obtains an output voltage V OUT is: In the above equation, C SENS represents the capacitance of the sensor capacitor, C REF represents the capacitance of the reference capacitor, C DACP represents the capacitance of the first capacitor array, C DACN represents the capacitance of the second capacitor array, V DD represents the voltage across.

4. The front-end sense circuit of claim 1, wherein, In a pre-charge phase, the second end of the first multiplexer switch is grounded, the second end of the second multiplexer switch receives the external voltage, the reference capacitor and the sensor capacitor are charged, while the first switch, the seventh switch, the eighth switch are open, the rest of the switches are closed, and the first capacitor array is discharged; In a sampling phase, the second end of the first multiplexer switch receives the external voltage, the second end of the second multiplexer switch is grounded, while the first switch, the fourth switch, the seventh switch, the ninth switch, the tenth switch are open, the rest of the switches are closed, and the upper plate of the first capacitor array and the lower plate of the second capacitor array are sampled simultaneously; In a quantization phase, the second end of the first multiplexer switch receives the external voltage, the second end of the second multiplexer switch is grounded, while the second switch, the third switch, the fourth switch, the fifth switch, the sixth switch, the tenth switch are open, the rest of the switches are closed.

5. The front-end sense circuit of claim 4, wherein, In the quantization phase, the lower plates of the first and second capacitor arrays each receive the bias voltage, and the upper plate of the first capacitor array receives an output voltage V OUT , and the upper plate of the second capacitor array receives a differential voltage: 2V CM -V OUT .

6. A correlated double sampling capacitance-to-digital converter, comprising: The capacitive digital converter comprises the front-end readout circuit according to any one of claims 1-5.

7. A sensor, characterized by The sensor comprises the front-end readout circuit according to any one of claims 1-5.

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