Wafer testing method, system and chip application method

Abstract

Embodiments of the present application disclose a wafer testing method, a wafer testing system and a chip application method. The wafer testing method comprises the following steps: providing a wafer to be tested, the wafer to be tested being integrated with a plurality of dies; testing and setting the dies respectively according to a plurality of preset application types; generating a plurality of trimming conditions corresponding to the plurality of preset application types according to testing parameters and setting parameters of the dies; and storing the plurality of trimming conditions into the dies.

Description

[0001] This application is a divisional application of the patent with the application number 202110460709.X and the application date 2021-04-27, and the invention name is wafer testing method, system and chip application method. TECHNICAL FIELD

[0002] Embodiments of the present application relate to the field of semiconductor manufacturing, and in particular to a wafer testing method, system and chip application method. BACKGROUND

[0003] Wafer manufacturing is a process of manufacturing integrated circuits on a wafer. After manufacturing, an array of dies is formed on the wafer. Then, in a wafer testing step, the dies are electrically tested, and unqualified dies are eliminated. Qualified dies are cut from the wafer into individual dies. Wafer testing (CP) is a test of the electrical capability and circuit function of each die on the wafer after wafer manufacturing is completed. Wafer testing is also called die sorting or wafer sorting. Then, packaging is performed to package and wire the qualified dies to form packaged chips. Finally, electrical testing is performed to ensure the quality of the integrated circuits.

[0004] However, the traditional wafer testing method is single and cannot meet the increasing demand for chips. SUMMARY

[0005] Therefore, embodiments of the present application provide a wafer testing method, system and chip application method to solve at least one problem in the prior art.

[0006] To achieve the above-mentioned purpose, the technical scheme of the embodiments of the present application is as follows:

[0007] In a first aspect, the embodiments of the present application provide a wafer testing method, which comprises:

[0008] providing a wafer to be tested, wherein the wafer to be tested has integrated therein a plurality of dies;

[0009] testing and setting the dies according to a plurality of preset application types;

[0010] generating a plurality of trimming conditions corresponding to the plurality of preset application types according to test parameters and setting parameters of the dies;

[0011] storing the plurality of trimming conditions into the dies.

[0012] In an optional embodiment, each of the plurality of trimming conditions has a different storage page address.

[0013] In an optional implementation, the method further includes:

[0014] According to the plurality of tuning conditions, a plurality of reset commands corresponding to the plurality of tuning conditions are set.

[0015] In an optional implementation, the preset application type at least includes one of the following: enterprise application, mobile application, and customer application.

[0016] In a second aspect, an embodiment of the present application provides a chip application method, the method includes:

[0017] According to the application type of the chip, a reset command corresponding to the application type is acquired;

[0018] According to the reset command, a tuning condition corresponding to the reset command is loaded;

[0019] According to the tuning condition, a chip application operation is performed.

[0020] In an optional implementation, the chip stores a plurality of tuning conditions; and each of the plurality of tuning conditions has a different storage page address.

[0021] In a third aspect, an embodiment of the present application provides a wafer test system, including:

[0022] A test unit is configured to test and set the dies according to a plurality of preset application types, respectively;

[0023] A generation unit is configured to generate a plurality of tuning conditions corresponding to the plurality of preset application types according to test parameters and setting parameters of the dies;

[0024] A storage unit is configured to store the plurality of tuning conditions into the dies.

[0025] In an optional implementation, each of the plurality of tuning conditions has a different storage page address.

[0026] In an optional implementation, the method further includes:

[0027] A setting unit is configured to set a plurality of reset commands corresponding to the plurality of tuning conditions according to the plurality of tuning conditions.

[0028] In an optional implementation, the preset application type at least includes one of the following: enterprise application, mobile application, and customer application.

[0029] The embodiment of the present application discloses a wafer testing method, the method comprises: providing a wafer to be tested, the wafer to be tested is integrated with a plurality of dies; according to a plurality of preset application types, the dies are tested and set respectively; according to the test parameters and the setting parameters of the dies, a plurality of trimming conditions corresponding to the plurality of preset application types are generated; the plurality of trimming conditions are stored in the dies. The embodiment of the present application provides a die testing method, in which a plurality of trimming conditions corresponding to a plurality of preset application types are generated, and the plurality of trimming conditions are stored in the dies, so that the application of the die in the embodiment of the present application is not fixed at the wafer testing time, but a plurality of trimming conditions are stored in the die, so that different applications can be performed based on different trimming conditions in subsequent application classification. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 An implementation flow diagram of a wafer testing method provided by the embodiment of the present application is shown in the figure.

[0031] Figure 2 A corresponding relationship diagram of a reset command and a trimming condition provided by the embodiment of the present application is shown in the figure.

[0032] Figure 3 An implementation flow diagram of a chip application method provided by the embodiment of the present application is shown in the figure.

[0033] Figure 4 A power-on reset logic diagram of a chip provided by the embodiment of the present application is shown in the figure.

[0034] Figure 5 A component structure diagram of a wafer testing system provided by the embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0035] The exemplary embodiments of the present application disclosed herein will be described in conjunction with the drawings as follows. Although the exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided so that this application can be more thoroughly and completely conveyed to those skilled in the art.

[0036] In the following description, a large number of specific details are given in order to provide a more thorough understanding of the present application. However, it should be apparent to those skilled in the art that the present application can be implemented without one or more of these details. In other instances, some well-known features are not described in detail in order to avoid obscuring the present application. That is, not all of the features of the actual implementation are described in this detailed description. Skilled artisans appreciate that in the development of any such actual implementation, numerous implementation-specific decisions can be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which can vary from one implementation to another. Moreover, it is to be understood that the application can be practiced without the specific details set forth in this description.

[0037] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of associated items.

[0038] Applications of a NAND product are often classified into Enterprise, Mobile, Client, etc. Different application categories have different preferences on reliability (such as endurance, data retention, operating temperature, etc.) and performance. The manufacturing process of a NAND product is the same, but different applications of the NAND product are achieved by writing different trim profiles in the product during wafer testing.

[0039] However, in the conventional product application classification, only one set of trim profiles can be written in a wafer during wafer testing, in other words, the application of the wafer is limited during wafer testing.

[0040] In the case that only one set of trim profiles can be written in a wafer, NAND products of the same design and manufacturing technology will generate multiple products (each product corresponds to a different application) from wafer testing. For example, A-NAND has only one manufacturing process, but the A-NAND can have multiple product IDs during wafer testing, and each product ID corresponds to a product application. In this way, as the applications of NAND increase, the A-NAND product will also have more and more product IDs, which will make the material planning and inventory management more and more complex and difficult to manage.

[0041] To this end, the following technical solutions of the embodiments of the present application are proposed.

[0042] The embodiments of the present application provide a wafer testing method, Figure 1 The implementation flowchart of the wafer testing method provided by the embodiments of the present application is shown in Figure 1 The method mainly includes the following steps:

[0043] Step 110, providing a wafer to be tested, the wafer to be tested has a plurality of dies integrated thereon.

[0044] Step 120, respectively testing and setting the dies according to a plurality of preset application types.

[0045] In the embodiments of the present application, the test on the die can be a trim test. In the production process of the die, various factors such as process deviation, circuit mismatch, and different production batches of the die can cause a large deviation between the actual die-related parameters and the expected value of the design simulation. This brings great difficulty to the design and manufacture of the die with high parameter requirements. Therefore, in the wafer test stage, in order to improve the yield and quality of the die, it is necessary to trim some parameters of the die as needed, so as to achieve higher performance or differentiated functions. Here, "trimming" usually refers to selectively fusing resistive networks, fuses, or zener diodes and the like in the wafer to improve the performance of the wafer and select different functions of the wafer. After trimming, the wafer after trimming can be measured again by the measurement probe to determine whether the trimming purpose or the design specification is achieved. In actual application, the trim test on the die can include trim by die and trim to target.

[0046] In the embodiments of the present application, after the test on the die, the parameter setting of the die can be performed based on the test result, so as to realize the function of the die. In some embodiments, the parameter setting of the die can also be performed at the same time as the test on the die.

[0047] In the embodiments of the present application, the preset application types at least include one of the following: Enterprise application, Mobile application, and Client application. In some embodiments, the plurality of preset application types can include Enterprise application, Mobile application, and Client application.

[0048] Step 130, generating a plurality of trimming conditions corresponding to the plurality of preset application types according to the test parameters and the setting parameters of the die.

[0049] In the embodiments of the present application, the test parameters are data generated in the test process, and the test parameters include the test result. The setting parameters are setting parameters for realizing the function of the die. According to the test parameters and the setting parameters corresponding to different preset application types, the trimming conditions corresponding to the preset application types are generated. Here, the trimming conditions can be used to represent the application types of the die.

[0050] In the embodiments of the present application, the storage page addresses of each of the plurality of trimming conditions are different. In other words, in each die, the storage page addresses of each trimming condition are different.

[0051] Step 140, storing the plurality of trimming conditions in the die.

[0052] In the embodiments of the present application, the die stores a plurality of trimming conditions, so that the die can implement a plurality of preset application types corresponding to the plurality of trimming conditions, and thus after packaging into a chip, the application type of the die can be determined according to actual customer demand (application demand) by selecting which trimming condition to enable.

[0053] In the embodiments of the present application, different trimming conditions are written to different designated storage page addresses of the die.

[0054] In the embodiments of the present application, the application of the die is not fixed at wafer testing, but a plurality of trimming conditions are stored in the die, so that different applications can be performed based on different trimming conditions during subsequent application classification. In this way, it is not necessary to correspond different trimming conditions (application types) by product ID, so that the product ID of NAND with the same design and manufacturing technology is greatly reduced, and thus material planning and inventory management become easy to manage.

[0055] In the embodiments of the present application, the wafer to be tested can be a general wafer, and all the dies on the general wafer are dies formed by using the same manufacturing process. Generally, the applications of the dies on a wafer are the same, so that when the wafer to be tested is tested and set, the testing and setting can be performed based on the same test parameters and setting parameters. After the dies on the wafer are segmented and packaged into chips, the storage type of the chip can be selectively determined based on the plurality of trimming conditions stored in the chip, so that it is not necessary to fix the application type of the chip at wafer testing, and it is also beneficial to material planning and inventory management.

[0056] The wafer to be tested provided in the embodiments of the present application can also be a multi-project wafer (MPW). The multi-project wafer is a special type of wafer. The wafer is a wafer on which a plurality of integrated circuit designs using the same process are placed for flow, and after manufacturing, each design can obtain tens of chip samples. The characteristic of such a wafer is that each wafer is divided into a plurality of regions, different regions use different integrated circuit designs to implement different tasks, and each region is usually composed of a plurality of the same independent circuits. The dies in different regions store a plurality of trimming conditions, and after the dies on the wafer are segmented and packaged into chips, the storage type of the chip can be selectively determined based on the plurality of trimming conditions stored in the chip, so that it is not necessary to fix the application type of the chip at wafer testing, and it is also beneficial to material planning and inventory management.

[0057] It should be noted that when the trimming test is performed on the dies on the common wafer, since the manufacturing process and the structure of each die are the same, the trimming test can be performed on only one die to generate the multiple trimming conditions corresponding to the multiple preset application types, and the multiple trimming conditions are stored in each die, so that the number of test procedures during the wafer test can be reduced, the maintenance cost can be reduced, and the wafer test time can be reduced. It should be noted that the trimming test is not the wafer test, and the wafer test needs to be performed on each die.

[0058] It should be further noted that when the trimming test is performed on the dies on the multi-target task wafer, since the manufacturing process and the structure of the dies in each region are the same, for each region, the trimming test can be performed on only one die in the region to generate the multiple trimming conditions corresponding to the multiple preset application types, and the multiple trimming conditions are stored in each die in the region, so that the number of test procedures during the wafer test can be reduced, the maintenance cost can be reduced, and the wafer test time can be reduced. It should be noted that the trimming test is not the wafer test, and the wafer test needs to be performed on each die.

[0059] In the embodiment of the present application, multiple trimming conditions corresponding to the multiple preset application types are generated by using the test process of the die during the wafer test, and the multiple trimming conditions are stored in the die. Here, the trimming condition and the preset application type are one-to-one corresponding, and each preset application type corresponds to one trimming condition, so that the application of the preset application type of the die can be realized based on the trimming condition.

[0060] In the embodiment of the present application, according to the multiple trimming conditions, multiple reset commands corresponding to the trimming conditions are set. Here, the trimming condition and the reset command are one-to-one corresponding, and each trimming condition corresponds to one reset command, in other words, each reset command corresponds to one trimming condition, so that in the subsequent power-on reset process, the corresponding trimming condition can be loaded based on the reset command, and the application of the preset application type of the die can be realized based on the trimming condition.

[0061] Figure 2 The corresponding relationship diagram of the reset command and the trimming condition provided in the embodiment of the present application is shown in FIG. 1, in addition to the conventional FFh reset command, the reserved reset commands (such as FEh, FDh, and FCh) are similar to the FFh reset command in logic, and different reset commands are set corresponding to different preset application types. Figure 2 Figure 2 ​As shown, the FFh reset command corresponds to the first trimming condition; the FEh reset command corresponds to the second trimming condition; the FDh reset command corresponds to the third trimming condition; and the FCh reset command corresponds to the fourth trimming condition. Here, the four trimming conditions correspond to four application types. It should be noted that, Figure 2 In the embodiment, only four trimming conditions are taken as an example, and in actual application, a corresponding number of reset commands can be set according to the actual number of trimming conditions. Figure 2 The four trimming conditions in the embodiment are stored in different memory page addresses of the die.

[0062] The embodiment of the present application discloses a wafer testing method, which comprises the following steps: providing a wafer to be tested, wherein a plurality of dies are integrated on the wafer to be tested; respectively testing and setting the dies according to a plurality of preset application types; generating a plurality of trimming conditions corresponding to the plurality of preset application types according to testing parameters and setting parameters of the dies; and storing the plurality of trimming conditions in the dies. The embodiment of the present application provides a wafer testing method, wherein a plurality of trimming conditions corresponding to a plurality of preset application types are generated, and the plurality of trimming conditions are stored in the dies, so that the application of the die in the embodiment of the present application is not fixed at the time of wafer testing, but a plurality of trimming conditions are stored in the die, so that different applications can be performed based on different trimming conditions in subsequent application classification.

[0063] The embodiment of the present application provides a chip application method, Figure 3 The implementation process schematic diagram of the chip application method provided by the embodiment of the present application is as shown in Figure 3 As shown, the method mainly comprises the following steps:

[0064] In step 310, a reset command corresponding to an application type of a chip is acquired.

[0065] In step 320, a trimming condition corresponding to the reset command is loaded according to the reset command.

[0066] In step 330, a chip application operation is performed according to the trimming condition.

[0067] In the embodiment of the present application, since the application type and the trimming condition have a one-to-one correspondence, and the reset command and the trimming condition have a one-to-one correspondence, the reset command required by the chip can be determined based on the application type of the chip, so that the corresponding trimming condition can be loaded based on the reset command.

[0068] In the embodiment of the present application, the die on the wafer to be tested is segmented and packaged to obtain a chip. As Figure 2As shown, multiple reset commands corresponding to multiple trimming conditions are set in the embodiment of the present application, so that in the power-on reset process of the chip, the corresponding trimming condition can be loaded by different reset commands according to the actual application requirement, and the chip application operation is executed based on the trimming condition. Here, the chip application operation is to apply the chip, and the application is the preset application type corresponding to the trimming condition.

[0069] In some embodiments, when the power-on reset is performed, the reset internal register can read repair data and REM data in addition to the trimming condition from the chip. The repair data is the repair relationship of the bad block in the die, and the REM data is the function trimming data of the die. Here, the trimming condition and the REM data corresponding to different reset commands are stored in different storage page addresses.

[0070] In the process of powering on the chip, the power-on reset signal is generated to reset the chip, and the power-on reset signal is disabled after the power voltage reaches the target voltage. The chip executes the initialization process, and after the initialization process is completed, the chip can normally accept user instructions. Therefore, the user can load the corresponding trimming condition by using the reset signal in the power-on reset process, so as to determine the application of the chip.

[0071] The power-on reset logic of the chip is as shown in Figure 4 As shown, CLE is command latch enable, ALE is address latch enable, WE_n is write enable, RE_n is read enable, IOx is data input / output, which is used to transmit commands, data, and addresses, and R / B_n is ready / busy output signal. Among them, FFh is the reset command input by IOx, and tRST is the time when the state pin R / B_n becomes high level after the reset command FFh is written into the command register of the chip (that is, the time when the state of the chip becomes idle).

[0072] In the embodiment of the present application, multiple trimming conditions are stored in the chip, and the storage page addresses of each trimming condition in the multiple trimming conditions are different. Since multiple trimming conditions are stored in the chip in the embodiment of the present application, and each trimming condition corresponds to a different application type, different trimming conditions can be loaded based on different reset commands, that is, different applications of the chip can be realized. In this way, it is not necessary to fix the application type of the chip during wafer testing, and the application of the chip can be determined after packaging, thereby facilitating material planning and inventory management. Further, the application scenarios of the chip can be expanded, and the user can send different reset commands when the chip is powered on and reset, so as to determine the application of the chip.

[0073] The embodiment of the present application discloses a chip application method, the method comprises: according to the application type of chip, the reset command corresponding to the application type is acquired;According to the reset command, the trimming condition corresponding to the reset command is loaded;According to the trimming condition, the chip application operation is executed.The application type of the chip can be determined when the chip is powered on and reset in the embodiment of the present application, different reset commands are selected based on the application of the chip, and the corresponding trimming condition is loaded, and the chip application operation can be executed based on the trimming condition.

[0074] Based on the same technical concept as the wafer test method, the embodiment of the present application provides a wafer test system, in some embodiments, the wafer test system can be realized in the form of a software module, Figure 5 The wafer test system provided in the embodiment of the present application is shown in the component structure diagram, see Figure 5 The wafer test system 500 provided in the embodiment of the present application comprises:

[0075] The test unit 501 is used for testing and setting the die according to a plurality of preset application types respectively;

[0076] The generation unit 502 is used for generating a plurality of trimming conditions corresponding to the plurality of preset application types according to the test parameters and the setting parameters of the die;

[0077] The storage unit 503 is used for storing the plurality of trimming conditions in the die.

[0078] In other embodiments, the storage page address of each trimming condition in the plurality of trimming conditions is different.

[0079] In other embodiments, the method further comprises:

[0080] The setting unit 504 is used for setting a plurality of reset commands corresponding to the plurality of trimming conditions according to the plurality of trimming conditions.

[0081] In other embodiments, the preset application type at least comprises one of the following: enterprise application, mobile application, customer application.

[0082] The components in the embodiment of the present application can be integrated in a processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software function module.

[0083] If the integrated unit is implemented in the form of a software function module and is not sold or used as an independent product, it can be stored in a computer readable storage medium based on this understanding. The technical solutions of the embodiments of the present application essentially or the part of the prior art that contributes to the technical solutions or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a device (such as a transmission electron microscope) with processor function to execute all or part of the steps of the method described in the embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (Read Only Memory, ROM), a random access memory (Random Access Memory, RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0084] It can be understood that the embodiments described herein can be implemented in hardware, software, firmware, middleware, microcode, or a combination thereof. For hardware implementation, the processing unit can be implemented in one or more application specific integrated circuits (Application Specific Integrated Circuits, ASICs), digital signal processors (Digital Signal Processing, DSP), digital signal processing devices (DSP Device, DSPD), programmable logic devices (Programmable Logic Device, PLD), field programmable gate arrays (Field-Programmable Gate Array, FPGA), general processors, controllers, microcontrollers, microprocessors, other electronic units for executing functions described in the present application, or a combination thereof.

[0085] For software implementation, the technology described herein can be implemented by modules (such as processes, functions, etc.) that perform functions described herein. Software code can be stored in a memory and executed by a processor. The memory can be implemented in the processor or outside the processor.

[0086] It should be understood that the "application embodiments" or "some embodiments" mentioned throughout the specification mean that the specific features, structures or characteristics related to the embodiments are included in at least one embodiment of the present application. Therefore, "in the embodiments of the present application" or "in some embodiments" appearing throughout the specification does not necessarily mean the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner.

[0087] It should be understood that the size of the serial number of the above processes in various embodiments of the present application does not mean the order of execution, the execution order of the processes should be determined by its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The serial number of the above embodiments of the present application is only for description, not representing the advantages and disadvantages of the embodiments.

[0088] The methods disclosed in the several method embodiments provided by the present application can be combined arbitrarily without conflict to obtain new method embodiments.

[0089] The features disclosed in the several device embodiments provided by the present application can be combined arbitrarily without conflict to obtain new device embodiments.

[0090] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A memory test method characterized by, The method comprises: According to a plurality of preset application types, at least one memory is tested and set respectively; The memory is a bare chip with storage function; According to the test parameters and the setting parameters of the memory, a plurality of trimming conditions corresponding to the plurality of preset application types are generated; Before the memory is segmented, For each of the memories, the plurality of trimming conditions are stored in the memory.

2. The memory test method of claim 1, wherein, The storage page address of each of the plurality of trimming conditions is different.

3. The memory test method of claim 1, wherein, The method further comprises: According to a plurality of trimming conditions, a plurality of reset commands corresponding to the plurality of trimming conditions are set.

4. The memory test method of claim 1, wherein, The preset application type at least includes one of the following: enterprise application, mobile application, and customer application.

5. A memory manufacturing method, characterized by, The method comprises: Obtaining a plurality of trimming conditions generated according to a plurality of preset application types; Before the memory is segmented, For each of the memories, the plurality of trimming conditions are stored in the memory; The memory is a bare chip with storage function.

6. The memory fabrication method of claim 5, wherein, The storage page address of each of the plurality of trimming conditions is different.

7. The memory fabrication method of claim 5, wherein, The obtaining of the plurality of trimming conditions generated according to a plurality of preset application types comprises: According to a plurality of preset application types, at least one sample memory is tested and set; according to the test parameters and the setting parameters of the sample memory, a plurality of trimming conditions corresponding to the plurality of preset application types are generated.

8. The memory fabrication method of claim 5, wherein, The method further comprises: According to the plurality of trimming conditions, a plurality of reset commands corresponding to the plurality of trimming conditions are set; the correspondence between the plurality of trimming conditions and the plurality of reset commands is stored in the memory.

9. The memory fabrication method of claim 5, wherein, The preset application type at least includes one of the following: enterprise application, mobile application, and customer application.

10. A memory chip, characterized by The storage chip stores a plurality of trimming conditions corresponding to a plurality of preset application types; The storage chip is packaged by a memory bare chip; Each of the memory bare chips stores a plurality of trimming conditions corresponding to a plurality of preset application types; The storage chip is configured to obtain the trimming condition corresponding to the preset application type according to the preset application type.

11. The memory chip of claim 10, wherein, The storage chip is configured to obtain the trimming condition corresponding to the preset application type according to the reset command corresponding to the preset application type.

12. A wafer, characterized by, Comprise: At least one memory bare chip; each of the memory bare chips stores a plurality of trimming conditions corresponding to a plurality of preset application types.

13. The wafer of claim 12, wherein, The memory bare chip is configured to obtain the trimming condition corresponding to the preset application type according to the preset application type.

14. A storage system, comprising: Comprise: A storage chip and a controller; The storage chip stores a plurality of trimming conditions corresponding to a plurality of preset application types; The storage chip is packaged by a memory bare chip; Each of the memory bare chips stores a plurality of trimming conditions corresponding to a plurality of preset application types; The controller is configured to load the trimming condition corresponding to the preset application type in the memory according to the preset application type.

15. The storage system of claim 14, wherein, The storage system stores the correspondence between a plurality of trimming conditions and a plurality of reset commands; The controller is specifically configured to send the reset command corresponding to a preset application type to the memory chip according to the preset application type, so as to load the trimming condition corresponding to the preset application type.

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