Structure, manufacturing method and power electronics device of nanosheet power device

Abstract

The application discloses a structure and a manufacturing method of a nanosheet power device and power electronic equipment, and belongs to the technical field of semiconductors. The nanosheet power device comprises a nanosheet stacking part and a gate structure. The nanosheet stacking part is in an H type in a horizontal plane and comprises a plurality of sacrificial layers and a plurality of nanosheet layers arranged alternately in parallel. In the nanosheet layer, a first semiconductor type region, a second semiconductor type region, a third semiconductor type region and a fourth semiconductor type region are arranged in sequence along a transverse direction, and the second semiconductor type region is located in the middle of a horizontal line of the H type. The nanosheet layer further comprises a fifth semiconductor type region located at a reentrant corner position of the third semiconductor type region. A region of the sacrificial layer overlapping the second semiconductor type region in a vertical direction is hollowed out, and the gate structure is arranged around the second semiconductor type region in the hollowed-out region. The fifth semiconductor type region and the third semiconductor type region are N-type regions and P-type regions, respectively. The reverse withstand voltage capacity of the nanosheet power device is improved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular relates to a structure and manufacturing method of a nanosheet power device and a power electronic device. Background Art

[0002] As various nanosheet processes have been proposed, difficulties have arisen when applying nanosheet structures to high-voltage devices such as insulated gate bipolar transistors (IGBTs) and vertical double-diffusion metal-oxide-semiconductors (VDMOSs).

[0003] Since a drift layer must be added to the three-terminal transistor to improve the device's ability to withstand reverse voltage, however, during reverse bias operation, the electric field strength at the junction of the drift layer and the gate is large, making avalanche effect prone to occur.

[0004] Therefore, the related nanosheet power devices have the defect of being prone to avalanche effect and having poor reverse voltage resistance. Summary of the Invention

[0005] The purpose of this application is to provide a structure, a manufacturing method and a power electronic device of a nanosheet power device, aiming to solve the problem that the related nanosheet power devices are prone to avalanche effect and thus have poor reverse voltage withstand capability.

[0006] The present invention provides a nanosheet power device structure.

[0007] including a nanosheet stacking portion and a gate structure;

[0008] The nanosheet stack portion is H-shaped in a horizontal plane, comprising a plurality of sacrificial layers and a plurality of nanosheet layers arranged alternately in parallel; wherein, in the nanosheet layer, a first semiconductor type region, a second semiconductor type region, a third semiconductor type region, and a fourth semiconductor type region are sequentially arranged in a transverse direction, and the second semiconductor type region is located in the middle of a transverse line of the H-shape; the nanosheet layer further comprises a fifth semiconductor type region, the fifth semiconductor type region being located at a concave corner position of the third semiconductor type region;

[0009] The region of the sacrificial layer that overlaps with the second semiconductor type region in the vertical direction is hollowed out, and the gate structure is arranged in the hollowed-out region surrounding the second semiconductor type region;

[0010] The fifth semiconductor type region and the third semiconductor type region are respectively an N-type region and a P-type region.

[0011] In one embodiment, the fifth semiconductor type region and the third semiconductor type region form a super junction structure.

[0012] In one embodiment, on a horizontal plane, the gate structure extends upward and downward to form an extension portion of the gate structure, and a support portion is provided between the extension portion and two vertical lines of the H-shape.

[0013] In one embodiment, the first semiconductor type region is a highly doped first N-type region, the second semiconductor type region is a highly doped first P-type region, the third semiconductor type region is a low-doped first N-type region, the fourth semiconductor type region is a highly doped second P-type region, and the fifth semiconductor type region is a highly doped third P-type region.

[0014] In one embodiment, the first semiconductor type region serves as the emitter of the nanosheet power device, the gate structure serves as the gate of the nanosheet power device, and the fourth semiconductor type region serves as the collector of the nanosheet power device.

[0015] In one embodiment, the first semiconductor type region is a third N-type region, the second semiconductor type region is a fourth P-type region, the third semiconductor type region is a fourth N-type region, the fourth semiconductor type region is a fifth N-type region, and the fifth semiconductor type region is a fifth P-type region.

[0016] In one embodiment, the first semiconductor type region is the sixth P-type region, the second semiconductor type region is the sixth N-type region, the third semiconductor type region is the seventh P-type region, the fourth semiconductor type region is the eighth P-type region, and the fifth semiconductor type region is the seventh N-type region.

[0017] The present invention also provides a method for manufacturing a nanosheet power device, wherein the method comprises:

[0018] Step A: forming a sacrificial layer on the upper surface of the substrate;

[0019] Step B: forming a nanosheet layer on the upper surface of the sacrificial layer; wherein, in the nanosheet layer, the first semiconductor type region, the second semiconductor type region, the third semiconductor type region, and the fourth semiconductor type region are sequentially arranged in a lateral direction;

[0020] Step C: forming a fifth semiconductor type region at the upper edge and the lower edge of the region of the third semiconductor type region that intersects with the second semiconductor type region; wherein the fifth semiconductor type region and the third semiconductor type region are an N-type region and a P-type region, respectively;

[0021] Repeating steps A to C n times to form a nanosheet stacking structure; wherein n is a natural number greater than 1;

[0022] Step D: imaging the nanosheet stack structure to form an H-shape; wherein the second semiconductor type region is located in the middle of the horizontal line of the H-shape;

[0023] Step E: forming a support portion inside the two vertical lines of the H-shaped portion;

[0024] Step F: removing the sacrificial layer that overlaps with the second semiconductor type region in a vertical direction to form a hollow region;

[0025] Step G: Filling the hollow region and the H-shaped gap region with a conductive material to form a gate structure.

[0026] In one embodiment, the first semiconductor type region is a highly doped first N-type region, the second semiconductor type region is a highly doped first P-type region, the third semiconductor type region is a low-doped first N-type region, the fourth semiconductor type region is a highly doped second P-type region, and the fifth semiconductor type region is a highly doped third P-type region; step B comprises:

[0027] forming a single crystal silicon layer on the upper surface of the sacrificial layer;

[0028] Ion implantation is performed on the upper surface of the single crystal silicon layer to form the highly doped first N-type region, the highly doped first P-type region, the low doped second N-type region and the highly doped second P-type region which are sequentially arranged in a lateral direction;

[0029] The step C specifically includes forming the highly doped third P-type region at the upper edge and the lower edge of the region in the low doped first N-type region that borders the highly doped first P-type region.

[0030] In one embodiment, the first semiconductor type region is a third N-type region, the second semiconductor type region is a fourth P-type region, the third semiconductor type region is a fourth N-type region, the fourth semiconductor type region is a fifth N-type region, and the fifth semiconductor type region is a fifth P-type region; step B comprises:

[0031] forming a single crystal silicon layer on the upper surface of the sacrificial layer;

[0032] Ion implantation is performed on the upper surface of the single crystal silicon layer to form the third N-type region, the fourth P-type region, the fourth N-type region, and the fifth N-type region arranged in sequence along the lateral direction;

[0033] The step C specifically includes forming the fifth P-type region at the upper edge and the lower edge of the fourth N-type region at the junction with the fourth P-type region.

[0034] In one embodiment, the first semiconductor type region is a sixth P-type region, the second semiconductor type region is a sixth N-type region, the third semiconductor type region is a seventh P-type region, the fourth semiconductor type region is an eighth P-type region, and the fifth semiconductor type region is a seventh N-type region; step B comprises:

[0035] forming a single crystal silicon layer on the upper surface of the sacrificial layer;

[0036] Ion implantation is performed on the upper surface of the single crystal silicon layer to form the sixth P-type region, the sixth N-type region, the seventh P-type region, and the eighth P-type region arranged in sequence along the lateral direction;

[0037] The step C specifically includes forming the seventh N-type region at the upper edge and the lower edge of the seventh P-type region at the junction with the sixth N-type region.

[0038] In one embodiment, the step E comprises:

[0039] Filling the H-shaped groove position with a spacer layer material to form a spacer layer;

[0040] An extension region of the spacer layer in the longitudinal direction with respect to the second semiconductor type region is removed so that the remaining spacer layer forms a supporting portion.

[0041] In one embodiment, step G comprises:

[0042] A conductive material is filled in the hollow region and the H-shaped gap region by vapor deposition or sputtering to form a gate structure.

[0043] An embodiment of the present application further provides a power electronic device, which includes the structure of the nanosheet power device described above.

[0044] The beneficial effects of the embodiments of the present invention compared with the prior art are: since the fifth semiconductor type region and the third semiconductor type region are respectively an N-type region and a P-type region; the fifth semiconductor type region and the third semiconductor type region interact with each other, thereby reducing the electric field strength at the junction of the third semiconductor type region and the second semiconductor type region (gate) during reverse bias operation, preventing the occurrence of avalanche effect, improving the reverse voltage withstand capability of the nanosheet power device, and thus improving the reliability of the nanosheet power device. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description only relate to some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0046] Figure 1 A three-dimensional structural schematic diagram of a structure of a nanosheet power device provided by an embodiment of the present application;

[0047] Figure 2 A comparison schematic diagram of the relationship between the electric field intensity and the position of the third semiconductor type region with / without a super-junction structure of a nanosheet power device provided by an embodiment of the present application;

[0048] Figure 3 A schematic diagram of forming a sacrificial layer in a manufacturing method of a nanosheet power device provided by an embodiment of the present application;

[0049] Figure 4 A schematic diagram of forming a nanosheet layer in a manufacturing method of a nanosheet power device provided by an embodiment of the present application;

[0050] Figure 5 A schematic diagram of forming a fifth semiconductor type region in a manufacturing method of a nanosheet power device provided by an embodiment of the present application;

[0051] Figure 6 A schematic diagram of forming a nanosheet stack structure in a manufacturing method of a nanosheet power device provided by an embodiment of the present application;

[0052] Figure 7 A schematic diagram of making the nanosheet stack structure into an H type in a manufacturing method of a nanosheet power device provided by an embodiment of the present application;

[0053] Figure 8 A schematic diagram of forming a support part in a manufacturing method of a nanosheet power device provided by an embodiment of the present application;

[0054] Figure 9 A schematic diagram of forming a hollow region in a manufacturing method of a nanosheet power device provided by an embodiment of the present application;

[0055] Figure 10 A schematic diagram of forming a gate structure in a manufacturing method of a nanosheet power device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0056] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, this application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0057] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0058] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0059] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0060] Figure 1 The module structure of the nanosheet power device provided by the embodiment of the present invention is shown. For the sake of convenience, only the parts related to the embodiment of the present invention are shown, which are detailed as follows:

[0061] The structure of the nanosheet power device includes a nanosheet stack 10 and a gate structure 40 .

[0062] The nanosheet stack portion 10 is H-shaped in the horizontal plane, including multiple sacrificial layers 20 and multiple nanosheet layers 30 arranged in parallel and alternating order; wherein, in the nanosheet layer 30, the first semiconductor type region 31, the second semiconductor type region 32, the third semiconductor type region 33 and the fourth semiconductor type region 34 are arranged in sequence along the lateral direction, and the second semiconductor type region 32 is located in the middle of the horizontal line position of the H shape; the nanosheet layer 30 also includes a fifth semiconductor type region 35, which is located at a concave corner position of the third semiconductor type region 33.

[0063] The region of the sacrificial layer 20 overlapping with the second semiconductor type region 32 in the vertical direction is hollowed out, and the gate structure 40 is arranged around the second semiconductor type region 32 in the hollowed-out region; wherein the fifth semiconductor type region 35 and the third semiconductor type region 33 are N-type region and P-type region respectively.

[0064] It is worth emphasizing that the fifth semiconductor type region 35 and the third semiconductor type region 33 form a super-junction structure.

[0065] The fifth semiconductor type region 35 and the third semiconductor type region 33 interact to form a super-junction structure; as Figure 2 shown, the dashed line represents the relationship between the electric field intensity and the position of the third semiconductor type region 33 without the fifth semiconductor type region 35, and the solid line represents the relationship between the electric field intensity and the position of the third semiconductor type region 33 with the fifth semiconductor type region 35. It can be seen that after the fifth semiconductor type region 35 and the third semiconductor type region 33 form a super-junction structure, the electric field intensity at the junction of the third semiconductor type region 33 and the second semiconductor type region 32 (gate) is reduced during reverse bias operation, preventing the occurrence of avalanche effect, improving the reverse withstand voltage capability of the nanosheet power device, and making the nanosheet power device have the characteristics of low on-resistance, fast switching speed, small chip size, and low heat generation, thereby improving the reliability of the nanosheet power device.

[0066] As an example but not limitation, as Figure 2 shown, in the horizontal plane, the gate structure 40 extends upward and downward to form an extension of the gate structure 40, and a support part 50 is arranged between the extension and the two vertical lines of the H-shaped structure.

[0067] By arranging the support part 50 between the extension and the two vertical lines of the H-shaped structure, the strength of the nanosheet power device is improved, and the reliability and convenience of use of the nanosheet power device are improved.

[0068] As an example but not limitation, the first semiconductor type region 31 is a highly doped first N-type region 31, the second semiconductor type region 32 is a highly doped first P-type region 32, the third semiconductor type region 33 is a lowly doped first N-type region 31, the fourth semiconductor type region 34 is a highly doped second P-type region 34, and the fifth semiconductor type region 35 is a highly doped third P-type region 35. It should be noted that the first semiconductor type region 31 is the emitter of the nanosheet power device, the gate structure 40 is the gate of the nanosheet power device, the fourth semiconductor type region 34 is the collector of the nanosheet power device, and the third semiconductor type region 33 is the drift region of the nanosheet power device.

[0069] The high-doped first N-type region 31, the high-doped first P-type region 32, the low-doped second N-type region 33, the high-doped second P-type region 34 and the high-doped third P-type region 35 in the plurality of nanosheet layers 30 form an IGBT tube, which reduces the switching time and reduces the switching loss.

[0070] By way of example and not limitation, the first semiconductor type region 31 is a third N-type region 31, the second semiconductor type region 32 is a fourth P-type region 32, the third semiconductor type region 33 is a fourth N-type region 33, the fourth semiconductor type region 34 is a fifth N-type region 34, and the fifth semiconductor type region 35 is a fifth P-type region 35. It is noted that the first semiconductor type region 31 is a drain of the nanosheet power device, the gate structure 40 is a gate of the nanosheet power device, and the third semiconductor type region 33 and the fourth semiconductor type region 34 are sources of the nanosheet power device.

[0071] The third N-type region 31, the fourth P-type region 32, the fourth N-type region 33, the fifth N-type region 34 and the fifth P-type region 35 in the plurality of nanosheet layers 30 form an N-type VDMOS tube.

[0072] By way of example and not limitation, the first semiconductor type region 31 is a sixth P-type region 31, the second semiconductor type region 32 is a sixth N-type region 32, the third semiconductor type region 33 is a seventh P-type region 33, the fourth semiconductor type region 34 is an eighth P-type region 34, and the fifth semiconductor type region 35 is a seventh N-type region 35. It is noted that the first semiconductor type region 31 is a drain of the nanosheet power device, the gate structure 40 is a gate of the nanosheet power device, and the third semiconductor type region 33 and the fourth semiconductor type region 34 are sources of the nanosheet power device.

[0073] The sixth P-type region 31, the sixth N-type region 32, the seventh P-type region 33, the eighth P-type region and the seventh N-type region 35 in the plurality of nanosheet layers 30 form a P-type VDMOS tube.

[0074] Corresponding to one embodiment of the nanosheet power device, the present application also provides one embodiment of a manufacturing method of the nanosheet power device.

[0075] A manufacturing method of a nanosheet power device, the method comprising steps 301 to 306.

[0076] In step 301, as shown in FIG. 1, a sacrificial layer 20 is formed on the surface of a substrate 80. Figure 3

[0077] The sacrificial layer 20 is formed on the surface of the substrate 80 by vapor deposition or sputtering.

[0078] In step 302, as shown in FIG. 2, a first semiconductor type region 31 is formed on the surface of the sacrificial layer 20. Figure 4 ​As shown, a nanosheet layer 30 is formed on the upper surface of the sacrificial layer 20 ; wherein, in the nanosheet layer 30 , a first semiconductor type region 31 , a second semiconductor type region 32 , a third semiconductor type region 33 and a fourth semiconductor type region 34 are sequentially arranged along the lateral direction.

[0079] In step 303, if Figure 5 As shown, a fifth semiconductor type region is formed at the upper and lower edges of the region where the third semiconductor type region 33 borders the second semiconductor type region 32. The fifth semiconductor type region 35 and the third semiconductor type region 33 are N-type and P-type regions, respectively.

[0080] The fifth semiconductor type region is formed by ion implantation at the upper surface of the upper edge and the upper surface of the lower edge of the region bordering the second semiconductor type region 32 in the third semiconductor type region 33 .

[0081] In a specific implementation, there are three cases for step 302 and step 303. In the first case, the first semiconductor type region 31 is a highly doped first N-type region 31, the second semiconductor type region 32 is a highly doped first P-type region 32, the third semiconductor type region 33 is a low-doped first N-type region 31, the fourth semiconductor type region 34 is a highly doped second P-type region 34, and the fifth semiconductor type region 35 is a highly doped third P-type region 35; step 302 includes steps 302-1a and 302-2a, and step 303 specifically forms the highly doped third P-type region 35 at the upper and lower edges of the region of the low-doped first N-type region 33 that intersects with the highly doped first P-type region 32.

[0082] In step 302 - 1 a , a single crystal silicon layer is formed on the upper surface of the sacrificial layer 20 . The single crystal silicon layer can be formed on the upper surface of the sacrificial layer 20 by vapor deposition or sputtering.

[0083] In step 302 - 2 a , ions are implanted on the upper surface of the single crystal silicon layer to form a highly doped first N-type region 31 , a highly doped first P-type region 32 , a low doped second N-type region 33 and a high doped second P-type region 34 arranged in sequence along the lateral direction.

[0084] Three ion implantations are performed on the single crystal silicon layer to form a highly doped first N-type region 31 , a highly doped first P-type region 32 , a low doped second N-type region 33 and a high doped second P-type region 34 arranged in sequence along the lateral direction.

[0085] In the second case, the first semiconductor type region 31 is the third N-type region 31, the second semiconductor type region 32 is the fourth P-type region 32, the third semiconductor type region 33 is the fourth N-type region 33, the fourth semiconductor type region 34 is the fifth N-type region 34, and the fifth semiconductor type region 35 is the fifth P-type region 35; step 302 includes step 302-1b and step 302-2b, and step 303 is specifically: forming the fifth P-type region 35 at the upper edge and lower edge of the area in the fourth N-type region 33 that intersects with the fourth P-type region 32.

[0086] In step 302 - 1 b , a single crystal silicon layer is formed on the upper surface of the sacrificial layer 20 .

[0087] In step 302 - 2 b , ions are implanted on the upper surface of the single crystal silicon layer to form the third N-type region 31 , the fourth P-type region 32 , the fourth N-type region 33 and the fifth N-type region 34 arranged in sequence along the lateral direction.

[0088] In the third case, the first semiconductor type region 31 is the sixth P-type region 31, the second semiconductor type region 32 is the sixth N-type region 32, the third semiconductor type region 33 is the seventh P-type region 33, the fourth semiconductor type region 34 is the eighth P-type region 34, and the fifth semiconductor type region 35 is the seventh N-type region 35; step 302 includes step 302-1c and step 302-2c, and step 303 is specifically: forming the seventh N-type region 35 at the upper edge and lower edge of the area in the seventh P-type region 33 that intersects with the sixth N-type region 32.

[0089] In step 302 - 1 c , a single crystal silicon layer is formed on the upper surface of the sacrificial layer 20 .

[0090] In step 302-2c, ions are implanted on the upper surface of the single crystal silicon layer to form the sixth P-type region 31, the sixth N-type region 32, the seventh P-type region 33 and the eighth P-type region 34 arranged in sequence along the lateral direction.

[0091] Repeat steps 301 to 303 n times to form a nanosheet stacking structure, such as Figure 6 As shown; n is a natural number greater than 1.

[0092] In step 304, if Figure 7 As shown, the nanosheet stacking structure is made into an H-shape by imaging; wherein the second semiconductor type region 32 is located in the middle of the horizontal line position of the H-shape; wherein the imaging includes an etching process.

[0093] In step 305, if Figure 8 As shown, a support portion 50 is formed inside the two vertical lines of the H-shape.

[0094] In a specific implementation, step 305 includes step 305 - 1 and step 305 - 2 .

[0095] In step 305 - 1 , a spacer material is filled in the H-shaped groove to form a spacer layer.

[0096] The H-shaped groove position is filled with a spacer layer material by vapor deposition or sputtering to form a spacer layer.

[0097] In step 305 - 2 , the region of the spacer layer extending in the longitudinal direction from the second semiconductor type region 32 is removed so that the remaining spacer layer forms the support portion 50 .

[0098] The region of the spacer layer extending in the longitudinal direction from the second semiconductor type region 32 is removed by etching so that the remaining spacer layer forms the support portion 50 .

[0099] In step 306, if Figure 9 As shown, the sacrificial layer 20 vertically overlapping the second semiconductor type region 32 is removed to form a hollow region.

[0100] The sacrificial layer 20 vertically overlapping with the second semiconductor type region 32 is removed by etching to form a hollow region.

[0101] In step 307, if Figure 10 As shown, the hollow region and the H-shaped gap region are filled with conductive material to form a gate structure 40 .

[0102] In a specific implementation, the gate structure 40 may be formed by filling the hollow region and the H-shaped gap region with a conductive material by vapor deposition or sputtering.

[0103] It is worth noting that the sacrificial layer 20 may be SiGe, the gate structure 40 may be gold or palladium, and the support portion 50 and the spacer layer may be silicon oxide or silicon nitride.

[0104] The embodiment of the present invention comprises a nanosheet stack and a gate structure; the nanosheet stack is H-shaped in a horizontal plane, comprising a plurality of sacrificial layers and a plurality of nanosheet layers arranged alternately in parallel; wherein, in the nanosheet layer, a first semiconductor type region, a second semiconductor type region, a third semiconductor type region, and a fourth semiconductor type region are arranged sequentially in a lateral direction, with the second semiconductor type region located in the middle of the horizontal line of the H-shape; the nanosheet layer also includes a fifth semiconductor type region located at a recessed corner of the third semiconductor type region; the region of the sacrificial layer that vertically overlaps with the second semiconductor type region is hollowed out, and a gate structure is provided in the hollowed-out region surrounding the second semiconductor type region; the fifth semiconductor type region and the third semiconductor type region are respectively an N-type region and a P-type region. Due to the interaction between the fifth semiconductor type region and the third semiconductor type region, the electric field strength at the interface between the third semiconductor type region and the second semiconductor type region (gate) is reduced during reverse bias operation, preventing the occurrence of an avalanche effect, improving the reverse withstand voltage capability of the nanosheet power device, and thus improving the reliability of the nanosheet power device.

[0105] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0106] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A structure of a nanosheet power device, characterized in that: including a nanosheet stacking portion and a gate structure; The nanosheet stack portion is H-shaped in a horizontal plane, comprising a plurality of sacrificial layers and a plurality of nanosheet layers arranged alternately in parallel; wherein, in the nanosheet layer, a first semiconductor type region, a second semiconductor type region, a third semiconductor type region, and a fourth semiconductor type region are sequentially arranged in a transverse direction, and the second semiconductor type region is located in the middle of a transverse line of the H-shape; the nanosheet layer further comprises a fifth semiconductor type region, the fifth semiconductor type region being located at a concave corner position of the third semiconductor type region; The region of the sacrificial layer that overlaps with the second semiconductor type region in the vertical direction is hollowed out, and the gate structure is arranged in the hollowed-out region surrounding the second semiconductor type region; wherein the first semiconductor type region is a highly doped first N-type region, the second semiconductor type region is a highly doped first P-type region, the third semiconductor type region is a low-doped first N-type region, the fourth semiconductor type region is a highly doped second P-type region, and the fifth semiconductor type region is a highly doped third P-type region; or The first semiconductor type region is a third N-type region, the second semiconductor type region is a fourth P-type region, the third semiconductor type region is a fourth N-type region, the fourth semiconductor type region is a fifth N-type region, and the fifth semiconductor type region is a fifth P-type region; or The first semiconductor type region is the sixth P-type region, the second semiconductor type region is the sixth N-type region, the third semiconductor type region is the seventh P-type region, the fourth semiconductor type region is the eighth P-type region, and the fifth semiconductor type region is the seventh N-type region.

2. The structure of the nanosheet power device according to claim 1, wherein: The fifth semiconductor type region and the third semiconductor type region form a super junction structure.

3. The structure of the nanosheet power device according to claim 1, wherein: On a horizontal plane, the gate structure extends upward and downward to form an extension portion of the gate structure, and a support portion is provided between the extension portion and two vertical lines of the H-shape.

4. The structure of the nanosheet power device according to claim 1, wherein: The first semiconductor type region serves as an emitter of the nanosheet power device, the gate structure serves as a gate of the nanosheet power device, and the fourth semiconductor type region serves as a collector of the nanosheet power device.

5. A method for manufacturing a nanosheet power device, characterized in that: The manufacturing method comprises: Step A: forming a sacrificial layer on the upper surface of the substrate; Step B: forming a nanosheet layer on the upper surface of the sacrificial layer; wherein, in the nanosheet layer, the first semiconductor type region, the second semiconductor type region, the third semiconductor type region, and the fourth semiconductor type region are sequentially arranged in a lateral direction; Step C: forming a fifth semiconductor type region at the upper edge and the lower edge of the region of the third semiconductor type region that borders the second semiconductor type region; Repeating steps A to C n times to form a nanosheet stacking structure; wherein n is a natural number greater than 1; Step D: imaging the nanosheet stack structure to form an H-shape; wherein the second semiconductor type region is located in the middle of the horizontal line of the H-shape; Step E: forming a support portion inside the two vertical lines of the H-shaped portion; Step F: removing the sacrificial layer that overlaps with the second semiconductor type region in a vertical direction to form a hollow region; Step G: Filling the hollow area and the H-shaped gap area with a conductive material to form a gate structure; wherein the first semiconductor type region is a highly doped first N-type region, the second semiconductor type region is a highly doped first P-type region, the third semiconductor type region is a low-doped first N-type region, the fourth semiconductor type region is a highly doped second P-type region, and the fifth semiconductor type region is a highly doped third P-type region; or The first semiconductor type region is a third N-type region, the second semiconductor type region is a fourth P-type region, the third semiconductor type region is a fourth N-type region, the fourth semiconductor type region is a fifth N-type region, and the fifth semiconductor type region is a fifth P-type region; or The first semiconductor type region is the sixth P-type region, the second semiconductor type region is the sixth N-type region, the third semiconductor type region is the seventh P-type region, the fourth semiconductor type region is the eighth P-type region, and the fifth semiconductor type region is the seventh N-type region.

6. The method for manufacturing a nanosheet power device according to claim 5, characterized in that: The first semiconductor type region is a highly doped first N-type region, the second semiconductor type region is a highly doped first P-type region, the third semiconductor type region is a low-doped first N-type region, the fourth semiconductor type region is a highly doped second P-type region, and the fifth semiconductor type region is a highly doped third P-type region; step B comprises: forming a single crystal silicon layer on the upper surface of the sacrificial layer; Ion implantation is performed on the upper surface of the single crystal silicon layer to form the highly doped first N-type region, the highly doped first P-type region, the low doped first N-type region and the highly doped second P-type region which are sequentially arranged in a lateral direction; The step C specifically includes forming the highly doped third P-type region at the upper edge and the lower edge of the region in the low doped first N-type region that borders the highly doped first P-type region.

7. The method for manufacturing a nanosheet power device according to claim 5, wherein: The first semiconductor type region is a third N-type region, the second semiconductor type region is a fourth P-type region, the third semiconductor type region is a fourth N-type region, the fourth semiconductor type region is a fifth N-type region, and the fifth semiconductor type region is a fifth P-type region; step B comprises: forming a single crystal silicon layer on the upper surface of the sacrificial layer; Ion implantation is performed on the upper surface of the single crystal silicon layer to form the third N-type region, the fourth P-type region, the fourth N-type region, and the fifth N-type region arranged in sequence along the lateral direction; The step C specifically includes forming the fifth P-type region at the upper edge and the lower edge of the fourth N-type region at the junction with the fourth P-type region.

8. The method for manufacturing a nanosheet power device according to claim 5, wherein: The first semiconductor type region is a sixth P-type region, the second semiconductor type region is a sixth N-type region, the third semiconductor type region is a seventh P-type region, the fourth semiconductor type region is an eighth P-type region, and the fifth semiconductor type region is a seventh N-type region; step B comprises: forming a single crystal silicon layer on the upper surface of the sacrificial layer; Ion implantation is performed on the upper surface of the single crystal silicon layer to form the sixth P-type region, the sixth N-type region, the seventh P-type region, and the eighth P-type region arranged in sequence along the lateral direction; The step C specifically includes forming the seventh N-type region at the upper edge and the lower edge of the seventh P-type region at the junction with the sixth N-type region.

9. The method for manufacturing a nanosheet power device according to claim 5, wherein: The step E comprises: Filling the H-shaped groove position with a spacer layer material to form a spacer layer; An extension region of the spacer layer in the longitudinal direction with respect to the second semiconductor type region is removed so that the remaining spacer layer forms a supporting portion.

10. The method for manufacturing a nanosheet power device according to claim 5, wherein: The step G comprises: A conductive material is filled in the hollow region and the H-shaped gap region by vapor deposition or sputtering to form a gate structure.

11. A power electronic device, characterized in that: The power electronic device comprises the structure of the nanosheet power device according to any one of claims 1 to 4.

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