Analog-to-digital converter with single counter circuit

Abstract

Analog-to-digital converter (300), ADC, for implementing a calculation of a difference between a first analog signal level (Vsig) and a second analog signal level (Vres), the ADC (300) comprising: at least one input (311) for receiving an input signal, the input signal comprising one of the first analog signal level (Vsig) and the second analog signal level (Vres); an input (310) for receiving a ramp signal (Vramp); an input (313) for receiving an input clock (CLK); a counter (303) configurable to count in a count direction, the count direction being any one of a first count direction and a second count direction; a comparator (301) configured to generate a comparator output signal based on a comparison of the ramp signal (Vramp) and the input signal; and a control stage configured to enable the counter (303) to count in the first count direction based on the comparator output signal, and to enable the counter (303) to count in the second count direction based on an inversion of the comparator output signal.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to analog-to-digital converters (ADCs) with a single counter circuit, in particular with signal-independent power consumption, ADCs with a ramp ADC double edge counter using a single counter circuit. The present disclosure relates in particular to column-parallel ADCs that can be used in CMOS image sensors. BACKGROUND

[0002] Image sensors typically contain a large number of ADCs, one per column of the pixel array, and need to accommodate very small pitches equal to the pixel pitch. For such image sensor ADCs the following constraints should be met: good control of the power supply is necessary to avoid that one ADC is affected by one or more of the other, concurrently operating, ADCs. Possible cross-talk between two ADCs would be very visible in the image and would disturb the image quality. Typically, the A / D converter is the main component in an image sensor. In particular, using a ramp type of ADC, the counting clock signal is run at a high frequency and is distributed over the entire width of the pixel array. To limit the power consumption, it is beneficial to count on both edges of the counting clock signal. This halves the clock frequency needed to operate the counter compared to single edge counting, while keeping the same counter resolution for each given conversion time. The circuit needs to be as compact as possible.

[0003] The simplest solution is to use a single counter. This limits the area, but does not solve the reduced clock frequency and constant power consumption. This solution can suffer from cross-talk between the ADCs due to a shared and poorly controlled power supply.

[0004] A prior art solution that solves both the reduced clock frequency and constant power consumption is described in US patent application publication US 2014 / 0203956 Al, where the example is shown in Figure 1 and Figure 2 A detailed explanation of the functioning of the described prior art solution is provided in US 2014 / 0203956 Al, which is familiar to the skilled person.

[0005] Figure 1 The architecture of one of the column analog-to-digital converters introduced in the above mentioned application is shown. The single column ADC 100 contains two counters: one up counter 61 (rising edge) and one down counter 62 (falling edge).

[0006] Figure 2 The timing diagram in Fig. 2 shows a typical operation of such a ramp ADC 100 in an image sensor. The purpose of the ADC 100 is to directly convert the reset signal level (V res ) and the integrated pixel signal level (V sigThe difference between the ramp signal (V) and the ramp signal (V). Therefore, when the ramp signal (V) is... ramp )205 and reset signal V res At the point of intersection and before the ramp signal 205 intersects with the integrated pixel signal 204, the rising edge increment counter 61 is active. The activity of the decrement counter 62 is complementary to that of the increment counter 61. The total number of ADC clock cycles is predetermined as: 'x' clock cycles for reset transitions and 'y' clock cycles for signal transitions. When the two counter values ​​are summed (by adder 65), the resulting ADC value returns a value relative to V. sig With V res The difference between them plus a fixed offset, such as Figure 2 The linear measure shown in the equation, this fixed offset can be adjusted in data post-processing.

[0007] The drawback of this existing solution is that it requires two counters for each pixel column, and therefore each ADC requires a large area. Summary of the Invention

[0008] This disclosure provides techniques for addressing the aforementioned problems. In particular, this disclosure provides an ADC for image sensors with limited power consumption and improved crosstalk characteristics, which allows for smaller circuit layout and smaller pixel pitch than existing solutions.

[0009] The features of the independent claims provide a solution for implementing such a technique. Other implementations are provided by the dependent claims, the specification, and the figures.

[0010] The solution described below, based on this disclosure, introduces a novel ADC architecture based on a single counter circuit. The ADC's power consumption is independent of the converted signal because the counter is always active. This ensures signal independence for each individual ADC in the ADC sensor array. Therefore, crosstalk between parallel ADCs via supply and ground networks can be avoided.

[0011] A fundamental concept of this disclosure can be summarized as replacing the circuitry containing an increment counter, a decrement counter, and an adder in each column of the ADC with a single counter for each column. This allows for both increment and decrement counting and enables dynamic switching during the AD conversion process, i.e., without stopping the input clock signal. Therefore, one of the two counters and the adder circuitry in the solution of US 2014 / 0203956 A1 can be eliminated.

[0012] According to a first aspect, the disclosure relates to an analog-to-digital converter (ADC) for implementing a calculation of a difference between a first analog signal level (Vsig) and a second analog signal level (Vres), the ADC comprising: at least one input for receiving an input signal, the input signal comprising one of the first analog signal level (Vsig) and the second analog signal level (Vres); an input for receiving a ramp signal (Vramp); an input for receiving an input clock (CLK); a counter configurable to count in a counting direction, the counting direction being any one of a first counting direction and a second counting direction; a comparator configured to generate a comparator output signal based on a comparison of the ramp signal (Vramp) and the input signal; and a control stage configured to: enable the counter to count in the first counting direction based on the comparator output signal, and enable the counter to count in the second counting direction based on an inversion of the comparator output signal.

[0013] With this ADC, the power consumption is independent of the signal being converted, as the counter is always active. This ensures a signal-independent supply and ground for each individual ADC used in an array of ADCs, e.g. an array of ADCs of an image sensor. Thus, cross-talk generated by the supply and ground net between parallel ADCs can be avoided. When illuminating an image sensor using such an array of ADCs, the consumption of the image sensor does not depend on the illumination level.

[0014] The first counting direction can be an up-counting, and the second counting direction can be a down-counting, or the first counting direction can be a down-counting, and the second counting direction can be an up-counting.

[0015] There can be a correspondence between the initial counting direction of the counter and a particular input signal or conversion. The correspondence can be that the initial counting direction is in the first counting direction when initially inputting the first analog signal level, and the initial counting direction is in the second counting direction when initially inputting the second analog signal level. In other words, for each input signal, the initial counting direction is opposite to each other during a first time portion of each input signal.

[0016] The input signals can be input sequentially, e.g. the first analog signal level (Vsig) is input, and then the second analog signal level (Vres).

[0017] In an exemplary implementation form of the ADC, the control stage is configured to invert the counting direction of the counter during a conversion of one of the input signals without stopping the input clock (CLK).

[0018] This provides the technical advantage that inverting the counting direction of the counter has no impact on the timing of the ADC.

[0019] Reversing the counting direction without stopping the input clock enables switching in a dynamic manner during conversion. This enables the counter to be continuously active (on average) during conversion, which ensures a signal-independent supply and ground for each individual ADC. Thus, cross-talk through the supply and ground net between parallel ADCs is avoided.

[0020] In an exemplary implementation form of the ADC, the counter comprises a plurality of flip-flops connected in series, in particular JK flip-flops or T flip-flops.

[0021] This provides the technical advantage that the counter can be easily implemented by using standard hardware circuits.

[0022] The counter can be implemented as an asynchronous binary ripple counter.

[0023] The number of flip-flops of the counter can correspond to a predefined resolution of the ADC. This provides the technical advantage that the resolution (and complexity) of the ADC is scalable depending on the design of the counter.

[0024] In an exemplary implementation form of the ADC, the counter comprises a plurality of multiplexer units, each multiplexer unit being connected between an output and an input of two consecutive flip-flops of the counter, wherein the control stage is configured to reverse the counting direction of the counter by switching the multiplexer units between the flip-flops.

[0025] This provides the technical advantage that using such multiplexing allows designing the counting direction reversal in an efficient manner.

[0026] In an exemplary implementation form of the ADC, the control stage is configured to let the last clock cycle of the input clock (CLK) pass completely through the counter before switching the multiplexer units. In an exemplary implementation form of the ADC, the number of flip-flops of the state machine circuitry is predetermined according to a delay with respect to a stable counter state before the reversal of the counting direction.

[0027] This provides the technical advantage that the counter is in a predefined state before each reversal of the counting direction.

[0028] In an exemplary implementation form, the ADC comprises a state machine circuitry consisting of a plurality of flip-flops connected in series.

[0029] This provides the technical advantage that such a state machine circuitry can be efficiently used for controlling the counter state.

[0030] In an exemplary implementation form of the ADC, the control stage is configured to trigger the state machine circuitry based on an inversion of the comparator output signal.

[0031] This provides the technical advantage that the state machine can be synchronized with the comparator output signal, i.e. the difference between the ramp signal and the input signal.

[0032] The inversion of the comparator output signal is the result from the comparison of the input signal and Vramp during the conversion.

[0033] The control stage can also be configured to trigger the counter to enter a freeze state. This can happen simultaneously with triggering the state machine circuitry, also based on the inversion of the comparator output signal.

[0034] The delay is predetermined and can be measured in a predetermined number of clock pulses. This allows for an error-free count direction change.

[0035] In an exemplary implementation form of the ADC, the counter comprises clock control circuitry configured to enable the clocking of the counter based on the inversion of the comparator output signal and an output signal of the state machine circuitry, the output signal signaling a stable counter state.

[0036] This provides the technical advantage that the counter can be synchronized with the clock signal and the comparator output signal, i.e. the difference between the ramp signal and the input signal.

[0037] Whether the counter state is stable is not determined by the circuitry disclosed herein. Only a certain time is allowed for the stable state to occur.

[0038] In an exemplary implementation form of the ADC, the ADC comprises an input for receiving an inverted input clock (CLK_B) corresponding to an input clock (CLK) inverted by an inverter.

[0039] This provides the technical advantage that the counter can count two ADC counts per clock cycle.

[0040] In an exemplary implementation form of the ADC, the state machine circuitry comprises clock control circuitry configured to enable the clocking of the state machine circuitry based on the inverted input clock (CLK_B) or based on the input clock (CLK).

[0041] This provides the technical advantage that the state machine circuitry can be clocked on the rising edge of the clock signal as well as on the falling edge of the clock signal, enabling two ADC counts per clock cycle.

[0042] In an exemplary implementation form of the ADC, the control stage is configured to: deactivate the clocking of the counter by the input clock (CLK) based on the inversion of the comparator output signal; and activate the clocking of the state machine circuitry by the inverted input clock (CLK_B) when the clocking of the counter by the input clock (CLK) is deactivated.

[0043] This provides the technical advantage that the conversion between the incrementing counting and the decrementing counting can be effectively implemented.

[0044] In an example implementation form of the ADC, the counter is configured to perform the counting twice per clock cycle of an input clock (CLK).

[0045] This provides the technical advantage that both the incrementing counting and the decrementing counting can be implemented within a single clock cycle of the input clock of the ADC.

[0046] In an example implementation form of the ADC, the ADC is configured to clock the counter on one edge of an input clock (CLK) and to clock the state machine circuitry on another edge of the input clock (CLK).

[0047] This provides the technical advantage that a flexible clocking can be implemented.

[0048] In an example implementation form of the ADC, the ADC uses only a single counter to count in either of the first counting direction and the second counting direction.

[0049] This provides the technical advantage that by using a single counter, hardware resources can be saved and the design of the ADC is facilitated.

[0050] In an example implementation form of the ADC, the counter is incrementing / decrementing reversible in response to a direction control signal from the state machine circuitry based on the comparator output signal.

[0051] This provides the technical advantage that a flexible incrementing / decrementing counting can be implemented.

[0052] In an example implementation form of the ADC, the ADC is configured to implement the calculation of the difference between the first analog signal level (Vsig) and the second analog signal level (Vres) without using an adder.

[0053] This provides the technical advantage that by not using an adder, hardware resources can be saved and the design of the ADC is facilitated.

[0054] The ADC provides an output code based on the outputs (B0, B1, B2, B3) of the counter-based (JK or T) flip-flops (Q outputs).

[0055] In an example implementation form of the ADC, the control stage is configured to invert the comparator output signal in response to an inversion control signal and to provide the counter with the comparator output signal inverted thereby only for the conversion of one of the input signals.

[0056] This provides the technical advantage that this is the way the input signals are subtracted from each other. Without this controlled inversion, only addition is possible.

[0057] In an exemplary implementation form of the ADC, the counting direction is changed during a first conversion of one of the input signals and then remains within a second conversion of one of the input signals.

[0058] This provides the same technical advantage as described above, i.e. that this is the way the input signals are subtracted. Without this controlled inversion, only addition is possible.

[0059] According to a second aspect, the disclosure relates to a method for implementing a calculation of a difference between a first analog signal level (Vsig) and a second analog signal level (Vres), the method comprising: receiving an input signal, the input signal comprising one of the first analog signal level (Vsig) and the second analog signal level (Vres); receiving a ramp signal (Vramp); receiving an input clock (CLK); counting by a counter in a counting direction, the counting direction being any one of a first counting direction and a second counting direction; generating a comparator output signal based on a comparison of the ramp signal (Vramp) and the input signal; and enabling the counter to count in the first counting direction based on the comparator output signal and enabling the counter to count in the second counting direction based on an inversion of the comparator output signal.

[0060] By using this method, the power consumption is independent of the converted signal, as the counter is always active. This ensures a signal independent supply and ground for each individual conversion. Using this method, an array of ADCs in a sensor array will have better cross-talk characteristics, as cross-talk between parallel ADCs generated by the supply and ground net can be avoided. When illuminating an image sensor comprising an array of ADCs based on this method, the consumption of the image sensor is independent of the illumination level.

[0061] The entities described in this disclosure can comprise processors or processing circuitry that handle the respective functions. A processor as described in this disclosure can comprise hardware and / or software. The hardware can comprise digital circuitry, or both analog and digital circuitry. The digital circuitry can comprise components such as application specific integrated circuits (ASICs), field programmable arrays (FPGAs), digital signal processors (DSPs), or general purpose processors. In one implementation, the processor comprises one or more processor cores and a non-transitory memory connected to the one or more processor cores. The non-transitory memory can carry executable program code that, when executed by the one or more processor cores, causes the device to perform the operations or methods described herein. BRIEF DESCRIPTION OF DRAWINGS

[0062] Other embodiments of the present application will be described with respect to the following figures, in which:

[0063] Figure 1 A block diagram is shown that illustrates a prior solution for a column ADC 100 in an image sensor with two counters (incrementing and decrementing) and an adder;

[0064] Figure 2 A timing diagram 200 is shown for the column ADC 100 shown in Figure 1

[0065] Figure 3 A block diagram is shown for an ADC 300 according to the present disclosure with a single (incrementing / decrementing) counter;

[0066] Figure 4 A timing diagram 400 is shown for the ADC 300 shown in Figure 3

[0067] A block diagram is shown for an exemplary counter circuitry 500 for the ADC 300 shown in Figure 5 Figure 3

[0068] An exemplary timing diagram 601 is shown that illustrates the operation of the ADC 300 shown in Figure 6a Figure 3 An exemplary timing diagram 602 is shown that illustrates the operation of the ADC 300 shown in

[0069] Figure 6b Figure 3 An exemplary timing diagram 603 is shown that illustrates the operation of the ADC 300 shown in

[0070] Figure 6c An exemplary timing diagram 603 is shown that illustrates the operation of the ADC 300 shown in Figure 3 DETAILED DESCRIPTION

[0071] ​​​​​In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which are shown, by way of illustration, specific aspects in which the disclosure can be practiced. It is understood that other aspects can be utilized and structural or logical changes can be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of the disclosure is defined by the appended claims and equivalents thereof.

[0072] It should be understood that any references to steps or operations in the described methods also refer to corresponding units or systems configured to perform the steps or operations, and any references to units or systems configured to perform steps or operations also refer to the corresponding steps or operations. For example, if a particular method step is described, a corresponding unit or system can include a unit that performs the described method step, even if such unit is not explicitly described or shown in the figures. Furthermore, it should be understood that the features of the various exemplary aspects described herein can be combined with each other, unless explicitly stated otherwise.

[0073] The described apparatuses can include integrated circuits and / or passive circuit elements, and can be manufactured according to various technologies. For example, the circuits can be designed as logic integrated circuits, analog integrated circuits, mixed-signal integrated circuits, optical circuits, memory circuits, and / or integrated passive devices.

[0074] Figure 3 A block diagram of an ADC 300 with a single (increment / decrement) counter according to the present disclosure is shown.

[0075] The ADC 300 includes a comparator 301, a level shifter and inverter 302, an increment / decrement counter 303, and a memory, e.g., SRAM 304. The comparator 301 receives a ramp signal V ramp at a first input 310, e.g., a negative input (-), and a reset signal V res / integrated pixel signal V sig at a second input 311, e.g., a positive input (+). The comparator 301 is based on the ramp signal V ramp and the reset signal V res / integrated pixel signal V sigThe comparison provides a comparator output signal COMP OUT at an output 318 of the comparator connected to a first input of a level shifter and inverter 302. An inversion signal (INV) is received at a second input 312 of the level shifter and inverter 302. Depending on the state of the inversion signal (INV), the level shifter and inverter 302 provides the comparator output signal COMP OUT or an inverted comparator output signal at an output of the level shifter and inverter connected to a first input 315 of a counter 303. The up / down counter 303 provides a count result at an output 317 depending on the comparator output signal COMP OUT, a clock signal CLK at a second input of the counter 303 and an MR signal at a third input 314 of the counter 303 according to a counter logic. An example of such a counter logic is shown in Figure 5 The output 317 of the counter 303 is connected to a first input of an SRAM 304. Depending on a STORE signal provided at a further input 316 of the SRAM 304, the count result can be stored in the SRAM 304.

[0076] The analog-to-digital converter 300 can be used to implement a calculation of a difference between a first analog signal level Vsig and a second analog signal level Vres. The ADC 300 comprises at least one input 311 for receiving an input signal comprising one of the first analog signal level Vsig and the second analog signal level Vres, an input 310 for receiving a ramp signal Vramp, an input 313 for receiving an input clock CLK, a counter 303 configurable to count in a count direction, the count direction being any one of a first count direction and a second count direction, a comparator 301 configured to generate a comparator output signal based on a comparison of the ramp signal Vramp and the input signal, and a control stage (not shown in Figure 3 The control stage is configured to enable the counter 303 to count in the first count direction based on the comparator output signal and to enable the counter 303 to count in the second count direction based on an inversion of the comparator output signal.

[0077] The control stage can invert the count direction of the counter 303 during a conversion of one of the input signals without stopping the input clock CLK. The counter 303 can be implemented according to the description of the counter 510 with regard to Figure 5 The counter 303 can comprise a plurality of flip-flops 511 connected in series, for example, as described below with regard to Figure 5The triggers can be implemented as JK triggers or T triggers. The number of triggers 511 of the counter 303, 510 can correspond to the predefined resolution of the ADC 300. That is, a higher resolution ADC requires more triggers compared to a lower resolution ADC.

[0078] The counter 303 can comprise a plurality of multiplexer units (MUX0, MUX1, etc.) 512, each connected between the output and the input of two consecutive triggers 511 of the counter 303, 510, e.g., as shown in Figure 5 The control stage can be configured to reverse the counting direction of the counter 303, 510 by switching the multiplexer units 512 between the triggers 511.

[0079] In an exemplary implementation, the control stage can be configured to let the last clock cycle of the input clock CLK pass completely through the counter 303, 510 before switching the multiplexer units 512.

[0080] In an exemplary implementation, the ADC 300 comprises state machine circuitry 520 consisting of a plurality of triggers 521 connected in series, e.g., as described below with respect to Figure 5 The control stage can be configured to trigger the state machine circuitry 520 based on the inversion of the comparator output signal COMP OUT.

[0081] The number of triggers 521 of the state machine circuitry 520 can be predetermined according to the delay with respect to the stable counter state before the reversal of the counting direction.

[0082] In an exemplary implementation, the counter 303, 510 comprises clock control circuitry 514 configured to enable the clocking of the counter 303, 510 based on the inversion of the comparator output signal COMP OUT and an output signal 526 of the state machine circuitry 520, which signals the stable counter state, e.g., as described below with respect to Figure 5

[0083] In an exemplary implementation, the ADC 300 can comprise an input 535 for receiving an inverted input clock CLK B corresponding to the input clock CLK inverted by an inverter 531, e.g., as shown in Figure 5 The state machine circuitry 520 can comprise clock control circuitry 523 configured to enable the clocking of the state machine circuitry 520 based on the inverted input clock CLK B or based on the input clock CLK, e.g., as shown in Figure 5 ​​

[0084] The control stage can be configured to deactivate the clocking of the counter 303, 510 by the input clock CLK based on the inversion of the comparator output signal, and to activate the clocking of the state machine circuitry 520 by the inverted input clock CLK_B when the clocking of the counter 303, 510 is deactivated by the input clock CLK.

[0085] The counter 303, 510 can perform the counting twice per clock cycle of the input clock CLK.

[0086] The ADC 300 can be configured to clock the counter 303 on one edge of the input clock CLK and the state machine circuitry 520 (shown in Figure 5 ) on the other edge of the input clock CLK.

[0087] The ADC 300 uses only a single counter to count in either of the first and second count directions.

[0088] The counter 303 can be increment / decrement reversible based on the comparator output signal in response to a direction control signal from the state machine circuitry 520 (shown in Figure 1 ).

[0089] The ADC 300 can be configured to implement the calculation of the difference between the first analog signal level Vsig and the second analog signal level Vres without using an adder.

[0090] The control stage can be configured to invert the comparator output signal in response to an inversion control signal and thus to provide the inverted comparator output signal to the counter (303, 510) only for the conversion of one of the input signals.

[0091] The count direction can be changed during a first conversion of one of the input signals and then held for a second conversion of one of the input signals.

[0092] Thus, compared to the ADC shown in Figure 5 , the newly presented solution applies very similar conversion techniques and timing, but uses a single binary ripple counter 303 that can be transformed from an incrementing to a decrementing counter without stopping the input clock signal. This can be achieved, for example, by internally stopping the clock while the externally applied clock keeps running. When switching the counter direction, the local clock signal is gated for a known amount of clock pulses, which allows an error-free count direction change of the ripple counter, even at very high clock frequencies.

[0093] The circuit includes a ripple counter based on JK flip-flops. In an alternative solution, the counter can be based on T flip-flops. The functionality is that the counter can reverse direction. Other techniques that provide reversible counting can be used. The counter direction can be reversed by toggling the MUX cells between JK flip-flops. To switch the count direction of the ripple counter in an error-free manner, it is helpful that the last clock cycle before the switch passes completely through the asynchronous ripple counter like a ripple. Therefore, in the exemplary implementation, a 'counter switch state machine' 520 (see Figure 4 ) is added. This state machine 520 is triggered when the "COMP_OUT" signal switches. The counter clock will be gated by the circuit for a predetermined number of clock cycles. This time allows the ripple counter 303, 510 to settle. After the ripple counter 303, 510 has settled, the "CTR_DIR" select signal is switched. The clock input is again applied to the ripple counter 303, 510 after one more clock cycle.

[0094] Figure 3 An exemplary timing diagram 400 for the ADC 300 shown in Figure 4 is shown.

[0095] The ADC 300 receives two analog signals, the reset voltage V res and the signal voltage V sig . In an implementation of a sensor array, the two signals can be received from a column output bus of the sensor array. The reset voltage can be the voltage of the pixel after a reset. The signal voltage can be the voltage of the pixel after exposure to light during an exposure period. The ADC 300 converts the difference between the two analog signals V res and V sig to a digital value. The ramp signal V ramp can be generated by a ramp generator, and the clock signal CLK can be generated by a clock generator. Figure 5 The operation of the ADC 300 is shown. In this example, one analog-to-digital conversion period to convert the difference between the two analog signals V res and V sig occurs over two periods of the ramp signal V ramp .

[0096] During the first period 404 of the ramp signal V ramp , V sig is compared to the ramp signal V ramp . Based on the comparison, the counter 303 is enabled, and the counter 303 counts the counter value from an initial value INIT_VAL at the start 401 of the A / D conversion period. As long as the ramp voltage V ramp is below the signal level V sigThe increment count is enabled just after the signal level V ramp intersects the ramp voltage V sig , i.e. after time 402. The counter 303 stops counting when the clock signal CLK is inactive. Between time 402 and 402a the state machine (as described herein with respect to Figure 5 ) is active.

[0097] During the second period 405 of the ramp signal V ramp , V res is compared to the ramp signal V ramp . Based on the comparison the counter 303 is enabled and continues counting. As long as the ramp voltage V ramp is below the reset level V res the decrement count is enabled. After the ramp voltage V ramp intersects the reset level V res , i.e. after time 403, the increment count is enabled. The counter 303 stops counting when the clock signal CLK is inactive. Between time 403 and 403a the state machine (as described herein with respect to Figure 4 ) is active.

[0098] The INV signal is low during the first period of the ramp signal V ramp and high during the second period of the ramp signal V ramp . The MR signal is low during the first and second period of the ramp signal V ramp and high otherwise.

[0099] It can be seen that during the conversion the counter 303 counts both increment and decrement. The count direction is reversed during the reset conversion by inverting the comparator output 318. Figure 4 A possible "dead time" is also shown, the "dead time" is the time (or time slot) between the two conversions 404, 405 (see definition below). At this time the INV signal goes high and the clock is idle as can be seen in Figure 5 . The dead time depends on the circuit and topology details / implementation. It does not affect the counter value.

[0100] The control stage of the ADC can reverse the count direction of the counter during a conversion of one of the input signals (Vsig, Vres) without stopping the input clock (CLK). This provides the technical advantage that the reversing of the count direction of the counter has no impact on the timing of the ADC.

[0101] Reversing the count direction without stopping the input clock enables switching in a dynamic way during conversion. This enables the counter to be continuously active (on average) during conversion, which ensures a signal independent supply and ground for each individual ADC. Thus, cross-talk through the supply and ground net between parallel ADCs is avoided.

[0102] In detail, the counter is (internally) stopped twice - the first time during time 402 to 402a, and the second time during time 403 to 403a. These intervals are defined by an integer number of clock cycles during which the state machine is active. However, the total number of counts made (increment + decrement) does not depend on the input value. Thus, on average, the counter is continuously active.

[0103] Reversing the count direction means changing from a first count direction to a second count direction, or from a second count direction to a first count direction.

[0104] The control stage can be configured to reverse the count direction of the counter once during the reset conversion 404 and once during the signal conversion 405.

[0105] With respect to the conversions 404, 405 of the input signal level, it is meant the time period during which the input signal level is compared to the ramp signal (Vramp). There is a corresponding conversion 404 with respect to the reset signal (Vres), and a corresponding conversion 405 with respect to the signal conversion (Vsig). The reset conversion 404 is based on a comparison of the ramp signal to a first analog signal level (Vsig), while the signal conversion 405 is based on a comparison of the ramp signal to a second analog signal level (Vres).

[0106] For each conversion period of one input signal, there is a fixed (predetermined) number of total counts (which can be the number x of reset conversions and the number y of signal conversions according to prior art solutions), and there is a fixed (predetermined) number of counts gated by the state machine (as outlined herein with respect to Figure 4

[0107] For a first time portion of each conversion, the count direction is in one direction. For another portion of each conversion, the count direction is in the other direction. These portions can be adjacent in time, such that the other portion is a second time portion following the first time portion. In a second conversion following a first conversion, the count direction can be the same as the count direction in the second time portion of the first conversion.

[0108] In the present disclosure, the following definitions apply:

[0109] ​“Stable time”: The time required for the counter to propagate the increment to the last flip-flop. The state machine must ensure that this time has passed before freezing the counter. Does not affect the counter value;

[0110] “Counting down time”: The time after the comparator is switched and the state machine has re-enabled the counter. Depends on the value of the analog input signal. Does affect the counter value;

[0111] “Dead time”: The time between two conversions. Depends on the circuit and topology details / implementation. Does not affect the counter value.

[0112] Note that in the preferred implementation, the count does not invert between the reset conversion and the signal conversion. Rather, in this implementation, the count direction can change during the first conversion and then remain for the second conversion. Note that not inverting means negating the conversion, while inverting means adding the two conversions.

[0113] In another exemplary implementation, both values can be stored in registers, rather than keeping the counter value.

[0114] During the conversion of the signal, INV is low and the output of comparator 301 is passed to the counter (state I). At a certain point 402, Vsig and Vramp cross and comparator 301 switches, thus inverting for the first time (state II). The clock is kept running longer for a few clock cycles (until 402a as shown in Figure 4 Then, the internal clock is stopped and the ramp is reset. Comparator 301 switches again to the state it was initially in for the conversion of the signal (state I). Because the reset level needs to be subtracted, the counter needs to count down initially. Thus, the output of the comparator is inverted by the INV control (state III). The ramp and clock start, and when the ramp crosses the reset level, comparator 301 switches for the second time (state IV). And again, the ADC counts for more clock cycles until the conversion is complete. As can be seen from Figure 3 The comparator 301 switches at least twice, and the count is inverted twice. After the first comparator switch, the inverted count is kept until the second comparator switch.

[0115] The comparator 301 switches four times. The first switch is from state I to state II. The second switch refers to the reset to initial at the end of the first conversion period from state II back to state I. The third switch is from state III to state IV. The fourth switch is from state IV back to state I, and thus refers to the end of the second conversion period.

[0116] Thus, the first switch causes a first change in the configuration of the counter of the count direction (increment count -> decrement count).

[0117] The third switch during the second conversion causes a second change in the configuration of the counter (decrementing count -> incrementing count) in the direction of the count. The counter then counts to a stable state.

[0118] In addition, for the entire second (Vres) conversion time (but only one of the conversions, not the higher level conversion), the output of the comparator 301 is inverted by the control INV signal, since it is assumed that Vres is a lower value than Vsignal, and therefore, a decrementing count of the count value is required.

[0119] The conversion can be succinctly described as: increment (sig) -> decrement (sig) -> clock stops between conversions and ramp reset -> decrement (res) -> increment (res).

[0120] In a preferred implementation, as shown in Figure 4 and Figure 5 both values are converted without storing the intermediate result.

[0121] Figure 3 A block diagram of an exemplary counter circuitry 500 according to the present disclosure is shown for the ADC 300 shown in Figure 3

[0122] The counter circuitry 500 comprises a counter 510, e.g. corresponding to the incrementing / decrementing counter 303 shown in Figure 4 and state machine circuitry 520 for controlling the counter 510. The counter circuitry 500 comprises an input 532 for receiving the MR signal, e.g. as shown in Figure 4 an input 533 for receiving the clock signal CLK, e.g. as shown in Figure 3 and an input 534 for receiving the COMP OUT signal, e.g. as shown in Figure 5 An inverter 531 is used to invert the clock signal CLK to generate an inverted clock signal CLK B at another input 535.

[0123] The counter 510 is implemented by a series of flip-flops 511, e.g. JK flip-flops 511, and multiplexers 512 connected between the flip-flops 511. The respective Q output of each flip-flop implements a respective output of the counter that can form part or all of the counter value of the counter 510. In Figure 5 ​In the example shown, four flip-flops 511 are used, wherein the counter value is formed by the values of B0, B1, B2 and B3. Clock control circuitry 514 enables the clocking of the counter based on the inverted comparator output signal COMP_OUT and an output signal SM_FINISHED of state machine circuitry 520, which signals a fully settled counter state.

[0124] State machine circuitry 520 is implemented by a series of flip-flops 521, e.g. D-flip-flops 521. The Q output of each flip-flop is connected to the D input of the next flip-flop in the series, and the MR signal is applied to the R input of each flip-flop 521. The inverted comparator output signal COMP_OUT is applied to the D input of the first flip-flop 521. Clock control circuitry 523 enables the clocking of the state machine circuitry based on the inverted input clock CLK_B and the inverted comparator output signal COMP_OUT. The output signal SM_FINISHED is provided at the Q output of the last flip-flop of state machine circuitry 520 to signal a fully settled counter state.

[0125] The presented counter architecture eliminates the need for two counters and an adder in a single column ADC. The actual counter 510 can be composed of the upper flip-flops 511, i.e. as shown in the upper part of Figure 5 In the bottom part of Figure 5 , the state machine 520 can be seen. The clocking to the two parts 510, 520 can be enabled by their respective latches.

[0126] Figure 5 A preferred implementation of a counter circuitry according to the present disclosure is shown. The counter can also be referred to as a ripple counter. The ripple counter in this circuit 500 can be implemented as a counter that counts on the rising edge of the clock signal. In an alternative example, a counter that counts on the falling edge of the clock signal can also be implemented. The increment / decrement switching is configured by MUX units 512 between the counter flip-flops 511. These MUX units 512 are controlled by the “CTR_DIR” signal, which originates from the ‘counter switching’ state machine 520.

[0127] Note that in this implementation example shown in Figure 5 , the resolution of the ripple counter 500 is limited to 4 bits only. In practice, the number of bits can be larger to accommodate the desired ADC resolution.

[0128] The number of flip-flops 521 in the state machine 520 can be adjusted to the required delay (or can be designed according to the required delay) to ensure a fully stable ripple counter state before the actual counter direction switch. That is, the last transition should ripple through the entire chain of flip-flops. The required delay and number of flip-flops can be in the following relationship: when UD / COMP_OUT goes high, the input to the ripple counter 510 is frozen. The last clock pulse provided to the counter 510 needs to propagate from the input of bit 0 all the way up to bit 3. This delay is an intrinsic delay and will depend on the actual implementation (device parasitics, layout, technology, etc.). In the example shown in Figure 5 , the delay is fixed to a number of clock cycles.

[0129] In the example implementation shown in Figure 6a , the clock facing the local state machine 520 (“CLK_B”) is activated only when the clock to the counter (“CLK”) is deactivated. The clock is inverted, so in the state machine, each flip-flop 521 is clocked at the falling edge of the input clock. This inverted clocking edge is the key to obtaining two counts per ADC clock cycle. An illustration of this feature is shown in the timing diagrams 601, 602, 603 in Figure 6b , Figure 6c and Figure 6a . Note that in alternative implementations, each flip-flop 521 of the state machine circuitry can be clocked at the rising edge of the input clock.

[0130] Figure 6b , Figure 6c and Figure 3 show example timing diagrams 601, 602, 603 showing the 2x count per clock cycle operation of the ADC 300 shown in Figure 5 and the counter circuitry 500 implementation shown in Figure 6a , where the comparator switches after 2.5 clock cycles ( Figure 6b ), after 3.0 clock cycles ( Figure 6c ) and after 3.5 clock cycles ( Figure 6a ). The timing diagrams 601, 602, 603 show the 2x count per clock cycle operation.

[0131] Figure 6b , Figure 6c , Figure 5 show three timing diagrams 601, 602, 603 where the switching of the comparator 301 is shifted by 0.5 clock periods for each case. For example, using a 4-bit counter, for example having outputs B0, B1, B2, B3 as shown in Figure 6aThe reset condition is set to the middle column, which is set by the specific connection of "MR". A pulse of "MR" low (or " / MR" high) resets both the state machine 520 and the counter 510. "SM_FINISHED" will be set to 0, disabling the clock to the state machine until "COMP_OUT" goes high. On the other hand, a low value of "SM_FINISHED" enables the clock to the counter.

[0132] In Figure 6a the timing diagram 601 shown in Figure 6b the right side of

[0133] In Figure 6a the timing diagram 602 shown in Figure 6c the timing diagram 601 shown in

[0134] In ​ the timing diagram 603 shown in

[0135] These examples clearly show that the circuit 500 produces 2 ADC counts per clock cycle because the output code is increased by 1 every 0.5 clock cycles.

[0136] In an example implementation, the "COMP OUT" signal is also inverted when the reset value is converted. This is necessary because the reset signal is subtracted from the signal level. In another example implementation, synchronization is implemented between the clock and other control signals or the comparator output ("COMP OUT"). In another implementation, the counter overflow is properly handled and / or detected.

[0137] While specific features or aspects of the disclosure can be disclosed relative to only one or a few implementations, each feature or aspect can be combined with any or all other implementations, if that is desired, based on their relevance. Furthermore, to the extent that the terms "includes", "containing", "having", or other variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term "comprising." Additionally, the terms "exemplary", "for example", and "e.g." are merely meant for

[0138] Although specific aspects have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement, which is functionally equivalent to those

[0139] Although the elements in the claims have been presented in a specific sequence, people having ordinary skill in the art will recognize that certain configurations can be implemented where such specific ordering is not employed. Thus, the disclosures are not intended to be limited to the specifics of any implementation example described.

[0140] In light of the teachings above, those of skill in the art will appreciate the various adaptations and modifications of the specific implementations described. It is intended that each of these implementations can be used as alternatives to the specific implementations described. Indeed, this disclosure is intended to cover all adaptations and modifications of the specific implementations described. It is intended that each of the implementations described herein can be implemented independently of any other implementations. It is intended that each of the implementations can be implemented independently of any other implementation or implementation described herein. Many alternatives, modifications, and variations will be apparent to those of ordinary skill in the art without departing from the scope of the application. The references cited herein are incorporated by reference in their entirety.

Claims

1. An analog-to-digital converter (300), ADC, for implementing a calculation of a difference between a first analog signal level (Vsig) and a second analog signal level (Vres), the ADC (300) comprising: at least one input (311) for receiving an input signal, the input signal comprising one of the first analog signal level (Vsig) and the second analog signal level (Vres); an input (310) for receiving a ramp signal (Vramp); an input (313) for receiving an input clock (CLK); a counter (303) configurable to count in a count direction, the count direction being either one of a first count direction and a second count direction; a comparator (301) configured to generate a comparator output signal based on a comparison of the ramp signal (Vramp) and the input signal; and a control stage configured to enable the counter (303) to count in the first count direction based on the comparator output signal and to enable the counter (303) to count in the second count direction based on an inversion of the comparator output signal, wherein the control stage is configured to invert the count direction of the counter (303) during a conversion of one of the input signals without stopping the input clock (CLK) by gating a local clock signal for a known number of clock pulses when the count direction of the counter (303) is switched between the first count direction and the second count direction.

2. The ADC (300) according to claim 1, the counter (303, 510) comprising a plurality of flip-flops (511), in particular JK flip-flops or T flip-flops, connected in series. wherein, 3. The ADC (300) according to claim 2, the counter (303, 510) comprising a plurality of multiplexer units (512), each multiplexer unit (512) being connected between an output and an input of two consecutive flip-flops (511) of the counter (510), wherein wherein the control stage is configured to invert the count direction of the counter (510) by switching the multiplexer units (512) between the flip-flops (511).

4. The ADC (300) according to claim 3, the control stage being configured to let a last clock cycle of the input clock (CLK) pass completely through the counter (510) before switching the multiplexer units (512). wherein 5. The ADC (300) according to one of the preceding claims, comprising: a state machine circuitry (520) consisting of a plurality of flip-flops (521) connected in series.

6. The ADC (300) according to claim 5, the control stage being configured to trigger the state machine circuitry (520) based on an inversion of the comparator output signal. wherein 7. The ADC (300) according to claim 5, ​ wherein, The number of flip-flops (521) of the state machine circuitry (520) is predetermined according to a delay with respect to a stable counter state before reversal in the counting direction.

8. The ADC (300) of claim 5, wherein The counter (303) comprises clock control circuitry (514) configured to enable clocking of the counter (510) based on a reversal of the comparator output signal and an output signal (SM FINISHED) of the state machine circuitry (520), the output signal of the state machine circuitry signaling a stable counter state.

9. The ADC (300) of claim 5, comprises an input for receiving a reversed input clock (CLK B), the reversed input clock being reversed by an inverter, corresponding to the input clock (CLK).

10. The ADC (300) of claim 9, wherein The state machine circuitry (520) comprises clock control circuitry (523) to enable clocking of the state machine circuitry (520) based on the reversed input clock (CLK B) or based on the input clock (CLK).

11. The ADC (300) of claim 9, wherein The control stage is configured to: deactivate clocking of the counter (303, 510) by the input clock (CLK) based on a reversal of the comparator output signal; and activate clocking of the state machine circuitry (520) by the reversed input clock (CLK B) when clocking of the counter is deactivated by the input clock (CLK).

12. The ADC (300) of claim 5, wherein The counter (303, 510) is configured to perform a count twice per clock cycle of the input clock (CLK).

13. The ADC (300) of claim 5, configured to clock the counter (303, 510) on one edge of the input clock (CLK) and to clock the state machine circuitry (520) on another edge of the input clock (CLK).

14. The ADC (300) of any one of claims 1 to 4, wherein The ADC (300) uses only a single counter to count in either of the first and second counting directions.

15. The ADC (300) of claim 5, wherein The counter (303, 510) is increment / decrement reversible based on the comparator output signal, responsive to a direction control signal from the state machine circuitry (520).

16. The ADC (300) of any one of claims 1 to 4, configured to implement the calculation of the difference between the first analog signal level (Vsig) and the second analog signal level (Vres) without using a summer.

17. The ADC (300) of any one of claims 1 to 4, wherein The control stage is configured to invert the comparator output signal in response to an inversion control signal only for conversion of one of the input signals, and to provide the thus inverted comparator output signal to the counter (303, 510).

18. The ADC (300) according to any one of claims 1 to 4, wherein The counting direction is changed during a first conversion of one of the input signals, and then remains within a second conversion of one of the input signals.

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