Binary Instruction Translation and Execution Method and Device

Abstract

The present invention provides a binary instruction translation and execution method and apparatus, including: according to the flag bit information sent by the CPU to a preset instruction unit, reading a target flag bit corresponding to a target X86 instruction from the flag bit information; in the case where it is determined that the target flag bit is not empty, sending a first interrupt signal to the CPU, so that after receiving the first interrupt signal, the CPU reads and executes an ARM instruction set corresponding to the target X86 instruction from the preset instruction unit; the preset instruction unit stores the ARM instruction set. The present invention can effectively avoid the defect in the prior art that frequently called binary instructions need to be repeatedly translated, resulting in waste of system memory resources, and greatly improves the efficiency of binary translation and execution of X86 instructions to ARM instructions.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and particularly to a binary instruction translation and execution method and apparatus. Background Art

[0002] Due to the obvious platform differences of computer devices for various different applications, the requirement for interoperability between computer systems is also getting higher and higher. Software is required to be portable and run on different machines. However, the workload of redeveloping code is huge, which will cause waste of various resources and still need to solve the software compatibility problem. In view of the above problems, the existing conventional solution is to adopt binary instruction translation technology to directly transplant the application program from the original platform to the new hardware platform to enhance the portability and interoperability between heterogeneous processors.

[0003] However, in the binary translation technology from X86 instructions to ARM instructions, there are some binary instruction functions or instruction codes that are frequently called by the system, and the system needs to perform multiple repeated translations on these instruction functions or codes, which will inevitably cause waste of a large amount of memory resources in the system, and the efficiency of binary instruction translation and execution by the system needs to be improved.

[0004] Therefore, how to improve the efficiency of binary instruction translation and execution in the binary translation from X86 instructions to ARM instructions has become an urgent problem to be solved in the industry. Summary of the Invention

[0005] The present invention provides a binary instruction translation and execution method and apparatus to solve the defect of memory resource waste in the binary translation from X86 instructions to ARM instructions in the prior art, and to improve the efficiency of binary instruction translation and execution in the binary translation from X86 instructions to ARM instructions, which has become an urgent need in the industry.

[0006] The present invention provides a binary instruction translation and execution method, including:

[0007] According to the flag bit information sent by the CPU to the preset instruction unit, read the target flag bit corresponding to the target X86 instruction from the flag bit information;

[0008] When it is determined that the target flag bit is not empty, send a first interrupt signal to the CPU, so that after receiving the first interrupt signal, the CPU reads and executes the ARM instruction set corresponding to the target X86 instruction from the preset instruction unit; the ARM instruction set is stored in the preset instruction unit.

[0009] A binary instruction translation and execution method provided by the present invention, after reading the target flag bit corresponding to the target X86 instruction from the flag bit information, further includes:

[0010] When it is determined that the target flag bit is empty, read the target X86 instruction according to the storage address of the target X86 instruction, and translate the target X86 instruction to generate an ARM instruction set corresponding to the target X86 instruction;

[0011] Store the ARM instruction set into the preset instruction unit, and send a second interrupt signal to the CPU, so that after the CPU receives the second interrupt signal, execute each ARM instruction in the ARM instruction set, and set the target flag bit to non-empty.

[0012] A binary instruction translation and execution method provided by the present invention, when it is determined that the target flag bit is empty, read the target X86 instruction according to the storage address of the target X86 instruction, and translate the target X86 instruction to generate an ARM instruction set corresponding to the target X86 instruction, including:

[0013] When it is determined that the target flag bit is empty, call the first bus interface to read the target X86 instruction from the storage address of the target X86 instruction, and store the target X86 instruction into the first cache queue;

[0014] Call the decoder to read and translate the target X86 instruction from the first cache queue to generate an ARM instruction set corresponding to the target X86 instruction.

[0015] A binary instruction translation and execution method provided by the present invention, after generating the ARM instruction set corresponding to the target X86 instruction, further includes:

[0016] Call the decoder, calculate the storage address of the ARM instruction set according to the starting storage address of the ARM instruction sent by the CPU, and store the ARM instruction set and the storage address of the ARM instruction set into the second cache queue;

[0017] Call the second bus interface, read the ARM instruction set and the storage address of the ARM instruction set from the second cache queue, and store the ARM instruction set into the preset instruction unit according to the storage address of the ARM instruction set.

[0018] A binary instruction translation and execution method provided by the present invention, before reading the target flag bit corresponding to the target X86 instruction from the flag bit information according to the flag bit information sent by the CPU to the preset instruction unit, further includes:

[0019] The call signal transmission sub-module is used to receive the storage address of the target X86 instruction sent by the CPU, the flag bit information of the preset instruction unit, and the starting storage address of the ARM instruction.

[0020] The present invention also provides a binary instruction translation and execution device, including:

[0021] A first reading module, configured to read the target flag bit corresponding to the target X86 instruction from the flag bit information according to the flag bit information of the preset instruction unit sent by the CPU;

[0022] A first execution module, configured to send a first interrupt signal to the CPU when it is determined that the target flag bit is non-empty, so that after the CPU receives the first interrupt signal, it reads and executes the ARM instruction set corresponding to the target X86 instruction from the preset instruction unit; the ARM instruction set is stored in the preset instruction unit.

[0023] According to a binary instruction translation and execution device provided by the present invention, the device further includes:

[0024] A first translation module, configured to read the target X86 instruction according to the storage address of the target X86 instruction and translate the target X86 instruction to generate the ARM instruction set corresponding to the target X86 instruction when it is determined that the target flag bit is empty;

[0025] A second execution module, configured to store the ARM instruction set into the preset instruction unit and send a second interrupt signal to the CPU, so that after the CPU receives the second interrupt signal, it executes each ARM instruction in the ARM instruction set and sets the target flag bit to non-empty.

[0026] According to a binary instruction translation and execution device provided by the present invention, the first translation module includes:

[0027] A first processing sub-module, configured to call a first bus interface to read the target X86 instruction from the storage address of the target X86 instruction and store the target X86 instruction into a first cache queue when it is determined that the target flag bit is empty;

[0028] A first translation sub-module, configured to call a decoder to read and translate the target X86 instruction from the first cache queue to generate the ARM instruction set corresponding to the target X86 instruction.

[0029] According to a binary instruction translation and execution device provided by the present invention, the device further includes:

[0030] The first call module is used to call the decoder, calculate the storage address of the ARM instruction set according to the starting storage address of the ARM instruction sent by the CPU, and store the ARM instruction set and the storage address of the ARM instruction set into the second cache queue;

[0031] The second call module is used to call the second bus interface, read the ARM instruction set and the storage address of the ARM instruction set from the second cache queue, and store the ARM instruction set into the preset instruction unit according to the storage address of the ARM instruction set.

[0032] A binary instruction translation and execution device according to the present invention, the device further includes:

[0033] The third call module is used to call the signal transmission sub-module to receive the storage address of the target X86 instruction sent by the CPU, the flag bit information of the preset instruction unit, and the starting storage address of the ARM instruction. The present invention also provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, it implements the binary instruction translation and execution method as described in any one of the above.

[0034] The present invention also provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements the binary instruction translation and execution method as described in any one of the above.

[0035] The present invention also provides a computer program product, including a computer program. When the computer program is executed by a processor, it implements the binary instruction translation and execution method as described in any one of the above.

[0036] A binary instruction translation and execution method and device provided by the present invention, by setting a preset instruction unit, which is used to store the ARM instruction set after each target X86 instruction is translated, and determining whether the translated ARM instruction set has been stored according to its flag bit information. Thus, the target flag bit corresponding to the target X86 instruction can be read from the flag bit information according to the flag bit information of the preset instruction unit sent by the CPU; thereby, when it is determined that the target flag bit is not empty and the preset instruction unit has stored the ARM instruction set corresponding to each target X86 instruction, a first interrupt signal is sent to the CPU. After the CPU receives the first interrupt signal, the ARM instruction set corresponding to each target X86 instruction can be directly called and executed from the preset instruction unit according to the target flag bit, which can effectively avoid the defect that the binary instructions frequently called in the prior art need to be repeatedly translated, resulting in waste of system memory resources, and greatly improve the efficiency of binary translation and execution of X86 instructions to ARM instructions. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] To more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the accompanying drawings required for the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can also be obtained based on these drawings.

[0038] Figure 1 Flow chart of the binary instruction translation and execution method provided by the present invention;

[0039] Figure 2 Structural diagram of the binary instruction translation and execution device provided by the present invention;

[0040] Figure 3 Entity structure diagram of the electronic device provided by the present invention. Detailed implementation manners

[0041] To make the objectives, technical solutions, and advantages of the present invention clearer, the following will clearly and completely describe the technical solutions in the present invention in conjunction with the accompanying drawings in the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art without creative efforts based on the embodiments in the present invention belong to the scope of protection of the present invention.

[0042] The following combines Figures 1 - 3 to describe the binary instruction translation and execution method and device of the present invention.

[0043] Figure 1 is the flow chart of the binary instruction translation and execution method provided by the present invention. As Figure 1 shown, it includes:

[0044] Step 110, according to the flag bit information sent by the CPU to the preset instruction unit, read the target flag bit corresponding to the target X86 instruction from the flag bit information;

[0045] Specifically, the target X86 instruction described in the embodiments of the present invention refers to an instruction that is frequently called in the system X86 instruction set, such as an instruction composed of the general instruction "move instruction" or a floating-point operation instruction with a high usage frequency.

[0046] The preset instruction unit described in the embodiments of the present invention refers to a preset storage unit, which is used to store ARM instructions translated from multiple target X86 instructions.

[0047] Optionally, in an embodiment of the present invention, since the size of the storage unit memory is limited, there will definitely be a situation where the cache is full. Therefore, the system can maintain an instruction unit replacement policy, such as using a first-in, first-out (FIFO) storage method, that is, the first-entered instruction will be cleared first to make room for the next instruction unit.

[0048] The flag bit information described in the embodiments of the present invention refers to the status information of the flag register group set for a preset instruction unit, which may include multiple flag bits, respectively corresponding to different target X86 instructions, and can be used to represent whether the ARM instructions corresponding to all target X86 instructions have been stored in the preset instruction unit.

[0049] The target flag bit described in the embodiments of the present invention refers to the flag bits corresponding to multiple target X86 instructions in the flag bit information, which is used to represent whether the ARM instructions corresponding to multiple target X86 instructions have been stored in the preset instruction unit.

[0050] In an embodiment of the present invention, it is possible to determine whether the ARM instruction corresponding to each target X86 instruction has been stored in the preset instruction unit by setting the flag bit information to be empty or non-empty. For example, if the target flag bit is non-empty, it means that the ARM instruction corresponding to the target X86 instruction has been stored in the preset instruction unit; otherwise, it means that the target X86 instruction has not been translated and the ARM instruction set corresponding to the target X86 instruction is not stored in the preset instruction unit.

[0051] Furthermore, according to the flag bit information of the preset instruction unit sent by the CPU, the target flag bit corresponding to the target X86 instruction can be read from the flag bit information;

[0052] Based on the content of the above embodiments, as an optional embodiment,

[0053] Before reading the target flag bit corresponding to the target X86 instruction from the flag bit information according to the flag bit information of the preset instruction unit sent by the CPU, it further includes:

[0054] Call the signal transmission sub-module to receive the storage address of the target X86 instruction, the flag bit information of the preset instruction unit, and the starting storage address of the ARM instruction sent by the CPU.

[0055] It should be noted that in the embodiments of the present invention, the AMBA (Advanced Microcontroller Bus Architecture) on-chip bus standard is adopted in the ARM system, which includes an AHB (Advanced High-performance Bus) high-speed bus part for realizing communication between the processor and high-speed devices.

[0056] Specifically, in an embodiment of the present invention, before starting the translation of X86 instructions into ARM instructions, it is necessary to call the signal transmission (Communicate) sub-module to communicate with the CPU. The Communicate sub-module, as an AHB bus slave module, is responsible for receiving the control signals of the CPU and transmitting the corresponding signals in the control signals to other module parts.

[0057] The method of the embodiment of the present invention, by introducing a signal transmission sub-module, which is used to communicate with the CPU and transfer the control signals sent by the CPU, so as to control the orderly operation of each module for binary translation, is beneficial to improving the stability and efficiency of the execution of the binary instruction translation process.

[0058] Step 120, when it is determined that the target flag bit is non-empty, send a first interrupt signal to the CPU, so that after the CPU receives the first interrupt signal, read and execute the ARM instruction set corresponding to the target X86 instruction from the preset instruction unit; the preset instruction unit stores the ARM instruction set.

[0059] Specifically, the first interrupt signal described in the embodiment of the present invention refers to an interrupt signal indicating that the ARM instruction set corresponding to the target X86 instruction has been translated when it is determined that the target flag bit is non-empty.

[0060] It should be noted that due to the different architectures of the X86 processor and the ARM processor, binary translation requires a corresponding relationship between the addresses of the two types of instructions. Otherwise, when encountering an X86 jump instruction, it will be impossible to calculate the destination address to which the ARM instruction should jump. Therefore, there is a corresponding relationship between the instruction addresses of the two.

[0061] In an embodiment of the present invention, before translating instructions, it is necessary to consider that generally X86 instructions have complex functions and are variable-length instructions, and there may be situations where one X86 instruction corresponds to multiple ARM instructions. For the above problems, the 1-bit space of the X86 instruction can correspond to the 4-bit space of the ARM instruction. Thus, when translating the target X86 instruction, the corresponding ARM instruction set is obtained.

[0062] Further, in the embodiments of the present invention, when it is determined that the target flag bit is non-empty, a first interrupt signal is sent to the CPU. After the CPU receives the first interrupt signal, it is determined that the ARM instruction set corresponding to the target X86 instruction has been translated, and it is determined that the preset instruction unit has stored the ARM instruction set corresponding to the target X86 instruction. Thus, according to the address mapping relationship between the target flag bit and the ARM instruction set corresponding to the target X86 instruction in the preset instruction unit, the ARM instruction set corresponding to each target X86 instruction can be read and executed from the preset instruction unit.

[0063] The binary instruction translation and execution method of the embodiments of the present invention. The present invention provides a binary instruction translation and execution method and device. By setting a preset instruction unit, which is used to store the ARM instruction set after each target X86 instruction is translated, and according to its flag bit information, it is determined whether the translated ARM instruction set has been stored. Thus, the target flag bit corresponding to the target X86 instruction can be read from the flag bit information sent by the CPU; thus, when it is determined that the target flag bit is non-empty and it is determined that the preset instruction unit has stored the ARM instruction set corresponding to each target X86 instruction, a first interrupt signal is sent to the CPU. After the CPU receives the first interrupt signal, each ARM instruction set corresponding to the target X86 instruction can be directly called and executed from the preset instruction unit according to the target flag bit, which can effectively avoid the defect that the binary instructions frequently called in the prior art need to be repeatedly translated, resulting in waste of system memory resources, and greatly improve the efficiency of binary translation and execution of X86 instructions to ARM instructions.

[0064] Based on the content of the above embodiments, as an optional embodiment, after reading the target flag bit corresponding to the target X86 instruction from the flag bit information, it further includes:

[0065] When it is determined that the target flag bit is empty, the target X86 instruction is read according to the storage address of the target X86 instruction, and the target X86 instruction is translated to generate the ARM instruction set corresponding to the target X86 instruction;

[0066] The ARM instruction set is stored in the preset instruction unit, and a second interrupt signal is sent to the CPU. After the CPU receives the second interrupt signal, each ARM instruction in the ARM instruction set is executed, and the target flag bit is set to non-empty.

[0067] Specifically, the storage address of the target X86 instruction described in the embodiments of the present invention refers to the physical address where the target X86 instruction is stored in the off-chip ROM memory.

[0068] The second interrupt signal described in the embodiments of the present invention refers to an interrupt signal that characterizes that the ARM instruction set corresponding to the target X86 instruction has been translated when it is determined that the target flag bit is empty, and is used to determine whether the current instruction decoding thread has ended.

[0069] Further, when it is determined that the target flag bit is empty, it is determined that the target X86 instruction has not been translated. Thus, the target X86 instruction can be read from off-chip according to the storage address of the target X86 instruction, and the target X86 instruction can be translated to generate the ARM instruction set corresponding to the target X86 instruction.

[0070] Based on the content of the above embodiments, as an alternative embodiment, when it is determined that the target flag bit is empty, reading the target X86 instruction according to the storage address of the target X86 instruction and translating the target X86 instruction to generate the ARM instruction set corresponding to the target X86 instruction includes:

[0071] When it is determined that the target flag bit is empty, call the first bus interface to read the target X86 instruction from the storage address of the target X86 instruction, and store the target X86 instruction in the first cache queue;

[0072] Call the decoder to read and translate the target X86 instruction from the first cache queue to generate the ARM instruction set corresponding to the target X86 instruction.

[0073] Specifically, the first bus interface described in the embodiments of the present invention serves as an AHB bus master interface, which is responsible for reading each target X86 instruction from off-chip storage.

[0074] The decoder Decoder described in the embodiments of the present invention refers to a module used to perform translation operations and address calculations on the target X86 instruction, and its output is the ARM instruction set corresponding to the target X86 instruction and the storage address of the generated ARM instruction set.

[0075] The first cache queue described in the embodiments of the present invention refers to a queue used to store multiple target X86 instructions read by the first bus interface, facilitating subsequent reading and translation of the target X86 instruction by the decoder.

[0076] In the embodiments of the present invention, the first cache queue can adopt a FIFO queue. When the FIFO queue is not full, the first bus interface can always read the target X86 instruction from off-chip storage and store these target X86 instructions and instruction addresses into the FIFO queue at the same time until the target X86 instruction ends.

[0077] Further, in this embodiment, when it is determined that the target flag bit is empty, the first bus interface can be called to read the target X86 instruction based on the storage address of the target X86 instruction and store the target X86 instruction in the first cache queue; then, by calling the decoder, the target X86 instruction can be read and translated from the first cache queue, and the ARM instruction set corresponding to the target X86 instruction can be generated.

[0078] In the embodiment of the present invention, through the first bus interface and the first cache queue set inside the system, when translating the target X86 instruction, the first bus interface can be called to read the target X86 instruction from outside the chip. By storing the target X86 instruction through the first cache queue, it is convenient for the decoder to read and translate the target X86 instruction, and the transplantation of the application program based on the target X86 instruction to the ARM architecture can be effectively realized.

[0079] Based on the content of the above embodiment, as an optional embodiment, after generating the ARM instruction set corresponding to the target X86 instruction, it further includes:

[0080] Call the decoder to calculate the storage address of the ARM instruction set according to the starting storage address of the ARM instruction sent by the CPU, and store the ARM instruction set and the storage address of the ARM instruction set in the second cache queue;

[0081] Call the second bus interface to read the ARM instruction set and the storage address of the ARM instruction set from the second cache queue, and store the ARM instruction set in the preset instruction unit according to the storage address of the ARM instruction set.

[0082] Specifically, the starting storage address of the ARM instruction described in the embodiment of the present invention refers to the starting storage address allocated by the CPU for the ARM instructions translated from multiple target X86 instructions, which specifically refers to the starting storage address of these ARM instructions in the preset instruction unit.

[0083] The second cache queue described in the embodiment of the present invention refers to the queue used to store the ARM instruction set translated from the target X86 instruction and the storage address of the ARM instruction set. Specifically, it can adopt a FIFO queue.

[0084] The second bus interface described in the embodiment of the present invention, as another master of the AHB bus, is used to read each ARM instruction and the address of each ARM instruction in the ARM instruction set from the second cache queue, and store each ARM instruction in the preset instruction unit.

[0085] In an embodiment of the present invention, by invoking a decoder, according to the starting storage address of the ARM instruction sent by the CPU, in combination with the mapping relationship between the target X86 instruction address and the translated multiple ARM instruction addresses, the storage address of the ARM instruction set is calculated, and the ARM instruction set and the storage address of the ARM instruction set are stored in the second cache queue;

[0086] Further, by invoking the second bus interface, the ARM instruction set and the storage address of the ARM instruction set can be read from the second cache queue, and according to the storage address of the ARM instruction set, the ARM instruction set is stored in a preset instruction unit;

[0087] Further, in an embodiment of the present invention, by invoking the second bus interface, a second interrupt signal can also be sent to the CPU to notify the CPU that the current instruction decoding thread has ended.

[0088] In an embodiment of the present invention, through the second bus interface and the second cache queue set inside the system, after the translation of the target X86 instruction is completed, the decoder can store the generated ARM instruction set in the second cache queue, facilitating the invocation of the second bus interface to read each ARM instruction and the address of each ARM instruction in the ARM instruction set, and then each ARM instruction can be stored in a preset instruction unit, which can effectively store the generated ARM instruction set, facilitating the subsequent system to directly call the ARM instruction set from the preset instruction unit, and can effectively avoid the defect that the binary instructions frequently called in the prior art need to be repeatedly translated, resulting in waste of system memory resources.

[0089] Further, after storing the ARM instruction set corresponding to the target X86 instruction in the preset instruction unit, a second interrupt signal is sent to the CPU, so that after the CPU receives the second interrupt signal, it executes the ARM instruction set corresponding to the target X86 instruction and sets the target flag to non-empty to realize the direct call of the ARM instruction set generated by the next translation of the target X86 instruction.

[0090] The method of the embodiment of the present invention, by translating the target X86 instruction to generate the corresponding ARM instruction set when it is determined that the target flag is empty, storing the ARM instruction set in a preset instruction unit, and sending a second interrupt signal to the CPU, so that after the CPU receives the second interrupt signal, it executes the ARM instruction set corresponding to the target X86 instruction and sets the target flag to non-empty, can effectively realize the direct call of the ARM instruction set generated by the translation of the target X86 instruction, which is beneficial to improving the efficiency of binary translation and execution of X86 instructions to ARM instructions.

[0091] The binary instruction translation and execution device provided by the present invention will be described below. The binary instruction translation and execution device described below can be correspondingly referred to the binary instruction translation and execution method described above.

[0092] Figure 2 It is a schematic structural diagram of the binary instruction translation and execution device provided by the present invention. As Figure 2 shown, it includes:

[0093] A first reading module 210, configured to read a target flag bit corresponding to a target X86 instruction from the flag bit information according to the flag bit information of a preset instruction unit sent by the CPU;

[0094] A first execution module 220, configured to send a first interrupt signal to the CPU when it is determined that the target flag bit is not empty, so that after the CPU receives the first interrupt signal, it reads and executes the ARM instruction set corresponding to the target X86 instruction from the preset instruction unit; the ARM instruction set is stored in the preset instruction unit.

[0095] Optionally, the device further includes:

[0096] A first translation module, configured to read the target X86 instruction according to the storage address of the target X86 instruction when it is determined that the target flag bit is empty, and translate the target X86 instruction to generate the ARM instruction set corresponding to the target X86 instruction;

[0097] A second execution module, configured to store the ARM instruction set into the preset instruction unit, and send a second interrupt signal to the CPU, so that after the CPU receives the second interrupt signal, it executes each ARM instruction in the ARM instruction set and sets the target flag bit to non-empty.

[0098] Optionally, the first translation module includes:

[0099] A first processing sub-module, configured to call a first bus interface to read the target X86 instruction from the storage address of the target X86 instruction when it is determined that the target flag bit is empty, and store the target X86 instruction into a first cache queue;

[0100] A first translation sub-module, configured to call a decoder to read and translate the target X86 instruction from the first cache queue to generate the ARM instruction set corresponding to the target X86 instruction.

[0101] Optionally, the device further includes:

[0102] The first calling module is used to call the decoder, calculate the storage address of the ARM instruction set according to the starting storage address of the ARM instruction sent by the CPU, and store the ARM instruction set and the storage address of the ARM instruction set into the second cache queue;

[0103] The second calling module is used to call the second bus interface, read the ARM instruction set and the storage address of the ARM instruction set from the second cache queue, and store the ARM instruction set into the preset instruction unit according to the storage address of the ARM instruction set.

[0104] Optionally, the device further includes:

[0105] The third calling module is used to call the signal transmission sub-module to receive the storage address of the target X86 instruction sent by the CPU, the flag bit information of the preset instruction unit, and the starting storage address of the ARM instruction.

[0106] The binary instruction translation and execution device described in this embodiment can be used to execute the binary instruction translation and execution method embodiment above. The principle and technical effect are similar and will not be elaborated here.

[0107] The binary instruction translation and execution device of the embodiment of the present invention, a binary instruction translation and execution method and device provided by the present invention, by setting a preset instruction unit, which is used to store the ARM instruction set after translation of each target X86 instruction, and determine whether the translated ARM instruction set has been stored according to its flag bit information. Thus, the target flag bit corresponding to the target X86 instruction can be read from the flag bit information according to the flag bit information of the preset instruction unit sent by the CPU; thereby, when it is determined that the target flag bit is not empty and the preset instruction unit has stored the ARM instruction set corresponding to each target X86 instruction, a first interrupt signal is sent to the CPU, so that after the CPU receives the first interrupt signal, the ARM instruction set corresponding to each target X86 instruction can be directly called and executed from the preset instruction unit according to the target flag bit, which can effectively avoid the defect that the binary instructions frequently called in the prior art need to be repeatedly translated, resulting in waste of system memory resources, and greatly improve the efficiency of binary translation and execution of X86 instructions to ARM instructions.

[0108] Figure 3 It is a schematic diagram of the physical structure of the electronic device provided by the present invention, as Figure 3As shown, the electronic device may include: a processor 310, a communications interface 320, a memory 330, and a communication bus 340. Among them, the processor 310, the communications interface 320, and the memory 330 communicate with each other through the communication bus 340. The processor 310 can call the logical instructions in the memory 330 to execute the binary instruction translation execution method provided by each of the above methods. The method includes: according to the flag bit information sent by the CPU to the preset instruction unit, reading the target flag bit corresponding to the target X86 instruction from the flag bit information;

[0109] When it is determined that the target flag bit is non-empty, a first interrupt signal is sent to the CPU, so that after the CPU receives the first interrupt signal, the ARM instruction set corresponding to the target X86 instruction is read and executed from the preset instruction unit according to the target flag bit; the ARM instruction set is stored in the preset instruction unit.

[0110] In addition, when the logical instructions in the above-mentioned memory 330 are implemented in the form of software function modules and sold or used as an independent product, they can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The foregoing storage medium includes: various media such as a USB flash drive, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk, or an optical disc that can store program codes.

[0111] On the other hand, the present invention also provides a computer program product. The computer program product includes a computer program. The computer program can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the binary instruction translation execution method provided by each of the above methods. The method includes: according to the flag bit information sent by the CPU to the preset instruction unit, reading the target flag bit corresponding to the target X86 instruction from the flag bit information; when it is determined that the target flag bit is non-empty, a first interrupt signal is sent to the CPU, so that after the CPU receives the first interrupt signal, the ARM instruction set corresponding to the target X86 instruction is read and executed from the preset instruction unit according to the target flag bit; the ARM instruction set is stored in the preset instruction unit.

[0112] In another aspect, the present invention also provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements a binary instruction translation execution method provided by the above-mentioned various methods. The method includes: according to the flag bit information sent by the CPU to a preset instruction unit, reading a target flag bit corresponding to a target X86 instruction from the flag bit information; in the case of determining that the target flag bit is not empty, sending a first interrupt signal to the CPU, so that after the CPU receives the first interrupt signal, reading and executing an ARM instruction set corresponding to the target X86 instruction from the preset instruction unit according to the target flag bit; the preset instruction unit stores the ARM instruction set.

[0113] The device embodiments described above are merely illustrative. The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed to multiple network modules. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art can understand and implement it without creative labor.

[0114] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the essence of the above technical solution, or the part that contributes to the prior art, can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0115] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A binary instruction translation and execution method, characterized in that, It includes: According to the flag bit information sent by the CPU to the preset instruction unit, read the target flag bit corresponding to the target X86 instruction from the flag bit information; When it is determined that the target flag bit is not empty, send a first interrupt signal to the CPU, so that after the CPU receives the first interrupt signal, read and execute the ARM instruction set corresponding to the target X86 instruction from the preset instruction unit according to the target flag bit; the ARM instruction set is stored in the preset instruction unit; Wherein, after reading the target flag bit corresponding to the target X86 instruction from the flag bit information, it further includes: When it is determined that the target flag bit is empty, read the target X86 instruction according to the storage address of the target X86 instruction, and translate the target X86 instruction to generate the ARM instruction set corresponding to the target X86 instruction; Store the ARM instruction set into the preset instruction unit, and send a second interrupt signal to the CPU, so that after the CPU receives the second interrupt signal, execute each ARM instruction in the ARM instruction set and set the target flag bit to non-empty.

2. The binary instruction translation and execution method according to claim 1, wherein When it is determined that the target flag bit is empty, reading the target X86 instruction according to the storage address of the target X86 instruction and translating the target X86 instruction to generate the ARM instruction set corresponding to the target X86 instruction includes: When it is determined that the target flag bit is empty, call the first bus interface to read the target X86 instruction from the storage address of the target X86 instruction and store the target X86 instruction into the first cache queue; Call the decoder to read and translate the target X86 instruction from the first cache queue to generate the ARM instruction set corresponding to the target X86 instruction.

3. The binary instruction translation and execution method according to claim 2, characterized in that After generating the ARM instruction set corresponding to the target X86 instruction, it further includes: Call the decoder, calculate the storage address of the ARM instruction set according to the starting storage address of the ARM instruction sent by the CPU, and store the ARM instruction set and the storage address of the ARM instruction set into the second cache queue; Call the second bus interface, read the ARM instruction set and the storage address of the ARM instruction set from the second cache queue, and store the ARM instruction set into the preset instruction unit according to the storage address of the ARM instruction set.

4. The binary instruction translation and execution method according to any one of claims 1-3, characterized in that, Before reading the target flag bit corresponding to the target X86 instruction from the flag bit information sent by the CPU to the preset instruction unit, it further includes: Call the signal transmission sub-module to receive the storage address of the target X86 instruction, the flag bit information of the preset instruction unit and the starting storage address of the ARM instruction sent by the CPU.

5. A binary instruction translation and execution device, characterized in that, It includes: The first reading module is used to read the target flag bit corresponding to the target X86 instruction from the flag bit information according to the flag bit information sent by the CPU to the preset instruction unit; A first execution module, configured to send a first interrupt signal to the CPU when it is determined that the target flag bit is non-empty, so that after receiving the first interrupt signal, the CPU reads and executes the ARM instruction set corresponding to the target X86 instruction from the preset instruction unit according to the target flag bit; The preset instruction unit stores the ARM instruction set; The device further includes: A first translation module, configured to read the target X86 instruction according to the storage address of the target X86 instruction and translate the target X86 instruction to generate the ARM instruction set corresponding to the target X86 instruction when it is determined that the target flag bit is empty; A second execution module, configured to store the ARM instruction set into the preset instruction unit and send a second interrupt signal to the CPU, so that after receiving the second interrupt signal, the CPU executes each ARM instruction in the ARM instruction set and sets the target flag bit to non-empty.

6. The binary instruction translation and execution device according to claim 5, characterized in that The first translation module includes: A first processing sub-module, configured to read the target X86 instruction from the storage address of the target X86 instruction by calling a first bus interface and store the target X86 instruction into a first cache queue when it is determined that the target flag bit is empty; A first translation sub-module, configured to read and translate the target X86 instruction from the first cache queue by calling a decoder to generate the ARM instruction set corresponding to the target X86 instruction.

7. The binary instruction translation and execution device according to claim 6, wherein The device further includes: A first call module, configured to call the decoder to calculate the storage address of the ARM instruction set according to the starting storage address of the ARM instruction sent by the CPU, and store the ARM instruction set and the storage address of the ARM instruction set into a second cache queue; A second call module, configured to call a second bus interface to read the ARM instruction set and the storage address of the ARM instruction set from the second cache queue, and store the ARM instruction set into the preset instruction unit according to the storage address of the ARM instruction set.

8. The binary instruction translation and execution device according to any one of claims 5-7, characterized in that The device further includes: A third call module, configured to call a signal transmission sub-module to receive the storage address of the target X86 instruction, the flag bit information of the preset instruction unit, and the starting storage address of the ARM instruction sent by the CPU.

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