Display panel driving method and display device

Abstract

This invention provides a driving method and display device for a display panel, improving screen flickering during power-on and power-off. The display panel includes a pixel circuit, which includes a driving transistor and a data writing transistor. The gate of the data writing transistor is electrically connected to a first scan signal line, the first terminal of the data writing transistor is electrically connected to a data line, and the second terminal of the data writing transistor is electrically connected to the driving transistor. The first scan signal line is used to provide a first enable voltage and a first disable voltage to the gate of the data writing transistor. The driving process of the display panel includes a first stage and a display stage, with the first stage occurring before and / or after the display stage. The driving method of the display panel includes: during at least a portion of the time period of the first stage, a display driving chip provides a voltage less than the first disable voltage to the data line.

Description

[Technical field]

[0001] The present invention relates to the field of display technology, and in particular to a display panel driving method and a display device. [Background technology]

[0002] With the continuous development of display technology, users have higher and higher requirements for the performance of display devices. However, at present, due to the unreasonable design of power-on and power-off timing, the display device often experiences power-on and power-off screen flashing. Although the screen flashing phenomenon is short-lived, it is still visible to users, thus greatly affecting the user experience. [Summary of the invention]

[0003] In view of this, an embodiment of the present invention provides a display panel driving method and a display device, so as to effectively improve the screen flickering phenomenon of the display device during power on and power off.

[0004] On the one hand, an embodiment of the present invention provides a method for driving a display panel, wherein the display panel includes a pixel circuit, wherein the pixel circuit includes a driving transistor and a data writing transistor, wherein a gate of the data writing transistor is electrically connected to a first scanning signal line, a first electrode of the data writing transistor is electrically connected to a data line, a second electrode of the data writing transistor is electrically connected to the driving transistor, and the first scanning signal line is used to provide a first enabling voltage and a first disabling voltage to the gate of the data writing transistor;

[0005] The driving process of the display panel includes a first stage and a display stage, wherein the first stage is located before and / or after the display stage;

[0006] The driving method comprises: in at least a part of a time period of the first stage, the display driving chip provides a voltage less than the first non-enabling voltage to the data line.

[0007] In another aspect, an embodiment of the present invention provides a display device, including:

[0008] A display panel, comprising a pixel circuit, wherein the pixel circuit comprises a driving transistor and a data writing transistor, wherein a gate of the data writing transistor is electrically connected to a first scanning signal line, a first electrode of the data writing transistor is electrically connected to a data line, a second electrode of the data writing transistor is electrically connected to the driving transistor, and the first scanning signal line is used to provide a first enabling voltage and a first disabling voltage to the gate of the data writing transistor;

[0009] A display driver chip is electrically connected to the data line, and is used to provide a voltage less than the first non-enable voltage to the data line in a first stage, and to provide a data voltage to the data line in a display stage, wherein the first stage is before and / or after the display stage

[0010] One of the above technical solutions has the following beneficial effects:

[0011] The inventors found during the research that leakage of electricity from the data line to the light-emitting element is one of the main factors causing screen flickering during power-on and power-off. In the first stage, that is, during the power-on and power-off stage, the first scanning signal line performs normal line-by-line refresh on the pixel circuits from the first row to the last row. When the pixel circuit is not refreshed by the first scanning signal line, the gate of the data writing transistor in the pixel circuit receives the first non-enabling voltage. The embodiment of the present invention provides a voltage less than the first non-enabling voltage to the data line during at least part of the time period of the first stage, so that the gate-source voltage Vgs1 (Vgs1=V GH -V Data ) is greater than 0, so that the gate-source voltage Vgs1 is much greater than the threshold voltage of the data writing transistor. At this time, the data writing transistor can be controlled to be in a completely cut-off state, effectively cutting off the connection path between the data line and the light-emitting element, and preventing the voltage on the data line from leaking to the light-emitting element. Since the time when the pixel circuit is not refreshed by the first scanning signal line within one frame time is much longer than the time when it is refreshed by the first scanning signal line, the embodiment of the present invention can effectively prevent the light-emitting element from emitting abnormal light during the power-on and power-off process, thereby effectively improving the screen flickering phenomenon during the power-on and power-off process.

Brief Description of the Drawings

[0012] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0013] Figure 1 A schematic diagram of the structure of a display device provided by an embodiment of the present invention;

[0014] Figure 2 A schematic diagram of a structure of a pixel circuit provided by an embodiment of the present invention;

[0015] Figure 3 A timing diagram corresponding to the pixel circuit provided by an embodiment of the present invention;

[0016] Figure 4 A timing diagram of a display panel in a first stage and a display stage provided by an embodiment of the present invention;

[0017] Figure 5 Another timing diagram of a display panel in a first stage and a display stage provided by an embodiment of the present invention;

[0018] Figure 6 Another timing diagram of the display panel in the first stage and the display stage provided by the embodiment of the present invention;

[0019] Figure 7 Another timing diagram of a display panel in a first stage and a display stage provided by an embodiment of the present invention;

[0020] Figure 8 Another timing diagram of a display panel in a first stage and a display stage provided by an embodiment of the present invention;

[0021] Fig. 9 Another timing diagram of a display panel in a first stage and a display stage provided by an embodiment of the present invention;

[0022] Fig.10 Another timing diagram of a display panel in a first stage and a display stage provided by an embodiment of the present invention;

[0023] Fig.11 A schematic diagram of a circuit structure of a first transmission shift circuit provided by an embodiment of the present invention;

[0024] Fig.12 Another timing diagram of a display panel in a first stage and a display stage provided by an embodiment of the present invention;

[0025] Fig.13 Another timing diagram of a display panel in a first stage and a display stage provided by an embodiment of the present invention;

[0026] Fig.14 Another timing diagram of a display panel in a first stage and a display stage provided by an embodiment of the present invention;

[0027] Fig.15 Another schematic diagram of the structure of the display device provided by the embodiment of the present invention;

[0028] Fig.16 Another structural schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0029] Fig.17 Another timing diagram corresponding to the pixel circuit provided by the embodiment of the present invention;

[0030] Fig.18 Another timing diagram of a display panel in a first stage and a display stage provided by an embodiment of the present invention;

[0031] Fig.19A schematic diagram of another structure of a pixel circuit provided by an embodiment of the present invention;

[0032] Fig. 20 This is another timing diagram corresponding to the pixel circuit provided in the embodiment of the present invention. [Specific implementation method]

[0033] In order to better understand the technical solution of the present invention, the embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0034] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0035] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms "a", "said" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0036] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0037] An embodiment of the present invention provides a method for driving a display panel. The method can be applied to Figure 1 In the display device shown.

[0038] like Figure 1 As shown, Figure 1 This is a schematic diagram of the structure of a display device provided by an embodiment of the present invention. The display device includes a display panel 100 and a display driver chip 200 , wherein the display panel 100 includes a pixel circuit 1 and a light-emitting element 2 that are electrically connected.

[0039] like Figure 2 and Figure 3 As shown, Figure 2 A schematic diagram of the structure of a pixel circuit 1 provided in an embodiment of the present invention is shown in FIG. Figure 3A timing diagram corresponding to the pixel circuit 1 provided in an embodiment of the present invention, the pixel circuit 1 includes a driving transistor M0 and a data writing transistor M1, wherein the gate of the data writing transistor M1 is electrically connected to the first scanning signal line Scan1, the first electrode of the data writing transistor M1 is electrically connected to the data line Data, and the second electrode of the data writing transistor M1 is electrically connected to the driving transistor M0, specifically, it can be electrically connected to the first electrode of the driving transistor M0.

[0040] The first scan signal line Scan1 is used to provide a first enable voltage V to the gate of the data writing transistor M1. GL and the first non-enable voltage V GH When the first scan signal line Scan1 provides a first enable voltage, the data write transistor M1 is turned on, and the data voltage V Data The first electrode of the data writing driving transistor M0 is turned off when the first scanning signal line Scan1 provides a first non-enabling voltage, and the data writing transistor M1 is turned off. Data Unable to write to drive transistor M0.

[0041] like Figure 4 As shown, Figure 4 A timing diagram of a display panel 100 in a first stage T1 and a display stage T2 provided in an embodiment of the present invention, wherein the driving process of the display panel 100 includes a first stage T1 and a display stage T2, and the first stage T1 is located before and / or after the display stage T2. The embodiment of the present invention is illustrated by taking the driving process of the display panel 100 including two first stages T1 as an example, wherein one first stage T1 is located before the display stage T2, and the first stage T1 is a power-on stage before the display panel 100 enters normal display, such as a power-on stage / wake-up stage, and the other first stage T1 is located after the display stage T2, and the first stage T1 is a power-off stage after the display panel 100 ends normal display, such as a power-off stage / sleep stage.

[0042] Based on this, combined Figure 1 to Figure 3 The driving method provided by the embodiment of the present invention includes: in at least a part of the time period of the first stage T1, the display driver chip 200 provides a voltage less than a first non-enabling voltage V to the data line Data. GH voltage.

[0043] In the pixel circuit 1 , the driving transistor M0 and the data writing transistor M1 are both P-type transistors, and the threshold voltage of the P-type transistor is less than 0, for example, the threshold voltage may be between -1V and -2V.

[0044] The inventors found during the research that the leakage of the data line Data to the light emitting element 2 is one of the main factors causing the screen to flicker. In the first stage T1, the first scanning signal line Scan1 performs normal row-by-row refresh of the pixel circuits 1 from the first row to the last row. When the pixel circuit 1 is not refreshed by the first scanning signal line Scan1, the gate of the data writing transistor M1 in the pixel circuit 1 receives the first non-enabling voltage V GH In the embodiment of the present invention, a voltage lower than the first non-enabling voltage V is provided to the data line Data during at least a part of the time period of the first stage T1. GH The voltage can make the data written into the gate-source voltage Vgs1 of the transistor M1 (Vgs1 = V GH -V Data ) is greater than 0, so that the gate-source voltage Vgs1 is much greater than the threshold voltage of the data writing transistor M1. At this time, the data writing transistor M1 can be controlled to be in a completely cut-off state, effectively cutting off the connection path between the data line Data and the light-emitting element 2, and preventing the voltage on the data line Data from leaking to the light-emitting element 2. Since the time when the pixel circuit 1 is not refreshed by the first scanning signal line Scan1 within one frame time is much longer than the time when it is refreshed by the first scanning signal line Scan1, the embodiment of the present invention can effectively prevent the light-emitting element 2 from emitting abnormal light during the power-on and power-off process, thereby effectively improving the screen flickering phenomenon during the power-on and power-off process.

[0045] In addition, it should be noted that, again, Figure 2 , the pixel circuit 1 further includes a second light emission control transistor M2, which is also a P-type transistor. The gate of the second light emission control transistor M2 is electrically connected to the light emission control signal line Emit, the first electrode of the second light emission control transistor M2 is electrically connected to the driving transistor M0, specifically to the second electrode of the driving transistor M0, and the second electrode of the second light emission control transistor M2 is electrically connected to the light emitting element 2. Figure 3 The light emitting control signal line Emit is used to provide a light emitting enable voltage V to the gate of the second light emitting control transistor M2. GL ' and the light-emitting non-enable voltage V GH ', where the light-emitting enable voltage V GL ' can be connected to the first enable voltage V GL Equal, light-emitting non-enable voltage V GH ' can be connected to the first non-enable voltage V GH equal.

[0046] When the light-emitting control signal line Emit provides a light-emitting enable voltage V GL ', the second light-emitting control transistor M2 is turned on, driving current to flow to the light-emitting element 2, controlling the light-emitting element 2 to emit light, and when the light-emitting control signal line Emit provides a light-emitting non-enabling voltage V GH', the second light emitting control transistor M2 is turned off, and the driving current cannot flow to the light emitting element 2, causing the light emitting element 2 to not emit light.

[0047] In the first stage T1, when the light emitting control signal line Emit provides the light emitting non-enabling voltage V to the pixel circuit 1, GH ', if the potential of the first electrode of the second light-emitting control transistor M2 is too high, the second light-emitting control transistor M2 may not be properly turned off, and the light-emitting element 2 may still emit light abnormally. In the first stage T1, the embodiment of the present invention provides a voltage less than the first non-enabling voltage V GH When the data write transistor M1 is refreshed by the first scan signal line Scan1, the gate of the data write transistor M1 receives the first enable voltage V GL When the data writing transistor M1 is turned on, the voltage transmitted on the data line Data is transmitted to the first electrode of the second light emitting control transistor M2, so that the first electrode of the second light emitting control transistor M2 receives a voltage less than the light emitting non-enabling voltage V GH '(first non-enable voltage V GH ) voltage, at this time, the gate-source voltage Vgs2 (Vgs2 = V GH ′-V Data ) is greater than 0, which is much greater than the threshold voltage of the second light-emitting control transistor M2, thereby further improving the off-state reliability of the second light-emitting control transistor M2, avoiding leakage current flowing to the light-emitting element 2, and avoiding abnormal light emission of the light-emitting element 2 to a greater extent.

[0048] In order to further improve the screen flickering phenomenon during power on and off, in the embodiment of the present invention, during the entire first stage T1, the display driver chip 200 provides a voltage less than the first non-enable voltage V GH voltage.

[0049] In one possible implementation, see again Figure 1 and Figure 2 , the display device further includes a power driving chip 300. The pixel circuit 1 further includes a first light emission control transistor M3, which is a P-type transistor. The gate of the first light emission control transistor M3 is electrically connected to the light emission control signal line Emit, the first electrode of the first light emission control transistor M3 is electrically connected to the power signal line PVDD, and the second electrode of the first light emission control transistor M3 is electrically connected to the driving transistor M0, specifically, it can be electrically connected to the first electrode of the driving transistor M0. The light emission control signal line Emit is used to provide a light emission enable voltage V to the gate of the first light emission control transistor M3. GL ' and the light-emitting non-enable voltage V GH ', where the light-emitting enable voltage V GL' can be connected to the first enable voltage V GL Equal, light-emitting non-enable voltage V GH ' can be connected to the first non-enable voltage V GH equal.

[0050] When the light-emitting control signal line Emit provides a light-emitting enable voltage V GL ', the first light-emitting control transistor M3 is turned on, and the power signal provided by the power signal line PVDD is written into the first electrode of the driving transistor M0. When the light-emitting control signal line Emit provides the light-emitting non-enabling voltage V GH ', the first light emitting control transistor M3 is turned off, and the power signal cannot be written into the first electrode of the driving transistor M0.

[0051] Based on this, see again Figure 4 The first stage T1 includes a non-power supply period t1 and a power supply period t2, and the power supply period t2 is located between the non-power supply period t1 and the display stage T2. The driving method also includes: in the non-power supply period t1, the power driver chip 300 does not provide a power supply voltage to the power signal line PVDD, and in the power supply period t2, the power driver chip 300 provides a power supply voltage V to the power signal line PVDD. PVDD .

[0052] Taking the first stage T1 as the power-on stage as an example, when the display panel 100 is powered on, the display panel 100 first enters the non-power supply period t1. If a screen flicker phenomenon occurs during the non-power supply period t1, since there is a certain time interval between the non-power supply period t1 and the subsequent display stage T2, the screen flicker phenomenon is more easily detected by the human eye. For example: when the display panel is turned off, in order to reduce power consumption, basically all signals are in a floating state. Especially the data line. Therefore, some charges may accumulate when the screen is off, resulting in different potentials for each data line. If the power supply stage t2 is entered at the beginning, when the power signal line PVDD provides the corresponding potential, the panel has the basic conditions for emitting light. The accumulated charge on the data line will greatly increase the probability of screen flicker. Entering the non-power supply stage t1 first can reduce the risk of screen flicker. Therefore, by preventing the power driver chip 300 from supplying power to the power signal line PVDD during the non-power supply period t1, the pixel circuit 1 cannot receive the power supply voltage V PVDD , thus the light emitting element 2 can be prevented from emitting abnormal light during the non-power supply period t1 to a greater extent.

[0053] In addition, it should be noted that, since the embodiment of the present invention can control the data write transistor M1 to be cut off when the data write transistor M1 is not refreshed, and control the second light-emitting control transistor M1 to be cut off when the data write transistor M1 is refreshed, so as to cut off the connection path between the data write transistor M1 and the light-emitting element 2, even if the power driver chip 300 normally supplies power to the power signal line PVDD during the power supply period t2, it can still avoid the abnormal light emission of the light-emitting element 2 during the power supply period t2.

[0054] In a possible implementation, Figure 5 As shown, Figure 5 Another timing diagram of the display panel 100 in the first stage T1 and the display stage T2 provided by the embodiment of the present invention, in the first stage T1, the process of the display driver chip 200 providing a voltage to the data line Data includes: in the power supply period t2, the display driver chip 200 provides a black state voltage V to the data line Data GMP It should be noted that the black state voltage V GMP is less than the first non-enable voltage V GH The black state voltage may specifically be a voltage of 0 gray scale.

[0055] In the embodiment of the present invention, a black state voltage V is provided to the data line Data during the power supply period t2. GMP , even if the data writing transistor M1 is refreshed by the first scanning signal line Scan1, the black state voltage V GMP Write drive transistor M0, light emitting element 2 will only be in the black state voltage V GMP Under the action of, it appears black and does not shine.

[0056] In one possible implementation, see again Figure 5 In the first stage T1, the process in which the display driver chip 200 provides a voltage to the data line Data also includes: in the non-power supply period t1, the display driver chip 200 provides a constant voltage V1 to the data line Data, and the constant voltage V1 is less than the first non-enable voltage V GH , thereby effectively controlling the working state of the data writing transistor M1 and reducing the voltage jump on the data line Data, thereby reducing power consumption.

[0057] Furthermore, the constant voltage V1 and the first non-enable voltage V GH The voltage difference between them is △V. In order to ensure that the gate-source voltage Vgs1 of the data writing transistor M1 is greater than the threshold voltage of the data writing transistor M1 to a greater extent, △V≥1V.

[0058] In a possible implementation, combining Figure 5 ,like Figure 6 As shown, Figure 6 Another timing diagram of the display panel 100 in the first stage T1 and the display stage T2 provided by the embodiment of the present invention, in the first stage T1, the process of the display driver chip 200 providing a voltage to the data line Data also includes: in the non-power supply period t1, the display driver chip 200 provides a voltage less than or equal to the black state voltage V to the data line Data GMP voltage.

[0059] In the non-power supply period t1, a voltage less than or equal to the black state voltage V is provided to the data line Data. GMP The voltage can avoid the data voltage being too high during this period, saving power consumption to a certain extent. In particular, see Figure 6 , when the constant voltage V1 is equal to the black state voltage V GMP That is, the display driver chip 200 provides the black state voltage V to the data line Data in both the power supply period t2 and the non-power supply period t1. GMP , the data line Data has no voltage jump in the entire first stage T1, and the power consumption is lower.

[0060] In a possible implementation, Figure 7 As shown, Figure 7 Another timing diagram of the display panel 100 in the first stage T1 and the display stage T2 provided by the embodiment of the present invention, the non-power supply period t1 includes x sub-periods t11, the voltage provided to the data line Data in the sub-period t11_i is less than the voltage provided to the data line Data in the sub-period t11_i+1, x is a positive integer greater than or equal to 2, 1≤i≤x-1. For clear illustration, Figure 6 The i-th sub-period is denoted by reference symbol t11_i.

[0061] In this configuration, during the x sub-periods t11 of the non-power supply period t1, the voltage provided by the display driver chip 200 to the data line Data gradually increases until it is increased to the same voltage as the black state voltage V in the xth sub-period t11_x. GMP Close to or equal to the black state voltage V GMP At this time, it can be prevented that when the non-power supply period t1 enters the power supply period t2, the voltage jump amplitude on the data line Data is too large to cause impact on the screen.

[0062] Furthermore, the duration of the sub-period t11 is t0. Wherein, k is a positive integer greater than or equal to 1, and f1 is the frequency of the first scanning signal output by the first scanning signal line Scan1 in the display stage T2. One frame time.

[0063] In this way, the duration of each sub-period t11 is an integer multiple of a frame time, so that within a frame time, when the first scanning signal line Scan1 performs a round of refreshing on the first row of sub-pixel circuits 1 to the last row of pixel circuits 1, the data voltage V written into the first row of sub-pixel circuits 1 to the last row of pixel circuits 1 is Data Each corresponds to a constant data voltage V provided to the data line Data in a sub-period t11. Data , that is, the data voltage V written by the multiple rows of pixel circuits 1 Data are the same, so within one frame time, the data voltage V Data The data writing transistors M1 in the multiple rows of pixel circuits 1 are regulated to the same extent, thereby improving the uniformity of regulation of different pixel circuits 1 within the same frame time.

[0064] Further, the voltage provided to the data line Data in the first sub-period t11_1 is less than 2.5V, or the ground voltage is provided to the data line Data in the first sub-period t11_1.

[0065] In the above configuration, by providing a voltage less than 2.5V to the data line Data in the first sub-period t11_1 or directly providing a ground voltage, the voltage provided to the data line Data in the first sub-period t11_1 can be made smaller, that is, the voltage provided to the data line Data in the first sub-period t11_1 is equal to the black state voltage V GMP If the non-power supply period t1 includes a large number of sub-periods t11, the subsequent sub-periods t11 have a large voltage difference on the data voltage V Data When the voltage is gradually increased, the voltage increase space is large, so that the data voltage V corresponding to the subsequent other sub-periods t11 Data The design is more flexible.

[0066] In a feasible implementation, the display panel 100 has at least two display modes, for example, the display panel 100 has a normal mode, an always on display (AOD) mode, and a high brightness (HBM) mode. When the display panel 100 performs the always on display mode in the display stage T2, the display panel 100 usually only displays part of the content, such as only displaying time information, etc., so in this display mode, the display panel 100 usually displays at a lower brightness, and when the display panel 100 performs the high brightness mode in the display stage T2, in order to optimize the display performance, the display panel 100 usually displays at a higher brightness.

[0067] Since different display modes correspond to different brightness levels, when the display panel 100 executes different display modes in the display stage T2, the black state voltages V corresponding to the different display modes are GMP , power supply voltage V PVDD and the first non-enable voltage V GH For example, compared with the normal mode, the brightness level in the highlight mode is higher, so when the display panel 100 performs the highlight mode in the display stage T2, its corresponding black state voltage V GMP Bigger.

[0068] like Figure 8 As shown, Figure 8 Another timing diagram of the display panel 100 in the first stage T1 and the display stage T2 provided by the embodiment of the present invention, when the display panel 100 performs different display modes in the display stage T2, the first non-enable voltage V corresponding to the first stage T1 is GH Equal, power supply voltage V PVDD Equal, black state voltage V GMP Also equal.

[0069] Taking the first stage T1 as the power-on stage as an example, no matter what display mode the display panel 100 performs after entering the display stage T2 after power-on, in the first stage T1, the data voltage V provided to the data line Data is set. Data When the data voltage V Data All are based on the same first non-enable voltage V GH For example, the first non-enable voltage V GH is the first non-enabling voltage V corresponding to the display panel 100 when executing the normal mode in the display stage T2. GH1 The voltage provided by the power driver chip 300 to the power signal line PVDD is also the same power voltage V PVDD , for example, the power supply voltage V PVDD is the power supply voltage V corresponding to the display panel 100 when executing the normal mode in the display stage T2 PVDD1 The display driver chip 200 provides a black state voltage V to the data line Data during the power supply period t2. GMP is also the same voltage, for example, the black state voltage V GMP is the black state voltage V corresponding to the display panel 100 when executing the normal mode in the display stage T2 GMP1 .

[0070] With such configuration, no matter which display mode the display panel 100 performs in the display stage T2 , the same type of voltages in the first stage T1 follow the same voltage setting, which simplifies the setting of each voltage in the first stage T1 .

[0071] Alternatively, in another feasible implementation, when the display panel 100 executes different display modes in the display stage T2 , different voltage settings may be performed for the same type of voltage in the first stage T1 .

[0072] The first stage T1 is before the display stage T2, and the display mode executed by the display panel 100 after the first stage T1 ends is the first display mode. Alternatively, the first stage T1 is after the display stage T2, and the display mode executed by the display panel 100 before entering the first stage T1 is the first display mode.

[0073] It should be noted that, in the display stage T2, the display panel 100 can switch the display mode it executes according to the user's usage requirements. The above-mentioned first display mode refers to the display mode that the display panel 100 needs to execute at the beginning when the display panel 100 just enters the display stage T2, or the display mode that the display panel 100 finally executes when the display panel 100 is about to end the display stage T2. For example, taking the first stage T1 as the power-on stage as an example, when the display panel 100 ends the power-on and starts to display the normal picture, the display panel 100 executes the normal mode at the beginning of the display stage T2, and switches to the highlight mode after a period of time. At this time, the first display mode refers to the normal mode.

[0074] like Fig. 9 As shown, Fig. 9 Another timing diagram of the display panel 100 in the first stage T1 and the display stage T2 provided by the embodiment of the present invention, when the first display mode is the normal mode, the first non-enable voltage corresponding to the first stage T1 is V GH1 , the power supply voltage is V PVDD1 , black state voltage is V GMP1 The first non-enable voltage V GH1 , power supply voltage V PVDD1 and black state voltage V GMP1 They are respectively a first non-enable voltage, a power voltage and a black state voltage corresponding to when the display panel 100 executes a normal mode in the display stage T2.

[0075] When the first display mode is the highlight mode, the first non-enable voltage corresponding to the first stage T1 is V GH2 , the power supply voltage is V PVDD2 , black state voltage is V GMP2 The first non-enable voltage is V GH2 , the power supply voltage is V PVDD2 , black state voltage is V GMP2They are respectively the first non-enable voltage, power supply voltage and black state voltage corresponding to the display panel 100 when executing the highlight mode in the display stage T2. Since the highlight mode gives priority to performance requirements, the first non-enable voltage, power supply voltage and black state voltage in the highlight mode can all be adjusted upwards compared to the normal mode. Fig. 9 When the first display mode is the highlight mode, the first non-enable voltage V corresponding to the first stage T1 is GH2 , power supply voltage V PVDD2 and black state voltage V GMP2 Satisfaction: V GH2 >V GH1 , V PVDD2 >V PVDD1 , V GMP2 >V GMP1 , V GH2 -V GH1 ≥V GMP2 -V GMP1 ≥V PVDD2 -V PVDD1 .

[0076] When the first display mode is the constant display mode, the first non-enable voltage corresponding to the first stage T1 is V GH3 , the power supply voltage is V PVDD3 , black state voltage is V GMP3 The first non-enable voltage V GH3 , power supply voltage V PVDD3 , Black state voltage V GMP3 They are respectively the first non-enabled voltage, the power supply voltage and the black state voltage corresponding to the display panel 100 when executing the normal display mode in the display stage T2. Since the brightness level corresponding to the normal display mode is not as high as the brightness level corresponding to the highlight mode, in order to save power consumption, the upward adjustment degree of each voltage in the normal display mode can be smaller than that in the highlight mode. At this time, refer again to Fig. 9 When the first display mode is the constant display mode, the first non-enable voltage V corresponding to the first stage T1 is GH3 , power supply voltage V PVDD3 and black state voltage V GMP3 Satisfies: Among them, V GH1 <V GH3 <V GH2 , V PVDD1 <V PVDD3 <V PVDD2 , V GMP1 <V GMP3 <V GMP2 , and V GH3 -V GH1 ≥V GMP3 -V GMP1 ≥V PVDD3 -V PVDD1.

[0077] Or, to further reduce power consumption, such as Fig.10 As shown, Fig.10 Another timing diagram of the display panel 100 in the first stage T1 and the display stage T2 provided by the embodiment of the present invention, when the first display mode is the normal display mode, the first non-enable voltage V corresponding to the first stage T1 GH3 , power supply voltage V PVDD3 and black state voltage V GMP3 It can also satisfy: V GH3 <V GH1 , V PVDD3 <V PVDD1 , V GMP3 <V GMP1 , and V GH1 -V GH3 ≤V GMP1 -V GMP3 ≤V PVDD1 -V PVDD3 .

[0078] In a feasible implementation manner, the duration of the non-power supply period t1 is t1, The duration of the power supply period t2 is t2, Wherein, f1 is the frequency of the first scanning signal output by the first scanning signal line Scan1 in the display stage T2.

[0079] By setting the duration of the non-power supply period t1 and the power supply period t2 to at least one frame, the first scanning signal line Scan1 can perform at least one complete refresh of the pixel circuits 1 in the first row to the last row in the non-power supply period t1 and the power supply period t2, so that the voltage transmitted on the data line Data can effectively regulate all pixel circuits 1, ensuring that the screen flickering phenomenon in different areas of the display area is effectively improved. By further setting the duration of the non-power supply period t1 and the power supply period t2 to at most three frames, it is possible to avoid the power on and off process being too long and affecting the user experience.

[0080] In a feasible implementation, the first scanning signal output by the first scanning signal line Scan1 in the display stage T2 has multiple frequencies, and f1 is the maximum value of the frequency of the first scanning signal. It can be understood that the higher the frequency of the first scanning signal, the shorter the corresponding frame time. When the display panel 100 is variable frequency driven in the display stage T2, by setting f1 to the maximum value of the frequency of the first scanning signal, the time of the power-on and power-off process can be shortened, thereby optimizing the user experience.

[0081] In a feasible implementation manner, the duration of the non-power supply period t1 is t1, The duration of the power supply period t2 is t2, m and n are integers greater than or equal to 0. Wherein, f1 is the frequency of the first scan signal output by the first scan signal line Scan1 in the display stage T2, and f2 is the frequency of the light emitting control signal output by the light emitting control signal line Emit in the display stage T2.

[0082] When the display panel 100 is driven at a low frequency, in order to improve flicker, the refresh frequency of the light emitting control signal may be greater than the refresh frequency of the first scanning signal. Figure 3 , the frequency of the first scanning signal is 30Hz, and the frequency of the light emitting control signal can be 60Hz, that is, In order to shorten the power-on and power-off time, the non-power supply period t1 and the power supply period t2 may not be set to an integer multiple of one frame, provided that they are both greater than one frame. Integer multiples of are also acceptable.

[0083] In a feasible implementation manner, the durations of the non-power supply period t1 and the power supply period t2 may be set to be unequal.

[0084] Since the power supply period t2 needs to be powered on, there is a long time delay. In order to ensure that the voltage is switched to stability, the power supply period t2 can be made longer, that is, the duration of the non-power supply period t1 is shorter than the duration of the power supply period t2. Exemplarily, the duration of the non-power supply period t1 is 2 frames, and the duration of the power supply period t2 is 3 frames.

[0085] In one possible implementation, see again Figure 1 and Figure 2 The pixel circuit 1 includes a second light-emitting control transistor M2, a gate of the second light-emitting control transistor M2 is electrically connected to the light-emitting control signal line Emit, a first electrode of the second light-emitting control transistor M2 is electrically connected to the driving transistor M0, a second electrode of the second light-emitting control transistor M2 is electrically connected to the light-emitting element 2, and the light-emitting control signal line Emit is used to provide a light-emitting enable voltage V to the gate of the second light-emitting control transistor M2. GL ' and the light-emitting non-enable voltage V GH ′.

[0086] The display panel 100 further includes a plurality of cascaded emission shift circuits 3, which are electrically connected to the light emission control signal line Emit. The emission shift circuit 3 includes a first emission shift circuit 4, which is also electrically connected to the emission frame start signal line STV_E.

[0087] like Fig.11 As shown, Fig.11A schematic diagram of a circuit structure of a first emission shift circuit 4 provided in an embodiment of the present invention, wherein the first emission shift circuit 4 further comprises a first control transistor M1′ and a first output transistor M2′. The first control transistor M1′ is electrically connected between the emission frame start signal line STV_E and the gate of the first output transistor M2′, the first electrode of the first output transistor M2′ is electrically connected to the first fixed potential signal line VGL, and the second electrode of the first output transistor M2′ is electrically connected to the light emission control signal line Emit, wherein the first fixed potential signal line VGL is used to provide a light emission enable voltage V GL ′.

[0088] like Fig.12 As shown, Fig.12 Another timing diagram of the display panel 100 in the first stage T1 and the display stage T2 provided by the embodiment of the present invention, the driving method further includes: in the first stage T1, the display driver chip 200 provides a non-enable voltage of the first output transistor M2′ to the emission frame start signal line STV_E, and the non-enable voltage can be connected to the first non-enable voltage V GH equal.

[0089] It should be noted that, combined with Fig.11 and Fig.12 The emission shift register is also connected to the first emission clock signal line CK1_E and the second emission clock signal line CK2_E respectively. In the first stage T1, the first emission clock signal line CK1_E and the second emission clock signal line CK2_E can normally give pulse signals in the first stage T1.

[0090] Based on the circuit structure of the current emission shift register, when the disabling voltage of the first output transistor M2′ is provided to the emission frame start signal line STV_E, the disabling voltage is transmitted to the first output transistor M2′ via the turned-on first control transistor M1′, and the first output transistor M2′ is controlled to be turned off, so that the first emission shift circuit 4 cannot output the light-emitting enabling voltage V GL ', and it is impossible to achieve sequential downward shifting. In this way, it is possible to avoid the emission shift circuit 3 transmitting the light-emitting enable voltage V to the emission control signal line. GL ', preventing the second light emitting control transistor M2 in the pixel circuit 1 from being turned on, thereby preventing the leakage current of the data line Data from flowing to the light emitting element 2, thereby improving the problem of upper and lower electrical flash screen to a greater extent.

[0091] Further, see again Fig.11The first emission shift circuit 4 includes a protection transistor M3′, the gate of the protection transistor M3′ is electrically connected to the control signal line RST, the first electrode of the protection transistor M3′ is electrically connected to the second fixed potential signal line VGH, the second fixed potential signal line VGH is used to provide a non-enabling voltage for the first output transistor M2′, the second electrode of the protection transistor M3′ is electrically connected to the gate of the first output transistor M2′, and the control signal line RST is used to provide a second enabling voltage V GL1 and the second non-enable voltage V GH1 , the second enabling voltage V GL1 Can be connected with the first enable voltage V GL equal to, the second non-enable voltage V GH1 can be connected to the first non-enable voltage V GH equal.

[0092] See again Fig.12 The driving method of the display panel 100 includes: in a first stage T1, the display driving chip 200 provides a second non-enabling voltage V to the control signal line RST GH1 .

[0093] In the emission shift circuit 3, the protection transistor M3′ is a transistor for preventing abnormal power failure. In the first stage T1, the second non-enabling voltage V is provided to the control signal line RST. GH1 , the protection transistor M3′ remains cut off, and the high level provided by the second fixed potential signal line VGH charges the parasitic capacitance in the protection transistor M3′. If an abnormal power failure occurs during the power supply process of the first stage T1, the protection transistor M3′ can transmit the high level stored in itself to the gate of the first output transistor M2′ to ensure that the first output transistor M2′ is cut off, so that the first emission shift circuit 4 cannot output the light-emitting enable voltage V GL ', thereby controlling the light emitting element 2 to be unable to emit light, and controlling the first emission shift circuit 4 to be unable to continue to shift downward.

[0094] In addition, it should be noted that the first emission shift circuit 4 may also include: a second control transistor M4′ to a sixth control transistor M8′, a second output transistor M9′, a first capacitor C1, a second capacitor C2 and a third capacitor C3. The connection method of the above structure is the same as that of the prior art and will not be repeated here.

[0095] In another possible implementation, if Fig.13 As shown, Fig.13Another timing diagram of the display panel 100 in the first stage T1 and the display stage T2 provided in an embodiment of the present invention, during the power supply period t2, the display driver chip 200 can also provide a clock signal to the emission frame start signal line STV_E, that is, control the light emitting control signal line Emit to refresh the pixel circuit 1 normally.

[0096] Since the embodiment of the present invention can cut off the connection path between the data line Data and the light-emitting element 2 in the first stage T1, even if the light-emitting control signal line Emit drives the pixel circuit 1 normally in the first stage T1, the screen flickering phenomenon can still be effectively improved.

[0097] In one possible implementation, see again Figure 1 The display panel further includes a plurality of first scan shift circuits 5 arranged in cascade connection, and the first scan shift circuits 5 are electrically connected to the first A scan clock signal line CK1_S1, the first B scan clock signal line CK2_S1 and the first scan signal line Scan1 respectively. The first scan shift circuit 5 includes a first A scan shift circuit 6, and the first A scan shift circuit 6 is also electrically connected to the first scan frame start signal line STV_S1.

[0098] Based on this, Fig.14 As shown, Fig.14 Another timing diagram of the display panel 100 in the first stage T1 and the display stage T2 provided in an embodiment of the present invention, the driving method also includes: in the first stage T1, the display driver chip 200 provides pulse signals to the first A scan clock signal line CK1_S1, the first B scan clock signal line CK2_S1 and the first scan frame start signal line STV_S1 respectively.

[0099] In the above setting method, the first scan shift circuit works normally in the first stage T1, so that the first scan signal line Scan1 refreshes the pixel circuit 1 normally. However, as mentioned above, based on the embodiment of the present invention, the data voltage V Data By setting the first scanning signal line Scan1 to refresh the pixel circuit 1 normally, the light emitting element 2 can still be prevented from emitting abnormal light in the first stage T1.

[0100] In one possible setting, Figure 15 to Figure 17 As shown, Fig.15 Another schematic diagram of the structure of the display device provided by the embodiment of the present invention is shown in FIG. Fig.16 Another structural schematic diagram of the pixel circuit 1 provided in an embodiment of the present invention is shown in FIG. Fig.17Another timing diagram corresponding to the pixel circuit 1 provided in an embodiment of the present invention, the pixel circuit 1 includes a control transistor M7, the gate of the control transistor M7 is electrically connected to the second scan signal line Scan2, the first electrode of the control transistor M7 is electrically connected to the control signal line DVH, and the second electrode of the control transistor M7 is electrically connected to the driving transistor M0, specifically, electrically connected to the first electrode of the driving transistor M0.

[0101] Can A Jin Fig.15 The display panel 100 further includes a plurality of second scan shift circuits 7 arranged in cascade connection, and the second scan shift circuits 7 are electrically connected to the second A scan clock signal line CK1_S2, the second B scan clock signal line CK2_S2, and the second scan signal line Scan2, respectively. The second scan shift circuit 7 includes a second A scan shift circuit 8, and the second A scan shift circuit 8 is also electrically connected to the second scan frame start signal line STV_S2.

[0102] like Fig.18 As shown, Fig.18 Another timing diagram of the display panel 100 in the first stage T1 and the display stage T2 provided in an embodiment of the present invention, the driving method also includes: in the first stage T1, the display driver chip 200 provides pulse signals to the second A scan clock signal line CK1_S2, the second B scan clock signal line CK2_S2 and the second scan frame start signal line STV_S2 respectively.

[0103] The pixel circuit 1 includes a control transistor M7, combined with Fig.17 Before resetting the gate of the driving transistor M0, by controlling the control transistor M7 to turn on, the bias voltage provided by the control signal line DVH can be written into the first electrode of the driving transistor M0, and the potential of the first electrode of the driving transistor M0 is refreshed, so that the device characteristics of the driving transistor M0 are set to a certain initial state, eliminating the influence of the data signal written in the previous frame on the device characteristics of the driving transistor M0. Data Afterwards, the voltage of the first electrode of the driving transistor M0 will leak, especially under low-frequency driving, the leakage is more obvious, resulting in a large deviation of the potential of the first electrode of the driving transistor M0. At this time, by controlling the control transistor M7 to turn on, the control transistor M7 is used to write a bias voltage to the first electrode of the driving transistor M0, so that the bias state of the driving transistor M0 can be consistent with the data voltage V just written. Data The bias state is maintained consistent to improve the stability of the working state of the driving transistor M0.

[0104] In addition, it should be noted that see Figure 2 and Fig.16The pixel circuit 1 further includes a storage capacitor Cst, a first reset transistor M4, a second reset transistor M5 and a threshold compensation transistor M6. In one implementation example, the first reset transistor M4, the second reset transistor M5 and the threshold compensation transistor M6 may all be P-type transistors.

[0105] The gate of the first reset transistor M4 is electrically connected to the third scan signal line Scan3, the first electrode of the first reset transistor M4 is electrically connected to the reset signal line Vref, and the second electrode of the first reset transistor M4 is electrically connected to the drive transistor M0, specifically to the gate of the drive transistor M0. The first reset transistor M4 is used to respond to the low level provided by the third scan signal line Scan3, write the reset signal provided by the reset signal line Vref into the gate of the drive transistor M0, and realize resetting the gate of the drive transistor M0.

[0106] The gate of the second reset transistor M5 is electrically connected to the third scan signal line Scan3, the first electrode of the second reset transistor M5 is electrically connected to the reset signal line Vref, and the second electrode of the second reset transistor M5 is electrically connected to the anode of the light emitting element 2. The second reset transistor M5 is used to respond to the low level provided by the third scan signal line Scan3, write the reset signal provided by the reset signal line Vref into the anode of the light emitting element 2, and realize the reset of the anode of the light emitting element 2.

[0107] The gate of the threshold compensation transistor M6 is electrically connected to the first scan signal line Scan1, the first electrode of the threshold compensation transistor M6 is electrically connected to the second electrode of the driving transistor M0, and the second electrode of the threshold compensation transistor M6 is electrically connected to the gate of the driving transistor M0. The threshold compensation transistor M6 is used to respond to the low level (first enable voltage V GL ), threshold compensation is performed on the driving transistor M0.

[0108] Or, in another embodiment, Fig.19 and Fig. 20 As shown, Fig.19 FIG. 1 is another structural diagram of the pixel circuit 1 provided in an embodiment of the present invention. Fig. 20 In another timing diagram corresponding to the pixel circuit 1 provided in an embodiment of the present invention, the second reset transistor M5 is a P-type transistor, and in order to reduce the influence of leakage current on the gate potential stability of the driving transistor M0, the first reset transistor M4 and the threshold compensation transistor M6 can also be indium gallium zinc oxide transistors (Indiumgallium zinc oxide, IGZO), that is, the first reset transistor M4 and the threshold compensation transistor M6 are N-type transistors.

[0109] At this time, the gate of the first reset transistor M4 is electrically connected to the fourth scan signal line Scan4, the first electrode of the first reset transistor M4 is electrically connected to the reset signal line Vref, and the second electrode of the first reset transistor M4 is electrically connected to the drive transistor M0, specifically to the gate of the drive transistor M0. The first reset transistor M4 is used to respond to the high level provided by the fourth scan signal line Scan4, write the reset signal provided by the reset signal line Vref into the gate of the drive transistor M0, and realize resetting the gate of the drive transistor M0.

[0110] The gate of the second reset transistor M5 is electrically connected to the second scan signal line Scan2, the first electrode of the second reset transistor M5 is electrically connected to the reset signal line Vref, and the second electrode of the second reset transistor M5 is electrically connected to the anode of the light emitting element 2. The second reset transistor M5 is used to respond to the low level provided by the second scan signal line Scan2, write the reset signal provided by the reset signal line Vref into the anode of the light emitting element 2, and achieve the reset of the anode of the light emitting element 2. It should be noted that, since the second scan signal line Scan2 is set low twice within one frame time, the second reset transistor M5 can achieve the reset of the anode of the light emitting element 2 twice.

[0111] The gate of the threshold compensation transistor M6 is electrically connected to the fifth scan signal line Scan5, the first electrode of the threshold compensation transistor M6 is electrically connected to the second electrode of the driving transistor M0, and the second electrode of the threshold compensation transistor M6 is electrically connected to the gate of the driving transistor M0. The threshold compensation transistor M6 is used to respond to the high level provided by the fifth scan signal line Scan5 to perform threshold compensation on the driving transistor M0.

[0112] Based on the same inventive concept, an embodiment of the present invention further provides a display device, see again Figure 1 and Figure 2 , the display device includes a display panel 100 and a display driving chip 200 .

[0113] The display panel 100 includes a pixel circuit 1, the pixel circuit 1 includes a driving transistor M0 and a data writing transistor M1, wherein the gate of the data writing transistor M1 is electrically connected to the first scanning signal line Scan1, the first electrode of the data writing transistor M1 is electrically connected to the data line Data, the second electrode of the data writing transistor M1 is electrically connected to the driving transistor M0, and the first scanning signal line Scan1 is used to provide a first enabling voltage V to the gate of the data writing transistor M1. GL and the first non-enable voltage V GH .

[0114] The display driver chip 200 is electrically connected to the data line Data, and is used to provide a voltage less than a first non-enable voltage V to the data line Data in the first stage T1.GH The voltage of the display stage T2 provides the data line Data with a data voltage V Data , the first stage T1 is located before and / or after the display stage T2.

[0115] In the first stage T1, the first scan signal line Scan1 performs normal row-by-row refresh on the pixel circuits 1 from the first row to the last row. When the pixel circuit 1 is not refreshed by the first scan signal line Scan1, the gate of the data writing transistor M1 in the pixel circuit 1 receives the first non-enabling voltage V GH In the embodiment of the present invention, a voltage lower than the first non-enabling voltage V is provided to the data line Data during at least a part of the time period of the first stage T1. GH The voltage Vgs1 of the data writing transistor M1 can make the gate-source voltage Vgs1 of the data writing transistor M1 greater than 0, making it much greater than the threshold voltage of the data writing transistor M1. At this time, the data writing transistor M1 can be controlled to be in a completely cut-off state, effectively cutting off the connection path between the data line Data and the light-emitting element 2, and preventing the voltage on the data line Data from leaking to the light-emitting element 2. Since the time when the pixel circuit 1 is not refreshed by the first scanning signal line Scan1 within one frame time is much longer than the time when it is refreshed by the first scanning signal line Scan1, the embodiment of the present invention can effectively prevent the light-emitting element 2 from abnormally emitting light during the power-on and power-off process, thereby effectively improving the screen flickering phenomenon during the power-on and power-off process.

[0116] Further, see again Figure 1 and Figure 2 The pixel circuit 1 also includes a first light emitting control transistor M3, a gate of the first light emitting control transistor M3 is electrically connected to the light emitting control signal line Emit, a first electrode of the first light emitting control transistor M3 is electrically connected to the power signal line PVDD, and a second electrode of the first light emitting control transistor M3 is electrically connected to the driving transistor M0.

[0117] The first stage T1 includes a non-power supply period t1 and a power supply period t2, wherein the power supply period t2 is located between the non-power supply period t1 and the display stage T2. The display device further includes a power driver chip 300, which is used to not provide a power supply voltage to the power signal line PVDD during the non-power supply period t1 of the first stage T1, and to provide a power supply voltage V to the power signal line PVDD during the power supply period t2. PVDD .

[0118] Taking the first stage T1 as the power-on stage as an example, when the display panel 100 is powered on, the display panel 100 first enters the non-power supply period t1. If a screen flicker phenomenon occurs during the non-power supply period t1, since there is a certain time interval between the non-power supply period t1 and the subsequent display stage T2, the screen flicker phenomenon is more easily perceived by the human eye. Therefore, by making the power driver chip 300 not supply power to the power signal line PVDD during the non-power supply period t1, the pixel circuit 1 cannot receive the power supply voltage V PVDD , thus the light emitting element 2 can be prevented from emitting abnormal light during the non-power supply period t1 to a greater extent.

[0119] In addition, it should be noted that, since the embodiment of the present invention can control the data write transistor M1 to be cut off when the data write transistor M1 is not refreshed, and control the second light-emitting control transistor M1 to be cut off when the data write transistor M1 is refreshed, so as to cut off the connection path between the data write transistor M1 and the light-emitting element 2, even if the power driver chip 300 normally supplies power to the power signal line PVDD during the power supply period t2, it can still avoid the abnormal light emission of the light-emitting element 2 during the power supply period t2.

[0120] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

[0121] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for driving a display panel, characterized in that: The display panel includes a pixel circuit, the pixel circuit includes a driving transistor and a data writing transistor, wherein a gate of the data writing transistor is electrically connected to a first scanning signal line, a first electrode of the data writing transistor is electrically connected to a data line, a second electrode of the data writing transistor is electrically connected to the driving transistor, and the first scanning signal line is used to provide a first enabling voltage and a first non-enabling voltage to the gate of the data writing transistor; The driving process of the display panel includes a first stage and a display stage, wherein the first stage is located before and / or after the display stage; wherein the first stage is a power-on stage before the display panel enters normal display and / or a power-off stage after the display panel ends normal display; The pixel circuit includes a second light emitting control transistor, a gate of the second light emitting control transistor is electrically connected to a light emitting control signal line, a first electrode of the second light emitting control transistor is electrically connected to the driving transistor, a second electrode of the second light emitting control transistor is electrically connected to a light emitting element, and the light emitting control signal line is used to provide a light emitting enable voltage and a light emitting disable voltage to the gate of the second light emitting control transistor; the light emitting disable voltage is equal to the first disable voltage; The driving method includes: during at least part of the time period of the first stage, the display driver chip provides a voltage less than the first non-enable voltage to the data line, so that when the first scanning signal line provides the first non-enable voltage to the gate of the data writing transistor, the data writing transistor is in a completely cut-off state, and when the light-emitting control signal line provides the light-emitting non-enable voltage to the gate of the second light-emitting control transistor, the second light-emitting control transistor is in a completely cut-off state.

2. The driving method according to claim 1, characterized in that: The pixel circuit further includes a first light emission control transistor, a gate of the first light emission control transistor is electrically connected to a light emission control signal line, a first electrode of the first light emission control transistor is electrically connected to a power supply signal line, and a second electrode of the first light emission control transistor is electrically connected to the driving transistor; The first stage includes a non-power supply period and a power supply period, and the power supply period is located between the non-power supply period and the display stage; The driving method further includes: in the non-power supply period, the power driving chip does not provide the power supply voltage to the power signal line, and in the power supply period, the power driving chip provides the power supply voltage to the power signal line.

3. The driving method according to claim 2, characterized in that: In the first stage, the process of the display driver chip providing a voltage to the data line includes: in the power supply period, the display driver chip provides a black state voltage to the data line.

4. The driving method according to claim 2, characterized in that: In the first stage, the process of the display driver chip providing a voltage to the data line further includes: in the non-power supply period, the display driver chip provides a constant voltage to the data line.

5. The driving method according to claim 4, characterized in that: A voltage difference between the constant voltage and the first non-enable voltage is ΔV, where ΔV≥1V.

6. The driving method according to claim 2, characterized in that: In the first stage, the process of the display driver chip providing a voltage to the data line further includes: in the non-power supply period, the display driver chip provides a voltage less than or equal to a black state voltage to the data line.

7. The driving method according to claim 6, characterized in that: The non-power supply period includes x sub-periods, the voltage provided to the data line in the i-th sub-period is less than the voltage provided to the data line in the i+1-th sub-period, x is a positive integer greater than or equal to 2, 1≤i≤x-1.

8. The driving method according to claim 7, characterized in that: The duration of the sub-period is t0, t0=k× , wherein k is a positive integer greater than or equal to 1, and f1 is the frequency of the first scanning signal output by the first scanning signal line in the display stage.

9. The driving method according to claim 7, characterized in that: The voltage provided to the data line in the first sub-period is less than 2.5V, or the ground voltage is provided to the data line in the first sub-period.

10. The driving method according to claim 3, characterized in that: The display panel has at least two display modes. When the display panel performs different display modes in the display stage, the first non-enable voltages, the power supply voltages, and the black state voltages corresponding to the first stage are equal.

11. The driving method according to claim 3, characterized in that: The first stage is before the display stage, and the display mode executed by the display panel after the first stage is the first display mode; or, the first stage is after the display stage, and the display mode executed by the display panel before entering the first stage is the first display mode; The first display mode is a normal mode, and the first non-enable voltage corresponding to the first stage is V GH1 , the power supply voltage is V PVDD1 , the black state voltage is V GMP1 ; The first display mode is a highlight mode, and the first non-enable voltage corresponding to the first stage is V GH2 , the power supply voltage is V PVDD2 , the black state voltage is V GMP2 , where V GH2 >V GH1 , V PVDD2 >V PVDD1 , V GMP2 >V GMP1 , and V GH2 -V GH1 ≥V GMP2 -V GMP1 ≥V PVDD2 -V PVDD1 ; The first display mode is a constant display mode, and the first non-enable voltage corresponding to the first stage is V GH3 , the power supply voltage is V PVDD3 , the black state voltage is V GMP3 , where V GH1 <V GH3 <V GH2 , V PVDD1 <V PVDD3 <V PVDD2 , V GMP1 <V GMP3 <V GMP2 , and V GH3 -V GH1 ≥V GMP3 -V GMP1 ≥V PVDD3 -V PVDD1 , or, V GH3 <V GH1 , V PVDD3 <V PVDD1 , V GMP3 <V GMP1 , and V GH1 -V GH3 ≤V GMP1 -V GMP3 ≤V PVDD1 -V PVDD3 .

12. The driving method according to claim 2, characterized in that: The duration of the non-power supply period is t1, ≤t1≤ , the duration of the power supply period is t2, ≤t2≤ , wherein f1 is the frequency of the first scanning signal output by the first scanning signal line in the display stage.

13. The driving method according to claim 12, characterized in that: The first scanning signal output by the first scanning signal line in the display stage has a plurality of frequencies, and f1 is the maximum value of the frequencies of the first scanning signal.

14. The driving method according to claim 2, characterized in that: The duration of the non-power supply period is t1, t1= , the duration of the power supply period is t2, t2= , m and n are integers greater than or equal to 0; Wherein, f1 is the frequency of the first scanning signal output by the first scanning signal line in the display stage, and f2 is the frequency of the light emitting control signal output by the light emitting control signal line in the display stage.

15. The driving method according to claim 2, characterized in that: The duration of the non-power supply period is shorter than the duration of the power supply period.

16. The driving method according to claim 1, characterized in that: The display panel further comprises a plurality of emission shift circuits arranged in cascade, the emission shift circuits being electrically connected to the light emission control signal line, the emission shift circuits comprising a first emission shift circuit, and the first emission shift circuit being also electrically connected to an emission frame start signal line; The first emission shift circuit includes a first control transistor and a first output transistor, the first control transistor is electrically connected between the emission frame start signal line and the gate of the first output transistor, the first electrode of the first output transistor is electrically connected to the first fixed potential signal line, and the second electrode of the first output transistor is electrically connected to the light emission control signal line, wherein the first fixed potential signal line is used to provide the light emission enable voltage; The driving method further includes: in the first stage, the display driving chip provides a non-enabling voltage of the first output transistor to the transmission frame start signal line.

17. The driving method according to claim 16, characterized in that: The emission shift circuit further includes a protection transistor, a gate of the protection transistor is electrically connected to a control signal line, a first electrode of the protection transistor is electrically connected to a second fixed potential signal line, a second electrode of the protection transistor is electrically connected to a gate of the first output transistor, and the control signal line is used to provide a second enable voltage and a second disable voltage to the gate of the protection transistor; The display panel driving method comprises: in the first stage, the display driving chip provides the second non-enabling voltage to the control signal line.

18. The driving method according to claim 1, characterized in that: The display panel further comprises a plurality of first scan shift circuits arranged in cascade connection, wherein the first scan shift circuits are electrically connected to the first A scan clock signal line, the first B scan clock signal line and the first scan signal line respectively; wherein the first scan shift circuit comprises a first A scan shift circuit, and the first A scan shift circuit is also electrically connected to the first scan frame start signal line; The driving method further includes: in the first stage, the display driving chip provides pulse signals to the first A scanning clock signal line, the first B scanning clock signal line and the first scanning frame start signal line respectively.

19. The driving method according to claim 1, characterized in that: The pixel circuit comprises a control transistor, a gate of the control transistor is electrically connected to the second scanning signal line, a first electrode of the control transistor is electrically connected to the control signal line, and a second electrode of the control transistor is electrically connected to the driving transistor; The display panel further comprises a plurality of second scan shift circuits arranged in cascade connection, wherein the second scan shift circuits are electrically connected to the second A scan clock signal line, the second B scan clock signal line and the second scan signal line respectively; wherein the second scan shift circuit comprises a second A scan shift circuit, and the second A scan shift circuit is also electrically connected to the second scan frame start signal line; The driving method further includes: in the first stage, the display driving chip provides pulse signals to the second A scanning clock signal line, the second B scanning clock signal line and the second scanning frame start signal line respectively.

20. A display device, characterized in that: include: A display panel, comprising a pixel circuit, wherein the pixel circuit comprises a driving transistor and a data writing transistor, wherein a gate of the data writing transistor is electrically connected to a first scanning signal line, a first electrode of the data writing transistor is electrically connected to a data line, a second electrode of the data writing transistor is electrically connected to the driving transistor, and the first scanning signal line is used to provide a first enabling voltage and a first non-enabling voltage to the gate of the data writing transistor; the pixel circuit further comprises a second light emitting control transistor, a gate of the second light emitting control transistor is electrically connected to a light emitting control signal line, a first electrode of the second light emitting control transistor is electrically connected to the driving transistor, a second electrode of the second light emitting control transistor is electrically connected to a light emitting element, and the light emitting control signal line is used to provide a light emitting enabling voltage and a light emitting non-enabling voltage to the gate of the second light emitting control transistor; the light emitting non-enabling voltage is equal to the first non-enabling voltage; A display driver chip is electrically connected to the data line, and is used to provide a voltage less than the first non-enable voltage to the data line in a first stage, and to provide a data voltage to the data line in a display stage, wherein the first stage is located before and / or after the display stage; wherein the first stage is a power-on stage before the display panel enters normal display and / or a power-off stage after the display panel ends normal display; wherein the display driver chip provides a voltage less than the first non-enable voltage to the data line in the first stage, so that when the first scanning signal line provides the first non-enable voltage to the gate of the data write transistor, the data write transistor is in a completely cut-off state, and when the light-emitting control signal line provides the light-emitting non-enable voltage to the gate of the second light-emitting control transistor, the second light-emitting control transistor is in a completely cut-off state.

21. The display device according to claim 20, characterized in that: The pixel circuit further includes a first light emission control transistor, a gate of the first light emission control transistor is electrically connected to a light emission control signal line, a first electrode of the first light emission control transistor is electrically connected to a power supply signal line, and a second electrode of the first light emission control transistor is electrically connected to the driving transistor; The first stage includes a non-power supply period and a power supply period, and the power supply period is located between the non-power supply period and the display stage; The display device further includes a power driving chip configured to not provide a power voltage to the power signal line during a non-power supply period of the first stage, and to provide the power voltage to the power signal line during a power supply period.

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