Method for finding a common optimal reference voltage, storage system

Abstract

The application relates to the technical field of data storage, and discloses a method for searching for a common optimal reference voltage and a storage system. The method comprises the following steps: providing a lookup table of reference voltage offsets corresponding to each bit storage unit and 1-count difference voltage offsets corresponding to boundary bit storage units under different time intervals; when a UECC occurs or a storage particle with a bit error rate exceeding a standard exists in the storage system, detecting a current 1-count difference voltage offset of the boundary bit storage unit, and obtaining reference voltage offsets corresponding to each bit storage unit in the lookup table by taking the current 1-count difference voltage offset as an index; and applying the corresponding reference voltage offsets to an initial common reference voltage of all storage particles in the storage system. The application can accurately adjust the reference voltage.

Description

Technical Field

[0001] This application relates to the field of data storage technology, and in particular to a method and storage system for finding a common optimal reference voltage. Background Technology

[0002] Non-volatile memory systems have become an important way to store data because the data stored in them is not lost when power is off. Among these non-volatile memory systems, NAND flash memory is popular due to its advantages of low power consumption and high efficiency.

[0003] To verify the correctness of a non-volatile memory product, the threshold voltage of the reference cell in the non-volatile memory chip under test must first be precisely adjusted. Taking SLC (Single Layer Cell) flash memory as an example, its readout principle is briefly described: The same gate and source voltages are applied to the memory cell and the reference cell, and their drain currents are compared. If the current of the memory cell is greater than that of the reference cell, the memory cell is defined as storing "1"; otherwise, it is defined as storing "0". Therefore, the threshold voltage of the reference cell is the determination point for stored data and is the foundation of the entire flash memory readout system, requiring precise adjustment before testing. As the integration density of flash memory increases, the operating speed can be improved; however, changes in the operating environment can affect the distribution of the threshold voltage, potentially increasing readout errors. Summary of the Invention

[0004] The purpose of this application is to provide a method and storage system for finding a common optimal reference voltage, which can precisely adjust the reference voltage.

[0005] This application discloses a method for finding a common optimal reference voltage, including:

[0006] Provides lookup tables for the reference voltage offset of each bit storage cell and the 1 count difference voltage offset of the boundary bit storage cell at different time intervals;

[0007] When a storage system has a memory chip experiencing UECC or a bit error rate exceeding the standard, the current 1-count difference voltage offset of the boundary bit memory cell is detected, and the corresponding reference voltage offset for each bit memory cell is retrieved from the lookup table using the current 1-count difference voltage offset as an index; and

[0008] The corresponding reference voltage offset is applied to the initial common reference voltage of all memory chips in the memory system.

[0009] In a preferred embodiment, the lookup table is generated in the following manner:

[0010] Power on the storage system and leave it idle;

[0011] Obtain the common reference voltage distribution of each bit storage cell in several sample blocks of the storage system at different time intervals, and the 1 count difference voltage of the bit storage cell at the boundary of a certain sample word line of the storage system.

[0012] Record the reference voltage offset of each bit storage cell and the 1 count difference voltage offset of the boundary bit storage cell under different time intervals, and form a lookup table for the reference voltage offset of each bit storage cell and the 1 count difference voltage offset of the boundary bit storage cell under different time intervals.

[0013] In a preferred embodiment, the storage system does not perform read, write, or erase operations during the resting process.

[0014] In a preferred embodiment, when a memory chip experiences UECC or a bit error rate exceeding the standard during the use of the storage system, the current 1 count difference voltage offset of the boundary bit memory cell is detected and a corresponding reference voltage offset is obtained. The corresponding reference voltage offset is applied to the initial common reference voltage of all memory chips in the storage system. Furthermore, if the storage system still has memory chips experiencing UECC or a bit error rate exceeding the standard, the corresponding reference voltage offset is applied to the corresponding initial common reference voltage of the memory chips experiencing UECC or a bit error rate exceeding the standard.

[0015] In a preferred embodiment, after the storage system is powered off and then powered on again, the current 1 count difference voltage offset of the boundary bit storage cell on a certain sample word line in the storage system is detected and the corresponding reference voltage offset is obtained. The corresponding reference voltage offset is then applied to the initial common reference voltage of all storage chips in the storage system.

[0016] In a preferred embodiment, after the corresponding reference voltage offset is applied to the initial common reference voltage of all memory chips in the memory system, when there is a memory chip in the memory system that experiences UECC or has a bit error rate exceeding the standard, the corresponding reference voltage offset is applied to the corresponding initial common reference voltage of the memory chip that experienced UECC or had a bit error rate exceeding the standard.

[0017] In a preferred embodiment, the storage system includes a plurality of storage chips, the storage system having a common reference voltage applicable to all storage chips, and the plurality of storage chips are divided into multiple groups, each group of storage chips having its own common reference voltage.

[0018] This application also discloses a storage system comprising:

[0019] One or more storage particles;

[0020] A memory controller coupled to the one or more memory chips, the memory controller storing a lookup table of reference voltage offsets for each bit memory cell and count difference voltage offsets for boundary bit memory cells at different time intervals, wherein the memory controller is configured to:

[0021] When the storage system has memory chips experiencing UECC or a bit error rate exceeding the standard, the current 1-count difference voltage offset of the boundary bit memory cell is detected, and the corresponding reference voltage offset for each bit memory cell is retrieved from the lookup table using the current 1-count difference voltage offset as an index; and

[0022] The corresponding reference voltage offset is applied to the initial common reference voltage of all memory chips in the memory system.

[0023] In a preferred embodiment, the lookup table is generated in the following manner:

[0024] Power on the storage system and leave it idle;

[0025] Obtain the common reference voltage distribution of each bit storage cell in several sample blocks of the storage system at different time intervals, and the 1 count difference voltage of the bit storage cell at the boundary of a certain sample word line of the storage system.

[0026] Record the reference voltage offset of each bit storage cell and the 1 count difference voltage offset of the boundary bit storage cell under different time intervals, and form a lookup table for the reference voltage offset of each bit storage cell and the 1 count difference voltage offset of the boundary bit storage cell under different time intervals.

[0027] In a preferred embodiment, the storage system does not perform read, write, or erase operations during the resting process.

[0028] In a preferred embodiment, the memory controller is configured to: when a memory chip experiencing UECC or a bit error rate exceeding the standard exists during the use of the memory system, detect the current 1 count difference voltage offset of the boundary bit memory cell and obtain the corresponding reference voltage offset, apply the corresponding reference voltage offset to the initial common reference voltage of all memory chips in the memory system, and if the memory system still has memory chips experiencing UECC or a bit error rate exceeding the standard, apply the corresponding reference voltage offset to the corresponding initial common reference voltage of the memory chip experiencing UECC or a bit error rate exceeding the standard.

[0029] In a preferred embodiment, the memory controller is configured to: after the memory system is powered off and then powered on again, detect the current 1 count difference voltage offset of the boundary bit memory cell on a certain sample word line in the memory system and obtain the corresponding reference voltage offset, and apply the corresponding reference voltage offset to the initial common reference voltage of all memory chips in the memory system.

[0030] In a preferred embodiment, the memory controller is further configured to: after applying the corresponding reference voltage offset to the initial common reference voltage of all memory chips in the memory system, when there is a memory chip in the memory system that has experienced UECC or has a bit error rate exceeding the standard, apply the corresponding reference voltage offset to the corresponding initial common reference voltage of the memory chip that has experienced UECC or has a bit error rate exceeding the standard.

[0031] In this embodiment, the voltage distribution of the storage system changes with charging or discharging during rest. A lookup table is provided for the reference voltage offset of each bit storage cell and the 1-count difference voltage offset of the boundary bit storage cell at different rest times. The 1-count difference voltage offset of the boundary bit storage cell changes with the rest time and can be used to determine the current rest time and obtain the reference voltage offset of each cell. This allows for precise adjustment of the storage system reference voltage when the storage system experiences UECC or the bit error rate exceeds the standard.

[0032] The specification of this application contains numerous technical features distributed across various technical solutions. Listing all possible combinations of these technical features (i.e., technical solutions) would make the specification excessively lengthy. To avoid this problem, the various technical features disclosed in the above-described invention, the various technical features disclosed in the following embodiments and examples, and the various technical features disclosed in the accompanying drawings can be freely combined to form various new technical solutions (all of which should be considered as described in this specification), unless such a combination of technical features is technically infeasible. For example, one example discloses feature A+B+C, and another example discloses feature A+B+D+E. Features C and D are equivalent technical means that serve the same function, and technically only one needs to be used; they cannot be used simultaneously. Feature E can technically be combined with feature C. Therefore, the solution A+B+C+D should not be considered as described because it is technically infeasible, while the solution A+B+C+E should be considered as described. Attached Figure Description

[0033] Figure 1 This is a flowchart illustrating a method for finding a common optimal reference voltage according to one embodiment of this application.

[0034] Figure 2 This is a schematic diagram of the reference voltage distribution of each bit storage cell when the storage system according to one embodiment of this application is kept at rest.

[0035] Figure 3 This is a schematic diagram of the reference voltage distribution offset of the boundary bit storage cell under different resting times according to one embodiment of this application.

[0036] Figure 4 This is a schematic diagram of the 1 count difference voltage offset of the boundary bit storage cell under different resting times according to one embodiment of this application.

[0037] Figure 5 This is a block diagram of a storage system according to one embodiment of the present application. Detailed Implementation

[0038] In the following description, many technical details are presented to help the reader better understand this application. However, those skilled in the art will understand that the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0039] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0040] The first embodiment of this application relates to a method for finding a common optimal reference voltage. Figure 1 A flowchart of a method 100 for finding a common optimal reference voltage in one embodiment is shown, the method comprising the following steps:

[0041] Step 102 provides a lookup table for the reference voltage offset of each bit cell and the 1 count difference voltage offset of the boundary bit cell at different time intervals.

[0042] In one embodiment, the lookup table is generated in the following manner:

[0043] First, the storage system is powered on and left idle. In one embodiment, no read, write, or erase operations are performed on the storage system while it is left idle.

[0044] In one embodiment, the storage system may include a plurality of NAND flash memory chips, each NAND having one or more dies, and the storage system having a single common reference voltage applicable to all memory chips. Furthermore, the plurality of memory chips may be divided into multiple groups, with each group of memory chips having its own common reference voltage; that is, the storage system may have multiple common reference voltages applicable to different groups of memory chips.

[0045] Typically, the optimal read reference voltage for multiple NAND pages is determined by scanning the read voltage distribution of each page, finding the highest error bit count across all pages under Error Correction Code (ECC) constraints, and identifying the voltage with the lowest error bit count as the optimal reference voltage shared by all pages. Variations in the read voltage distribution are primarily caused by variations in reference voltage between different NAND chips. The valley window corresponding to the highest error bit count across all pages under ECC constraints is usually asymmetrical. Since the center of the valley window under ECC constraints provides a more balanced edge reference voltage distance than the point with the lowest error bit count, the reference voltage at its center can be selected as the optimal reference voltage shared by multiple pages.

[0046] A common optimal reference voltage can be extracted from all NAND flash chips or all chips in a storage system. Since scanning all pages is time-consuming, it is preferable to scan a sample page or block of samples for each chip to find the common optimal reference voltage. As the number of chips in a storage system increases and the ECC valley window shrinks, multiple chips can be grouped into smaller groups or groups with similar valley window ranges. Each group of chips has its own common optimal reference voltage.

[0047] Secondly, the common reference voltage distribution of each bit storage cell in several sample blocks of the storage system at different time intervals is obtained, as well as the 1 count difference voltage of the bit storage cell at the boundary of a certain sample word line of the storage system.

[0048] Figure 2 A schematic diagram of the reference voltage distribution of each cell in one embodiment of the storage system is shown. The reference voltage of the boundary bit storage cell shifts to different degrees depending on the length of the storage system's resting time. As can be seen from the figure, the longer the resting time, the greater the shift in the reference voltage of the boundary bit storage cell.

[0049] Figure 3 A schematic diagram illustrating the reference voltage distribution offset of a boundary bit memory cell under different resting times is shown in one embodiment. The reference voltage of the boundary bit memory cell corresponding to the 1-count index point (e.g., 300) is the 1-count difference voltage, which shifts under different resting times. For example, from resting time T0 to T1, the 1-count difference voltage shifts by D1; from resting time T1 to T2, the 1-count difference voltage shifts by D2; and from resting time T2 to T3, the 1-count difference voltage shifts by D3. Figure 4 This diagram illustrates the voltage offset of the 1 count difference of the boundary bit storage cell under different resting times in this embodiment.

[0050] Then, the reference voltage offset of each bit storage cell and the 1-count difference voltage offset of the boundary bit storage cell are recorded at different time intervals. Furthermore, a lookup table is formed for the reference voltage offset of each bit storage cell and the 1-count difference voltage offset of the boundary bit storage cell at different time intervals. Table 1 below shows a lookup table in one embodiment.

[0051]

[0052] Table 1 shows the reference voltage offset and the 1-count difference voltage offset for each bit storage unit under different resting times.

[0053] The voltage distribution of the storage system changes with charging or discharging during rest, and the voltage offset of the 1 count difference of the boundary bit storage cell changes with the rest time, which can be used to determine the current rest time. As the change in cell voltage distribution causes the bit error rate (BER) to exceed an acceptable standard, this patent introduces an optimal reference voltage setting method adapted to the current rest time, which can precisely adjust the reference voltage.

[0054] Step 104: When the storage system has a storage particle that has experienced UECC or whose bit error rate exceeds the standard, detect the current 1 count difference voltage offset of the boundary bit storage cell, and obtain the corresponding reference voltage offset of each bit storage cell in the lookup table using the current 1 count difference voltage offset as an index.

[0055] Step 106: Apply the corresponding reference voltage offset to the initial common reference voltage of all memory chips in the memory system.

[0056] In one embodiment, when a memory chip experiences UECC or a bit error rate exceeding the standard during the use of the storage system, the current 1 count difference voltage offset of the boundary bit memory cell is detected and a corresponding reference voltage offset is obtained. This corresponding reference voltage offset is then applied to the initial common reference voltage of all memory chips in the storage system. If ECC can correct the error at this point, the correction process ends. If the storage system still has memory chips experiencing UECC or a bit error rate exceeding the standard, the corresponding reference voltage offset is applied to the corresponding initial common reference voltage of those memory chips experiencing UECC or a bit error rate exceeding the standard.

[0057] The following is a specific example. Suppose that the storage system has four memory chips, so there is a set of common optimal reference voltages shared by the four chips, as shown in Table 2 below. Each of the four chips also has its own common optimal reference voltage, as shown in Table 3 below.

[0058]

[0059] Table 2 shows the common optimal reference voltage shared by a group of memory chips.

[0060]

[0061] Table 3 shows the common optimal reference voltage for each storage chip in a set of storage chips.

[0062] The process described above is used to obtain the lookup table of the 1 count difference voltage offset corresponding to the boundary bit storage cell under different resting times (as shown in Table 4 below) and the lookup table of the reference voltage offset corresponding to each bit storage cell under different resting times (as shown in Table 5 below).

[0063] resting time 1. Count difference offset T0 0 T1 -2 T2 -3 T3 -4

[0064] Table 4. Voltage offset of 1-count difference corresponding to boundary bit storage units under different resting times.

[0065] resting time V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 T0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T1 0 0 1 0 1 0 1 0 0 0 0 -1 -1 -1 -1 T2 -1 0 0 0 0 0 0 0 0 0 -1 -2 -2 -2 -2 T3 -1 0 1 0 0 0 0 0 0 0 -1 -2 -2 -3 -2

[0066] Table 5. Reference voltage offset for each bit memory cell under different resting times.

[0067] Taking QLC as an example, the correction will have two stages:

[0068] (1) When UECC or ECC exceeds the standard, we first find a set of reference voltage offsets by using the resting time corresponding to the reference voltage index table, and then add the reference voltage offsets to a set of common best reference voltages shared by a set of memory chips. After obtaining a set of best read voltages, we try to read and correct them. If the correction is successful, the correction process ends.

[0069] (2) If UECC still occurs, then the corresponding set of reference voltage offsets is applied to the common optimal reference voltage of the particle that caused the UECC to obtain the optimal read voltage for that particle, and then the read correction is attempted again. The reason for doing this is that the optimal read voltage for a single particle is more accurate than a set of shared optimal read voltages, so the probability of UECC being corrected is also higher.

[0070] In one embodiment, after the storage system is powered off and then powered on again, the current 1 count difference voltage offset of the boundary bit storage cell on a certain sample word line in the storage system is detected and the corresponding reference voltage offset is obtained. The corresponding reference voltage offset is then applied to the initial common reference voltage of all storage chips in the storage system. In another embodiment, after applying the corresponding reference voltage offset to the initial common reference voltage of all storage chips in the storage system, if there is a storage chip in the storage system that experiences UECC or has a bit error rate exceeding the standard, the corresponding reference voltage offset is applied to the corresponding initial common reference voltage of the storage chip that experienced UECC or had a bit error rate exceeding the standard.

[0071] The second embodiment of this application relates to a storage system. Figure 5A storage system 500 according to an embodiment of the present disclosure is illustrated. The storage system 500 may include storage chips 504 and a memory controller 502 coupled to the storage chips 504. When the memory controller 502 is coupled to a host, it can provide data storage and / or access to the stored data for the host. According to this embodiment, the memory controller 502 receives control signals and performs operations corresponding to the control signals. The storage chip 504 sends the execution result of the operation corresponding to the control signal to the memory controller 502. The storage chip 504 may be a non-volatile memory (NVM) based storage device, such as NAND flash memory, NOR flash memory, magnetoresistive random access memory (MRAM), resistive random access memory (RRAM), phase-change random access memory (PCRAM), Nano-RAM, etc. NAND flash memory can be used as an example. It should be noted that the storage system 100 may include multiple storage chips, and the storage chip 504 may be shown as a representative of multiple storage chips.

[0072] The memory controller 502 may include a processor, memory, and an ECC engine. The processor may be a computer processor, such as, but not limited to, a microprocessor or microcontroller. The memory may be a non-transitory computer-readable storage medium, such as DRAM or SRAM, to store computer-executable instructions that will be executed by the processor. The ECC engine can correct errors in the stored data retrieved from the memory chip 504.

[0073] The memory controller 502 stores a lookup table containing the reference voltage offset for each bit storage cell and the 1-count difference voltage offset for each boundary bit storage cell at different time intervals. This lookup table can be stored in memory, for example. The lookup table is generated through the process described in detail above. Specifically, the memory controller is configured to: when the memory system has memory chips experiencing UECC or exceeding the standard bit error rate, detect the current 1-count difference voltage offset of the boundary bit storage cell, and retrieve the corresponding reference voltage offset for each bit storage cell from the lookup table using the current 1-count difference voltage offset as an index. The corresponding reference voltage offset is then applied to the initial common reference voltage of all memory chips in the memory system. Furthermore, if the memory system still has memory chips experiencing UECC or exceeding the standard bit error rate, the corresponding reference voltage offset is applied to the corresponding initial common reference voltage of the memory chips experiencing UECC or exceeding the standard bit error rate.

[0074] It should be noted that in this patent application, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. In this patent application, if it refers to performing an action according to an element, it means performing the action at least according to that element, including two cases: performing the action only according to that element, and performing the action according to that element and other elements. Expressions such as "multiple," "repeatedly," and "various" include two, two times, two kinds, and more than two, more than two times, and more than two kinds.

[0075] All references to this specification are considered to be incorporated integrally into the disclosure of this application so that they can serve as the basis for modifications if necessary. Furthermore, it should be understood that the above descriptions are merely preferred embodiments of this specification and are not intended to limit the scope of protection of this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments of this specification should be included within the scope of protection of one or more embodiments of this specification.

[0076] In some cases, the actions or steps described in the claims can be performed in a different order than that shown in the embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

Claims

1. A method for finding a common optimal reference voltage, characterized in that, include: Provides lookup tables for the reference voltage offset of each bit storage cell and the 1 count difference voltage offset of the boundary bit storage cell at different time intervals; When the storage system has a storage particle that has experienced UECC or whose bit error rate exceeds the standard, the current 1 count difference voltage offset of the boundary bit storage cell is detected, and the reference voltage offset corresponding to each bit storage cell is obtained from the lookup table using the current 1 count difference voltage offset as an index. as well as The corresponding reference voltage offset is applied to the initial common reference voltage of all memory chips in the memory system.

2. The method for finding a common optimal reference voltage according to claim 1, characterized in that, The lookup table is generated in the following way: Power on the storage system and leave it idle; Obtain the common reference voltage distribution of each bit storage cell in several sample blocks of the storage system at different time intervals, and the 1 count difference voltage of the bit storage cell at the boundary of a certain sample word line of the storage system. Record the reference voltage offset of each bit storage cell and the 1 count difference voltage offset of the boundary bit storage cell under different time intervals, and form a lookup table for the reference voltage offset of each bit storage cell and the 1 count difference voltage offset of the boundary bit storage cell under different time intervals.

3. The method for finding a common optimal reference voltage according to claim 2, characterized in that, The storage system does not perform read, write, or erase operations while remaining stationary.

4. The method for finding a common optimal reference voltage according to claim 1, characterized in that, When a memory chip experiences UECC or a bit error rate exceeding the standard during the use of the storage system, the current 1 count difference voltage offset of the boundary bit memory cell is detected and the corresponding reference voltage offset is obtained. The corresponding reference voltage offset is applied to the initial common reference voltage of all memory chips in the storage system. Furthermore, if the storage system still has memory chips experiencing UECC or a bit error rate exceeding the standard, the corresponding reference voltage offset is applied to the corresponding initial common reference voltage of the memory chips experiencing UECC or a bit error rate exceeding the standard.

5. The method for finding a common optimal reference voltage according to claim 1, characterized in that, After the storage system is powered off and then powered on again, the current 1 count difference voltage offset of the boundary bit storage cell on a certain sample word line in the storage system is detected and the corresponding reference voltage offset is obtained. The corresponding reference voltage offset is then applied to the initial common reference voltage of all storage chips in the storage system.

6. The method for finding a common optimal reference voltage according to claim 5, characterized in that, After applying the corresponding reference voltage offset to the initial common reference voltage of all memory chips in the memory system, when there is a memory chip in the memory system that experiences UECC or has a bit error rate exceeding the standard, the corresponding reference voltage offset is applied to the corresponding initial common reference voltage of the memory chip that experienced UECC or had a bit error rate exceeding the standard.

7. The method for finding a common optimal reference voltage according to claim 1, characterized in that, The storage system includes a plurality of storage particles, the storage system has a common reference voltage applicable to all storage particles, and the plurality of storage particles are divided into multiple groups, each group of storage particles having its own common reference voltage.

8. A storage system, characterized in that, include: One or more storage particles; A memory controller coupled to the one or more memory chips, the memory controller storing a lookup table of reference voltage offsets for each bit memory cell and count difference voltage offsets for boundary bit memory cells at different time intervals, wherein the memory controller is configured to: When the storage system has a storage particle that has experienced UECC or whose bit error rate exceeds the standard, the current 1 count difference voltage offset of the boundary bit storage cell is detected, and the reference voltage offset corresponding to each bit storage cell is obtained from the lookup table using the current 1 count difference voltage offset as an index. as well as The corresponding reference voltage offset is applied to the initial common reference voltage of all memory chips in the memory system.

9. The storage system according to claim 8, characterized in that, The lookup table is generated in the following way: Power on the storage system and leave it idle; Obtain the common reference voltage distribution of each bit storage cell in several sample blocks of the storage system at different time intervals, and the 1 count difference voltage of the bit storage cell at the boundary of a certain sample word line of the storage system. Record the reference voltage offset of each bit storage cell and the 1 count difference voltage offset of the boundary bit storage cell under different time intervals, and form a lookup table for the reference voltage offset of each bit storage cell and the 1 count difference voltage offset of the boundary bit storage cell under different time intervals.

10. The storage system according to claim 9, characterized in that, The storage system does not perform read, write, or erase operations while remaining stationary.

11. The storage system according to claim 8, characterized in that, The memory controller is configured to: when a memory chip experiences UECC or a bit error rate exceeding the standard during the use of the memory system, detect the current 1 count difference voltage offset of the boundary bit memory cell and obtain the corresponding reference voltage offset, apply the corresponding reference voltage offset to the initial common reference voltage of all memory chips in the memory system, and if the memory system still has memory chips experiencing UECC or a bit error rate exceeding the standard, apply the corresponding reference voltage offset to the corresponding initial common reference voltage of the memory chips experiencing UECC or a bit error rate exceeding the standard.

12. The storage system according to claim 8, characterized in that, The memory controller is configured to: after the memory system is powered off and powered on again, detect the current 1 count difference voltage offset of the boundary bit memory cell on a certain sample word line in the memory system and obtain the corresponding reference voltage offset, and apply the corresponding reference voltage offset to the initial common reference voltage of all memory chips in the memory system.

13. The storage system according to claim 12, characterized in that, The memory controller is further configured to: after applying the corresponding reference voltage offset to the initial common reference voltage of all memory chips in the memory system, when there is a memory chip in the memory system that has experienced UECC or whose bit error rate exceeds the standard, apply the corresponding reference voltage offset to the corresponding initial common reference voltage of the memory chip that has experienced UECC or whose bit error rate exceeds the standard.

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