Reset Read Disturb Mitigation

Abstract

The present application relates to reset read disturb mitigation. Methods and systems include a memory device having a plurality of memory cells configured to store data. The memory device also includes a control circuit system, the control circuit system including a retry circuit system. The retry circuit system is configured to receive a read command having a target address. The retry circuit system is also configured to determine that the target address of the data stored in the memory cell is to be reused from a previous read operation. In addition, the retry circuit system is configured to cause the data to be read from the sense amplifier latch from the previous read operation by reusing the target address. Specifically, reusing the target address includes bypassing rereading the data from the memory cell into the sense amplifier latch for a current read operation.

Description

Technical Field

[0001] The present application relates to reset read disturb mitigation. Background Art

[0002] This paragraph is intended to introduce the reader to various aspects of the art that may be relevant to various aspects of the present technology described and / or claimed below. It is believed that this discussion helps to provide the reader with background information to facilitate a better understanding of various aspects of the present disclosure. Therefore, it should be understood that these statements should be read from this perspective and that these statements are not admissions of the prior art.

[0003] Typically, a computing system includes a processing circuit system, such as one or more processors or other suitable components, and a memory device, such as a chip or integrated circuit. One or more memory devices may be used in a memory module, such as a dual in-line memory module (DIMM), to store data accessible to the processing circuit system. For example, based on a user input to the computing system, the processing circuit system may request the memory module to retrieve data corresponding to the user input from its memory device. In some examples, the retrieved data may include firmware, or instructions that can be executed by the processing circuit system to perform an operation, and / or may include data to be used as input to the operation. In addition, in some cases, data output from an operation may be stored in a memory, such as to enable data to be retrieved from the memory later.

[0004] Some memory devices include memory cells that can be accessed by turning on a transistor that couples the memory cell (e.g., a capacitor) to a word line or a bit line. In contrast, a threshold type memory device includes a memory device that is accessed by providing a voltage across a memory cell, wherein a data value is stored based on a threshold voltage of the memory cell. For example, the data value may be based on whether a threshold voltage of the memory cell is exceeded, and the memory cell conducts current in response to the voltage provided across the memory cell. The stored data value may be changed, such as by applying a voltage sufficient to change the threshold voltage of the memory cell. One example of a threshold type memory cell may be a cross point memory cell.

[0005] For threshold type memories, a threshold voltage (VTH) determines when certain actions are performed. However, this threshold may be affected by reliability issues where reset read disturb (RDR) disrupts the polarization effect by soft programming the opposite polarity. Specifically, as the number of read disturbs increases, the reliability issues may lead to cumulative VTH degradation (e.g., a decrease in VTH) until the memory operation fails. These reliability issues may be greater or more problematic for certain aspects of the memory device (e.g., reset read disturb (RDR)) than for other aspects (e.g., write operations). Summary of the invention

[0006] In one aspect, the present application provides a memory device comprising: a plurality of memory cells configured to store data; and a control circuit system comprising a retry circuit system configured to: receive a read command having a target address; determine that the data in the target address is to be reused from a sense amplifier latch from a previous read operation; and cause the data to be read from the sense amplifier latch from the previous read operation by reusing the target address, wherein reusing the target address comprises bypassing rereading the data from the plurality of memory cells into the sense amplifier latch for a current read operation.

[0007] In another aspect, the present application further provides a method comprising: receiving a first read command corresponding to a first read operation; receiving a second read command corresponding to a second read operation subsequent to the first read operation; determining rows, columns, and partitions corresponding to both the first read operation and the second read operation; and based at least in part on the determination of the rows, columns, and partitions for both the first read operation and the second read operation, reading data from a sense amplifier latch for the second read operation without loading the data from a memory array to the sense amplifier latch during the second read operation.

[0008] In yet another aspect, the present application further provides a memory device comprising: a plurality of memory cells configured to store data; a plurality of sense amplifiers configured to read from corresponding memory cells in the plurality of memory cells; a plurality of sense amplifier latches configured to latch outputs from corresponding sense amplifiers in the plurality of sense amplifiers; and a control circuit system comprising a retry circuit system configured to: receive a first read command having a target address; in response to receiving the first read command, sense data from the target address using a sense amplifier in the plurality of sense amplifiers; in response to sensing the data, latch the data from the sense amplifier into a sense amplifier latch in the plurality of sense amplifier latches; based at least in part on latching the data and the first read command, drive the data from the sense amplifier latch onto a data bus; receive a second read command having the target address; and based at least in part on the second read command subsequent to the first read command, redrive the data from the data from the sense amplifier latch without re-latching the data from the sense amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Various aspects of the present disclosure may be better understood after reading the following detailed description and after referring to the accompanying drawings, in which:

[0010] Figure 1 is a simplified block diagram illustrating certain features of a memory device including retry circuitry and a memory array of memory cells according to an embodiment of the present disclosure;

[0011] Figure 2 The present invention is described in accordance with an embodiment of the present disclosure. Figure 1 a side view of a portion of a memory array;

[0012] Figure 3 According to the embodiment of the present disclosure Figure 1 A timing diagram of consecutive read operations of the same address in a partition of a memory device;

[0013] Figure 4 According to the embodiment of the present disclosure Figure 1 A simplified block diagram of a read operation of a memory device;

[0014] Figure 5 The use of the embodiments according to the present disclosure Figure 3 The timing diagram of voltage versus raw error rate for different read times;

[0015] Figure 6 According to an embodiment of the present disclosure, Figure 1 A flowchart of a process for reading a reused address for a sense amplifier in a memory device of the present invention;

[0016] Figure 7 The use of the embodiments according to the present disclosure Figure 1 The retry circuit system uses the value in the sense amplifier latch in the continuous read operation. Figure 1 A simplified block diagram of a read operation of a memory device of FIG. 1 ; and

[0017] Figure 8 According to the embodiment of the present disclosure Figure 1 A circuit diagram of at least a portion of a retry circuit system. DETAILED DESCRIPTION

[0018] One or more specific embodiments will be described below. In order to provide a concise description of these embodiments, not all features of the actual implementation are described in this specification. It should be understood that in the development of any such actual implementation, as in any engineering management or design project, many implementation-specific decisions must be made to achieve the developer's specific goals, such as meeting system-related and business-related constraints, which may vary from implementation to implementation. In addition, it should be understood that such development efforts can be complex and time-consuming, but will be a routine task of design, fabrication, and manufacture for those of ordinary skill in the art who benefit from the present disclosure.

[0019] The memory typically includes an array of memory cells, wherein each memory cell is coupled between at least two access lines. For example, the memory cells may be coupled to access lines, such as bit lines and word lines. Each access line may be coupled to a large number of memory cells. To select a memory cell, one or more drivers may provide a selection signal (e.g., a voltage and / or current) on the access line to access the storage capacity of the memory cell. By applying a voltage and / or current to the corresponding access line, the memory cell may be accessed, for example, data may be written to the memory cell and / or data may be read from the memory cell.

[0020] In some memories, the memory cells of the array may be organized into stacks of memory cells. A memory cell stack may be a single plane of memory cells disposed between word line layers and bit line layers. The array may be a stack of stacks including any number of memory cell stacks (e.g., 0 stacks, 1 stack, 2 stacks, 4 stacks, any number of stacks) as different layers of the array.

[0021] Within the stack, a two-dimensional array of memory cells may be arranged at different intersections of word lines and bit lines in a plane. As previously described for threshold-type memories, the threshold voltage (VTH) may be affected by the reliability issue of reset read disturbance (RDR) destroying the polarization effect by soft programming the opposite polarity. Specifically, as the number of read disturbances increases, the reliability issue may lead to cumulative VTH degradation (e.g., a reduction in VTH) until the memory operation fails repeatedly. Rereading the same (or other) address in a partition shortly after the previous read in the partition may exacerbate the VTH degradation. Alternatively, the minimum read to read (mR2R) duration may be specified as the minimum time between readings of the partition (and / or address). A short mR2R duration for the same partition may exacerbate VTH degradation, but an excessively long mR2R duration may affect the performance of the memory device. In order to provide enhanced performance for RDR-based degradation mitigation, if the data is already in the sense amplifier latch, the rereading of the sense amplifier latch may be utilized without running the read process on the same physical cell location. The read process may include propagating clocks, currents, and / or voltages, which consume power and / or may result in degradation of the memory device unless avoided using a sense amplifier latch re-read. Some situations (e.g., error correction code errors, variations in demarcation voltage (VDM)) may cause the memory device to forgo such a re-read by instead utilizing a read process through the array because the data in the sense amplifier latch may no longer be considered to match the data in the memory cell.

[0022] Remember the previous introduction, Figure 11 is a block diagram of a portion of a memory device 100. The memory device 100 may be any suitable form of memory, such as non-volatile memory (e.g., cross-point memory) and / or volatile memory. The memory device 100 may include one or more memory cells 102, one or more bit lines 104 (e.g., 104-0, 104-1, 104-2, 104-3), one or more word lines 106 (e.g., 106-0, 106-1, 106-2, 106-3), one or more word line decoders 108 (e.g., word line decoding circuitry), and one or more bit line decoders 110 (e.g., bit line decoding circuitry). The memory cells 102, bit lines 104, word lines 106, word line decoders 108, and bit line decoders 110 may form a memory array 112.

[0023] Each of the memory cells 102 may include a selector and / or a storage element. When a voltage across the selector of the corresponding memory cell reaches a threshold, the storage element may be accessed to read a data value from the storage element and / or write a data value to the storage element. In some embodiments, each of the memory cells 102 may not include a separate selector and storage element, and have a configuration such that the memory cell still behaves as having a selector and a storage element (e.g., may include using materials that behave similarly to both the selector material and the storage element material). For ease of discussion, the bit lines 104, word lines 106, word line decoders 108, and bit line decoders 110 may be discussed. Figure 1 , but these designations are non-limiting. The scope of the present disclosure should be understood to cover memory cells 102 coupled to multiple access lines and accessed through corresponding decoders, wherein the access lines can be used to store data in the memory cells and read data from the memory cells 102. In addition, the memory device 100 may include other circuitry, such as biasing circuitry configured to bias the bit lines 104 or word lines 106 in corresponding directions. For example, the bit lines 104 can be biased with positive biasing circuitry, while the word lines 106 can be biased with negative biasing circuitry.

[0024] The bitline decoders 110 may be organized into a plurality of decoder groups. For example, the memory device 100 may include a first bitline decoder group 114 (e.g., a plurality of bitline decoders 110) and / or a second bitline decoder group 116 (e.g., a plurality of bitline decoders 110 of different groups). Similarly, the wordline decoders 108 may also be arranged into groups of wordline decoders 108, such as a first wordline decoder group 118 and / or a second wordline decoder group 120. When selecting a target memory cell 102A from the memory cells 102, the decoders may be used in combination with each other to drive the memory cell 102 (e.g., in pairs on either side of the wordline 106 and / or the bitline 104 and / or in pairs after the pairing). For example, the bitline decoder 110-3 may operate in conjunction with the bitline decoder 110'-3 and / or with the wordline decoders 108-0, 108'-0 to select the memory cell 102A. As may be understood herein, the decoder circuitry on either end of the word line 106 and / or the bit line 104 may be different.

[0025] Each of the bit lines 104 and / or word lines 106 may be metal traces disposed in the memory array 112 and formed of a metal such as copper, aluminum, silver, tungsten, etc. Thus, the bit lines 104 and word lines 106 may have a uniform resistance per length and a uniform parasitic capacitance per length so that the resulting parasitic load may increase uniformly per length. Note that the depicted components of the memory device 100 may include additional circuitry not specifically depicted and / or may be disposed in any suitable arrangement. For example, subsets of the word line decoders 108 and / or bit line decoders 110 may be disposed on different sides of the memory array 112 and / or on different physical sides of any plane that includes circuitry.

[0026] The memory device 100 may also include control circuitry 122. The control circuitry 122 may be communicatively coupled to the respective word line decoders 108 and / or bit line decoders 110 to perform memory operations, such as by causing the decoding circuitry (e.g., a subset of the word line decoders 108 and / or the bit line decoders 110) to generate a selection signal (e.g., a selection voltage and / or a selection current) for selecting a target of a memory cell. In some embodiments, a positive voltage and a negative voltage may be provided to the target of the memory cell 102 on one or more of the bit lines 104 and / or the word lines 106, respectively. In some embodiments, the decoder circuitry may provide biased electrical pulses (e.g., voltages and / or currents) to access the memory cells. The electrical pulses may be square pulses, or in other embodiments, other shaped pulses may be used. In some embodiments, the voltage provided to the access lines may be a constant voltage.

[0027] Activating the decoder circuit may enable an electrical pulse to be transmitted to the target of the memory cell 102, so that the control circuit 122 can access the data storage device of the target memory cell, such as reading from the data storage device or writing to the data storage device. After accessing the target of the memory cell 102, the data stored in the storage medium of the target memory cell can be read or written. Writing to the target memory cell may include changing the data value stored by the target memory cell. As previously discussed, the data value stored by the memory cell may be based on the threshold voltage of the memory cell. In some embodiments, the memory cell may be "set" to have a first threshold voltage, or may be "reset" to have a second threshold voltage. The memory cell that is set may have a lower threshold voltage than the memory cell that is reset. By setting or resetting the memory cell, different data values ​​may be stored by the memory cell. Reading the target of the memory cell 102 may include determining whether the target memory cell is characterized by a first threshold voltage and / or a second threshold voltage. In this way, the threshold voltage window may be analyzed to determine the value stored by the target of the memory cell 102. The threshold voltage window may be created by applying programming pulses with opposite polarity biases to the memory cells 102 (e.g., specifically, writing to the selector device (SD) material of the memory cells) and reading the memory cells 102 (e.g., specifically, reading the voltage stored by the SD material of the memory cells 102) using signals with a given (e.g., known) fixed polarity. In some embodiments, a select input 126 may be received from a host device 124, such as a host processor reading / writing data from / to the memory device 100, to cause the control circuitry 122 to access a particular memory cell 102 using corresponding select signals to the corresponding word line decoders 108 and bit line decoders 110. Furthermore, the control circuitry 122 may include a retry circuitry 128 that may be used to reduce threshold degradation by abandoning a portion of a read operation by reading data latched into the sense amplifier latches in a previous read operation without reading data from the memory cells 102 in a current read operation.

[0028] Figure 2 1 is a diagram illustrating a portion of a memory array 130 according to an embodiment of the present disclosure. Within the memory array 130, memory cells are positioned at the intersections of orthogonal lines. The memory array 130 may be a cross-point array including word lines 106 (e.g., 106-0, 106-1, ..., 106-N) and bit lines 104 (e.g., 104-0, 104-1, ..., 104-M). A memory cell 102 may be positioned at each of the intersections of the word lines 106 and the bit lines 104. The memory cell 102 may function in a dual-terminal architecture (e.g., where a particular word line 106 and bit line 104 combination serves as an electrode of the memory cell 102).

[0029] Each of the memory cells 102 may be a resistance variable memory cell, such as a resistance random access memory (RRAM) cell, a conductive bridge random access memory (CBRAM) cell, a phase change memory (PCM) cell, and / or a spin transfer torque magnetic random access memory (STT-RAM) cell, among other types of memory cells. Each of the memory cells 102 may include a memory element (e.g., a memory material) and a selector element (e.g., a selector device (SD) material) and / or a material layer that functionally replaces a separate memory element layer and a selector element layer. The selector element (e.g., SD material) may be disposed between a word line contact (e.g., a layer interface between a corresponding one of the word lines 106 and the memory material) and a bit line contact (e.g., a layer interface between a corresponding one of the bit lines 104 and the selector element) associated with a word line or a bit line forming the memory cell. When a read or write operation is performed on the memory cell, an electrical signal may be transmitted between the word line contact and the bit line contact.

[0030] The selector element may be a diode, a non-ohmic device (NOD), or a chalcogenide switching device, etc., or may be formed similarly to the underlying cell structure. In some examples, the selector element may include a selector material, a first electrode material, and a second electrode material. The memory element of the memory cell 102 may include a memory portion of the memory cell 102 (e.g., a portion that is programmable to different states). For example, in the resistance variable memory cell 102, the memory element may include a portion of the memory cell having a resistance that can be programmed to a specific level corresponding to a specific state in response to an applied programming voltage and / or current pulse. In some embodiments, the memory cell 102 may be characterized as a threshold type memory cell that is selected (e.g., activated) based on a voltage and / or current that exceeds a threshold associated with the selector element and / or the memory element. The embodiments are not limited to a specific resistance variable material or material associated with the memory element of the memory cell 102. For example, the resistance variable material may be a chalcogenide formed from various doped or undoped chalcogenide-based materials. Other examples of resistance variable materials that may be used to form memory elements include binary metal oxide materials, colossal magnetoresistive materials, and / or various polymer-based resistance variable materials, among others.

[0031] In operation, the memory cells 102 may be programmed by applying a voltage (e.g., a write voltage) across the memory cells 102 via selected word lines 106 and bit lines 104. A sensing (e.g., a read) operation may be performed to determine the state of the one or more memory cells 102 by sensing current. For example, current may be sensed on one or more bit lines 104 / one or more word lines 106 corresponding to the respective memory cells 102 in response to a particular voltage applied to the selected bit lines 104 / word lines 106 forming the respective memory cells 102.

[0032] As illustrated, the memory array 130 may be arranged in a cross-point memory array architecture (e.g., a three-dimensional (3D) cross-point memory array architecture) that extends along any direction (e.g., x-axis, y-axis, z-axis). The multi-stack cross-point memory array 130 may include a number of consecutive memory cells (e.g., 102B, 102C, 102D) disposed between alternating (e.g., interleaved) stacks of word lines 106 and bit lines 104. The number of stacks may be expanded, or may be reduced, and should not be limited to the volumes or arrangements depicted. Each of the memory cells 102 may be formed between a word line 106 and a bit line 104 (e.g., between two access lines) such that a respective one of the memory cells 102 may be directly electrically coupled (e.g., electrically coupled in series) with its respective bit line 104 and word line 106 pair and / or formed by electrodes (e.g., contacts) made of respective metal portions of the respective bit line 104 and word line 106 pair. For example, memory array 130 may include a three-dimensional matrix of individually addressable (e.g., randomly accessible) memory cells 102 that may be accessed for data operations (e.g., sensing and writing) at a granularity as small as a single storage element and / or multiple storage elements. In some cases, memory array 130 may include more than Figure 2 More or fewer bit lines 104, word lines 106, and / or memory cells 102 are shown in the examples of FIG. Each stack can include one or more memory cells 102 aligned in the same plane.

[0033] As previously described, reset read disturbance (RDR) may degrade the corresponding threshold. Specifically, the second threshold voltage corresponding to reset may be particularly susceptible to threshold voltage degradation due to RDR. As previously described, this degradation may be at least partially attributed to the destruction of polarization effects by RDR. In addition, the amount of degradation may be proportional to the magnitude of the polarization effect destroyed. In addition, when read disturbance occurs on a group, the first threshold voltage corresponding to the group may be less susceptible to such degradation or even immune to such degradation, but may obtain some benefits from threshold voltage degradation mitigation. In RDR, the memory device 100 may have a minimum read-to-read tolerance (e.g., 80ns or 150ns) for the memory array 130, which may limit the number of RDR counts (e.g., 130k or 1M) before the cell fails repeatedly. As previously described, this threshold degradation may depend on the mR2R duration and / or the frequency of accessing the partition (and / or the address within the partition) in the read disturbance.

[0034] Figure 31 is a timing diagram 140 of a command sequence used in the memory device 100. The timing diagram 140 shows a command 142 and a command 144. For example, the command 142 and the command 144 may be read commands. Each of the commands 142, 144 may specify a partition and an address (including one or more rows and / or columns). For example, the command 142 and the command 144 may specify the same address within the same partition. The mR2R duration 146 may specify the minimum required time delay between a first address and a second address (e.g., the first address or another address) in a read partition. As previously discussed, a relatively short mR2R duration 146 may exacerbate RDR-based VTH degradation without mitigation.

[0035] Figure 4 1 is a block diagram of a read process 150. A user interface 152 of the memory device 100 receives a clock 154 and a read command 156. The user interface 152 may be included in the control circuit 122, where the clock 154 and / or the read command 156 are received from the host device 124. The read command 156 may include any read command, such as a command address cycle (CAC) bit (e.g., 8 bits). After receiving the read command 156, the user interface 152 sends a signal to one or more array decoders 158, such as the word line decoder 108 and the bit line decoder 110. The signal specifies the address and data to the array decoder 158 to enable reading of the target memory cell of the memory array 130.

[0036] In addition to the signals to the one or more array decoders 158, the user interface 152 sends signals to the partition controller 160 corresponding to the target of the read command 156. The partition controller 160 controls a series of events for a specific partition specified in the read command 156 and controls the assertion of positive and / or negative voltages based on the polarity of the readout. Specifically, the partition controller 160 controls the power supply and mirror 162 used to propagate voltage and / or current to the memory array 130 for a read operation. The partition controller 160 also controls enabling the sense amplifier 164 to sense electrical parameters from the memory cells of the memory array 130 and amplify the logic level so that the data in the memory cells can be correctly interpreted. The partition controller 160 controls the timing and uses the sense enable signal 166 to implement sensing in the sense amplifier 164. When the data from the sense amplifier 164 is ready to be latched, the partition controller 160 also uses the latch enable signal 170 to enable the sense amplifier latch 168 to latch the value from the sense amplifier 164.

[0037] Load circuitry 171 is used to load the latched value in sense amplifier latch 168 to data bus 172 using enable data drive signal 174, which is timed to load the data after sensing of the memory cell has been completed and latched into sense amplifier latch 168. The data on data bus 172 may then be transmitted back to host device 124.

[0038] Using the read process 150 without mitigating the VTH degradation due to RDR may cause the memory device 100 to operate differently than intended. Figure 5 1 is a graph 180 comparing possible demarcation voltages 182 (including stress voltage level 183) to raw error rates 184 (e.g., before error correction codes are applied) for different RDR counts, each RDR count corresponding to lines 186, 188, 190, 192, 194, and 196. For example, each line may correspond to a different number of rapid consecutive reads. For example, line 186 may correspond to 130k reads, line 188 may correspond to 40k reads, line 190 may correspond to 10k reads, line 192 may correspond to 1k reads, line 194 may correspond to 100 reads, and line 196 may correspond to 2 reads. In general, an increase in RDR is associated with a higher error rate between the stress voltage level 183 and a certain demarcation voltage level 198. In addition to the VTH degradation shown, shorter mR2R durations may result in higher error rates, especially for higher demarcation voltages 182.

[0039] In some embodiments, the sense amplifier latches 168 can retain data even when the memory device 100 and / or the partitions are in an idle mode. Thus, as discussed below, in at least some scenarios, data remaining in the sense amplifier latches 168 from a previous read operation can be retransmitted from the sense amplifier latches 168 to the data bus 172 without using a memory device such as a memory device 100 or a partition. Figure 4 The read operation deployed in the read process 150 re-engages the array decoder 158, the partition controller 160 and / or the power supply and mirror 162.

[0040] Figure 6 2 is a flow chart of a process 220 for mitigating VDM threshold degradation due to RDR by reusing data stored in sense amplifier latches between reads. As illustrated, the process 220 includes receiving a read command (block 222). For example, the read command may be received at the control circuit 122 (e.g., the user interface 152). Figure 4156 of the read command 156. The retry circuitry 128 in the control circuitry 122 then determines whether the previously used address is to be reused in the reuse of the address with the direct latch read (block 224). For example, when the previous read used the same address (e.g., row and column) and partition, the previous address may be reused with the latch read. In some embodiments, the retry circuitry 128 may take into account other considerations for determining whether to read from the sense amplifier latches 168 without a new latch into the sense amplifier latches 168. For example, if the re-read is based on an error correction code (ECC) failure (e.g., a read retry), then the new CAC bit may indicate that the re-read is to be performed without reading from the sense amplifier latches 168 by reusing an address without reading data from the memory array 130. Figure 4 Similarly, a VDM change may also invoke a new run of the read process. When an address is reused, the retry circuit system 128 causes the data latched in the sense amplifier latch 168 to be reused without rerunning the read process (block 226). By reusing an address without performing a read process, the memory array 130 may be disabled along with the array decoder 158, the power supply and mirror 162 and its multiplexers, the partition controller 160, and the sense amplifiers 164, while extending the read-to-read duration. Additionally, by reusing addresses without causing memory cells to quickly reach voltage levels, the memory device 100 may increase the life of components of the memory device 100 before they fail. In addition to extending the duration between RDRs to the memory array 130 to mitigate VTH degradation, read power consumption used in a read operation is also reduced. If the address will not be reused, the retry circuit system 128 sends the memory device 100 to continue as described above. Figure 4 The read process described in the read process 150 of FIG. 1 may be indicated (block 228). For example, the retry circuit system 128 may send a signal to the partition controller 160 and / or the array decoder 158 to continue. Figure 4 The reading process 150 discussed in .

[0041] Figure 7 is with Figure 41 is a simplified block diagram of a read operation 250 that is identical to the read process 150 of FIG. 1 , except that the read operation 250 utilizes a retry circuit system 252 (e.g., the retry circuit system 128) between the user interface 152 and the array decoder 158 and the partition controller 160. As previously described, when an address is to be reused without using the entire read operation used in the read process 150, the retry circuit system 252 inhibits signals from the array decoder 158 and the partition controller 160 to enable the array decoder 158 and the partition controller 160 to remain at least partially inactive. This inactive state also occurs for downstream devices, such as the power supply and mirror 162, the memory array 130, and the sense amplifier 164. In addition, when the address is to be reused, the retry circuitry 252 sends a retry signal 254 to the user interface 152 to send the enable data drive signal 174 from the sense amplifier latch 168, even when the array decoder 158, the partition controller 160, the power supply and mirror 162, the memory array 130, and the sense amplifier 164 are inactive / skipping the read operation. When the address is not to be reused (i.e., new data is to be latched into the sense amplifier latch 168), the retry circuitry 252 causes the remainder of the read operation to proceed as described with respect to Figure 4 The reading process 150 continues as described.

[0042] Figure 81 is a schematic diagram of a retry circuit system 300 that may be included in the retry circuit system 128 and / or the retry circuit system 252. The retry circuit system 300 may be replicated in the control circuit 122 for different partitions of the memory device 100. For example, each partition may have a dedicated retry circuit system 300. Thus, the retry circuit system 300 is used to determine whether to reuse an address for a partition, while other instances of the retry circuit system 300 may be used for other partitions. The retry circuit system 300 includes a command check circuit system 302, a row check circuit system 304, a column check circuit system 306, a VDM check circuit system 308, a retry latch system 310, and an intermediate enable signal 314, which are received at a multiplexer 312 to control whether an output enable signal 316 (or other activation of the memory array 130) will be used to initiate a read process or whether a read address will be reused. The command checking circuitry 302 may check whether the incoming command 322 corresponds to an operation (e.g., a read operation) in which an address may be reused and / or has not changed since the last operation. The command checking circuitry 302 also receives a delayed clock 324. The delayed clock 324 is delayed to give time to perform a check of the command in one or more command flip-flops 326 without overwriting. The number of command flip-flops 326 (e.g., 2) may be equal to the number of bits in the command 322. The command checking circuitry 302 may include an XNOR 328 (or other comparator) that receives the input of the command flip-flops 326 as the current command 322 at a first input of the XNOR 328. The XNOR 328 may have an output 327 from the command flip-flops 326 as a second input received as a previous command 322. The XNOR 328 outputs an indication 330 of whether the command 322 has changed with each clock cycle of the delayed clock 324. In other words, in the illustrated embodiment, the indication 330 indicates whether the command has changed. Alternatively, command 322 may be a flag based on the command received from host device 124 that indicates whether the received command is related to an operation (eg, a read) in which addresses may be reused.

[0043] The row check circuit system 304 may be used to check whether the row address 332 is used again in a read operation. The row check circuit system 304 includes one or more row flip-flops 334. The number of row flip-flops 334 may be equal to the number of bits in the row address 332 (e.g., 13), with each row flip-flop 334 coupled to a corresponding bit of the row address 332. Each row flip-flop 334 outputs an output 336 indicating the same bit in the previous row address. Each output 336 is coupled to an XNOR 338 (or other comparator) along with the same bit of the row address 332. If the row address 332 has not changed between the previous read operation and the current read operation, then each of the XNORs 338 outputs an indication 340 of no change with a logic high when its corresponding input carries the same value. Otherwise, the indication 340 is a logic low, thereby preventing reading from the sense amplifier latch 168 without re-latching the data from the memory array 130 via the sense amplifier 164.

[0044] The column check circuitry 306 may be used to check whether the column address 341 is used again in a read operation. The column check circuitry 306 includes one or more column flip-flops 342. The number of column flip-flops 342 may be equal to the number of bits in the column address 341 (e.g., 13), with each column flip-flop 342 coupled to a corresponding bit of the column address 341. Each column flip-flop 342 outputs an output 344 indicating the same bit in the previous column address. Each output 344 is coupled to an XNOR 346 (or other comparator) along with the same bit of the column address 341. If the column address 341 has not changed between the previous read operation and the current read operation, then each of the XNORs 346 outputs an indication 348 of no change with a logic high when its corresponding input carries the same value. Otherwise, the indication 348 is a logic low, thereby preventing reading from the sense amplifier latch 168 without re-latching the data from the memory array 130 via the sense amplifier 164.

[0045] The VDM check circuit system 308 can be used to check whether the VDM 350 is used again in a read operation. The VDM 350 can be used to specify the VDM for the read operation. The VDM check circuit system 308 includes one or more VDM flip-flops 352. The number of VDM flip-flops 352 can be equal to the number of bits in the VDM 350 (e.g., 2), wherein each of the VDM flip-flops 352 is coupled to a corresponding bit of the VDM 350. Each VDM flip-flop 352 outputs an output 354 indicating the same bit in the previous VDM setting. Each output 354 is coupled to an XNOR 356 (or other comparator) together with the same bit of the VDM 350. If the VDM 350 has not changed, then when its corresponding input carries the same value, each of the XNORs 356 outputs an indication 358 of no change with a logic high. Otherwise, the indication 358 is a logic low, thereby preventing reading from the sense amplifier latch 168 without re-latching the data from the memory array 130 via the sense amplifier 164.

[0046] The retry latch 310 may be used to ensure that reuse of addresses is not used for a particular operation. The retry flag 318 may be used to indicate that reuse of addresses that may be latched into the retry latch 310 with the non-delayed clock 320 will not occur. For example, the retry flag 318 may be set to prevent reuse when the read operation is due to an ECC failure. The enable signal 314 may be used to initiate internal components in the array decoder 158, the partition controller 160, the power supply and mirror 162, the memory array 130, and / or the sense amplifier 164.

[0047] Using the retry circuitry 300, the memory device 100 may forgo initializing internal elements in the array decoder 158, the partition controller 160, the power supply and mirror 162, the memory array 130, and / or the sense amplifier 164 when the read of the partition is the same column and row and retry is not disabled by blocking the assertion of the enable signal 316. In these cases, the memory device 100 may read directly from the sense amplifier latch 168 without re-latching the data from the memory array 130 via the sense amplifier 164. Otherwise, the retry circuitry 300 may use the enable signal 316 to initialize internal elements in the array decoder 158, the partition controller 160, the power supply and mirror 162, the memory array 130, and / or the sense amplifier 164, thereby causing the data to be latched from the sense amplifier 164 but then loaded onto the data bus 172.

[0048] Although the present disclosure may have various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the present disclosure is not intended to be limited to the specific forms disclosed. Rather, the present disclosure is intended to cover all modifications, equivalents, and alternatives that fall within the spirit and scope of the present disclosure as defined by the appended claims.

[0049] The techniques presented and claimed herein are cited and applied to substantial objects and specific examples that demonstrably improve the actual nature of the art and are thus not abstract, intangible, or purely theoretical. In addition, if any claim appended to the end of this specification contains one or more elements indicated as "means for performing [function] ..." or "steps for performing [function] ...", then such elements should be interpreted in accordance with 35 U.S.C. 112(f). However, for any claim containing elements indicated in any other manner, it is intended that such elements not be interpreted in accordance with 35 U.S.C. 112(f).

Claims

1. A memory device, comprising: a plurality of memory cells configured to store data; one or more word line decoders; one or more bit line decoders; and control circuitry comprising retry circuitry configured to: receiving a read command having a target address; determining that the data in the target address will be reused from a sense amplifier latch from a previous read operation; and Causing the data to be read from the sense amplifier latches from the previous read operation by reusing the target address, wherein reusing the target address includes bypassing rereading the data from the plurality of memory cells into the sense amplifier latches and disabling the one or more word line decoders and the one or more bit line decoders for a current read operation.

2. The memory device of claim 1, wherein the target address comprises a row address and a column address.

3. The memory device of claim 2 , wherein the retry circuitry comprises a row check circuitry configured to check whether the row address for the current read operation matches the row address for the previous read operation, and the reuse of the target address is based at least in part on the row address for the current read operation matching the row address for the previous read operation.

4. The memory device of claim 3, wherein the row check circuitry comprises: a flip-flop configured to receive the row address for the current read operation and to output the row address for the previous read operation; and A comparator is configured to receive the row address for the current read operation and the row address for the previous read operation and determine whether the row address for the current read operation matches the row address for the previous read operation.

5. The memory device of claim 4, wherein the comparator comprises an XNOR gate.

6. A memory device according to claim 2, wherein the retry circuit system includes a column check circuit system, which is configured to check whether the column address for the current read operation matches the column address for the previous read operation, and the reuse of the target address is based at least in part on the column address for the current read operation matching the column address for the previous read operation.

7. The memory device of claim 6, wherein the column check circuitry comprises: a flip-flop configured to receive the column address for the current read operation and output the column address for the previous read operation; and A comparator is configured to receive the column address for the current read operation and the column address for the previous read operation and determine whether the column address for the current read operation matches the column address for the previous read operation.

8. The memory device of claim 1 , wherein the retry circuitry comprises a demarcation voltage checking circuitry configured to determine whether a demarcation voltage has changed between the previous read operation and the current read operation, and the reuse of the target address is based at least on the fact that the demarcation voltage has not changed between the previous read operation and the current read operation.

9. The memory device of claim 8, wherein the demarcation voltage check circuitry comprises: a flip-flop configured to receive an indication of the demarcation voltage for the current read operation and to output an indication of the demarcation voltage for the previous read operation; and A comparator is configured to receive the indication of the demarcation voltage for the current read operation and the indication of the demarcation voltage for the previous read operation and determine that the demarcation voltage has not changed between the previous read operation and the current read operation.

10. The memory device of claim 1, wherein the retry circuitry comprises a retry flip-flop configured to latch a retry signal indicating whether the data is to be re-read from the plurality of memory cells into the sense amplifier latch for the current read operation using bypass.

11. The memory device of claim 10, wherein the retry signal is configured to indicate that the previous read operation has failed due to an error correction code error.

12. The memory device of claim 1, wherein the retry circuitry is configured to: receiving a subsequent read command for a subsequent read operation having a second target address; determining that the second target address does not match the target address; activating a power source for the plurality of memory cells; and Data from the second target address is latched into a corresponding sense amplifier latch using the power supply as part of the subsequent read operation.

13. The memory device of claim 1, wherein the plurality of memory cells are organized into a plurality of partitions, wherein the control circuitry includes an instance of the retry circuitry for each of the plurality of partitions.

14. A memory reading method, comprising: receiving a first read command corresponding to a first read operation; receiving a second read command corresponding to a second read operation subsequent to the first read operation; determining rows, columns, and partitions corresponding to both the first read operation and the second read operation; and Based at least in part on the determination of the rows, columns, and partitions for both the first read operation and the second read operation, reading data from sense amplifier latches for the second read operation without loading the data from a memory array to the sense amplifier latches and without decoding word lines and bit lines of the memory array during the second read operation.

15. The memory read method of claim 14, wherein reading data from the sense amplifier latch for the second read operation without loading the data from the memory array to the sense amplifier latch during the second read operation comprises maintaining an inactive state of the memory array during the second read operation.

16. The memory reading method of claim 15, wherein maintaining the inactive state of the memory array comprises maintaining an inactive state of an array decoder of the memory array and maintaining an inactive state of a power supply of the memory array during the second reading operation.

17. The memory read method of claim 15, wherein maintaining the inactive state of the memory array comprises maintaining an inactive state of a partition controller during the second read operation, and wherein the partition controller is configured to control timing of read operations of the partitions.

18. A memory device comprising: a plurality of memory cells configured to store data; a plurality of sense amplifiers configured to read from corresponding memory cells of the plurality of memory cells; a plurality of sense amplifier latches configured to latch outputs from corresponding sense amplifiers of the plurality of sense amplifiers; and control circuitry comprising retry circuitry configured to: receiving a first read command having a target address; in response to receiving the first read command, sensing data from the target address using a sense amplifier from among the plurality of sense amplifiers; in response to sensing the data, latching the data from the sense amplifier into a sense amplifier latch of the plurality of sense amplifier latches; driving the data from the sense amplifier latch onto a data bus based at least in part on latching the data and the first read command; receiving a second read command having the target address; and Based at least in part on the second read command following the first read command, the data is redriven from the data from the sense amplifier latch without re-latching the data from the sense amplifier and without decoding word lines and bit lines of the plurality of memory cells.

19. The memory device of claim 18, wherein redriving the data from the data from the sense amplifier latch without relatching the data from the sense amplifier comprises redriving the data from the sense amplifier latch without resensing the data from the target address.

20. The memory device of claim 19, wherein the retry circuitry is configured to: receiving a third read command subsequent to the second read command, wherein the third read command has a target address different from the target address; in response to receiving the third read command, sensing additional data from the different target address using another sense amplifier of the plurality of sense amplifiers; in response to sensing the additional data, latching the additional data from the another sense amplifier into another sense amplifier latch of the plurality of sense amplifier latches; and Based at least in part on latching the additional data and the third read command, driving the additional data from the other sense amplifier latch onto the data bus.

21. The memory device of claim 18, wherein the plurality of memory cells are arranged into a plurality of partitions, and the first read command, the second read command, and the retry circuitry correspond to a partition of the plurality of partitions.

22. The memory device of claim 21 , wherein the control circuitry is configured to: receiving a third read command subsequent to the second read command, wherein the third read command has the target address for a different partition among the plurality of partitions; in response to receiving the third read command, sensing additional data from the target address of the different partition using another sense amplifier of the plurality of sense amplifiers; in response to sensing the additional data, latching the additional data from the another sense amplifier into another sense amplifier latch of the plurality of sense amplifier latches; and Based at least in part on latching the additional data and the third read command, driving the additional data from the other sense amplifier latch onto the data bus.

23. The memory device of claim 18, wherein the retry circuitry is configured to: receiving a third read command subsequent to the second read command, wherein the third read command has the target address; in response to receiving the third read command, sensing additional data from the target address using the sense amplifier; in response to sensing the additional data, latching the additional data from the sense amplifier into the sense amplifier latch; and Based at least in part on latching the additional data and the third read command, the additional data is driven from the sense amplifier latch onto the data bus.

24. The memory device of claim 23, wherein the third read command corresponds to a re-read of the target address based on an error correction code (ECC) based failure.

25. The memory device of claim 23, wherein a demarcation voltage for the memory device has changed between the second read command and the third read command.

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