Output module circuit of integrated circuit chip, chip and method for chip packaging

Abstract

The present invention belongs to the technical field of integrated circuit manufacturing, and specifically discloses an output module circuit of an integrated circuit chip, including: a first transistor, the first transistor having a first control end, a first current inflow end, and a first current outflow end; the first current inflow end is connected to a power supply; a second transistor, the second transistor having a second control end, a second current inflow end, and a second current outflow end; the second current outflow end is connected to the ground; the first control end and the second control end are used for connecting to a signal to be output. The advantages of the present invention are that the number of devices used in the output module circuit is reduced, the layout area is reduced, and the cost is lowered.

Description

Technical Field

[0001] The present invention relates to the field of integrated chip manufacturing technology, and particularly relates to an output module circuit for an integrated circuit chip, a chip, and a method for chip packaging. Background Art

[0002] Currently, there are usually two driving methods for the output pins of an integrated circuit chip: Push-Pull Output and Open Drain Output.

[0003] In order to save the cost of Tape Out, each manufacturer often designs the output module circuit of the chip to have both Push-Pull Output and Open Drain Output modes when designing the chip. During actual production, according to the customer's requirements, one of the output modes is selected and bonded to the package frame (pin), and the other output mode is redundant and not used. Therefore, in the existing packaging technology, one output path is wasted. At the same time, the wasted output path also occupies the chip layout area, resulting in double cost waste. Summary of the Invention

[0004] To solve the above defects and further save production costs, the present invention proposes an output module circuit for an integrated circuit chip, a chip, and a method for chip packaging, and proposes an output module circuit that can have both Push-Pull Output and Open Drain Output modes. Compared with the prior art, it reduces redundant devices, the operation process is simple when packaging the chip, and it is very friendly to existing production equipment without the need to modify the existing production equipment.

[0005] The present invention first provides an output module circuit for an integrated circuit chip, including:

[0006] A first transistor, the first transistor having a first control end, a first current inflow end, and a first current outflow end; the first current inflow end is connected to a power supply;

[0007] A second transistor, the second transistor having a second control end, a second current inflow end, and a second current outflow end; the second current outflow end is connected to the ground;

[0008] The first control end and the second control end are used to connect to a signal to be output.

[0009] For the above output module circuit, wherein, the integrated circuit chip includes a die and a package frame, the die is located in the package frame, and the package frame further includes pins for connecting to the die.

[0010] The above output module circuit, wherein the first current outflow terminal serves as the first connection point connected to the pin; the second current inflow terminal serves as the second connection point connected to the pin.

[0011] The above output module circuit, wherein when the second connection point is connected to the pin, the output mode of the output module circuit is the open-drain output mode.

[0012] The above output module circuit, wherein when the first connection point and the second connection point are connected to the same pin, the output mode of the output module circuit is the push-pull output mode.

[0013] The above output module circuit, wherein the first transistor and the second transistor are respectively a PMOS transistor and an NMOS transistor, or are respectively an NPN-type transistor and a PNP-type transistor.

[0014] The above output module circuit, wherein the first transistor and the second transistor are triodes or field-effect transistors.

[0015] The above output module circuit further includes an electrostatic protection unit.

[0016] Compared with the prior art, the output module circuit proposed by the present invention can reduce the number of output transistors and the electrostatic protection module accordingly while reducing the number of output transistors, thereby significantly reducing the layout area and also reducing the wiring difficulty. For integrated circuit chips in mass production, the economic cost is greatly saved. Secondly, the present invention also proposes an integrated circuit chip, the chip includes a core circuit, the above output module circuit and a package frame; wherein, the package frame includes pins;

[0017] During packaging, according to the connection relationship between the first connection point and the second connection point in the output module circuit and the pin, it is determined whether the output signal of the core circuit adopts the push-pull output mode or the open-drain output mode.

[0018] In the above chip, when the second connection point is connected to the pin, the output mode of the output module circuit is the open-drain output mode.

[0019] In the above chip, when the first connection point and the second connection point are connected to the same pin, the output mode of the output module circuit is the push-pull output mode.

[0020] Compared with the prior art, the integrated circuit chip provided by the present invention can directly use the existing packaging process and packaging equipment during the process of packaging the die into a finished chip, and has good adaptability to the subsequent processes.

[0021] Based on the same inventive concept, the present invention also provides a packaging method, which uses the above output module circuit for chip packaging, including connecting the first connection point and the second connection point in the output module circuit to the pins of the packaging frame according to a predetermined output mode;

[0022] When the predetermined output mode is the open-drain output mode, connect the second connection point to the pin;

[0023] When the predetermined output mode is the push-pull output mode, connect the first connection point and the second connection point to the same pin simultaneously.

[0024] Compared with the prior art, the packaging method provided by the present invention is simple to operate, and the output mode can be changed by bonding the connection points of different output module circuits. Description of the Drawings

[0025] Figure 1 is a circuit schematic diagram of the push-pull output mode;

[0026] Figure 2 is a circuit schematic diagram of the open-drain output mode;

[0027] Figure 3 is a circuit schematic diagram of the open-drain output mode with an external pull-up resistor;

[0028] Figure 4 is a circuit schematic diagram of the output module circuit in the prior art;

[0029] Figure 5 is a schematic diagram of an embodiment in which the output module circuit is bonded into the open-drain output mode in the present invention;

[0030] Figure 6 is a schematic diagram of an embodiment in which the output module circuit is bonded into the push-pull output mode in the present invention. Detailed Description of the Embodiment

[0031] The following specific embodiments illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. Although the description of the present invention will be introduced in conjunction with the preferred embodiments, this does not mean that the features of this invention are limited to this implementation manner. On the contrary, the purpose of introducing the invention in conjunction with the implementation manner is to cover other alternatives or modifications that may be extended based on the claims of the present invention. In order to provide a deep understanding of the present invention, many specific details will be included in the following description. The present invention can also be implemented without these details. In addition, in order to avoid confusing or obscuring the key points of the present invention, some specific details will be omitted in the description. It should be noted that, without conflict, the embodiments and features in the embodiments of the present invention can be combined with each other.

[0032] It should be noted that in this specification, similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings and is defaulted to the same definition.

[0033] The key idea of the inventive concept of the present invention lies in changing the structure of the existing conventional output module circuit, improving the utilization rate of the output transistors in the output module circuit, reducing the corresponding components, so as to reduce costs.

[0034] To make the objectives, technical solutions and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to the drawings.

[0035] Figure 1 The shown is a circuit schematic diagram of the push-pull output mode. The push-pull output mode includes a pair of complementary transistors V1 and V2. For example, transistor V1 is a PMOS transistor while transistor V2 is an NMOS transistor. Or for example, transistor V1 is an NPN-type transistor while transistor V2 is a PNP-type transistor. In the figure, under the control of the input signal VIN, transistors V1 and V2 always maintain a state where one is conducting and the other is cut off. Therefore, regardless of whether the output signal VOUT is high level or low level, the push-pull output mode has a strong driving ability.

[0036] However, when the output signals VOUT of two push-pull output modes are shorted together, if one VOUT outputs a high level (i.e., transistor V1 of the first push-pull structure is conducting) and the other VOUT outputs a low level (i.e., transistor V2 of the second push-pull structure is conducting), then, on the premise of ignoring the junction resistance of the transistors themselves, transistor V1 of the first push-pull structure and transistor V2 of the second push-pull structure will form an approximately zero-resistance path, and current can directly flow from the power supply to the ground, which may cause damage to the output port.

[0037] Figure 2 The shown is a circuit schematic diagram of the open-drain output mode. Those of ordinary skill in the art should know that the open-drain output mode and the open-collector output mode are two similar output modes, and their difference lies only in that the former uses MOS transistors while the latter uses bipolar transistors. In fact, the "drain" in the open-drain output mode refers to the drain of the MOS transistor, and the "collector" in the open-collector output mode refers to the collector of the bipolar transistor. The open-drain output mode and the open-collector output mode are both output modes corresponding to the push-pull output mode. Since MOS transistors are used more frequently in actual work, in order to simplify the writing in the present invention, the open-drain output mode is used to refer to both the open-drain output mode and the open-collector output mode at the same time.

[0038] As Figure 3As shown, the open-drain output mode itself does not have the function of driving a high level output. It is necessary to externally connect a pull-up resistor Rup to the output signal VOUT to output a high level. When the output signals VOUT of two open-drain output modes are shorted together, when both output signals VOUT are high levels, the shorted output signal is a high level; when any one or both of the two output signals VOUT are low levels, the shorted output signal is a low level, and there will be no problems such as current backflow and chip damage that may occur in the push-pull output mode.

[0039] Since Figure 1 the push-pull output mode shown and Figure 2 、 3 the open-drain output mode shown are the two most commonly used output modes. It is possible that the same core circuit (i.e., a die that implements a predetermined function) may sometimes require the open-drain output mode and sometimes require the push-pull output mode under different requirements. In order to save design costs, chip designers often configure two output modes for one output signal of the core circuit, as Figure 4 shown. When it is determined which output mode each output signal of the core circuit needs respectively, the manufacturer bonds the connection point of the push-pull output mode or the open-drain output mode to the output pin OUT of the chip package frame according to this need. The other unnecessary output mode is left idle in the package frame (chip).

[0040] Figure 4 The circuit schematic diagram of the output mode circuit block is shown. Among them, it includes a core circuit 1 and an output module circuit 2'. Among them, the core circuit 1 shows one output signal, and this one output signal is connected to the input end of the push-pull output module circuit 21 and the input end of the open-drain output module circuit 23 at the same time. That is to say, in the Figure 4 shown die state, in the output module circuit 2' configured for one output signal of the core circuit 1, it includes two output circuits with different performances. However, not all of these two output circuits are useful during the chip packaging stage. During the process of packaging the die into a finished chip, only one of the output ends of the push-pull output module circuit 21 and the output end of the open-drain output module circuit 23 can be selected to be bonded to the pin in the package frame. Therefore, in the illustrated circuit diagram, there is always one redundant output module circuit and the anti-static (ESD, Electro-Static Discharge) module 22 supporting this module.

[0041] Figure 5 and Figure 6 respectively show the schematic diagram of the embodiment in which the output module circuit is bonded into the open-drain output mode and the schematic diagram of the embodiment in which the output module circuit is bonded into the push-pull output mode of the present invention.

[0042] Among them, the output module circuit 2 is first improved. As shown in the figure, the output module circuit 2 includes a first transistor V1 and a second transistor V3. Among them, the first transistor V1 is a P-channel MOS transistor, and the second transistor V3 is an N-channel MOS transistor. Those of ordinary skill in the art know that the first transistor V1 and the second transistor V3 can also be a pair of complementary triodes. The gate (G pole) of the first transistor V1 is connected to an output signal VIN of the core circuit 1, the source (S pole) is connected to the power supply, and the drain (D pole) is temporarily suspended for connection to the first connection point J1. The gate of the second transistor V3 is connected to an output signal VIN of the core circuit 1, the drain is temporarily suspended for connection to the second connection point J2, and the source is connected to the ground.

[0043] In addition, the output module circuit 2 further includes an ESD module 22, and the ESD module 22 is connected between the drain of the second transistor V3 and the second connection point J2.

[0044] Figure 5 and Figure 6 A package frame 3 including the die is also shown. The die includes a core circuit 1 and an output module circuit 2, which has realized all the functions related to the electrical performance of the integrated circuit. The package frame 3 is used to provide housing protection and pins for soldering (electrical connection).

[0045] According to Figure 5 As shown in the figure, during packaging, the second connection point J2 is bonded to the pin OUT on the package frame 3, that is, the second connection point J2 is made conductive with the pin OUT on the package frame 3, so that the output signal VIN of the core circuit can be output to the pin OUT for use. In this bonding method, the pin OUT is in the open-drain output mode. Specifically, when the pull-up resistor Rup (see Figure 3 ) is externally connected to the pin OUT, if the output signal VIN of the core circuit turns off the second transistor V3, at this time, the second transistor V3 is equivalent to a resistor. Since this equivalent resistor is much larger than the externally connected pull-up resistor Rup, the current flows from the externally connected power supply through the pull-up resistor Rup, then flows into the second transistor V3 from the drain of the second transistor V3, and flows out of the second transistor V3 from the source of the second transistor V3, and the pin OUT outputs a high level; if the output signal VIN of the core circuit turns on the second transistor V3, at this time, the equivalent resistor of the second transistor V3 is much smaller than the pull-up resistor Rup, then the pin OUT is approximately connected to the ground and outputs a low level.

[0046] According to Figure 6As shown in the figure, during encapsulation, both the first connection point J1 and the second connection point J2 are bonded to the pin OUT on the encapsulation frame 3. That is to say, the first connection point J1, the second connection point J2, and the pin OUT are electrically connected to each other. Specifically, when the first connection point J1 and the second connection point J2 are conducting, the drain of the first transistor V1 is connected to the drain of the second transistor V3. In this bonding method, since the first transistor V1 is a P-channel MOS transistor and the second transistor V3 is an N-channel MOS transistor, and the two are a pair of complementary MOS transistors, the pin OUT is in a push-pull output mode. At this time, if the output signal VIN of the core circuit turns on the first transistor V1 and turns off the second transistor V3, the pin OUT outputs the power supply voltage, and the current flows from the power supply through the source and drain of the first transistor V1 to the pin OUT; if the output signal VIN of the core circuit turns off the first transistor V1 and turns on the second transistor V3, the pin OUT is directly connected to the ground and outputs a low level. That is to say, through the output module circuit 2 proposed by the present invention and Figure 6 the bonding method shown, this embodiment realizes the push-pull output function of the push-pull output module circuit 21 as shown in Figure 4 .

[0047] The output module circuit 2 proposed by the present invention Figure 4 compared with the output module circuit 2' shown reduces one transistor V2, but also realizes the function of selectable output mode for the same die. The redundant devices on the die are reduced, which can save economic costs, and the change of this circuit structure does not affect the upstream and downstream processes and has little impact on production. Taking the CMOS 180nm manufacturing process as an example, since the size of the transistors (output transistors) used in the output module circuit 2 is generally large, the layout area of the output module circuit with both complete push-pull output and open-drain output forms usually exceeds 150um * 150um. Since the push-pull output structure and the open-drain output structure both contain NMOS with the same structural size, the present invention effectively multiplexes the NMOS in the two output structures by selecting different bonding methods during encapsulation, reduces the number of large-size output transistors used, and at the same time reduces the corresponding ESD protection module, effectively reducing the area of the output module circuit by nearly 1 / 3, optimizing the layout design and saving costs. According to Figure 5 and Figure 6In the encapsulation reliability verification of the chip encapsulated by the shown solution, only the encapsulation bonding solution of the push-pull output structure needs to be verified, and there is no need to verify the encapsulation bonding solution of the open-drain output structure. For consumer electronics with the lowest encapsulation requirements, the encapsulation structure needs to undergo at least 168 hours of reliability verification. The present invention effectively reduces the total duration of the product encapsulation reliability verification for the two output structures and saves the verification cost. In the specification provided herein, a large number of specific details are described. However, it can be understood that the embodiments of the present invention can be practiced without these specific details. In some instances, well-known methods, structures, and technologies are not shown in detail so as not to obscure the understanding of this specification.

[0048] Similarly, it should be understood that, in order to streamline the present invention and assist in understanding one or more of the various inventive aspects, in the above description of the exemplary embodiments of the present invention, the various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, the disclosed method should not be construed as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as reflected by the claims, the inventive aspects lie in less than all the features of the single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into the detailed description, with each claim standing on its own as a separate embodiment of the present invention.

[0049] Those of ordinary skill in the art can understand that the modules in the devices in the embodiments can be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or components in the embodiments can be combined into one module or unit or component, and in addition, they can be divided into multiple sub-modules or sub-units or sub-components. Except that at least some of such features and / or processes or units are mutually exclusive, any combination can be used to combine all the features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all the processes or units of any method or device so disclosed. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) can be replaced by an alternative feature that provides the same, equivalent, or similar purpose.

[0050] In addition, those skilled in the art should be able to understand that although some of the embodiments described herein include certain features included in other embodiments rather than other features, the combination of the features of different embodiments means that it is within the scope of the present invention and forms different embodiments. For example, in the claims, any one of the claimed embodiments can be used in any combination.

Claims

1. An output module circuit of an integrated circuit chip, characterized in that, The integrated circuit chip includes a die and a package frame. The die includes the output module circuit and is located in the package frame. The package frame further includes pins for connecting to the die. The output module circuit includes: A first transistor having a first control terminal, a first current input terminal, and a first current output terminal. The first current input terminal is connected to a power supply. A second transistor having a second control terminal, a second current input terminal, and a second current output terminal. The second current output terminal is connected to ground. The first control terminal and the second control terminal are used for connecting to a signal to be output. Wherein, The first current output terminal serves as a first connection point for connecting to the pin. The second current input terminal serves as a second connection point for connecting to the pin. The gate of the first transistor is connected to an output signal, the source of the first transistor is connected to the power supply, and the drain of the first transistor is temporarily floating and is used for connecting to the first connection point. The gate of the second transistor is connected to the output signal, the drain is temporarily floating and is used for connecting to the second connection point, and the source is connected to ground. The output module circuit further includes an ESD module connected between the drain of the second transistor and the second connection point. During packaging, The second connection point is bonded to the pin OUT on the package frame, so that the pin OUT is in an open-drain output mode; or Both the first connection point and the second connection point are bonded to the pin OUT on the package frame, so that the pin OUT is in a push-pull output mode.

2. The output module circuit according to any one of claims 1, characterized in that, The first transistor and the second transistor are a PMOS transistor and an NMOS transistor respectively, or an NPN transistor and a PNP transistor respectively.

3. The output module circuit according to claim 1, characterized in that, The first transistor and the second transistor are a triode or a field effect transistor.

4. An integrated circuit chip, characterized in that, Includes a core circuit, the output module circuit according to any one of claims 1-3, and a package frame. Wherein, the package frame includes pins. During packaging, the output signal of the core circuit is determined to be in a push-pull output mode or an open-drain output mode according to the connection relationship between the first connection point and the second connection point in the output module circuit and the pins.

5. The chip according to claim 4, characterized in that, When the second connection point is connected to the pin, the output mode of the output module circuit is an open-drain output mode.

6. The chip according to claim 4, characterized in that, When the first connection point and the second connection point are connected to the same pin, the output mode of the chip is a push-pull output mode.

7. A method for chip packaging using the output module circuit according to any one of claims 1-3, characterized in that, Includes connecting the first connection point and the second connection point in the output module circuit to the pins on the package frame according to a predetermined output mode. In the case where the predetermined output mode is an open-drain output mode, the second connection point is connected to the pin. In the case where the predetermined output mode is a push-pull output mode, the first connection point and the second connection point are simultaneously connected to the same pin.

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