A synchronous rectification control system and method applied to a CLLC resonant converter

Abstract

The application discloses a synchronous rectification control system and method applied to a CLLC resonant converter, a sampling resistor is connected in series on a secondary side rectification bridge in a main power circuit of the CLLC resonant converter, two ends of the sampling resistor are connected with input ends of a proportional amplifier, output ends of the proportional amplifier are connected with input ends of a first comparator and input ends of a second comparator, output ends of the first comparator and the second comparator are connected with input ends of a signal enable circuit, the signal enable circuit is connected with a digital controller MCU and a driving signal generation circuit, the digital controller MCU is connected with the driving signal generation circuit, and the system and the method can effectively solve the problem of synchronous rectification opening oscillation of the CLLC resonant converter under light load.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of power electronic technology DC / DC converter, and relates to a synchronous rectification control system and method applied to a CLLC resonant converter. BACKGROUND

[0002] In recent years, with the continuous development of new energy power generation systems, energy storage systems, aerospace systems and other industrial fields, DC-DC converters have been widely researched and applied, and have become one of the research hotspots in the academic and industrial fields of power electronics. The focus of the research on bidirectional DC-DC converters is mainly how to improve the efficiency and power density of the converter as much as possible and reduce electromagnetic interference (EMI), and the bidirectional DC-DC converter is required to realize wide-range voltage regulation in a wide load range in the usual application occasions. DC-DC converters can be divided into two categories: isolated and non-isolated. The isolated DC-DC converter not only can provide electrical isolation between the front and rear stages to improve its stability and safety, but also can reduce its volume and weight through high-frequency transformer, thereby improving the power density. Therefore, compared with the non-isolated DC-DC converter, the isolated DC-DC converter is more likely to meet the technical requirements of industrial applications. At present, the most widely used isolated bidirectional DC-DC converter topologies mainly include double active bridge (DAB) and CLLC resonant converter. The double active bridge (DAB) has the problem of low efficiency caused by the loss of ZVS at light load, and compared with the double active bridge (DAB), the CLLC resonant converter has smaller current RMS and harmonic content, and can realize ZVS in the full load range, etc. Therefore, the research on the CLLC resonant converter has attracted widespread attention.

[0003] In the CLLC resonant converter, the synchronous rectification technology of the secondary side rectifier tube is an important link to improve the efficiency of the converter. The current detection scheme, voltage detection scheme and model prediction scheme are the three major categories of the synchronous rectification technology for resonant converters. The current detection scheme mainly uses a high-bandwidth current sensor to detect the current on the secondary side rectifier side to apply synchronous rectification drive according to the polarity thereof. This scheme is the most accurate, but the high-bandwidth current sensor is usually expensive and bulky, which restricts the improvement of the power density of the converter. The voltage detection scheme mainly detects the voltage across the synchronous rectifier tube. This scheme is often affected by the oscillation caused by parasitic parameters and the loss of duty cycle. The model prediction scheme mainly calculates the turn-on and turn-off time of the synchronous rectifier tube online by analyzing the working principle of the converter using a digital controller. This scheme does not require a high-frequency sensor, but it is heavily dependent on the accuracy of the model and the accuracy of the resonant parameters. In addition, the existing synchronous rectification methods do not solve the turn-on time oscillation problem at light load. Therefore, the traditional synchronous rectification technology for resonant converters has its own defects and needs to be improved. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a synchronous rectification control system and method for CLLC resonant converters. This system and method can effectively solve the problem of synchronous rectification turn-on oscillation under light load in CLLC resonant converters.

[0005] To achieve the above objectives, the synchronous rectification control system for a CLLC resonant converter described in this invention includes a sampling resistor, a proportional amplifier, a first comparator, a second comparator, a signal enable circuit, a digital controller (MCU), and a drive signal generation circuit.

[0006] The sampling resistor is connected in series to the secondary rectifier bridge in the main power circuit of the CLLC resonant converter. The two ends of the sampling resistor are connected to the input of the proportional amplifier. The output of the proportional amplifier is connected to the input of the first comparator and the input of the second comparator. The output of the first comparator and the output of the second comparator are connected to the input of the signal enable circuit. The signal enable circuit is connected to the digital controller MCU and the drive signal generation circuit. The digital controller MCU is connected to the drive signal generation circuit.

[0007] The drive signal generation circuit includes a first RS flip-flop and a second RS flip-flop;

[0008] The novel synchronous rectification control method for the CLLC resonant converter described in this invention includes the following steps:

[0009] 1) Collect the voltage V across the sampling resistor. s1 Then it is amplified by a proportional amplifier;

[0010] 2) Amplified sampled signal V s The voltage V is fed into the inverting input terminals of the first comparator and the second comparator, and the non-inverting input terminals of the first comparator and the second comparator are respectively fed into the first threshold voltage V. th1 and the second threshold voltage V th2 As a reference voltage, the first threshold voltage V th1 For a positive value or zero, when V s Less than V th1 If the first comparator outputs a high level (1), then the second threshold voltage V is 1; otherwise, the first comparator outputs a low level (0). th2 When V is negative s Less than V th2 If the condition is met, the second comparator outputs a high level (1); otherwise, the second comparator outputs a low level (0).

[0011] 3) The output signals of the first comparator and the second comparator are sent to the signal enable circuit for enable operation. The pulse signal V output by the first comparator...off V off With the turn-off enable level EN during the positive half-cycle off1 The operation yields the positive half-cycle turn-off pulse signal V. off1 V off With the negative half-cycle turn-off enable level EN off2 The operation yields the negative half-cycle turn-off pulse signal V. off2 The pulse signal output by the second comparator is V. rev The pulse signal V output by the second comparator rev The return current enable level EN during the positive half-cycle of the switching cycle rev1 The operation yields the positive half-cycle return pulse signal V. rev1 The return pulse signal V during the positive half-cycle rev1 The data is sent to the digital controller MCU.

[0012] 4) When the digital controller MCU detects the return pulse signal V during the positive half-cycle... rev1 When the level is high (1), the turn-on time t of the synchronous rectifier in the next cycle is... on ′=t on +ΔT,t on '≥0,t on The turn-on time of the synchronous rectifier diode in the current cycle is when the digital controller MCU detects the return pulse signal V during the positive half-cycle. rev1 When the level is low (0), the turn-on time t of the synchronous rectifier in the next cycle is... on ′=t on -ΔT,t on When ′≥0, the final digital controller MCU outputs the positive half-cycle turn-on pulse signal V. on1 and the turn-on pulse signal V during the negative half-cycle on2 ;

[0013] 5) The turn-on pulse signal V during the positive half-cycle on1 With the second RS flip-flop The signal output from the output terminal is ANDed and then fed into the S input terminal of the first RS flip-flop. The turn-off pulse signal V during the positive half-cycle is... off1 The signal is fed into the R input terminal of the first RS flip-flop, and then the Q output terminal of the first RS flip-flop outputs the synchronous rectified drive signal V for the positive half-cycle. SR1 The negative half-cycle turn-on pulse signal V on2 With the first RS flip-flop The signal output from the output terminal is ANDed and then fed into the S input terminal of the second RS flip-flop, which is the turn-off pulse signal V during the negative half-cycle. off2 The signal is fed into the R input terminal of the second RS flip-flop, and then the Q output terminal of the second RS flip-flop outputs the synchronous rectified drive signal V for the negative half-cycle. SR2 ;

[0014] 6) the positive half-cycle synchronous rectification drive signal V SR1 and the negative half-cycle synchronous rectification drive signal V SR2 are applied to the synchronous rectification tube after power amplification to achieve synchronous rectification control.

[0015] The amplification coefficient of the proportional amplifier is K, and the amplified sampling signal is V s = K·V s1 .

[0016] The positive half-cycle turn-off enable level EN off1 , the negative half-cycle turn-off enable level EN off2 , and the positive half-cycle backflow enable level EN rev1 are generated by the digital controller MCU.

[0017] The present application has the following beneficial effects:

[0018] The synchronous rectification control system and method applied to the CLLC resonant converter in the present application have the following advantages: in the specific operation, a sampling resistor is connected in series after the secondary side rectification bridge to obtain a feedback signal V s1 , the hardware cost is low, the implementation is simple, the voltage on the sampling resistor is not affected by the parasitic inductance between the drain and source of the synchronous rectification tube, and there is no problem of drive duty cycle loss. In addition, since the parasitic oscillation of the resonant circuit is mainly due to the junction capacitance C oss of the rectification tube and the internal inductance of the resonant cavity, and the parasitic parameters of the four rectification tubes of the secondary side rectification bridge usually have good consistency, compared with the secondary side resonant current before the secondary side rectification bridge, the sampled signal V s1 is less sensitive to the parasitic oscillation of the resonant circuit and has better reliability. In addition, it should be noted that the present application does not depend on the accuracy of the resonant converter resonant element parameters at all, and the system has good stability. At the same time, the present application introduces backflow detection to realize adaptive adjustment of the turn-on time of the synchronous rectification tube, which can eliminate the circulating current and reduce the diode conduction time under any load condition, so as to achieve the best synchronous rectification effect, and solve the problem of synchronous rectification turn-on oscillation of the CLLC resonant converter under light load. The turn-off time of the synchronous rectification tube is directly determined by the turn-off pulse signals V off1 and V off2 , without the need for processing by the digital controller MCU, thereby saving the resources of the digital controller. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 is a circuit structure schematic diagram of the present application;

[0020] Figure 2 is a working waveform schematic diagram of the present application under heavy load in the sub-resonance region.

[0021] Figure 3 The working waveform diagram of the application under light load in the sub-resonance region;

[0022] Figure 4 The working waveform diagram of the application under heavy load in the super-resonance region;

[0023] Figure 5 The working waveform diagram of the application under light load in the super-resonance region. DETAILED DESCRIPTION

[0024] In order to make the person skilled in the art better understand the application scheme, the technical solutions in the embodiments of the application will be described clearly and completely below in conjunction with the drawings in the embodiments of the application. Obviously, the described embodiments are only a part of the embodiments of the application, not all the embodiments, and are not intended to limit the scope of the application disclosed. In addition, in the following description, the description of the known structures and technologies is omitted to avoid unnecessary confusion of the concepts disclosed in the application. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor should belong to the scope of protection of the application.

[0025] The structural schematic diagram according to the disclosed embodiments of the application is shown in the drawings. These drawings are not drawn to scale, in which some details are enlarged for the purpose of clear expression, and some details can be omitted. The shapes of various regions, layers and their relative size and position relationship shown in the drawings are only exemplary, and in actuality, there can be deviations due to manufacturing tolerances or technical limitations, and the regions / layers with different shapes, sizes and relative positions can be additionally designed by those skilled in the art according to actual needs.

[0026] Reference Figure 1 The synchronous rectification control system applied to the CLLC resonant converter includes a sampling resistor R s , a proportional amplifier 10, a first comparator 21, a second comparator 22, a signal enabling circuit 30, a digital controller MCU 40 and a driving signal generation circuit 50.

[0027] The sampling resistor R s is connected in series to the secondary side rectifier bridge in the main power circuit of the CLLC resonant converter, and the sampling resistor R sThe two ends of the sampling resistor R are connected with the input end of the proportional amplifier 10, the output end of the proportional amplifier 10 is connected with the input end of the first comparator 21 and the input end of the second comparator 22, the output end of the first comparator 21 and the output end of the second comparator 22 are connected with the input end of the signal enable circuit 30, the signal enable circuit 30 is connected with the digital controller MCU 40 and the driving signal generation circuit 50, the digital controller MCU 40 is connected with the driving signal generation circuit 50;

[0028] The novel synchronous rectification control method of the CLLC resonant converter comprises the following steps:

[0029] 1) The sampling resistor R s is connected with the two ends of the rectifier bridge, and the voltage V s1 across the two ends of the sampling resistor R s1 is sampled, wherein V s = R rec · i rec , i s is the current after the rectifier bridge, and the sampling signal is amplified by the proportional amplifier 10, wherein the amplification coefficient of the proportional amplifier 10 is K, and the amplified sampling signal is V s1 = K· V s ;

[0030] 2) The amplified sampling signal V th1 enters the inverting input end of the first comparator 21 and the second comparator 22, the non-inverting input end of the first comparator 21 and the second comparator 22 respectively inputs the first threshold voltage V th2 and the second threshold voltage V th1 as a reference voltage reference, wherein the first threshold voltage V s is a positive value or zero, and is used for judging the turn-off moment, when V th1 is less than V th2 , the first comparator 21 outputs high level 1, indicating that the rectification side current is zero-crossing, at this time, the corresponding synchronous rectifier needs to be turned off, otherwise, the first comparator 21 outputs low level 0, indicating that the rectification side current is not zero-crossing; the second threshold voltage V s is a negative value, and is used for judging the backflow signal, when V th2 is less than V s , the second comparator 22 outputs high level 1, indicating that the rectification side current exists circulation, otherwise, the second comparator 22 outputs low level 0, indicating that the rectification side current does not exist circulation.

[0031] 3) Since the present application detects the voltage V s1Since it cannot distinguish between the positive and negative half-cycles of the switching cycle, it cannot be directly used to generate synchronous rectification drive signals. Therefore, the output signals of the first comparator 21 and the second comparator 22 need to be sent to the signal enable circuit 30 for enable operation, so as to filter out the valid signals of the positive and negative half-cycles respectively. Specifically, the pulse signal V output by the first comparator 21 off Characterizing the original turn-off pulse signal, V off With the turn-off enable level EN during the positive half-cycle off1 The operation yields the positive half-cycle turn-off pulse signal V. off1 V off With the negative half-cycle turn-off enable level EN off2 The operation yields the negative half-cycle turn-off pulse signal V. off2 The pulse signal output by the second comparator 22 is V. rev The original return pulse signal is represented by the pulse signal V. In order to ensure the symmetry of the positive and negative half-cycles of the switching cycle in this invention, only the pulse signal V output by the second comparator 22 is used. rev The return current enable level EN during the positive half-cycle of the switching cycle rev1 The operation yields the positive half-cycle return pulse signal V. rev1 Then the return pulse signal V during the positive half-cycle rev1 The signal is fed into the digital controller MCU40 for adaptive adjustment of the turn-on time. Specifically, when the synchronous rectification system starts working, the turn-on time of the secondary rectifier diodes is synchronized with the turn-on time of the primary rectifier diodes. At this time, the lag of the secondary rectifier diode turn-on time relative to the primary rectifier diode turn-on time is t. on =0 (When the CLLC resonant converter is working normally, the turn-on time of the secondary rectifier diode will not be earlier than the turn-on time of the primary diode), when the digital controller MCU40 detects the return pulse signal V of the positive half-cycle. rev1 When the signal is high (1), it is assumed that circulating current exists on the secondary rectifier side. In this case, the digital controller MCU40 will gradually increase the turn-on time t of the synchronous rectifier tube in the next cycle. on ′=t on +ΔT,t on ≥0, otherwise, when the digital controller MCU40 detects the return pulse signal V during the positive half-cycle. rev1 When the voltage level is low (0), it is assumed that there is no circulating current on the secondary rectifier side. At this time, the digital controller MCU40 gradually reduces the turn-on time t of the synchronous rectifier tube in the next cycle. on ′=t on -ΔT,t on The process is repeated until the optimal turn-on time is reached. After the above adaptive adjustment process is completed, the digital controller MCU40 outputs a positive half-cycle turn-on pulse signal V. on1 and the turn-on pulse signal V during the negative half-cycle on2, the mentioned turn-off enable level EN of the positive half cycle off1 , the turn-off enable level EN of the negative half cycle off2 and the return flow enable level EN of the positive half cycle rev1 are all generated by the digital controller MCU 40.

[0032] 4) the drive signal generating circuit 50 comprises a first RS flip-flop and a second RS flip-flop, wherein the turn-on pulse signal V on1 of the positive half cycle is sent into the S input end of the first RS flip-flop after being ANDed with the signal outputted by the output end of the second RS flip-flop, the turn-off pulse signal V off1 of the positive half cycle is sent into the R input end of the first RS flip-flop, then the Q output end of the first RS flip-flop outputs the synchronous rectification drive signal V SR1 of the positive half cycle; the turn-on pulse signal V on2 of the negative half cycle is sent into the S input end of the second RS flip-flop after being ANDed with the signal outputted by the output end of the first RS flip-flop, the turn-off pulse signal V off2 of the negative half cycle is sent into the R input end of the second RS flip-flop, then the Q output end of the second RS flip-flop outputs the synchronous rectification drive signal V SR2 of the negative half cycle.

[0033] 5) the synchronous rectification drive signal V SR1 of the positive half cycle and the synchronous rectification drive signal V SR2 of the negative half cycle are applied to the synchronous rectification tube after being power amplified, so as to realize the synchronous rectification control.

[0034] The working waveform schematic diagram of several typical working states of the present application is shown as Figures 2 to 5 , which respectively describes four typical waveforms of the present application under the heavy load and light load in the CLLC sub-resonance region and the heavy load and light load in the CLLC super-resonance region.

[0035] The above enumeration is only one specific embodiment of the present application. Obviously, the present application is not limited to the above embodiment, and there are many variations. For example, the strategy proposed by the present application can also be applied to the LLC resonant converter without distinction. The changes, modifications, replacements and variations of the embodiments made by the ordinary skilled in the art without departing from the principles of the present application, and all the variations directly derived or thought do not need to spend the creative labor, and should be considered as the protection range of the present application.

Claims

1. A novel synchronous rectification control method for a CLLC resonant converter, characterized in that, The application relates to a synchronous rectification control system applied to a CLLC resonant converter, which comprises a sampling resistor (R s ), a proportional amplifier (10), a first comparator (21), a second comparator (22), a signal enabling circuit (30), a digital controller MCU (40) and a driving signal generating circuit (50). A sampling resistor (R s ) is connected in series to a secondary side rectifier bridge in a main power circuit of a CLLC resonant converter, two ends of the sampling resistor (R s ) are connected to input ends of a proportional amplifier (10), an output end of the proportional amplifier (10) is connected to input ends of a first comparator (21) and a second comparator (22), output ends of the first comparator (21) and the second comparator (22) are connected to an input end of a signal enable circuit (30), the signal enable circuit (30) is connected to a digital controller MCU (40) and a driving signal generation circuit (50), the digital controller MCU (40) is connected to the driving signal generation circuit (50); The drive signal generating circuit (50) comprises a first RS flip-flop and a second RS flip-flop. comprising the steps of: 1) Collecting the sampling resistance R s The voltage V s1 , and then amplified by the proportional amplifier (10); 2) amplified sampling signal V s The inverted input terminals of the first comparator (21) and the second comparator (22) are inputted into the first threshold voltage V th1 and the second threshold voltage V th2 as reference voltage reference, wherein the first threshold voltage V th1 is positive or zero, when V s is less than V th1 , the first comparator (21) outputs high level 1, otherwise, the first comparator (21) outputs low level 0, the second threshold voltage V th2 is negative, when V s is less than V th2 , the second comparator (22) outputs high level 1, otherwise, the second comparator (22) outputs low level 0; 3) The output signals of the first comparator (21) and the second comparator (22) are sent to the signal enable circuit (30) for enable operation. Among them, the pulse signal V output by the first comparator (21) is... off V off With the turn-off enable level EN during the positive half-cycle off1 The operation yields the positive half-cycle turn-off pulse signal V. off1 V off With the negative half-cycle turn-off enable level EN off2 The operation yields the negative half-cycle turn-off pulse signal V. off2 The pulse signal output by the second comparator (22) is V. rev The pulse signal V output by the second comparator (22) rev The return current enable level EN during the positive half-cycle of the switching cycle rev1 The operation yields the positive half-cycle return pulse signal V. rev1 The return pulse signal V during the positive half-cycle rev1 The signal is sent to the digital controller MCU (40); 4) When the digital controller MCU (40) detects the backflow pulse signal V rev1 is high level 1, then the next cycle of the synchronous rectifier tube opening time , t on is the current cycle of the synchronous rectifier tube opening time, when the digital controller MCU (40) detects the backflow pulse signal V rev1 is low level 0, then the next cycle of the synchronous rectifier tube opening time , finally the digital controller MCU (40) outputs the positive half cycle of the opening pulse signal V on1 and the negative half cycle of the opening pulse signal V on2 ; 5) the turn-on pulse signal V of the positive half cycle on1 and the signal outputted by the output end of the second RS flip-flop after AND operation, is sent to the S input end of the first RS flip-flop, the turn-off pulse signal V of the positive half cycle off1 is sent to the R input end of the first RS flip-flop, then the Q output end of the first RS flip-flop outputs the synchronous rectification drive signal V of the positive half cycle SR1 ; the turn-on pulse signal V of the negative half cycle on2 and the signal outputted by the output end of the first RS flip-flop after AND operation, is sent to the S input end of the second RS flip-flop, the turn-off pulse signal V of the negative half cycle off2 is sent to the R input end of the second RS flip-flop, then the Q output end of the second RS flip-flop outputs the synchronous rectification drive signal V of the negative half cycle SR2 ; 6) the positive half-cycle synchronous rectification drive signal V SR1 and the negative half-cycle synchronous rectification drive signal V SR2 are applied to the synchronous rectifier tube after power amplification to achieve synchronous rectification control.

2. The novel synchronous rectification control method of CLLC resonant converter according to claim 1, characterized in that, The amplification factor of the proportional amplifier (10) is K, and the amplified sampling signal is .

3. The novel synchronous rectification control method of CLLC resonant converter according to claim 1, characterized in that, The off enable level EN of the positive half cycle off1 The off enable level EN of the negative half cycle off2 The backflow enable level EN of the positive half cycle rev1 are generated by the digital controller MCU (40).

Images