Network-on-chip topology generation

Abstract

The present disclosure provides computer-based methods and systems for synthesizing a NoC that advantageously generate balanced NoC topologies without requiring end-to-end fairness or arbitration based on local credits, and improve NoC performance when only one incoming physical link per channel is supported at target device bridge ports. More specifically, certain routers are assigned clock domains that satisfy the minimum frequency of that router, while reducing the number of clock domain transitions to neighboring routers, and traffic flows received by these routers are balanced based on the packet rate of the traffic flows.

Description

[0001] Cross-references to related applications

[0002] This application is a continuation-in-part (CIP) of U.S. Patent Application Serial No. 17 / 076,403 (filed October 21, 2020) and U.S. Patent Application Serial No. 16 / 518,254 (filed July 22, 2019, now U.S. Patent No. 10,817,627), the disclosures of which are incorporated herein by reference in their entirety. Background Technology

[0003] This disclosure relates to a network. More specifically, this disclosure relates to a network-on-a-chip (NoC).

[0004] Network-based communication subsystems (NoCs) implemented on integrated circuits (ICs), such as System-on-a-Chip (SoCs), enable IC modules to exchange data more efficiently than traditional bus or cross-switch architectures. More specifically, NoCs are router-based packet-switched networks that connect IC modules (such as intellectual property (IP) cores). NoCs include various components such as routers, size adjusters or serializers / parallelizers (SerDes), physical clock domain crossover (PCDC) buffers, pipelined elements, etc. NoC synthesis is the process of placing and configuring NoC components on the IC based on NoC input specifications. Generally, NoC designs must accommodate the data or traffic transmitted between IC modules while meeting various design constraints, such as power, performance, and area (PPA), and wiring costs, which may conflict with each other.

[0005] NoC synthesis specifically includes generating a topology for the NoC, which is the arrangement of routers, connections, and traffic paths or routes between IC modules. A poorly designed NoC topology can significantly impact the NoC's PPA (Power, Access, and Achievement), cabling costs, and may cause HoL (Hoisting Line) blocking across traffic classes. HoL blocking occurs when a sequence of packets from one traffic class is blocked by packets from another traffic class, even if the route for the blocked traffic class is clear. HoL blocking across traffic classes degrades NoC performance.

[0006] Importantly, a properly designed NoC is balanced to minimize interference between different input ports sending traffic to the same output port at each arbitration point (such as, for example, a router). In NoCs with no end-to-end Quality of Service (QoS) implementation and local fair arbitration schemes, an imbalance in arrival rates at input ports sharing the same output port on a router can lead to losses due to arbitration and subsequent performance degradation. The presence of bursts in traffic or variable packet sizes imposes additional constraints on designing topologies that meet performance requirements. Attached Figure Description

[0007] Figure 1 A block diagram of a NoC synthesis system according to one embodiment of the present disclosure is depicted.

[0008] Figure 2 A flowchart illustrating the NoC synthesis process according to one embodiment of this disclosure is provided.

[0009] Figure 3 The functionality associated with determining the topology of NoC according to one embodiment of this disclosure is described.

[0010] Figure 4 A graphical representation of the input specification of NoC according to one embodiment of this disclosure is depicted.

[0011] Figure 5 A HoL conflict diagram (HCG) of a NoC according to one embodiment of this disclosure is depicted.

[0012] Figure 6A A flow graph (TG) of NoC according to one embodiment of this disclosure is depicted.

[0013] Figures 6B to 6F An embodiment according to this disclosure is described. Figure 6A The series of graphs, grids, and topologies of TG depicted in the document.

[0014] Figure 7 Router merging for candidate topologies to be merged according to one embodiment of this disclosure is described.

[0015] Figure 8 A baseline topology for NoC according to one embodiment of this disclosure is described.

[0016] Figure 9A A flow flow view of the flow within a NoC according to one embodiment of this disclosure is depicted.

[0017] Figure 9B A flow flow view of the flow on a baseline topology of a NoC according to one embodiment of this disclosure is depicted.

[0018] Figure 10A A flow flow view of the flow on a baseline topology of a NoC according to one embodiment of the present disclosure is depicted.

[0019] Figure 10B A flow flow view of the flow on a first variant topology of a NoC according to an embodiment of the present disclosure is depicted.

[0020] Figure 10CA flow flow view of the flow on a second variant topology of NoC according to one embodiment of the present disclosure is depicted.

[0021] Figure 10D A flow flow view of the final topology of a NoC according to one embodiment of the present disclosure is depicted.

[0022] Figure 11 The final topology of NoC according to one embodiment of this disclosure is depicted.

[0023] Figure 12A , Figure 12B and Figure 12C A flowchart depicting a representation of the functionality associated with the synthesis of NoC according to one embodiment of this disclosure is provided. Detailed Implementation

[0024] Embodiments of this disclosure will now be described with reference to the accompanying drawings, wherein similar reference numerals always refer to similar components.

[0025] Embodiments of this disclosure advantageously provide a computer-based method and system for synthesizing NoCs, which generates balanced topologies without achieving end-to-end fairness or local credit-based arbitration, and improves NoC performance when the target device bridge port only supports one incoming physical link per channel. More specifically, embodiments of this disclosure allocate clock domains to certain routers that satisfy the router's minimum frequency while reducing clock domain translations to neighboring routers, and balance the traffic flows received by these routers based on the traffic flow packet rate.

[0026] In one implementation, a computer-based method for synthesizing a NoC is provided. The NoC-based input specification determines physical data, device data, bridge data, and traffic data. The physical data includes dimensions of the NoC; the device data includes multiple devices, each with a location and dimension; the bridge data includes multiple bridge ports, each associated with and having a location among the devices; and the traffic data includes multiple traffic flows, each with a packet rate. Virtual channels (VCs) are assigned to each traffic flow to create multiple VC allocations. A baseline topology is generated based on the physical data, device data, bridge data, traffic data, and VC allocations. This baseline topology includes multiple bridge ports, multiple routers, and multiple connections, each router having one or more input ports and one or more output ports. Each router with at least one output port is identified, shared by traffic flows received on at least two input ports. For each identified router, a minimum frequency for the identified router is calculated based on the packet rate of the traffic flows received by the identified router, and a clock domain is allocated to the identified router based on this minimum frequency. The traffic flows received by the identified router are balanced based on the packet rate of the traffic flows. The final topology is generated based on the baseline topology and the balanced traffic flow of the identified routers.

[0027] Figure 1 A block diagram of a NoC synthesis system 10 according to one embodiment of the present disclosure is depicted.

[0028] Computer 100 includes a bus 110, a processor 120, a storage element or memory 130, an I / O interface 140, a display interface 150, and one or more communication interfaces 160. Generally, I / O interface 140 is coupled to I / O device 142 using a wired or wireless connection, display interface 150 is coupled to display 152, and communication interface 160 is connected to network 20 using a wired or wireless connection.

[0029] Bus 110 is connected to processor 120, memory 130, I / O interface 140, display interface 150, and communication interface 160, as well as... Figure 1 A communication system for transmitting data between other components (not shown). Power connector 112 is coupled to bus 110 and power supply (not shown).

[0030] Processor 120 includes one or more general-purpose or special-purpose microprocessors that execute instructions to perform control, calculation, input / output, and other functions of computer 100. Processor 120 may include a single integrated circuit, such as a microprocessor device, or multiple integrated circuit devices and / or circuit boards that cooperate to implement the functions of processor 120. Additionally, processor 120 may execute computer programs or modules stored in memory 130, such as operating system 132, NoC synthesis module 134, other software modules 136, etc.

[0031] Generally, memory 130 stores instructions and data for execution by processor 120. Memory 130 may include various non-transitory computer-readable media accessible by processor 120. In various embodiments, memory 130 may include volatile and non-volatile media, non-removable media, and / or removable media. For example, memory 130 may include random access memory (RAM), dynamic RAM (DRAM), static RAM (SRAM), read-only memory (ROM), flash memory, cache memory, and / or any other combination of non-transitory computer-readable media.

[0032] Memory 130 contains various components for retrieving, presenting, modifying, and storing data. For example, memory 130 stores software modules that provide functionality when executed by processor 120. These software modules include an operating system 132 that provides operating system functionality to computer 100. The software modules also include a NoC synthesis module 134 that provides functionality for synthesizing a NoC architecture. In some embodiments, NoC synthesis module 134 may include multiple modules, each providing specific individual functionality for synthesizing a NoC architecture, such as, for example, an input module, a VC module, a topology module, a routing module, a network generation module, a PCDC module, a link size and size adjuster module, a pipeline and timing component module, an output module, etc. Other software modules 136 may cooperate with NoC synthesis module 134 to provide functionality for synthesizing a NoC architecture.

[0033] Data 138 may include data associated with operating system 132, NoC synthesis module 134, other software modules 136, etc.

[0034] I / O interface 140 is configured to transmit and / or receive data from I / O device 142. I / O interface 140 establishes a connection between processor 120 and I / O device 142 by encoding data to be transmitted from processor 120 to I / O device 142 and decoding data received from I / O device 142 for use by processor 120. Generally, data can be transmitted via wired and / or wireless connections. For example, I / O interface 140 may include one or more wired communication interfaces (such as USB, Ethernet, etc.) and / or one or more wireless communication interfaces coupled to one or more antennas (such as WiFi, Bluetooth, cellular, etc.).

[0035] Generally, I / O device 142 provides input to and / or output from computer 100. As discussed above, I / O device 142 is operatively connected to computer 100 using wired and / or wireless connections. I / O device 142 may include a local processor coupled to a communication interface configured to communicate with computer 100 using wired and / or wireless connections. For example, I / O device 142 may include a keyboard, mouse, touchpad, joystick, etc.

[0036] Display interface 150 is configured to transmit image data from computer 100 to monitor or display 152.

[0037] Communication interface 160 is configured to transmit data to and from network 20 using one or more wired and / or wireless connections. Network 20 may include one or more local area networks, wide area networks, the Internet, etc., which can execute various network protocols, such as wired and / or wireless Ethernet, Bluetooth, etc. Network 20 may also include various combinations of wired physical layers and / or wireless physical layers, such as copper wire or coaxial cable networks, fiber optic networks, Bluetooth wireless networks, WiFi wireless networks, CDMA, FDMA, and TDMA cellular wireless networks, etc.

[0038] Figure 2 A flowchart of NoC synthesis is depicted in 200, while Figure 3 The present disclosure describes 230 functions associated with determining the topology of the NoC according to an embodiment of the present disclosure.

[0039] As discussed above, the software module includes a NoC synthesis module 134, which provides functionality for synthesizing a NoC architecture. In some embodiments, the NoC synthesis module 134 includes multiple modules, each providing specific individual functionality for synthesizing a NoC architecture, such as, for example, an input module, a VC module, a topology module, a routing module, a network generation module, a PCDC module, a link size and size adjuster module, a pipeline and timing component module, an output module, etc.

[0040] At 210, the NoC input specification 202 is retrieved from memory 130, and the NoC design information is determined. For example, the NoC input specification 202 can be received via network 20 and then stored in memory 130 as data 138. In another example, the NoC input specification 202 can be created by the NoC designer using one or more software modules 136 and then stored in memory 130 as data 138.

[0041] NoC design information includes, for example, physical data, device data, bridge data, and flow data. Additional design information may include voltage domain data, power domain data, clock domain data, address domain data, and synthetic constraints.

[0042] Physical data includes the dimensions of the NoC and a list of unroutable regions. NoC components (such as bridges, routers, pipelines, resizing devices, connections, etc.) are typically not located within unroutable regions. In one example, the NoC is modeled as an array of cells arranged in rows and columns. The number of rows is defined by the height (in cells), and the number of columns is defined by the width (in cells). Cell widths, in millimeters, micrometers, inches, etc., can also be provided. Cells are numbered sequentially, starting from the top-left corner of the array. Data for each unroutable region includes location (cell number) and dimensions, such as width (in cells) and height (in cells). In another example, the NoC is modeled as a grid defined by Cartesian coordinates (X,Y), with the origin at the bottom-left corner of the grid. Height and width are provided in normalized units, and a normalization factor can also be provided. Data for each unroutable region includes location (X,Y) and dimensions, such as width (X) and height (Y).

[0043] Device data includes a list of devices located within the NoC, such as IP cores and IC modules. Each device includes one or more bridge ports (i.e., signal interfaces). Data for each device may include name, location (cell number, XY coordinates, etc.), dimensions (including width (in cells, X dimension, etc.) and height (in cells, Y dimension, etc.)), power domain, etc.

[0044] Bridge data includes a list of bridge ports for the devices. Data for each bridge port may include name, associated device name, location (cell number, XY coordinates, etc.), data width (in bits), low / high line indicators, etc.

[0045] In many implementations, NoC is a packet switching network that divides data packets into sequences of message flow control units or flits. Each flit has the same size (in bits) and is divided into data transmission sequences across physical connections or links. A physical unit or phit is the number of bits (i.e., the bit width of the link) that can be transmitted in parallel across a physical connection in a single data transmission cycle. In one example, the NoC flit size is 128 bits. A bridge port with a data width (phit size) of 32 bits requires 4 data transmission cycles to transmit each flit. In the context of this disclosure, the link size of this bridge port is 4 (each unit of the link size is 32 bits). Similarly, a bridge port with a data width of 16 bits requires 8 data transmission cycles to transmit each flit, and the link size is 8 (each unit of the link size is 16 bits), while a bridge port with a data width of 64 bits requires 2 data transmission cycles to transmit each flit, and the link size is 2 (each unit of the link size is 64 bits). Other chip sizes, such as 32-bit, 64-bit, 256-bit, and 512-bit, can also be used. Different flow control techniques can be used in alternative implementations.

[0046] Traffic data includes a list of traffic flows for the NoC. Data for each traffic flow includes the source bridge port, destination bridge port, peak traffic rate, average traffic rate, and traffic category. The source and destination bridge ports are included in the bridge port list. Peak and average traffic rates are provided in bits per second or bytes per second, such as, for example, b / s, kb / s, Mb / s, Gb / s, Tb / s, B / s, KB / s, MB / s, GB / s, TB / s, etc. Generally, traffic categories provide one or more metrics that differentiate the NoC performance level offered for each traffic flow. In many implementations, traffic categories include Quality of Service (QoS) metrics and Latency Sensitivity (LS) metrics. QoS metrics provide a mechanism for prioritizing traffic within the NoC, while LS metrics indicate the traffic's sensitivity to network latency. For example, eight different traffic categories are provided for an integer QoS metric with four possible values ​​(e.g., 0 to 3) and a Boolean LS metric with two possible values ​​(e.g., true or false). In this example, a QoS value of 0 and an LS value of true provide the best potential NoC performance. Other metrics can also be envisioned. Additionally, message types such as read requests, write requests, read / write requests, etc., can be provided.

[0047] Figure 4 A graphical representation of NoC input specification 202 according to one embodiment of this disclosure is depicted. The user can view NoC 300 on a display 152.

[0048] NoC 300 has a NoC height and a NoC width, and includes a non-routable area 301 located within the central portion of NoC 300. Nine devices are distributed throughout NoC 300, none of which are located within the non-routable area 301. Each device includes at least one bridge port (“P”). For ease of illustration, each device has a single bridge port. Device 310 includes bridge port 310a, device 311 includes bridge port 311a, device 312 includes bridge port 312a, device 313 includes bridge port 313a, device 314 includes bridge port 314a, device 315 includes bridge port 315a, device 316 includes bridge port 316a, device 317 includes bridge port 317a, and device 318 includes bridge port 318a. Generally, the location of each bridge port is limited by the location of the associated device and the coverage area (i.e., device width and height) of the devices within the NoC. For example, for an 8-cell × 8-cell NoC, a device located in cell 9 with a width of 1 cell and a height of 3 cells supports one or more bridge ports located in cells 9, 17, and / or 25.

[0049] Eight traffic flow sets between devices are depicted; each traffic flow set includes at least one traffic flow. For example, a traffic flow set may include a traffic flow defining a read request and a traffic flow defining a write request. Traffic flow set 320 flows between bridge port 310a and bridge port 318a. Traffic flow set 321 flows between bridge port 311a and bridge port 318a. Traffic flow set 322 flows between bridge port 312a and bridge port 318a. Traffic flow set 323 flows between bridge port 313a and bridge port 318a. Traffic flow set 324 flows between bridge port 314a and bridge port 318a. Traffic flow set 325 flows between bridge port 315a and bridge port 318a. Traffic flow set 326 flows between bridge port 316a and bridge port 318a. Traffic flow set 327 flows between bridge port 317a and bridge port 318a.

[0050] In many implementations, devices 310, 311, 312, 313, 314, 315, 316, and 317 may be AXI Slave Network Interfaces (ASNI), while device 318 may be an AXI Master Network Interface (AMNI). Generally, an AMNI can send data to or request data from an ASNI. For ease of explanation, device 310 is labeled "S0", device 311 is labeled "S1", device 312 is labeled "S2", device 313 is labeled "S3", device 314 is labeled "S4", device 315 is labeled "S5", device 316 is labeled "S6", device 317 is labeled "S7", and device 318 is labeled "M0". Other configurations and device types can be accommodated.

[0051] Return to reference Figure 2 At position 220, a VC is assigned to each flow. Generally, VC assignment aims to reduce collisions and simplify subsequent topology generation. In one implementation, an iterative estimation process is used to assign VCs, performing a specify-evaluate-refine loop until no significant improvement is produced in the estimation. Other assignment methods are also conceivable.

[0052] At position 230, the topology of NoC is determined.

[0053] Return to reference Figure 3 At position 232, HCG is constructed based on traffic data and VC allocation.

[0054] Figure 5 HCG 400 of NoC 300 according to one embodiment of this disclosure is depicted. HCG 400 can be viewed by a user on display 152.

[0055] In this implementation, HCG 400 includes traffic nodes 410 to 417 and has no HoL edges. Each traffic node represents a traffic flow and each HoL edge represents a HoL conflict. A HoL conflict is defined as two traffic flows assigned to the same VC but with different traffic classes (such as, for example, different QoS values ​​and / or different LS values). For illustrative purposes only, each traffic flow set 320, 321, 322, 323, 324, 325, 326, and 327 has a single traffic flow from the corresponding slave device to the master device 318, resulting in eight traffic nodes 410 to 417. Each traffic node 410 to 417 is then assigned a color to minimize HoL conflicts, where adjacent traffic nodes receive different colors. In some implementations, minimum vertex coloring is used to find the minimum number of colors assigned to traffic nodes 410 to 417. Since there are no HoL conflicts, HCG 400 includes eight traffic nodes 410 to 417 in one color (white).

[0056] Return to reference Figure 3 At position 234, a TG for each color is constructed based on physical data, bridge data, traffic data, and a modified HCG. In other words, multiple traffic graphs are constructed based on physical data, bridge data, traffic data, and a modified HCG.

[0057] Figure 6A A NoC 300 TG 500 according to one embodiment of this disclosure is depicted. TG500 includes the color from HCG400, namely white. The user can view TG500 on a monitor 152.

[0058] TG 500 includes nodes 510 to 518 and edges 520, 521, 522, 523, 524, 525, 526, and 527. Each node 510 to 518 is associated with a different bridge port, and each edge 520, 521, 522, 523, 524, 525, 526, and 527 connects a pair of nodes and is associated with a flow set between two bridge ports. As discussed above, each flow set includes at least one flow.

[0059] More specifically, node 510 is associated with bridge port 310a, node 511 with bridge port 311a, node 512 with bridge port 312a, node 513 with bridge port 313a, node 514 with bridge port 314a, node 515 with bridge port 315a, node 516 with bridge port 316a, node 517 with bridge port 317a, and node 518 with bridge port 318a. Similarly, edge 520 is associated with flow set 320, edge 521 with flow set 321, edge 522 with flow set 322, edge 523 with flow set 323, edge 524 with flow set 324, edge 525 with flow set 325, edge 526 with flow set 326, and edge 527 with flow set 327.

[0060] At position 236, candidate topologies for each color are generated based on the corresponding TG. In other words, a candidate topology is generated for each TG. This candidate topology includes bridge ports, routers, and connections.

[0061] Figures 6B to 6F A series of meshes and topologies of the TG 550 according to one embodiment of this disclosure are depicted. These meshes and topologies can be viewed by a user on a display 152.

[0062] First, a mesh is generated based on the TG (Transformer Geometry) algorithm. This mesh consists of nodes and intersections formed by grid lines passing through each node. Each node is associated with a different bridge port and located at a different intersection. In one implementation, the mesh is a Hannan mesh formed by orthogonal vertical and horizontal grid lines. Other types of meshes, such as lattice, square, or unit-distance meshes, can also be generated.

[0063] Generally, functions at positions 234 and 236 are performed for each color. In one implementation, function 234 is performed for all colors, and then function 236 is performed for all colors. In another implementation, function 234 is performed for the first color, and then function 236 is performed for the first color. Next, function 234 is performed for the second color, then function 236 is performed for the second color, and so on.

[0064] Figure 6B The Hanan grid 501 for TG 500 is depicted.

[0065] Nodes 510 to 518 are located at the corresponding intersections, and routers are added to the mesh at each intersection not occupied by a node. In this implementation, 27 routers (i.e., routers R01 to R27) are added to the mesh. Adjacent nodes and routers are then connected to create the initial mesh or topology.

[0066] Figure 6C The initial mesh or topology 502 of TG 500 is depicted.

[0067] Node 510 is connected to routers R14, R19, and R23. Node 511 is connected to routers R06, R10, and R14. Node 512 is connected to routers R02, R06, R07, and R10. Node 513 is connected to routers R02, R03, and R07. Node 514 is connected to routers R03, R07, R08, and R12. Node 515 is connected to routers R08, R12, R13, and R18. Node 516 is connected to routers R13, R18, and R22. Node 517 is connected to routers R18, R21, R22, and R26. Node 518 is connected to routers R20, R24, and R25.

[0068] Router R01 is connected to routers R02 and R06. Router R02 is connected to nodes 512 and 513, as well as router R01. Router R03 is connected to nodes 513 and 514, as well as router R04. Router R04 is connected to routers R03, R05, and R08. Router R05 is connected to routers R04 and R09. Router R06 is connected to nodes 511 and 512, as well as router R01. Router R07 is connected to nodes 512, 513, and 514, as well as router R11. Router R08 is connected to nodes 514 and 515, as well as routers R04 and R09. Router R09 is connected to routers R05, R08, and R13. Router R10 is connected to nodes 511 and 512, as well as routers R11 and R15. Router R11 is connected to routers R07, R10, R12, and R16. Router R12 is connected to nodes 514 and 515, as well as routers R11 and R17. Router R13 is connected to nodes 515 and 516, as well as router R09. Router R14 is connected to nodes 510 and 511, as well as router R15. Router R15 is connected to routers R10, R14, R16, and R19. Router R16 is connected to routers R11, R15, R17, and R20. Router R17 is connected to routers R12, R16, R18, and R21. Router R18 is connected to nodes 515, 516, and 517, as well as router R17. Router R19 is connected to node 510, as well as routers R15, R20, and R24. Router R20 is connected to node 518, as well as routers R16, R19, and R21. Router R21 is connected to node 517, as well as routers R17, R20, and R25. Router R22 is connected to nodes 516 and 517, as well as router R27. Router R23 is connected to node 510 and router R24. Router R24 ​​is connected to node 518, as well as routers R19 and R23. Router R25 is connected to node 518, as well as routers R21 and R26. Router R26 is connected to node 517, as well as routers R25 and R27. Router R27 is connected to routers R22 and R26.

[0069] The weights for each connection are then calculated based on the traffic data to create a weighted mesh or topology. In one implementation, a Traffic Criticality Index (TCI) is calculated for each traffic flow, and then the TCI for each traffic flow is added to a heating index added to each connection falling within the straight bounding box of that traffic flow. The TCI can be based on traffic criticality and rate. The straight bounding box of a particular traffic flow is defined by the source node (source bridge port) and the destination node (destination bridge port) of that traffic flow. In one implementation, the weight of each connection is inversely proportional to the heating index of that connection, while in another implementation, the weight is directly proportional to the heating index. The weights are then applied to the initial mesh or topology to create a weighted mesh or topology.

[0070] Figure 6D The weighted mesh or topology 503 of TG 500 is depicted.

[0071] The different weights of each connection are represented by different line thicknesses. The thinnest line represents a connection through which traffic does not flow. For example, edge 530 is associated with flow set 320, which includes at least one flow between node 510 (bridge port 310a) and node 518 (bridge port 318a). The linear bounding box of flow set 320 is defined by nodes 510 and 518 and is represented by connections 520a, 520b, 520c, and 520d. Connections 520c and 520d have the lowest weights, connection 520b has a greater weight than connections 520c and 520d, and connection 520a has the highest weight. Notably, the weight of connection 520a includes contributions from the remaining edges 521, 522, 523, 524, 525, 526, and 527, while the weight of connection 520b includes a contribution from edge 521.

[0072] Then, based on a weighted grid or topology deterministic constraint minimum cost grid or topology, this includes removing one or more connections and one or more routers. In one implementation, a deterministic constraint minimum cost Steiner tree is used, which generates multiple trees based on degree and number of nodes, and then selects the lowest cost tree. Then, connections and routers that traffic does not flow through are removed from the degree-constrained minimum cost grid or topology.

[0073] Figure 6E The degree-constrained minimum cost mesh or topology 504 for TG 500 is depicted.

[0074] The degree-constrained minimum cost topology 504 includes nodes 510 to 518, and routers R07 and R10 to R21. Connection weights and... Figure 6D same.

[0075] Node 510 is connected to router R19, node 511 is connected to router R10, nodes 512, 513 and 514 are connected to router R07, node 515 is connected to router R12, node 516 is connected to router R18, node 517 is connected to router R21, and node 518 is connected to router R20.

[0076] Router R07 is connected to nodes 512, 513, and 514, as well as router R05. Router R10 is connected to node 511 and router R15. Router R11 is connected to routers R07, R12, and R16. Router R12 is connected to node 515 and router R11. Router R15 is connected to routers R10 and R19. Router R16 is connected to router R17. Router R17 is connected to routers R16 and R18. Router R18 is connected to node 516 and router R17. Router R19 is connected to node 510, as well as routers R15 and R20. Router R20 is connected to node 518, as well as routers R16, R19, and R21. Router R21 is connected to node 517 and router R20.

[0077] Then, candidate topologies are generated from the degree-constrained minimum cost tree.

[0078] Figure 6F The candidate topology 505 for TG 500 is described.

[0079] Candidate topology 505 includes nodes 510 to 518, and routers R07, R10, R11, R12, and R16 to R21. The connections between the nodes and routers are... Figure 6D Same. Generally, users can view grid 501 and topologies 502 to 505 on monitor 152.

[0080] Return to reference Figure 3 At position 238, the baseline topology is generated.

[0081] The candidate topologies are then merged to create a merged candidate topology, and the routers are initially merged within the merged candidate topology to generate a baseline topology. In this implementation, candidate topology 505 is also the merged candidate topology 505.

[0082] Then the routers are merged, and a baseline topology is generated.

[0083] Figure 7 Router merging for candidate topology 505 for merging is depicted according to one embodiment of this disclosure.

[0084] Router merging, as illustrated in Figure 506, is the process for merging routers in a candidate topology 505. Generally, route merging reduces the number of routers in a topology by combining two or more routers into one. Merged routers can also be relocated, i.e., placed in locations that do not correspond to any grid position of the original routers. Router relocation may occur after the candidate topology merging for each color, and / or during subsequent optimization processes.

[0085] Routers R10 and R19 have been merged into router R15 and are also labeled as router 540 for clarity. Routers R07, R12, R16, R17, R18, and R21 have been merged into router R11 and are also labeled as router 542 for clarity. Router R20 is also labeled as router 544 for clarity.

[0086] Figure 8 A baseline topology 507 of NoC 300 according to one embodiment of this disclosure is depicted. The baseline topology 507 can be viewed on a display 152.

[0087] Baseline topology 507 has the same NoC height and width as NoC 300 and includes a non-routable area 301 located within the central portion of baseline topology 507. Device 310 is connected to router 540 via bridge port 310a. Device 311 is connected to router 540 via bridge port 311a. Device 312 is connected to router 542 via bridge port 312a. Device 313 is connected to router 542 via bridge port 313a. Device 314 is connected to router 542 via bridge port 314a. Device 315 is connected to router 542 via bridge port 315a. Device 316 is connected to router 542 via bridge port 316a. Device 317 is connected to router 542 via bridge port 317a. Device 318 is connected to router 544 via bridge port 318a.

[0088] The baseline topology 507 can be determined by the NoC synthesis module 134 based on the above method. Alternatively, the baseline topology 507, along with traffic data, can be developed by different software modules 136, different computer systems, etc., and retrieved from the memory 130, received by the computer 100, etc.

[0089] In many implementations, for various reasons, neither end-to-end QoS support nor arbitration based on local credit (i.e., using local credit to mitigate arbitration loss) can be applied to the baseline topology 507. Instead, arbitration decisions at each arbitration point (e.g., each router) are based solely on local information, such as, for example, Least Recently Used (LRU) arbitration, Round-Robin (RR) arbitration, etc. For routers with multiple input ports sharing a single output port, each arbitration decision grants access to the output port to only one input port per cycle.

[0090] The embodiments of this disclosure advantageously generate balanced topologies for NoCs without requiring end-to-end fairness or arbitration based on local credit, and improve NoC performance when each channel on the target device bridge port supports only one incoming physical link. More specifically, embodiments of this disclosure allocate clock domains to certain routers that satisfy the router's minimum frequency while reducing clock domain translations to neighboring routers, and balance the traffic flows received by these routers based on the traffic flow packet rate.

[0091] Return to reference Figure 2 At 240, an effective clock domain can be determined for each location, and an initial clock domain can be assigned based on the flow and topology.

[0092] Identify each router that has an output {port, VC} combination shared by traffic flows received at at least two input ports. Calculate the minimum frequency for each identified router based on the packet rate of the traffic flows at the input ports. Then, assign a clock domain that satisfies the router's minimum frequency to each identified router.

[0093] Minimum frequencies were not determined for the remaining "unidentified" routers, and their clock domains could be allocated based on location, traffic flow, topology, etc.

[0094] After the initial clock domain has been allocated at position 240, the minimum cost degree constraint Steiner tree calculation at position 236 can be revisited by adding performance costs to identify performance violations and enhance the PPA cost model used during initial topology exploration. For those implementations that receive baseline topology 507 from an external source, performance costs can be used to perform minimum cost degree constraint Steiner tree analysis at position 236 to identify performance violations.

[0095] This performance cost includes router clock domain (CD) violation costs and packet rate balancing costs. The router CD violation cost imposes a cost on routers that violate their minimum frequency requirements, as all such routers can potentially lead to bandwidth loss, which must be minimized. The packet rate balancing cost imposes a cost on imbalances in packet rates between input ports on routers sharing the same output port, which can lead to arbitration on the router causing credit losses, resulting in performance losses in strategies that cannot recover from credit losses. Generally, performance costs do not affect unidentified routers.

[0096] The process then proceeds to 238, which modifies the baseline topology 507 based on the modified minimum cost degree constraint Steiner tree calculation. The process then proceeds to 240, which modifies the clock domain allocation for the routers in the modified topology. This process can be repeated until the routers no longer violate the clock domain constraints and the packet arrival rates on all router input ports are balanced.

[0097] Figure 9A A flow flow view 600 depicts the flow of traffic within NoC 300 according to one embodiment of this disclosure.

[0098] Traffic flow view 600 presents a slightly different view of the TG 500 (nodes and edges of the TG 500 are indicated in brackets). Traffic flow view 600 describes devices 310 to 318 and their corresponding bridge ports, the operating frequency of each device, traffic flow sets 320, 321, 322, 323, 324, 325, 326, and 327, and the number of transactions per second for each traffic flow.

[0099] Devices 310, 311, and 318 operate at 1 GHz, while devices 312, 313, 314, 315, 316, and 317 operate at 0.5 GHz. Therefore, the effective clock domain for devices 310, 311, and 318 is the 1 GHz clock domain, while the effective clock domain for devices 310, 311, 312, 313, 314, 315, 316, and 317 is the 0.5 GHz clock domain. Each traffic stream set represents 100 x 102 times per second from each of devices 310, 311, 312, 313, 314, 315, 316, and 317 to device 318. 6 A single unidirectional flow of traffic for a transaction or group.

[0100] Flow sets 322, 323, 324, 325, 326, and 327 must cross clock domain boundaries because devices 312, 313, 314, 315, 316, and 317 reside in clock domains with different clock speeds than the clock domain in which device 318 resides. In many embodiments, flow sets 320 and 321 do not cross clock domain boundaries because devices 310, 311, and 318 reside in the same clock domain. In other embodiments, flow sets 320 and 321 may cross clock domain boundaries because devices 310, 311, and 318 reside in different clock domains with the same clock speed.

[0101] In many implementations, the minimum router frequency can be determined as follows.

[0102] For each edge in the TG, all source-destination (SD) endpoint pairs using that edge are identified, and the packet rates from all identified SD pairs are summed to generate the total packet rate for that edge. For flow view 600, edges 520, 521, 522, 523, 524, 525, 526, and 527 each have 100×10 6 Total packet rate per second.

[0103] Then, all routers with at least one output port shared by multiple input ports are identified, and several determinations are performed for each identified router. For each output port Oi The total output packet rate is generated by summing the data packet rates on all input ports sharing the same output port, and the minimum frequency O of the output port is calculated based on the total output packet rate. i-min Then set the router's minimum frequency r. min Set to the minimum frequency O for all output ports i-min The maximum value in r. Then identify the value that satisfies r. min The valid CD is then used to allocate the initial router clock domain.

[0104] Figure 9B A flow flow view 610 depicts the flow flow on a baseline topology 507 of NoC 300 according to one embodiment of the present disclosure.

[0105] Generally, routers can have up to 8 input ports, up to 8 output ports, and support up to 4 VCs to meet timing requirements. In the base topology 507, routers 540 and 544 receive traffic on 2 input ports and transmit traffic on 1 output port and 1 VC. Router 542 receives traffic on 6 input ports and transmits traffic on 1 output port and 1 VC. In other words, routers 540, 542, and 544 have at least one output shared by multiple input ports.

[0106] For Router 540, the sum of the packet rates on the two input ports sharing a single output port is 200 × 10⁻⁶. 6 Packets per second. The minimum frequency for a single output port is set at 0.2 GHz, which is also the router's minimum frequency r. min Then satisfy r min The effective CD is identified as 0.5GHz and 1GHz, and then based on r min And the initial router clock domain of 1GHz is allocated to the operating frequency of devices 310 and 311.

[0107] For router 542, the sum of the packet rates on the six input ports sharing a single output port is 600 × 10⁻⁶. 6 Packets per second. The minimum frequency for a single output port is set at 0.6 GHz, which is also the router's minimum frequency r. min Then satisfy r min The effective CD is identified as 0.5GHz and 1GHz, and then based on r min The operating frequency of devices 312, 313, 314, 315, 316 and 317 is allocated to the initial router clock domain of 0.5 GHz.

[0108] For router 544, the sum of the packet rates on the two input ports sharing a single output port is 800 × 10⁻⁶.6 Packets per second. The minimum frequency for a single output port is determined to be 0.8 GHz, which is also the router's minimum frequency r. min Then satisfy r min The effective CD is identified as 0.5GHz and 1GHz, and then based on r min The operating frequency of device 318 is allocated to the initial router clock domain of 1GHz.

[0109] Figure 10A A flow flow view 620 depicts the flow flow on a baseline topology 507 of NoC 300 according to one embodiment of the present disclosure.

[0110] While PCDC buffers can be added at later stages (e.g., at 270 below), in many implementations, they are added earlier to aid in clock domain allocation and optimization. In this implementation, PCDC buffer P11 has been added to the 1GHz clock domain and is located between router 542 and router 544. PCDC buffer P15 has been added to the 1GHz clock domain for flexibility and is located between router 540 and router 544.

[0111] With this initial allocation of the clock domain, 100 × 10⁻⁶ units per second can be generated based on the clocks derived from each of devices 310, 311, 312, 313, 314, 315, 316, and 317. 6 The normalized packet rate on the link between the device, router, and PCDC buffer is calculated using the traffic flow of individual transactions (or packets) and the clock domain frequency. The normalized packet rate for a specific link can be defined as the number of transactions per second divided by the frequency of the clock domain on which the link resides. For example, the normalized packet rate on the link between device 310 and router 540 is 100 × 10⁻⁶. 6 / 1×10 9 Or 0.1 packets / period, the normalized packet rate on the link between device 312 and router 542 is 100×10 6 / 0.5×10 9 Or 0.2 groups / cycle, and so on.

[0112] More specifically, router 540 receives 0.1 packets / cycle from device 310 through a first input port, receives 0.1 packets / cycle from device 311 through a second input port, and transmits 0.2 packets / cycle to PCDC buffer P15 through one output port and one VC. PCDC buffer P15 transmits 0.2 packets / cycle to router 544. These normalized packet rates are determined relative to a 1 GHz clock domain, where one cycle equals 1 × 10⁻¹⁰. -9 Second.

[0113] Router 542 receives 0.2 packets / cycle from device 312 through its first input port, 0.2 packets / cycle from device 313 through its second input port, 0.2 packets / cycle from device 314 through its third input port, 0.2 packets / cycle from device 315 through its fourth input port, 0.2 packets / cycle from device 316 through its fifth input port, and 0.2 packets / cycle from device 317 through its sixth input port. Router 542 transmits 1.2 packets / cycle to PCDC buffer P11 through one output port and one VC. PCDC buffer P11 transmits 0.6 packets / cycle to router 544. These normalized packet rates are determined relative to a 0.5 GHz clock domain, where one cycle equals 2 × 10⁻⁶. -9 Second.

[0114] Router 544 receives 0.2 packets / cycle from PCDC buffer P15 through its first input port, 0.6 packets / cycle from PCDC buffer P11 through its second input port, and transmits 0.8 packets / cycle to device 318. These normalized packet rates are determined relative to a 1 GHz clock domain, where one cycle equals 1 × 10⁻⁶. -9 Second.

[0115] Under the baseline topology 507, router 542 violates the minimum router frequency requirement because it has been assigned an initial clock domain of 0.5 GHz but has a minimum frequency r of 0.6 GHz. min This results in an allocation of 1.2 packets / cycle from a single output port and VC, which is greater than the maximum allowed normalized packet rate of 1 packet / cycle. This clock domain violation occurs in... Figure 10A The instructions are in accordance with the central government.

[0116] Furthermore, router 542 provides a normalized packet rate of 0.6 packets / cycle to one of the input ports of router 544, which creates a packet rate imbalance compared to the normalized packet rate of 0.2 packets / cycle provided by router 540 to the other input port of router 544. This packet rate imbalance also... Figure 10A The instructions state that clock domain violations can be eliminated at a performance cost, and that the normalized packet rate on the input ports of the router 544 can be balanced.

[0117] Generally speaking, for an assigned frequency less than its minimum frequency (i.e., r) min For each router, determine the maximum normalized packet rate difference parameter (i.e., P) for that router. router Then for P router The parameters are summed to generate the grouping rate balance cost for exploring other variations of the baseline topology.

[0118] More specifically, for each output port and VC combination {port, VC} on the router, i.e., OVC, the difference between the normalized packet rates, i.e., P, is calculated for each pair (or combination) of input ports {i, j} sharing the OVC. ij Then determine the maximum P of the OVC. ij and minimum P ij The difference between them, i.e., P OVC Then determine the router's maximum P. OVC Finally, for each router's P... OVC Sum the results to generate a grouping rate to balance the cost.

[0119] Figure 10B A flow flow view 630 depicts the flow flow on a first variant topology of NoC 300 according to one embodiment of the present disclosure.

[0120] In this implementation, router 542 has been relocated to the 1GHz clock domain, and PCDC buffers P2, P3, P4, P5, P6, and P7 have been added to the 1GHz clock domain. PCDC buffers P2, P3, P4, P5, P6, and P7 are located between router 542 and devices 312, 313, 314, 315, 316, and 317, respectively, to address clock domain violation issues.

[0121] More specifically, PCDC buffer P2 receives 0.2 packets / cycle from device 312 and transmits 0.1 packets / cycle to router 542. PCDC buffer P3 receives 0.2 packets / cycle from device 313 and transmits 0.1 packets / cycle to router 542. PCDC buffer P4 receives 0.2 packets / cycle from device 314 and transmits 0.1 packets / cycle to router 542. PCDC buffer P5 receives 0.2 packets / cycle from device 315 and transmits 0.1 packets / cycle to router 542. PCDC buffer P6 receives 0.2 packets / cycle from device 316 and transmits 0.1 packets / cycle to router 542. PCDC buffer P7 receives 0.2 packets / cycle from device 317 and transmits 0.1 packets / cycle to router 542. Router 542 transmits 0.6 packets / cycle to router 544 via a single output port and VC.

[0122] The traffic flow from devices 310, 311, and router 540 remains the same as the baseline topology 507. More specifically, router 540 receives 0.1 packets / cycle from device 310 through a first input port, receives 0.1 packets / cycle from device 311 through a second input port, and transmits 0.2 packets / cycle to PCDC buffer P15 through one output port and one VC. PCDC buffer P15 transmits 0.2 packets / cycle to router 544. Router 544 receives 0.2 packets / cycle from PCDC buffer P15 through a first input port, receives 0.6 packets / cycle from router 542 through a second input port, and transmits 0.8 packets / cycle to device 318.

[0123] Although the clock domain violation has been eliminated, the packet rate imbalance at router 544 has not been resolved, and... Figure 10B The instructions state that adding six PCDC buffers to the 1GHz clock domain may not meet other design requirements of NoC, such as PPA design constraints.

[0124] Figure 10C A flow flow view 640 depicts the flow flow on a second variant topology of NoC 300 according to one embodiment of the present disclosure.

[0125] In this implementation, router 542 has been relocated to the 0.5 GHz clock and split into two routers, namely router 542 (R11.1) and router 543 (R11.2), to address the clock domain violation issue. PCDC buffers 11.1 and 11.2 have also been introduced into the 1 GHz clock domain.

[0126] Router 540 receives 0.1 packets / cycle from device 310 through its first input port and 0.1 packets / cycle from device 311 through its second input port, and transmits 0.2 packets / cycle to PCDC buffer P15 through one output port and one VC. PCDC buffer P15 then transmits 0.2 packets / cycle to router 544.

[0127] Router 542 receives 0.2 packets / cycle from device 312 through its first input port, 0.2 packets / cycle from device 313 through its second input port, 0.2 packets / cycle from device 314 through its third input port, 0.2 packets / cycle from device 315 through its fourth input port, and 0.2 packets / cycle from device 316 through its fifth input port. Router 542 transmits 1.0 packets / cycle to PCDC buffer P11.1 through one output port and one VC. PCDC buffer P11.1 transmits 0.5 packets / cycle to router 544.

[0128] Router 543 receives 0.2 packets / cycle from device 317 through its first input port and transmits the 0.2 packets / cycle to PCDC buffer P11.2 through one output port and one VC. PCDC buffer P11.2 transmits 0.1 packets / cycle to router 544.

[0129] Router 544 receives 0.2 packets / cycle from PCDC buffer P15 through the first input port, 0.5 packets / cycle from router 542 through the second input port, and 0.1 packets / cycle from router 543 through the third input port, and transmits 0.8 packets / cycle to device 318.

[0130] Although the clock domain violation has been eliminated, the normalized packet rate output by router 542 is the maximum allowed normalized packet rate of 1 packet / cycle. This does not provide an optimal solution because any processing delay occurring at router 542 will result in lost packet transmissions to the PCDC buffer P11.1.

[0131] Furthermore, the packet rate imbalance at router 544 remains unresolved. Router 542 provides a normalized packet rate of 0.5 packets / cycle to the second input port of router 544, which results in a packet rate imbalance compared to the normalized packet rate of 0.2 packets / cycle provided by router 540 to the first input port of router 544 and the normalized packet rate of 0.2 packets / cycle provided by router 543 to the third input port of router 544. This packet rate imbalance... Figure 10C The instructions are in accordance with the central government.

[0132] Table 1 summarizes... Figure 10C The normalized packet rate and packet transmission period of certain links are described in the diagram. The link from PCDC buffer P15 to router 544 is identified as "P15 to R20", the link from PCDC buffer P11.1 to router 544 is identified as "P11.1 to R20", the link from PCDC buffer P11.2 to router 544 is identified as "P11.2 to R20", and the link from router 542 to PCDC buffer P11.1 is identified as "R11.1 to P11.1".

[0133] link Normalized grouping rate Packet transmission period P15 to R20 0.2 groups / cycles 0、5、10、15、20... P11.1 to R20 0.5 groups / cycle 0、2、4、6、8、10、12、14... P11.2 to R20 0.1 group / cycle 0、10、20... R11.1 to P11.1 1.0 Grouping / Period 0、1、2、3、4、5...

[0134] Table 1

[0135] In this implementation, during periods 0, 10, 20, etc., arbitration at router 544 (R20) forces packets transmitted via P11.1 to R20 to wait for two periods, which also causes packets transmitted via the R11.1 to P11.1 link to wait for one period. The performance loss on the R11.1 to P11.1 link is 20%.

[0136] Figure 10D A flow flow view 650 depicts the flow of traffic on the final topology of NoC 300 according to one embodiment of this disclosure.

[0137] In this implementation, two traffic flows (i.e., traffic flow sets 325 and 326) have been redistributed from router 542 to router 543.

[0138] Router 540 receives 0.1 packets / cycle from device 310 through its first input port and 0.1 packets / cycle from device 311 through its second input port, and transmits 0.2 packets / cycle to PCDC buffer P15 through one output port and one VC. PCDC buffer P15 then transmits 0.2 packets / cycle to router 544.

[0139] Router 542 receives 0.2 packets / cycle from device 312 through its first input port, 0.2 packets / cycle from device 313 through its second input port, and 0.2 packets / cycle from device 314 through its third input port. Router 542 transmits 0.6 packets / cycle to PCDC buffer P11.1 through one output port and one VC. PCDC buffer P11.1 transmits 0.3 packets / cycle to router 544.

[0140] Router 543 receives 0.2 packets / cycle from device 315 through its first input port, 0.2 packets / cycle from device 316 through its second input port, and 0.2 packets / cycle from device 317 through its third input port. Router 543 transmits 0.6 packets / cycle to PCDC buffer P11.2 through one output port and one VC. PCDC buffer P11.2 transmits 0.3 packets / cycle to router 544.

[0141] Router 544 receives 0.2 packets / cycle from PCDC buffer P15 through the first input port, receives 0.3 packets / cycle from router 542 through the second input port, receives 0.3 packets / cycle from router 543 through the third input port, and transmits 0.8 packets / cycle to device 318.

[0142] Table 2 summarizes... Figure 10DThe normalized packet rate and packet transmission period of certain links are described in the diagram. The link from PCDC buffer P15 to router 544 is identified as "P15 to R20", the link from PCDC buffer P11.1 to router 544 is identified as "P11.1 to R20", the link from PCDC buffer P11.2 to router 544 is identified as "P11.2 to R20", the link from router 542 to PCDC buffer P11.1 is identified as "R11.1 to P11.1", and the link from router 543 to PCDC buffer P11.2 is identified as "R11.2 to P11.2".

[0143] link Normalized grouping rate Packet transmission period P15 to R20 0.2 groups / cycles 0、5、10、15、20... P11.1 to R20 0.3 groups / cycle 0、3、6、10、13、16、20... P11.2 to R20 0.3 groups / cycle 0、3、6、10、13、16、20... R11.1 to P11.1 0.6 groups / cycle 0、2、4、5、6、8、10、12、14... R11.2 to P11.2 0.6 groups / cycle 0、2、4、5、6、8、10、12、14...

[0144] Table 2

[0145] In this implementation, during periods 0, 10, 20, etc., arbitration at router 544 (R20) forces packets transmitted to R20 via P11.1 or via P11.2 to R20 to wait for one period, but packets transmitted via the R11.1 to P11.1 link or the R11.2 to P11.2 link do not experience period loss. No performance loss occurs.

[0146] The final topology is a balanced NoC topology, which eliminates the clock domain violations and packet rate imbalances present in the baseline topology 507.

[0147] At point 250, the final route for each traffic flow is determined. In one implementation, shortest path routing is used, with optional constraints to uncycle loops in the resulting topology. Different routing methods can be employed, such as, for example, XY-YX routing, no-turn routing, etc.

[0148] At position 260, a configuration network is generated. In many implementations, the configuration network can be used for debugging purposes. This configuration network includes bridge ports, routers, connections, and routes. In one implementation, the configuration network simulates a data network. Additionally, the configuration network can be optimized independently, similar to a data network. The latency and performance of the configuration network are typically lenient to produce the simplest design with minimal area.

[0149] At position 270, a PCDC buffer is added to the connection between a bridge or router in the synchronous clock domain and an adjacent bridge or router in the asynchronous clock domain, and the clock domain allocation can be refined. Link sizes are also determined for each router in each route, and size adjusters are added between the bridge and routers with different link sizes or between adjacent routers with different link sizes. Generally, link sizes are determined using bridge data, traffic data, VC allocation, and topology to collectively meet average traffic performance requirements and individually meet peak traffic performance requirements. Additionally, the number of size adjusters added to the NoC is minimized to reduce latency encountered by traffic flows. In some implementations, it is permissible for certain bridge ports to reach peak traffic simultaneously.

[0150] At 280, pipelines and time-reordered components are added based on timing. To satisfy timing requirements, pipeline components are added at appropriate locations to keep the slack (i.e., the difference between the required time and the arrival time) within appropriate constraints. For example, one or more components may be repositioned, and if the repositioned components do not satisfy timing requirements, one or more pipeline components may be added. For example, component repositioning may be based on force-oriented arrangement, etc. In some implementations, boxes 260, 270, and 280 may be repeated until NoC has been optimized.

[0151] At point 290, NoC output specification 292 is generated and then stored in memory 130. Additionally, NoC output specification 292 can be transmitted via network 20, provided to software modules 136 used by NoC designers, etc. For example, NoC output specification 292 can be provided as input to the NoC manufacturing process of a chip foundry. Report 294 can also be generated and then stored in memory 130. For example, report 294 may contain information about components used in the design (e.g., routers, sizers, PCDCs, pipelines, etc.), traffic on each link, link utilization, latency across paths, etc.

[0152] Figure 11 A final topology 508 of NoC 300 according to one embodiment of this disclosure is depicted. The final topology 508 can be viewed by a user on a display 152.

[0153] NoC 300 now includes clock domains 302 and 303. Clock domain 302 is a 0.5 GHz clock domain, while clock domain 303 is a 1 GHz clock domain.

[0154] Devices 310 and 311 are connected to router 540. Devices 312, 313, and 314 are connected to router 542. Devices 315, 316, and 317 are connected to router 543. Device 318 is connected to router 544. Router 540 is connected to router 544 via PCDC buffer P15. Router 542 is connected to router 544 via PCDC buffer P11.1. Router 543 is connected to router 544 via PCDC buffer P11.2.

[0155] Figure 12A , Figure 12B and Figure 12C A flowchart depicting a representation of the functionality associated with the synthesis of NoC according to one embodiment of this disclosure is provided. Figure 12A Draw a flowchart 600. Figure 12B Draw flowchart 601, and Figure 12C Draw flowchart 602.

[0156] At 610, the input specification based on NoC determines physical data, device data, bridge data, and traffic data. The physical data includes NoC dimensions, the device data includes multiple devices, the bridge data includes multiple bridge ports, and the traffic data includes multiple traffic flows. Each device has a location and dimension, each bridge port is associated with and has a location within a device, and each traffic flow has a packet rate.

[0157] At 620, a virtual channel (VC) is assigned to each traffic flow to create multiple VC allocations.

[0158] At position 630, a baseline topology is generated based on physical data, device data, bridge data, traffic data, and VC allocation. This baseline topology includes bridge ports, routers, and connections. Each router has one or more input ports and one or more output ports.

[0159] In some implementations, the functions at positions 631 to 635 are performed to generate a baseline topology.

[0160] At point 631, a HoL (House of Lines) Conflict Graph (HCG) is constructed based on traffic data and VC allocation. This involves creating multiple nodes, multiple edges, and assigning a color to each node to minimize HoL conflicts. Each node represents a traffic flow, and each edge represents a HoL conflict.

[0161] At point 632, multiple flow maps (TGs) are constructed based on physical data, bridge data, flow data, and HCG, including constructing TGs for each color of HCG.

[0162] At position 633, candidate topologies are generated for each TG. Each candidate topology includes at least two bridge ports, at least one router, and at least two connections.

[0163] At position 634, candidate topologies are merged to create a baseline topology.

[0164] At 635, routers within the baseline topology are merged. The process then proceeds to 640.

[0165] In other implementations, the functions at 610, 620, and 630 are not performed. Instead, at 605, the computer 100 receives traffic data, VC allocation, and reference topology, or alternatively, retrieves traffic data, VC allocation, and reference topology from memory 130, and then the process proceeds to 640.

[0166] At 640, each router is identified as having at least one output port, which is shared by traffic streams received on at least two input ports.

[0167] Repeat the functions at 650 and 651 for each identified router.

[0168] At 650, the minimum frequency of the identified router is calculated based on the packet rate of the traffic flow received by the identified router.

[0169] At 651, a clock domain is assigned to the identified router based on the minimum frequency of the identified router.

[0170] At 660, packet rate balancing based on traffic flow is performed on the traffic flow received by the identified router.

[0171] At 670, the final topology is generated based on the baseline topology and the balanced traffic flow of the identified routers.

[0172] The embodiments disclosed herein advantageously provide a computer-based method and system for synthesizing networks on a chip (NoC). The embodiments described above and summarized below are composable.

[0173] In one implementation, a computer-based method for synthesizing a NoC is provided. The NoC-based input specification determines physical data, device data, bridge data, and traffic data. The physical data includes dimensions of the NoC; the device data includes multiple devices, each with a location and dimension; the bridge data includes multiple bridge ports, each associated with and having a location among the devices; and the traffic data includes multiple traffic flows, each with a packet rate. Virtual channels (VCs) are assigned to each traffic flow to create multiple VC allocations. A baseline topology is generated based on the physical data, device data, bridge data, traffic data, and VC allocations. This baseline topology includes multiple bridge ports, multiple routers, and multiple connections, each router having one or more input ports and one or more output ports. Each router with at least one output port is identified, shared by traffic flows received on at least two input ports. For each identified router, a minimum frequency for the identified router is calculated based on the packet rate of the traffic flows received by the identified router, and a clock domain is allocated to the identified router based on this minimum frequency. The traffic flows received by the identified router are balanced based on the packet rate of the traffic flows. The final topology is generated based on the baseline topology and the balanced traffic flow of the identified routers.

[0174] In another implementation of this method, each shared output port transmits traffic streams through a single VC.

[0175] In another embodiment of the method, the calculation of the minimum frequency of the identified router includes, for each output port: summing the packet rates of the traffic streams received on the input ports of the shared output ports to generate a total output packet rate, and calculating the minimum frequency of the output port based on the total output packet rate; determining the maximum frequency among the minimum frequencies of the output ports; and setting the minimum frequency of the identified router to the maximum frequency.

[0176] In another embodiment of the method, the method further includes: adding a Physical Clock Domain Cross (PCDC) buffer to each link between two routers assigned to different clock domains; determining a normalized packet rate of traffic flow between the bridge port, the router, and the PCDC buffer based on the assigned clock domain; and identifying clock domain violations of the identified router based on the assigned clock domain and the normalized packet rate.

[0177] In another embodiment of the method, balancing traffic flows includes: identifying packet rate imbalances in the identified routers based on normalized packet rates; determining performance costs based on the allocated clock domain and normalized packet rates; and correcting clock domain violations and packet rate imbalances based on the performance costs.

[0178] In another implementation of this method, performance costs include router clock domain violation costs and packet rate balancing costs.

[0179] In another embodiment of the method, correcting clock domain violations and packet rate imbalances includes at least one of the following: assigning different clock domains to one or more identified routers; routing one or more traffic flows to different identified routers; and adding one or more identified routers.

[0180] In another embodiment of the method, generating a baseline topology includes: constructing a HoL (Holly-Ended) Conflict Graph (HCG) based on traffic data and VC allocation, including creating multiple nodes, each node representing a traffic flow, creating multiple edges, each edge representing a HoL conflict, and assigning a color to each HCG node to minimize HoL conflicts; constructing multiple Traffic Graphs (TGs) based on physical data, bridge data, traffic data, and the HCG, including constructing TGs for each color of the HCG; generating candidate topologies for each TG, each candidate topology including at least two bridge ports, at least one router, and at least two connections; merging candidate topologies to create a baseline topology; and merging routers within the baseline topology.

[0181] In one embodiment, a system for synthesizing NoCs includes: a memory for storing input specifications of the NoCs; and a processor coupled to the memory. The processor is configured to: determine physical data, device data, bridge data, and traffic data based on the NoC input specifications, the physical data including dimensions of the NoCs, the device data including multiple devices, each device having a location and dimension, the bridge data including multiple bridge ports, each bridge port associated with and having a location among the devices, and the traffic data including multiple traffic flows, each traffic flow having a packet rate; allocate virtual channels (VCs) for each traffic flow to create multiple VC allocations; and generate a baseline topology based on the physical data, device data, bridge data, traffic data, and VC allocations, the baseline topology including multiple bridge ports, multiple routers, and multiple connections. Each router has one or more input ports and one or more output ports; each router with at least one output port is identified, which is shared by traffic flows received on at least two input ports; for each identified router: the minimum frequency of the identified router is calculated based on the packet rate of the traffic flows received by the identified router, and a clock domain is allocated to the identified router based on the minimum frequency of the identified router; the traffic flows received by the identified router are balanced based on the packet rate of the traffic flows; and a final topology is generated based on the baseline topology and the balanced traffic flows of the identified router.

[0182] In another implementation of the system, each shared output port transmits traffic streams through a single VC.

[0183] In another implementation of the system, calculating the minimum frequency of the identified router includes, for each output port: summing the packet rates of the traffic streams received on the input ports of the shared output ports to generate a total output packet rate, and calculating the minimum frequency of the output port based on the total output packet rate; determining the maximum frequency among the minimum frequencies of the output ports; and setting the minimum frequency of the identified router to the maximum frequency.

[0184] In another embodiment of the system, the processor is further configured to: add a Physical Clock Domain Cross (PCDC) buffer to each link between two routers assigned to different clock domains; determine the normalized packet rate of the traffic flow between the bridge port, the router, and the PCDC buffer based on the assigned clock domain; and identify clock domain violations of the identified router based on the assigned clock domain and the normalized packet rate.

[0185] In another implementation of the system, balancing traffic flows includes: identifying packet rate imbalances in identified routers based on normalized packet rates; determining performance costs based on allocated clock domains and normalized packet rates; and correcting clock domain violations and packet rate imbalances based on performance costs.

[0186] In another implementation of the system, performance costs include router clock domain violation costs and packet rate balancing costs.

[0187] In another implementation of the system, correcting clock domain violations and packet rate imbalances includes at least one of the following: assigning different clock domains to one or more identified routers; routing one or more traffic flows to different identified routers; and adding one or more identified routers.

[0188] In another implementation of the system, generating a baseline topology includes: constructing a HoL (Holly-Ended) Conflict Graph (HCG) based on traffic data and VC allocation, including creating multiple nodes, each node representing a traffic flow, creating multiple edges, each edge representing a HoL conflict, and assigning a color to each HCG node to minimize HoL conflicts; constructing multiple Traffic Graphs (TGs) based on physical data, bridge data, traffic data, and the HCG, including constructing TGs for each color of the HCG; generating candidate topologies for each TG, each candidate topology including at least two bridge ports, at least one router, and at least two connections; merging candidate topologies to create a baseline topology; and merging routers within the baseline topology.

[0189] In one implementation, another computer-based method for synthesizing NoC is provided. Traffic data, Virtual Channel (VC) allocations, and a baseline topology are received. The traffic data includes multiple traffic flows, and the baseline topology includes multiple bridge ports, multiple routers, and multiple connections. Each router has one or more input ports and one or more output ports, and each traffic flow has a packet rate. Each router with at least one output port is identified, which is shared by traffic flows received on at least two input ports. For each identified router: a minimum frequency for the identified router is calculated based on the packet rate of the traffic flows received by the identified router, and a clock domain is allocated to the identified router based on the minimum frequency of the identified router. The traffic flows received by the identified router are balanced based on the packet rates of the traffic flows. A final topology is generated based on the baseline topology and the balanced traffic flows of the identified routers.

[0190] In another embodiment of this alternative method, each shared output port transmits traffic streams through a single VC, and the calculation of the minimum frequency of the identified router includes, for each output port: summing the packet rates of the traffic streams received on the input ports of the shared output port to generate a total output packet rate, and calculating the minimum frequency of the output port based on the total output packet rate; determining the maximum frequency among the minimum frequencies of the output ports; and setting the minimum frequency of the identified router to the maximum frequency.

[0191] In another embodiment of this alternative method, the alternative method further includes: adding a Physical Clock Domain Cross-Connect (PCDC) buffer to each link between two routers assigned to different clock domains; determining a normalized packet rate for traffic flow between the bridge port, the router, and the PCDC buffer based on the assigned clock domain; and identifying clock domain violations of the identified routers based on the assigned clock domain and the normalized packet rate, wherein balancing the traffic flow includes: identifying packet rate imbalances of the identified routers based on the normalized packet rate, determining a performance cost based on the assigned clock domain and the normalized packet rate, the performance cost including router clock domain violation cost and packet rate balancing cost, and correcting clock domain violations and packet rate imbalances based on the performance cost.

[0192] In another embodiment of this alternative method, correcting clock domain violations and packet rate imbalances includes at least one of the following: assigning different clock domains to one or more identified routers; routing one or more traffic flows to different identified routers; and adding one or more identified routers.

[0193] While specific embodiments of this disclosure can take many different forms, the particular embodiments shown in the accompanying drawings and described in detail herein should be understood as examples of the principles of this disclosure and not intended to limit this disclosure to the specific embodiments shown and described. In the foregoing description, similar reference numerals may be used to describe the same, similar, or corresponding parts in several views of the drawings.

[0194] In this document, relational terms such as first and second, top and bottom, etc., are used only to distinguish one entity or action from another entity or action, and do not necessarily require or imply any actual such relationship or order between such entities or actions. The terms “comprising,” “including,” “containing,” “having,” or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but may also include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element preceded by “comprising…one” does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes that element, unless further limited.

[0195] Throughout this document, the terms “an embodiment,” “certain embodiments,” “implementation,” “specific implementation,” “aspect,” or similar terms refer to a particular feature, structure, or characteristic described in connection with that embodiment, which is included in at least one embodiment of this disclosure. Therefore, the appearance of such phrases in various places throughout this specification does not necessarily refer to the same embodiment. Furthermore, specific features, structures, or characteristics can be combined in any suitable manner without limitation in one or more embodiments.

[0196] As used herein, the term “or” will be interpreted as inclusive or meaning any one or any combination. Thus, “A, B, or C” means “any of the following: A; B; C; A and B; A and C; B and C; A, B, and C.” Exceptions to this definition will only occur if the combination of elements, functions, steps, or actions is inherently mutually exclusive in some way. Furthermore, grammatical connections are intended to express any and all combinations of separations and connections of connected items, clauses, words, etc., unless otherwise stated or clear from the context. Therefore, the term “or” should generally be understood to mean “and / or,” etc. References to singular items should be understood to include plural items and vice versa, unless otherwise explicitly stated or clearly evident from the text.

[0197] Unless otherwise specified, the descriptions of ranges of values ​​herein are not intended to be limiting, but rather to individually refer to any and all values ​​falling within such ranges, and each individual value within such ranges is incorporated herein as if individually described herein. When accompanied by numerical values, the terms “about,” “approximately,” etc., should be understood as indicating a deviation that, as would be understood by one of ordinary skill in the art, satisfactorily operates for the intended purpose. Ranges of values ​​and / or numerical values ​​are provided herein by way of example only and do not constitute a limitation on the scope of the described embodiments. The use of any and all examples or exemplary language (“e.g.,” “such as,” etc.) provided herein is intended only to better illustrate the embodiments and is not intended to limit the scope of the embodiments. No language in this specification should be construed as indicating that any unclaimed element is essential to the practice of the embodiments.

[0198] For simplicity and clarity, reference numerals may be repeated in the accompanying drawings to indicate corresponding or similar elements. Numerous details are set forth to provide an understanding of the embodiments described herein. These embodiments may be practiced without these details. In other instances, well-known methods, procedures, and components have not been described in detail to avoid obscuring the embodiments. This specification should not be construed as limiting the scope to the embodiments described herein.

[0199] In the following description, it should be understood that terms such as “first,” “second,” “top,” “bottom,” “upper,” “lower,” “above,” and “below” are used for convenience and should not be construed as restrictive terms. Furthermore, the terms device, equipment, and system are used interchangeably herein.

[0200] From the detailed description, many features and advantages of this disclosure will be apparent, and therefore the appended claims are intended to cover all such features and advantages of this disclosure that fall within its scope. Furthermore, since many modifications and variations will readily occur to those skilled in the art, it is not intended to limit this disclosure to the exact constructions and operations shown and described, and therefore all suitable modifications and equivalents falling within the scope of this disclosure are possible.

Claims

1. A computer-based method for synthesizing on-chip networks (NoC), the computer-based method comprising: Based on the input specifications of the NoC, physical data, device data, bridge data, and traffic data are determined. The physical data includes the dimensions of the NoC. The device data includes multiple devices, each with a location and dimension. The bridge data includes multiple bridge ports, each associated with one of the devices and having a location. The traffic data includes multiple traffic streams, each with a packet rate. Assign a virtual channel (VC) to each traffic flow to create multiple VC allocations; A baseline topology is generated based on the physical data, the device data, the bridge data, the traffic data, and the VC allocation. The baseline topology includes the multiple bridge ports, multiple routers, and multiple connections. Each router has one or more input ports and one or more output ports. Identify each router having at least one output port, each router having at least one output port being shared by traffic streams received on at least two input ports; For each identified router: The minimum frequency of the identified router is calculated based on the packet rate of the traffic flow received by the identified router, and Assign a clock domain to the identified router based on the minimum frequency of the identified router; The packet rate balance based on the traffic flow is the traffic flow received by the identified router. as well as The final topology is generated based on the baseline topology and the balanced traffic flow of the identified routers.

2. The computer-based method of claim 1, wherein each shared output port transmits the traffic stream through a single VC.

3. The computer-based method according to claim 2, wherein calculating the minimum frequency of the identified router includes: For each output port: The packet rates of the traffic streams received on the input ports sharing the output port are summed to generate the total output packet rate. Calculate the minimum frequency of the output port based on the total output packet rate; Determine the maximum frequency among the minimum frequencies of the output port; as well as Set the minimum frequency of the identified router to the maximum frequency.

4. The computer-based method according to claim 3 further includes: Add a Physical Clock Domain Cross (PCDC) buffer to each link between two routers assigned to different clock domains; The normalized packet rate of the traffic flow between the bridge port, router, and PCDC buffer is determined based on the allocated clock domain. as well as The clock domain violation of the identified router is identified based on the allocated clock domain and the normalized packet rate.

5. The computer-based method according to claim 4, wherein balancing the flow includes: The packet rate imbalance of the identified routers is based on the normalized packet rate identification. The performance cost is determined based on the allocated clock domain and the normalized packet rate. as well as The clock domain violation and the packet rate imbalance are corrected based on the performance cost.

6. The computer-based method according to claim 5, wherein the performance cost includes router clock domain violation cost and packet rate balancing cost.

7. The computer-based method of claim 6, wherein correcting the clock domain violation and the packet rate imbalance comprises at least one of the following: Assign different clock domains to one or more identified routers; Routing one or more traffic flows to different identified routers; and Add one or more of the identified routers.

8. The computer-based method according to claim 1, wherein generating the baseline topology comprises: Constructing a line-end (HoL) conflict graph (HCG) based on the traffic data and the VC allocation includes: Create multiple nodes, each representing a traffic flow. Create multiple edges, each representing a HoL conflict, and Assign a color to each HCG node to minimize HoL conflicts; Multiple flow maps (TGs) are constructed based on the physical data, the bridge data, the flow data, and the HCG, including constructing TGs for each color of the HCG; For each TG, a candidate topology is generated, and each candidate topology includes at least two bridge ports, at least one router, and at least two connections. Merging the candidate topologies to create the baseline topology; and Merge the routers within the baseline topology.

9. A system for synthesizing on-chip networks (NoC), the system comprising: A memory for storing the input specifications of NoC; and A processor, coupled to the memory, is configured to: Based on the input specifications of the NoC, physical data, device data, bridge data, and traffic data are determined. The physical data includes the dimensions of the NoC. The device data includes multiple devices, each with a location and dimension. The bridge data includes multiple bridge ports, each associated with one of the devices and having a location. The traffic data includes multiple traffic flows, each with a packet rate. Assign virtual channels (VCs) to each traffic flow to create multiple VC allocations. A baseline topology is generated based on the physical data, device data, bridge data, traffic data, and VC allocation. This baseline topology includes the multiple bridge ports, multiple routers, and multiple connections. Each router has one or more input ports and one or more output ports. Identify each router having at least one output port, wherein each router with at least one output port is shared by traffic streams received on at least two input ports. For each identified router: The minimum frequency of the identified router is calculated based on the packet rate of the traffic flow received by the identified router, and A clock domain is allocated to the identified router based on the minimum frequency of the identified router. The packet rate balancing based on the traffic flow is applied to the traffic flow received by the identified router, and The final topology is generated based on the baseline topology and the balanced traffic flow of the identified routers.

10. The system of claim 9, wherein each shared output port transmits the traffic stream via a single VC.

11. The system of claim 10, wherein the calculation of the minimum frequency of the identified router includes: For each output port: The packet rates of the traffic streams received on the input ports sharing the output port are summed to generate the total output packet rate. The minimum frequency of the output port is calculated based on the total output packet rate; Determine the maximum frequency among the minimum frequencies of the output port; as well as Set the minimum frequency of the identified router to the maximum frequency.

12. The system of claim 11, wherein the processor is further configured to: Add a Physical Clock Domain Cross (PCDC) buffer to each link between two routers assigned to different clock domains; The normalized packet rate of the traffic flow between the bridge port, router, and PCDC buffer is determined based on the allocated clock domain; and The clock domain violation of the identified router is identified based on the allocated clock domain and the normalized packet rate.

13. The system of claim 12, wherein balancing the flow rate comprises: The packet rate imbalance of the identified routers is identified based on the normalized packet rate. The performance cost is determined based on the allocated clock domain and the normalized packet rate. as well as The clock domain violation and the packet rate imbalance are corrected based on the performance cost.

14. The system of claim 13, wherein the performance cost includes router clock domain violation cost and packet rate balancing cost.

15. The system of claim 14, wherein correcting the clock domain violation and the packet rate imbalance comprises at least one of the following: Assign different clock domains to one or more identified routers; Routing one or more traffic flows to different identified routers; and Add one or more of the identified routers.

16. The system of claim 9, wherein generating the baseline topology comprises: Based on the traffic data and the VC allocation, a line-end (HoL) conflict graph (HCG) is constructed, including: Create multiple nodes, each representing a traffic flow. Create multiple edges, each representing a HoL conflict, and Assign a color to each HCG node to minimize HoL conflicts; Multiple flow maps (TGs) are constructed based on the physical data, the bridge data, the flow data, and the HCG, including constructing TGs for each color of the HCG; For each TG, a candidate topology is generated, and each candidate topology includes at least two bridge ports, at least one router, and at least two connections. Merging the candidate topologies to create the baseline topology; and Merge the routers within the baseline topology.

17. A computer-based method for synthesizing on-chip networks (NoC), the computer-based method comprising: The system receives traffic data, virtual channel (VC) allocations, and a baseline topology. The traffic data includes multiple traffic streams, and the baseline topology includes multiple bridge ports, multiple routers, and multiple connections. Each router has one or more input ports and one or more output ports, and each traffic stream has a packet rate. Identify each router having at least one output port, each router having at least one output port being shared by traffic streams received on at least two input ports; For each identified router: The minimum frequency of the identified router is calculated based on the packet rate of the traffic flow received by the identified router, and Assign a clock domain to the identified router based on the minimum frequency of the identified router; The packet rate balance based on the traffic flow is the traffic flow received by the identified router. as well as The final topology is generated based on the baseline topology and the balanced traffic flow of the identified routers.

18. The computer-based method of claim 17, wherein each shared output port transmits the traffic stream via a single VC, and the minimum frequency of the router identified by the calculation includes: For each output port: The packet rates of the traffic streams received on the input ports sharing the output port are summed to generate the total output packet rate. The minimum frequency of the output port is calculated based on the total output packet rate; Determine the maximum frequency among the minimum frequencies of the output port; as well as Set the minimum frequency of the identified router to the maximum frequency.

19. The computer-based method according to claim 18, further comprising: Add a Physical Clock Domain Cross (PCDC) buffer to each link between two routers assigned to different clock domains; The normalized packet rate of the traffic flow between the bridge port, router, and PCDC buffer is determined based on the allocated clock domain. as well as The clock domain violation of the identified router is identified based on the allocated clock domain and the normalized packet rate. The balancing of the flow rate includes: The packet rate imbalance of the identified routers is identified based on the normalized packet rate. The performance cost is determined based on the allocated clock domain and the normalized packet rate, the performance cost including router clock domain violation cost and packet rate balancing cost, and The clock domain violation and the packet rate imbalance are corrected based on the performance cost.

20. The computer-based method of claim 19, wherein correcting the clock domain violation and the packet rate imbalance comprises at least one of the following: Assign different clock domains to one or more identified routers; Routing one or more traffic flows to different identified routers; and Add one or more of the identified routers.

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