A high transmittance oxide TFT array substrate

Abstract

The present invention discloses a high transmittance oxide TFT array substrate, which includes a substrate, a first metal layer, a gate insulating layer, an active layer, a second metal layer, a second insulating layer, a third insulating layer, a third metal layer, a fourth insulating layer, a first electrode layer, a fifth insulating layer, a second electrode layer and a touch signal line. The first metal layer is disposed on the surface of the substrate. The first metal layer can serve as a gate and a driving signal line, and a gate insulating layer is disposed on the gate. The active layer is disposed on the gate insulating layer. Compared with the existing LCD array substrate with an embedded touch design, the embedded touch array substrate of the present invention has a more compact structure and a higher pixel aperture ratio, which is beneficial to the design of a high-resolution panel. Moreover, the source and drain of the TFT are respectively prepared by different metal layers, so that the signal overlapping region connecting the drain and the pixel electrode can cover the TFT active layer, reducing the unnecessary light-shielding area.

Description

Technical Field

[0001] The present invention belongs to the technical field of LCD array substrates, and particularly relates to a high transmittance oxide TFT array substrate. Background Art

[0002] Liquid crystal display is the current mainstream display mode, which is widely used in fields such as commercial advertising, mobile display, household TV, PC, laptop, etc. Liquid crystal screens have the advantages of long lifespan, small size, low power consumption, fine image quality, rich colors, etc. At present, liquid crystal screen display has penetrated into all walks of life and every corner of social life. The principle of liquid crystal display: A liquid crystal display is an active matrix liquid crystal display driven by thin film transistors. It mainly uses an electric current to stimulate liquid crystal molecules to generate dots, lines, and planes, combined with a backlight tube to form an image. Its working principle is that under the action of an electric field, the arrangement direction of liquid crystal molecules changes, causing the transmittance of external light sources to change (modulation), completing the electro-optical conversion. Then, through the different excitations of the R, G, and B primary color signals, and the combined action of the red, green, and blue primary color filter films, as well as the upper and lower polarizing layers, the color reproduction in the time domain and spatial domain is completed.

[0003] Liquid crystal screens rely on backlight sources to emit light. When light penetrates the panel, inevitable light loss will occur, such as the light being blocked by polarizing films, liquid crystals, filter films, and array films. Eventually, the light intensity reaching the human eye is only about 2 - 8% of the light intensity of the backlight source, resulting in low utilization rate of the backlight source light. Therefore, the present invention proposes a high transmittance oxide TFT array substrate. Summary of the Invention

[0004] The purpose of the present invention is to provide a high transmittance oxide TFT array substrate to solve the problems of large projected area of the light-blocking film layer and low light transmittance in the existing array substrate structure proposed in the above background art.

[0005] To achieve the above object, the present invention provides the following technical solution: a high transmittance oxide TFT array substrate, comprising a substrate, a first metal layer, a gate insulating layer, an active layer, a second metal layer, a second insulating layer, a third insulating layer, a third metal layer, a fourth insulating layer, a first electrode layer, a fifth insulating layer, a second electrode layer and a touch signal line. The gate is disposed on the surface of the substrate, and a gate insulating layer is disposed on the gate. The active layer is disposed on the gate insulating layer, and a second metal layer is disposed on the active layer. The second insulating layer is disposed on the second metal layer, and a third insulating layer is disposed on the second insulating layer. First through holes corresponding to each other in position are formed in both the second insulating layer and the third insulating layer, and a drain overlapping region is formed at the bottom end of the first through hole. The third metal layer is disposed on the third insulating layer. One end of the third metal layer covers the active layer through the first through hole. A fourth insulating layer is disposed on the third metal layer. The first electrode layer is disposed on the fourth insulating layer. The other end of the third metal layer can serve as a touch signal line and a common electrode signal line. The touch signal line contacts the first electrode layer through a via hole in the fourth insulating layer. The touch signal line can also function as a common electrode signal line. A fifth insulating layer is disposed on the first electrode layer. Second through holes corresponding to each other in position are formed in both the fourth insulating layer and the fifth insulating layer to expose the upper surface of the third metal layer. A drain pixel signal overlapping region is formed at the bottom end of the second through hole. The second electrode layer is disposed on the fifth insulating layer, and the second electrode layer is connected to the drain pixel signal overlapping region of the third metal layer through the second through hole. The drain pixel signal overlapping region and the TFT channel region overlap in the vertical projection plane on the substrate.

[0006] A high transmittance oxide TFT array substrate, comprising a substrate, a first metal layer, a first insulating layer, an active layer, a second metal layer, a second insulating layer, a third insulating layer, a third metal layer, a fourth insulating layer, a first electrode layer, a second electrode layer and a touch signal line. The first metal layer is disposed on the surface of the substrate as a gate and a gate driving signal line, and a first insulating layer is covered on the first metal layer as a gate insulating layer. An active layer is disposed on the gate insulating layer. A second metal layer is fabricated on the active layer. The second metal layer can be used as a TFT source electrode and a data signal line. At one end where the second metal layer serves as the source electrode, it is in direct contact with the active layer, and a second insulating layer is fabricated on the second metal layer. A third through hole is formed in the second insulating layer to expose the active layer. A drain overlapping region is formed at the bottom end of the third through hole. A third metal layer is fabricated on the second insulating layer, and the third metal layer contacts the upper surface of the active layer through the third through hole. The other end of the third metal layer covers the upper surface of the second insulating layer and is disposed above the channel of the TFT active layer away from the substrate. One end of the third metal layer can also be used as a touch signal line, and the touch signal line can also serve as a common electrode signal line function. A third insulating layer is prepared on the third metal layer. A fourth through hole is formed in the third insulating layer to expose the third metal layer. A first electrode layer is disposed on the third insulating layer. The first electrode layer is connected to the common electrode signal line through a via hole in the third insulating layer. A fourth insulating layer is disposed on the first electrode layer, and fifth through holes corresponding in position are formed in both the third insulating layer and the fourth insulating layer to expose the third metal layer. A drain pixel signal overlapping region is formed at the bottom end of the fifth through hole. A second electrode layer is disposed on the fourth insulating layer. The second electrode layer is connected to the drain pixel signal overlapping region through the fifth through hole.

[0007] Preferably, a connection through hole is formed in the gate insulating layer to expose the first metal layer for connecting the second metal layer.

[0008] Preferably, the gate, the second metal layer and the third metal layer are made of the same material, and the gate insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer are made of the same material.

[0009] Preferably, at one end of the third metal layer serving as the drain pixel signal overlapping region, the vertical projection area of its covering region on the substrate is not greater than the vertical projection area of the TFT gate on the substrate.

[0010] Preferably, an intermediate cushion layer can also be provided between the third metal layer and the active layer. In one structure, the second metal layer can be used as the intermediate layer.

[0011] Optionally, in some structures, the third insulating layer can be not provided.

[0012] Compared with the prior art, the beneficial effects of the present invention are as follows: Compared with the existing LCD array substrate with an inlaid touch design, the inlaid touch array substrate of the present invention has a more compact structure and a higher pixel aperture ratio, which is beneficial to the design of high-resolution panels;

[0013] Moreover, the source and drain electrodes of the TFT are respectively prepared by different metal layers, so that the signal overlapping area connecting the drain electrode and the pixel electrode can cover the TFT active layer, reducing unnecessary light-shielding area;

[0014] At the same time, by taking advantage of different metal layers, the routing distance between the touch signal line and the data signal line that must be reserved due to process accuracy can be reduced, so that the two metal traces can be designed to completely overlap, improving the light transmittance and aperture ratio of the panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a schematic structural diagram of Embodiment 1 of the present invention;

[0016] Figure 2 is a schematic structural diagram of Embodiment 2 of the present invention;

[0017] Figure 3 is a schematic structural diagram of Embodiment 3 of the present invention;

[0018] Figure 4 is a schematic structural diagram of Embodiment 4 of the present invention;

[0019] Figure 5 is a schematic structural diagram of Embodiment 5 of the present invention;

[0020] Figure 6 is a schematic top view structural diagram of the inlaid touch technology liquid crystal panel of the present invention;

[0021] In the figure: 1. Substrate; 2. Gate; 3. Gate insulating layer; 4. Active layer; 5. Second metal layer; 6. Second insulating layer; 7. Third insulating layer; 8. Third metal layer; 9. Fourth insulating layer; 10. First electrode layer; 11. Drain pixel signal overlapping area; 12. Fifth insulating layer; 13. Second electrode layer; 14. Touch signal line; 15. Drain overlapping area; 16. Pixel opening area; 17. Touch signal line; 18. Data signal line; 19. Source; 20. Drain; 21. Gate signal line. DETAILED DESCRIPTION OF THE INVENTION

[0022] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention. Embodiment

[0023] Please refer to Figure 1 and Figure 6 , the present invention provides a technical solution: a high transmittance oxide TFT array substrate, comprising a substrate 1, a gate 2, a gate insulating layer 3, an active layer 4, a second metal layer 5, a second insulating layer 6, a third insulating layer 7, a third metal layer 8, a fourth insulating layer 9, a first electrode layer 10, a fifth insulating layer 12, a second electrode layer 13 and a touch signal line 14. The gate 2 is disposed on the surface of the substrate 1. The gate 2 serves as the first metal layer. The metal film layer can be selected from one or more of excellent conductive metals such as aluminum, molybdenum, titanium, nickel, copper, silver, tungsten, etc., and alloys. The metal layer can use a sandwich structure such as Ti / Al / Ti, Al / Ti, Al / Mo, Mo / Al / Mo, etc. The gate insulating layer 3 is fabricated on the gate 2, and the material can be selected from inorganic oxides or insulating compounds, such as SiOx, SiNx, titanium oxide, aluminum oxide, etc. It should be noted that in the appendix Figure 1Outside the display area, the gate insulating layer 3 is provided with connection vias that expose the surface of the first metal layer, achieving the effect of connecting the first metal layer and the second metal layer 5. An active layer 4 is disposed on the gate insulating layer 3, and the optional materials are metal oxide semiconductor materials such as ZnO, IGZO, IGZTO, ITZO, Pr-IZO, etc. A second metal layer 5 is formed on the active layer 4. The process and material selection are the same as those of the first metal layer. The second metal layer 5 can be designed as the source electrode of the TFT signal input terminal or the circuit trace of the panel data signal according to the circuit design. A second insulating layer 6 is disposed on the second metal layer 5, and the material selection is the same as that of the gate insulating layer 3, such as SiOx, SiNx, alumina, titanium oxide, etc. And a third insulating layer 7 is disposed on the second insulating layer 6, and the optional materials are inorganic oxides or insulating compounds such as SiOx, SiNx, titanium oxide, alumina, etc., preferably organic materials. First through holes corresponding to each other in position are formed in both the second insulating layer 6 and the third insulating layer 7 to expose the surface of the active layer 4, and a drain overlap region 15 is formed at the bottom end of the first through hole. A third metal layer 8 is formed on the third insulating layer 7. The process and material selection are the same as those of the first metal layer. The third metal layer 8 can be the drain or the touch signal line according to the circuit design. One end of the third metal layer 8 covers the active layer 4 through the first through hole. A fourth insulating layer 9 is disposed on the third metal layer 8, and the material selection is the same as that of the gate insulating layer 3, such as SiOx, SiNx, alumina, titanium oxide, etc. This insulating layer serves to isolate the third metal layer 8 from the first electrode layer 10. The common electrode in the fringe field switching (FFS) display system is prepared using an electrode transparent conductive material. The first electrode layer 10 is disposed on the fourth insulating layer 9, and the first electrode layer 10 is connected to the common electrode signal line through an insulating layer via hole. It should be noted that this layer of electrode can also be used as the pixel electrode in the FFS display system. When used as the pixel electrode, this layer of electrode is connected to the drain pixel signal overlap region 11 through a second through hole. The other end of the third metal layer 8 can be used as the capacitive touch signal line 14, and this trace can also be used as the common electrode signal line for providing the common electrode required for liquid crystal deflection at the same time. The touch signal line 14 contacts the first electrode layer 10 through a via hole in the fourth insulating layer 9. A fifth insulating layer 12 is prepared on the first electrode layer 10. Second through holes corresponding to each other in position are formed in both the fourth insulating layer 9 and the fifth insulating layer 12 to expose the third metal layer 8, and a drain pixel signal overlap region 11 is formed at the bottom end of the second through hole. The pixel electrode is prepared using an electrode transparent conductive material. The second electrode layer 13 is disposed on the fifth insulating layer 12, and the second electrode layer 13 is connected to the drain pixel signal overlap region 11 through the second through hole. It should be noted that this layer of electrode can also be used as the common electrode in the FFS display system. When used as the common electrode, this layer of electrode is connected to the common electrode signal line. The drain pixel signal overlap region 11 overlaps with the vertical projection plane of the TFT channel region on the substrate 1. Embodiment

[0024] Please refer to Figure 2 and Figure 6 , the present invention provides a technical solution: a high transmittance oxide TFT array substrate, including a substrate 1, a gate electrode 2, a gate insulating layer 3, an active layer 4, a second metal layer 5, a second insulating layer 6, a third insulating layer 7, a third metal layer 8, a fourth insulating layer 9, a first electrode layer 10, a second electrode layer 13 and a touch signal line 14. A gate electrode 2 is formed on the substrate 1 as the first metal layer. The metal film layer can be selected from one or more of excellent conductive metals such as aluminum, molybdenum, titanium, nickel, copper, silver, tungsten, etc., and alloys; the metal layer can use a sandwich structure such as Ti / Al / Ti, Al / Ti, Al / Mo, Mo / Al / Mo, etc. The gate insulating layer 3 is made on the gate electrode 2. The material can be selected from inorganic oxides or insulating compounds such as SiOx, SiNx, titanium oxide, aluminum oxide, etc. It should be noted that in the appendix Figure 2Outside the display area, the gate insulating layer 3 is provided with connection vias that expose the surface of the first metal layer, achieving the effect of connecting the first metal layer and the second metal layer 5. An active layer 4 is fabricated on the gate insulating layer 3, and the optional materials are metal oxide semiconductor materials such as ZnO, IGZO, IGZTO, ITZO, Pr-IZO, etc. A second metal layer 5 is fabricated on the active layer 4, with the same process and material selection as the first metal layer. The second metal layer 5 can be designed as the source of the TFT signal input terminal or the circuit trace of the panel data signal according to the circuit design. A second insulating layer 6 is fabricated on the second metal layer 5, with the same material selection as the gate insulating layer 3, such as SiOx, SiNx, alumina, titanium oxide, etc. And a third via is fabricated on the second insulating layer 6 to expose the active layer 4. A drain overlap region 15 is formed at the bottom end of the third via. A third metal layer 8 is formed by film deposition on the second insulating layer 6, with the same process and material selection as the first metal layer. The third metal layer 8 can be the drain or the touch signal line according to the circuit design. And the third metal layer 8 contacts the upper surface of the active layer 4 through the third via. One end of the third metal layer 8 covers the active layer 4, and the other end of the third metal layer 8 can be used as the capacitive touch signal line 14, and this trace can also be used as the common electrode signal line for providing the common electrode required for liquid crystal deflection at the same time. The touch signal line 14 contacts the first electrode layer 10 through the via of the fourth insulating layer 9. A third insulating layer 7 is prepared on the third metal layer 8, and optional inorganic oxides or insulating compounds can be used, such as SiOx, SiNx, titanium oxide, alumina, etc., or organic materials. It can be selected to first prepare an inorganic insulating layer to cover the surface of the third metal layer 8, and then coat an organic insulating layer as the planarization layer. A fourth via is opened on the third insulating layer 7 to expose the third metal layer 8. The first electrode layer 10 is provided on the third insulating layer 7 using an electrode transparent conductive material for the in-plane switching (IPS) technology of the liquid crystal panel. The first electrode layer 10 is connected to the common electrode signal line through the via of the third insulating layer 7. It should be noted that this layer of electrode can also be used as the pixel electrode in the FFS display system. When used as the pixel electrode, this layer of electrode is connected to the drain pixel signal overlap region 11 through the second via. A fourth insulating layer 9 is provided on the first electrode layer 10, and a sixth via is opened on the fourth insulating layer 9 to expose the third metal layer 8. The drain pixel signal overlap region 11 is formed at the bottom ends of the fifth via and the sixth via. The second electrode layer 13 is provided on the fourth insulating layer 9 using an electrode transparent conductive material for the pixel electrode. The second electrode layer 13 is connected to the drain pixel signal overlap region 11 through the fifth via and the sixth via. It should be noted that this layer of electrode can also be used as the common electrode in the FFS display system. When used as the common electrode, this layer of electrode is connected to the common electrode signal line. The drain pixel signal overlap region 11 overlaps with the vertical projection plane of the TFT channel region on the substrate 1. Example

[0025] Please refer to Figure 3 andFigure 6 , the difference between this embodiment and Embodiment 1 is that: the third metal layer 8 may not be set as the touch signal line 14. The structure of this embodiment can still cover the TFT active layer through the drain pixel signal overlapping region 11, reduce unnecessary light-shielding area, improve the pixel aperture ratio, and increase the light transmittance of the panel. Embodiment

[0026] Please refer to Figure 4 and Figure 6 , the difference between this embodiment and Embodiment 2 is that: the third metal layer 8 may not be set as the touch signal line 14. The structure of this embodiment can still cover the TFT active layer through the drain pixel signal overlapping region 11, reduce unnecessary light-shielding area, improve the pixel aperture ratio, and increase the light transmittance of the panel. Embodiment

[0027] Please refer to Figure 5 and Figure 6 , the difference between this embodiment and Embodiment 1 is that: an intermediate cushion layer may be provided between the third metal layer 8 and the active layer 4. This cushion layer design can reduce the damage to the active layer during the preparation of the third via hole, improve the stability of the TFT, and in one structure, the second metal layer 5 can be used as the intermediate layer.

[0028] The features of the present invention are: Please refer to Figure 6

[0029] 1. The TFT source and drain metals are prepared with different metal film layers. The data signal line 18 and the touch signal line 17 are prepared with different metal layers, and an insulating layer is provided between the two metal layers for isolation.

[0030] 2. The TFT can be divided according to design requirements: 1) The source 19 is in direct contact with the active layer 4, and the drain 20 forms a drain overlapping region 15 in contact with the active layer 4 through an opening in the insulating layer. 2) The drain 20 is in direct contact with the active layer 4, and the source 19 forms a source contact region in contact with the active layer 4 through an opening in the insulating layer.

[0031] 3. The vertical projection planes of the touch signal line 17 and the data signal line 18 coincide. The TFT drain 20 is located above the active layer 4, and the projection plane coincides with the gate 2, and the projection area is less than or equal to the gate 2.

[0032] 4. The drain pixel signal overlapping region 11 is located above the active layer 4, that is, the drain pixel signal overlapping region 11 and the TFT channel region overlap in the vertical projection plane on the substrate 1, and no additional overlapping region is provided.

[0033] Although embodiments of the present invention have been shown and described, those of ordinary skill in the art will appreciate that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of the present invention. The scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A high transmittance oxide TFT array substrate, characterized in that: It includes a substrate (1), a first metal layer (2), a gate insulating layer (3), an active layer (4), a second metal layer (5), a second insulating layer (6), a third insulating layer (7), a third metal layer (8), a fourth insulating layer (9), a first electrode layer (10), a fifth insulating layer (12), a second electrode layer (13) and a touch signal line (14). The first metal layer (2) is disposed on the surface of the substrate (1). The first metal layer (2) can serve as a gate and a driving signal line, and a gate insulating layer (3) is provided on the gate. The active layer (4) is provided on the gate insulating layer (3), and the second metal layer (5) is provided on the active layer (4). The second insulating layer (6) is disposed on the second metal layer (5), and the third insulating layer (7) is provided on the second insulating layer (6). First through-holes corresponding to each other in position are formed in both the second insulating layer (6) and the third insulating layer (7), and a drain overlap region (15) is formed at the bottom end of the first through-hole. The third metal layer (8) is provided on the third insulating layer (7). One end of the third metal layer (8) contacts the upper surface of the active layer (4) through the first through-hole, and the other end of the third metal layer (8) covers the upper surface of the third insulating layer (7) and is disposed above the channel of the TFT active layer (4) away from the substrate (1). The fourth insulating layer (9) is provided on the third metal layer (8). The first electrode layer (10) is disposed on the fourth insulating layer (9). The other end of the third metal layer (8) can serve as the touch signal line (14) and the common electrode signal line. The touch signal line (14) contacts the first electrode layer (10) through a via hole in the fourth insulating layer (9). The fifth insulating layer (12) is provided on the first electrode layer (10). Second through-holes corresponding to each other in position are formed in both the fourth insulating layer (9) and the fifth insulating layer (12) to expose the surface of the third metal layer (8). A drain pixel signal overlap region (11) is formed at the bottom end of the second through-hole. The second electrode layer (13) is disposed on the fifth insulating layer (12), and the second electrode layer (13) is connected to the drain pixel signal overlap region (11) of the third metal layer (8) through the second through-hole. The drain pixel signal overlap region (11) overlaps the vertical projection surface of the TFT channel region on the substrate (1). One end of the third metal layer (8) serving as the drain of the TFT is disposed above the channel of the TFT active layer (4) away from the substrate (1) and serves as the drain pixel signal overlap region. On the side where the third metal layer (8) contacts the active layer (4), an intermediate cushion layer is provided between the third metal layer (8) and the active layer (4).

2. A high transmittance oxide TFT array substrate, characterized in that: It includes a substrate (1), a first metal layer (2), a gate insulating layer (3), an active layer (4), a second metal layer (5), a second insulating layer (6), a third insulating layer (7), a third metal layer (8), a fourth insulating layer (9), a first electrode layer (10), a second electrode layer (13) and a touch signal line (14). On the surface of the substrate (1), a first metal layer (2) is provided as a gate and a gate driving signal line. A first insulating layer is covered on the first metal layer (2) as the gate insulating layer (3). An active layer (4) is provided on the gate insulating layer (3). A second metal layer (5) is fabricated on the active layer (4), and a second insulating layer (6) is fabricated on the second metal layer (5). A third through hole is formed on the second insulating layer (6) to expose the active layer (4), and a drain overlap region (15) is formed at the bottom end of the third through hole. A third metal layer (8) is fabricated on the second insulating layer (6), and the third metal layer (8) contacts the upper surface of the active layer (4) through the third through hole. The other end of the third metal layer (8) covers the upper surface of the second insulating layer (6) and is disposed above the channel of the TFT active layer (4) away from the substrate (1). One end of the third metal layer (8) can be used as the touch signal line (14) and the common electrode signal line. A third insulating layer (7) is prepared on the third metal layer (8). A fourth through hole is formed on the third insulating layer (7) to expose the third metal layer (8). A first electrode layer (10) is provided on the third insulating layer (7). The first electrode layer (10) is connected to the common electrode signal line and the touch signal line (14) through the through hole in the third insulating layer (7). A fourth insulating layer (9) is provided on the first electrode layer (10). Fifth through holes corresponding in position are formed on both the third insulating layer (7) and the fourth insulating layer (9) to expose the third metal layer (8). A drain pixel signal overlap region (11) is formed at the bottom end of the fifth through hole. A second electrode layer (13) is provided on the fourth insulating layer (9). The second electrode layer (13) is connected to the drain pixel signal overlap region (11) through the fifth through hole; One end of the third metal layer (8) serving as the drain of the TFT is disposed above the channel of the TFT active layer (4) away from the substrate (1) and serves as the drain pixel signal overlap region. On the side where the third metal layer (8) contacts the active layer (4), an intermediate cushion layer is provided between the third metal layer (8) and the active layer (4).

3. A high transmittance oxide TFT array substrate according to claim 1 or 2, characterized in that: The second electrode layer (13) is connected to the third metal layer (8) through a through hole in the drain pixel signal overlap region (11). At this time, the second electrode layer (13) serves as a pixel electrode and the first electrode layer (10) serves as a common electrode, or the first electrode layer (10) contacts the third metal layer (8) through a through hole in the drain pixel signal overlap region (11). At this time, the first electrode layer (10) serves as a pixel electrode and the second electrode layer (13) serves as a common electrode.

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