A method, device and medium for I2C signal transparent transmission based on CPLD

Abstract

The embodiments of the present specification disclose a CPLD-based I2C signal transparent transmission method, device and medium, and relate to the technical field of switch hardware. The method comprises: based on the triggering of a reset signal of an I2C signal transparent transmission system, a direction signal of an I2C signal to be transmitted is generated according to the reset signal by a direction judgment module; wherein the direction signal of the I2C signal to be transmitted is used to indicate the transmission direction of the I2C signal to be transmitted, including a first direction and a second direction, the first direction being the signal transmission direction output by an I2C master device and input by an I2C slave device, and the second direction being the signal transmission direction output by an I2C slave device and input by an I2C master device; and according to the direction signal of the I2C signal to be transmitted, the I2C signal to be transmitted is controlled to be transparently transmitted according to the direction signal by a direction control module, the CPLD is only used for transmission, and there is no need to store data and then read it, thereby saving the hardware resources of the CPLD and ensuring the real-time performance of signal transmission.

Description

Technical Field

[0001] The present invention relates to the technical field of switch hardware, and in particular to a CPLD-based I2C signal transparent transmission method, device and medium. Background Art

[0002] When the switch uses optical modules that support digital diagnostic monitoring (DDM), it is necessary to read multiple optical modules through the I2C (Inter-Integrated Circuit) bus. Because the I2C device addresses of multiple optical modules are the same, multiple I2C buses are required to communicate with a single optical module respectively. In practice, a complex programmable logic device (CPLD) is usually used to expand the I2C bus, expand one I2C bus to multiple I2C buses, and perform bidirectional transparent transmission of I2C signals after selecting the channel.

[0003] The commonly used I2C signal transparent transmission method is to realize an I2C slave and an I2C host through CPLD respectively. The I2C host actively reads the DDM information of the optical module and stores the read DDM information to the CPLD. After the I2C slave reads the DDM information, it reports the DDM information. The signal transparent transmission method in the prior art occupies a large number of CPLD hardware resources and cannot guarantee the real-time transmission. Summary of the invention

[0004] One or more embodiments of this specification provide a CPLD-based I2C signal transparent transmission method, device and medium, which are used to solve the following technical problems: the signal transparent transmission method in the prior art occupies more CPLD hardware resources and cannot guarantee the real-time transmission.

[0005] One or more embodiments of this specification adopt the following technical solutions:

[0006] One or more embodiments of the present specification provide a CPLD-based I2C signal transparent transmission method, which is applied to an I2C signal transparent transmission system, wherein the I2C signal transparent transmission system includes a direction judgment module and a direction control module, an I2C master device, and an I2C slave device, which are arranged in the CPLD chip. The method includes: based on the triggering of a reset signal of the I2C signal transparent transmission system, generating a direction signal of the I2C signal to be transmitted according to the reset signal by the direction judgment module; wherein the direction signal of the I2C signal to be transmitted is used to indicate the transmission direction of the I2C signal to be transmitted, including a first direction and a second direction, the first direction being the signal transmission direction output by the I2C master device and input by the I2C slave device, and the second direction being the signal transmission direction output by the I2C slave device and input by the I2C master device; and controlling the I2C signal to be transmitted to be transparently transmitted according to the direction signal by the direction control module according to the direction signal of the I2C signal to be transmitted.

[0007] Further, the direction control module includes: a first inverter, a first tri-state buffer, a second tri-state buffer, a first buffer and a second buffer; wherein the input end of the first inverter is used to input the direction signal, and the output end of the first inverter is connected to the option card input end of the first tri-state buffer; the input end of the first tri-state buffer is used to receive the signal of the output end of the second buffer, and the output end of the first tri-state buffer is connected to the I2C master device; the input end of the first buffer is used to input the I2C signal to be transmitted of the I2C master device, and the output end of the first buffer is connected to the input end of the second tri-state buffer; the option card input end of the second tri-state buffer is used to input the direction signal, and the second The output end of the tri-state is connected to the I2C slave device; the input end of the second buffer is used to input the I2C signal to be transmitted of the I2C slave device; through the direction control module, according to the direction signal of the I2C signal to be transmitted, the I2C signal to be transmitted is controlled to be transparently transmitted according to the direction signal, specifically including: inputting the direction signal of the I2C signal to be transmitted to the input end of the first inverter and the option pass input end of the second tri-state buffer; determining the working state of the first tri-state buffer and the second tri-state buffer according to the direction signal of the I2C signal to be transmitted; generating a transparent transmission route between the I2C master device and the I2C slave device according to the working state of the first tri-state buffer and the second tri-state buffer.

[0008] Further, according to the direction signal of the I2C signal to be transmitted, the working states of the first three-state buffer and the second three-state buffer are determined, specifically including: when the direction signal of the I2C signal to be transmitted is the first direction, the first three-state buffer is in a disabled state, wherein the output end of the first three-state buffer is in a high-impedance state in the disabled state; when the direction signal of the I2C signal to be transmitted is the second direction, the second three-state buffer is in a disabled state, wherein the output end of the second three-state buffer is in a high-impedance state in the disabled state.

[0009] Further, according to the working states of the first tri-state buffer and the second tri-state buffer, a transparent transmission route between the I2C master device and the I2C slave device is generated, specifically including: when the first tri-state buffer is in a disabled state, the transparent transmission route between the I2C master device and the I2C slave device is: the I2C signal to be transmitted of the I2C master device is input to the input end of the first buffer, the I2C signal to be transmitted is output through the output end of the first buffer, and the I2C signal to be transmitted is input to the input end of the second tri-state buffer, and is output to the I2C slave device through the output end of the second tri-state buffer; when the second tri-state buffer is in a disabled state, the transparent transmission route between the I2C slave device and the I2C master device is: the I2C signal to be transmitted of the I2C slave device is input to the input end of the second buffer, the I2C signal to be transmitted is output through the output end of the second buffer, and the I2C signal to be transmitted is input to the input end of the first tri-state buffer, and is output to the I2C master device through the output end of the first tri-state buffer.

[0010] Further, the direction judgment module generates a direction signal of the I2C signal according to the reset signal, specifically including: determining the state machine state of the I2C signal transparent transmission system through the direction judgment module according to the reset signal, the state machine state of the I2C signal transparent transmission system including an idle state, a device address transmission state, a read / write flag determination state, a slave device response state, a first direction data transmission state, a second direction data transmission state and a master device response state; determining the direction signal of the I2C signal to be transmitted according to the state machine state of the I2C signal transparent transmission system.

[0011] Further, the idle state is used to indicate a state in which no signal is transmitted in the I2C signal transparent transmission system; the device address transmission state is used to indicate a state in which the I2C master device sequentially sends a device address of a specified number of bits to the I2C slave device; the read / write flag judgment state is used to indicate a state in which the I2C master device sends a read / write flag to the I2C slave device; the slave device response state is used to indicate a state in which the I2C slave device sends an acknowledgement bit or a negative acknowledgement bit to the I2C master device; the first-direction data transmission state is used to indicate a state in which the I2C master device sequentially sends specified data to the I2C slave device, wherein the specified data includes a register address of the I2C slave device or data in a register to be transmitted to the I2C slave device; the second-direction data transmission state is used to indicate a state in which the I2C slave device sequentially sends preset data to the I2C master device, wherein the preset data is data in a register to be transmitted to the I2C master device; the master device response state is used to indicate a state in which the I2C master device sends an acknowledgement bit or a negative acknowledgement bit to the I2 slave device.

[0012] Further, according to the state machine state of the I2C signal transparent transmission system, the direction signal of the I2C signal to be transmitted is determined, specifically including: when the state machine state of the I2C signal transparent transmission system is any one of the idle state, the device address transmission state, the first direction data transmission state and the master device response state, the direction signal of the I2C signal to be transmitted is determined to be the first direction.

[0013] Further, according to the state machine state of the I2C signal transparent transmission system, the direction signal of the I2C signal is determined, specifically including: when the state machine state of the I2C signal transparent transmission system is any one of the read-write flag judgment state, the slave device response state and the second direction data transmission state, the direction signal of the I2C signal to be transmitted is determined to be the second direction.

[0014] One or more embodiments of this specification provide an I2C signal transparent transmission device based on CPLD, including:

[0015] at least one processor; and,

[0016] a memory communicatively connected to the at least one processor; wherein,

[0017] The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can: based on the triggering of the reset signal of the I2C signal transparent transmission system, generate a direction signal of the I2C signal to be transmitted according to the reset signal through the direction judgment module; wherein the direction signal of the I2C signal to be transmitted is used to indicate the transmission direction of the I2C signal to be transmitted, including a first direction and a second direction, the first direction is the signal transmission direction output by the I2C master device and input by the I2C slave device, and the second direction is the signal transmission direction output by the I2C slave device and input by the I2C master device; through the direction control module, according to the direction signal of the I2C signal to be transmitted, control the I2C signal to be transmitted to be transparently transmitted according to the direction signal.

[0018] One or more embodiments of the present specification provide a non-volatile computer storage medium, which stores computer executable instructions, and the computer executable instructions are configured to: based on the triggering of a reset signal of an I2C signal transparent transmission system, generate a direction signal of an I2C signal to be transmitted according to the reset signal through a direction judgment module; wherein the direction signal of the I2C signal to be transmitted is used to indicate the transmission direction of the I2C signal to be transmitted, including a first direction and a second direction, the first direction being the signal transmission direction output by the I2C master device and input by the I2C slave device, and the second direction being the signal transmission direction output by the I2C slave device and input by the I2C master device; and through a direction control module, control the I2C signal to be transmitted to be transparently transmitted according to the direction signal according to the direction signal of the I2C signal to be transmitted.

[0019] At least one of the above technical solutions adopted in the embodiments of this specification can achieve the following beneficial effects: through the above technical solution, CPLD is only used for transmission, and there is no need to store and then read the data, which saves the hardware resources of CPLD and ensures the real-time performance of signal transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of this specification or the prior art, the following briefly introduces the drawings required for use in the embodiments or the prior art description. Obviously, the drawings described below are only some embodiments recorded in this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor. In the drawings:

[0021] Figure 1 A flowchart of a CPLD-based I2C signal transparent transmission method provided in an embodiment of this specification;

[0022] Figure 2 A schematic diagram of a determination method of a direction determination module provided in an embodiment of this specification;

[0023] Figure 3 A circuit connection diagram of a direction control module provided in an embodiment of this specification;

[0024] Figure 4 A schematic diagram of the structure of an I2C signal transparent transmission device based on CPLD provided in an embodiment of this specification. DETAILED DESCRIPTION

[0025] In order to enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below in conjunction with the drawings in the embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this specification, not all of the embodiments. Based on the embodiments of this specification, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this specification.

[0026] When the switch uses optical modules that support digital diagnostic monitoring (DDM), it is necessary to read multiple optical modules through the I2C (Inter-Integrated Circuit) bus. Because the I2C device addresses of multiple optical modules are the same, multiple I2C buses are required to communicate with a single optical module respectively. In practice, a complex programmable logic device (CPLD) is usually used to expand the I2C bus, expand one I2C bus to multiple I2C buses, and perform bidirectional transparent transmission of I2C signals after selecting the channel.

[0027] The commonly used I2C signal transparent transmission method is to realize an I2C slave and an I2C host through CPLD respectively. The I2C host actively reads the DDM information of the optical module and stores the read DDM information to the CPLD. After the I2C slave reads the DDM information, it reports the DDM information. The signal transparent transmission method in the prior art occupies a large number of CPLD hardware resources and cannot guarantee the real-time transmission.

[0028] The embodiment of this specification provides an I2C signal transparent transmission method based on CPLD. It should be noted that the execution subject in the embodiment of this specification can be a server or any device with data processing capability. It is applied to an I2C signal transparent transmission system, wherein the I2C signal transparent transmission system includes a direction judgment module and a direction control module set in the CPLD chip, an I2C master device and an I2C slave device. Figure 1 A flow chart of a CPLD-based I2C signal transparent transmission method provided in an embodiment of this specification is shown in FIG. Figure 1 As shown, it mainly includes the following steps:

[0029] Step S101 , based on the triggering of the reset signal of the I2C signal transparent transmission system, a direction signal of the I2C signal to be transmitted is generated by a direction determination module according to the reset signal.

[0030] The direction signal of the I2C signal to be transmitted is used to indicate the transmission direction of the I2C signal to be transmitted, including a first direction and a second direction, the first direction is the signal transmission direction (MasterOut Slave In, MOSI) output by the I2C master device and input by the I2C slave device, and the second direction is the signal transmission direction (Master In Slave Out, MISO) output by the I2C slave device and input by the I2C master device. It should be noted that the I2C bus includes a serial data line (SDA) and a serial clock line (SCL), wherein the serial data line is responsible for transmitting serial data between devices, and the serial clock line is responsible for generating synchronous clock pulses.

[0031] Specifically, the direction judgment module generates a direction signal of the I2C signal according to the reset signal, which specifically includes: according to the reset signal, determining the state machine state of the I2C signal transparent transmission system through the direction judgment module, the state machine state of the I2C signal transparent transmission system including an idle state, a device address transmission state, a read / write flag judgment state, a slave device response state, a first direction data transmission state, a second direction data transmission state and a master device response state; according to the state machine state of the I2C signal transparent transmission system, determining the direction signal of the I2C signal to be transmitted.

[0032] In one embodiment of the present specification, according to the reset signal, the state machine state of the I2C signal transparent transmission system is determined by the direction judgment module, and the corresponding direction signal is different in different states. It should be noted that in the embodiment of the present specification, the transmission direction and the direction signal are the same, and both are used to indicate the transmission direction of the signal or data. According to the state machine state of the I2C signal transparent transmission system, the direction signal of the I2C signal to be transmitted in the current state machine state is determined.

[0033] Specifically, the idle state is used to indicate a state in which no signal is transmitted in the I2C signal transparent transmission system; the device address transmission state is used to indicate a state in which the I2C master device sequentially sends a device address of a specified number of bits to the I2C slave device; the read-write flag judgment state is used to indicate a state in which the I2C master device sends a read-write flag to the I2C slave device; the slave device response state is used to indicate a state in which the I2C slave device sends an acknowledgement bit or a negative acknowledgement bit to the I2C master device; the first direction data transmission state is used to indicate a state in which the I2C master device sequentially sends specified data to the I2C slave device, wherein the specified data includes a register address of the I2C slave device or data to be transmitted to the register of the I2C slave device; the second direction data transmission state is used to indicate a state in which the I2C slave device sequentially sends preset data to the I2C master device, wherein the preset data is data to be transmitted to the register of the I2C master device; the master device response state is used to indicate a state in which the I2C master device sends an acknowledgement bit or a negative acknowledgement bit to the I2 slave device.

[0034] Specifically, according to the state machine state of the I2C signal transparent transmission system, determining the direction signal of the I2C signal to be transmitted specifically includes: when the state machine state of the I2C signal transparent transmission system is any one of the idle state, the device address transmission state, the first direction data transmission state, and the master device response state, determining the direction signal of the I2C signal to be transmitted as the first direction. When the state machine state of the I2C signal transparent transmission system is any one of the read-write flag determination state, the slave device response state, and the second direction data transmission state, determining the direction signal of the I2C signal to be transmitted as the second direction.

[0035] In one embodiment of this specification, combined with Figure 2 Conduct analysis, Figure 2 A schematic diagram of a determination method of a direction determination module provided in an embodiment of this specification, such as Figure 2 As shown, the system is synchronously reset by the reset signal driven by the falling edge of the clock signal, where the reset signal can be a Reset signal, or a START signal or a STOP signal, and enters the idle state. In the idle state, there is no signal transmission in the I2C signal transparent transmission system, the data bit register is set to 7, and the transmission direction register is set to the MOSI direction, that is, the first direction, from the master device to the slave device, and automatically jumps to the next state. The next state of the idle state is the device address transmission state.

[0036] In the device address transmission state, the transmission direction is the MOSI direction, so that the master device sends the device address to the slave device. When the falling edge of the clock signal is received, the master device sends the first seven bits of the slave device address to the slave device in sequence. Each time a device address is received, the data bit register is decremented by one bit until the data bit register is 0. When the data bit register is 0, it jumps to the read-write flag judgment state and sets the transmission direction register to the MISO direction.

[0037] In the read / write flag judgment state, it indicates that the master device sends the read / write flag state to the slave device, and judges the last bit in the current SDA signal, that is, the lowest bit of the device address. When the lowest bit is 1, it represents the read state, and when the lowest bit is 0, it represents the write state. The lowest bit of the device address is locked in the command register. In this state, the transmission direction is still the MISO direction, and jumps to the slave device response state.

[0038] In the slave device response state, the transmission direction is still the MISO direction, so that the slave device sends an acknowledge bit or a no acknowledge bit to the master device, and sets the data bit number register to 7. At this time, the next state is determined according to the read and write flag stored in the command register.

[0039] When the read / write flag stored in the command register is 0, the first direction data transmission state is entered, that is, in the next state, the master device sends data to the slave device. The data here can be register data or data to be transmitted. In this state, the transmission direction is the MOSI direction. Driven by the falling edge of the clock signal, the master device sends data to the slave device in sequence, and each time the data bit register is reduced by one, until the data bit register is 0, the transmission direction is changed to the MISO direction, and the slave device enters the response state. In the slave device response state, the transmission direction is the MISO direction, so that the slave device can send a response bit or a non-response bit to the master device according to the received data. When the master device receives the response bit, the data transmission here is completed.

[0040] When the read / write flag stored in the command register is 1, the second direction data transmission state is entered, that is, in the next state, the slave device sends data to the master device. In this state, the transmission direction is the MISO direction. Driven by the falling edge of the clock signal, the slave device sends data to the master device in sequence, and the data bit register is reduced by one each time it is sent, until the data bit register is 0, the transmission direction is changed to the MOSI direction, and the master device enters the response state. In the master device response state, the transmission direction is the MOSI direction, so that the master device can send an acknowledgement bit or a negative acknowledgement bit to the slave device according to the received data. If the slave device receives an acknowledgement bit, the byte transmission continues. If the slave device receives a negative acknowledgement bit, the transmission ends. In the master device response state, the level of the serial data line is read and latched into sda_bit. When sda_bit is 1, the transmission direction is set to the MOSI direction and jumps to the idle state; when sda_bit is 0, the transmission direction is set to the MISO direction, and the data position register is set to 7, jumping to the first direction transmission state.

[0041] Step S102, through the direction control module, according to the direction signal of the I2C signal to be transmitted, control the I2C signal to be transmitted to be transparently transmitted according to the direction signal.

[0042] In one embodiment of the present specification, different direction signals of the I2C signal to be transmitted are generated according to different states of the state machine. According to the corresponding direction signals in different states, transparent transmission of data signals between the master device and the slave device is achieved according to the direction signals.

[0043] Specifically, the direction control module includes: a first inverter, a first tri-state buffer, a second tri-state buffer, a first buffer and a second buffer; wherein the input end of the first inverter is used to input the direction signal, and the output end of the first inverter is connected to the option card input end of the first tri-state buffer; the input end of the first tri-state buffer is used to receive the signal of the output end of the second buffer, and the output end of the first tri-state buffer is connected to the I2C master device; the input end of the first buffer is used to input the I2C signal to be transmitted of the I2C master device, and the output end of the first buffer is connected to the input end of the second tri-state buffer; the option card input end of the second tri-state buffer is used to input the direction signal, and the output end of the second tri-state is connected to the I2C slave device; the input end of the second buffer is used to input the I2C signal to be transmitted of the I2C slave device.

[0044] Through the direction control module, according to the direction signal of the I2C signal to be transmitted, the I2C signal to be transmitted is controlled to be transparently transmitted according to the direction signal, specifically including: inputting the direction signal of the I2C signal to be transmitted to the input end of the first inverter and the option pass input end of the second tri-state buffer; determining the working states of the first tri-state buffer and the second tri-state buffer according to the direction signal of the I2C signal to be transmitted; and generating a transparent transmission route between the I2C master device and the I2C slave device according to the working states of the first tri-state buffer and the second tri-state buffer.

[0045] Specifically, according to the direction signal of the I2C signal to be transmitted, the working states of the first three-state buffer and the second three-state buffer are determined, specifically including: when the direction signal of the I2C signal to be transmitted is the first direction, the first three-state buffer is in a disabled state, wherein the output end of the first three-state buffer is in a high-impedance state in the disabled state; when the direction signal of the I2C signal to be transmitted is the second direction, the second three-state buffer is in a disabled state, wherein the output end of the second three-state buffer is in a high-impedance state in the disabled state.

[0046] Specifically, according to the working states of the first tri-state buffer and the second tri-state buffer, a transparent transmission route between the I2C master device and the I2C slave device is generated, specifically including: when the first tri-state buffer is in a disabled state, the transparent transmission route between the I2C master device and the I2C slave device is: the I2C signal to be transmitted of the I2C master device is input to the input end of the first buffer, the I2C signal to be transmitted is output through the output end of the first buffer, and the I2C signal to be transmitted is input to the second tri-state buffer The I2C signal to be transmitted is input to the input end of the second buffer, and is output to the I2C slave device through the output end of the second tri-state buffer; when the second tri-state buffer is in a disabled state, the transparent transmission route between the I2C slave device and the I2C master device is: the I2C signal to be transmitted of the I2C slave device is input to the input end of the second buffer, the I2C signal to be transmitted is output through the output end of the second buffer, and the I2C signal to be transmitted is input to the input end of the first tri-state buffer, and is output to the I2C master device through the output end of the first tri-state buffer.

[0047] In one embodiment of this specification, Figure 3 A circuit connection diagram of a direction control module provided in an embodiment of this specification, such as Figure 3As shown, the circuit of the direction control module includes a first inverter N1, a first tri-state buffer TR1, a second tri-state buffer TR2, a first buffer BF1 and a second buffer BF2. Among them, after the direction signal is input, one path enters the ENB pin of the second tri-state buffer TR2, that is, the option pass input terminal; the other direction signal passes through the first inverter N1 and then enters the ENB pin of the first tri-state buffer TR1. The output of the first tri-state buffer TR1 is connected to the master device signal, and the output of the second tri-state buffer TR2 is connected to the slave device signal. The master device signal passes through the first buffer BF1 and then connects to the input pin of the second tri-state buffer TR2; the slave device signal passes through the second buffer BF2 and then connects to the input pin of the first tri-state buffer TR1.

[0048] When the direction signal is in the MOSI direction, that is, high level 1, the enable pin ENB of the first tri-state buffer TR1 is low, the first tri-state buffer TR1 is disabled, and the first tri-state buffer TR1 outputs a high impedance state. The master device signal enters the input end of the second tri-state buffer TR2 through the first buffer BF1. At this time, the enable pin ENB of the second tri-state buffer TR2 is high level, the second tri-state buffer TR2 is enabled, the input signal is the master device signal, the output signal is the slave device signal, and the output signal is equal to the input signal, realizing transparent transmission from the host to the slave.

[0049] When the direction signal is MISO direction, that is, low level 0, the enable pin ENB of the second tri-state buffer TR2 is low, the second tri-state buffer TR2 is disabled, and the second tri-state buffer TR2 outputs a high impedance state. The slave device signal enters the input end of the first tri-state buffer TR1 through the second buffer BF2. At this time, the enable pin ENB of the first tri-state buffer TR1 is low level, the first tri-state buffer TR1 is enabled, the output signal is the master device signal, the input signal is the slave device signal, and the output signal is equal to the input signal, realizing transparent transmission from the slave to the host.

[0050] Through the above technical solution, CPLD is only used for transmission, and there is no need to store data before reading it, which saves the hardware resources of CPLD and ensures the real-time performance of signal transmission.

[0051] The embodiment of this specification also provides an I2C signal transparent transmission device based on CPLD, such as Figure 4As shown, the device includes: at least one processor; and a memory connected to the at least one processor in communication; wherein the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can: based on the triggering of the reset signal of the I2C signal transparent transmission system, generate a direction signal of the I2C signal to be transmitted according to the reset signal through a direction judgment module; wherein the direction signal of the I2C signal to be transmitted is used to indicate the transmission direction of the I2C signal to be transmitted, including a first direction and a second direction, the first direction is the signal transmission direction output by the I2C master device and input by the I2C slave device, and the second direction is the signal transmission direction output by the I2C slave device and input by the I2C master device; through the direction control module, according to the direction signal of the I2C signal to be transmitted, control the I2C signal to be transmitted to be transparently transmitted according to the direction signal.

[0052] The embodiment of the present specification also provides a non-volatile computer storage medium storing computer executable instructions, wherein the computer executable instructions are configured as follows:

[0053] Based on the triggering of the reset signal of the I2C signal transparent transmission system, a direction signal of the I2C signal to be transmitted is generated according to the reset signal through the direction judgment module; wherein the direction signal of the I2C signal to be transmitted is used to indicate the transmission direction of the I2C signal to be transmitted, including a first direction and a second direction, the first direction is the signal transmission direction output by the I2C master device and input by the I2C slave device, and the second direction is the signal transmission direction output by the I2C slave device and input by the I2C master device; through the direction control module, according to the direction signal of the I2C signal to be transmitted, the I2C signal to be transmitted is controlled to be transparently transmitted according to the direction signal.

[0054] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device, equipment, and non-volatile computer storage medium embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0055] The above is a description of a specific embodiment of the specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0056] The above are only one or more embodiments of this specification and are not intended to limit this specification. For those skilled in the art, one or more embodiments of this specification may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of one or more embodiments of this specification shall be included in the scope of the claims of this specification.

Claims

1. A CPLD-based I2C signal transparent transmission method, characterized in that: Applied to an I2C signal transparent transmission system, wherein the I2C signal transparent transmission system includes a direction judgment module and a direction control module, an I2C master device and an I2C slave device arranged in the CPLD chip, and the method includes: Based on the triggering of the reset signal of the I2C signal transparent transmission system, the direction judgment module generates a direction signal of the I2C signal to be transmitted according to the reset signal; The direction signal of the I2C signal to be transmitted is used to indicate the transmission direction of the I2C signal to be transmitted, including a first direction and a second direction, the first direction being the signal transmission direction output by the I2C master device and input by the I2C slave device, and the second direction being the signal transmission direction output by the I2C slave device and input by the I2C master device; By means of the direction control module, according to the direction signal of the I2C signal to be transmitted, controlling the I2C signal to be transmitted to be transparently transmitted according to the direction signal; The direction control module includes: a first inverter, a first tri-state buffer, a second tri-state buffer, a first buffer and a second buffer; Wherein, the input end of the first inverter is used to input the direction signal, and the output end of the first inverter is connected to the option card input end of the first tri-state buffer; The input end of the first tri-state buffer is used to receive a signal from the output end of the second buffer, and the output end of the first tri-state buffer is connected to the I2C master device; The input end of the first buffer is used to input the I2C signal to be transmitted of the I2C master device, and the output end of the first buffer is connected to the input end of the second tri-state buffer; The option card input terminal of the second tri-state buffer is used to input the direction signal, and the output terminal of the second tri-state is connected to the I2C slave device; The input end of the second buffer is used to input the I2C signal to be transmitted of the I2C slave device; By means of the direction control module, according to the direction signal of the I2C signal to be transmitted, controlling the I2C signal to be transmitted to be transparently transmitted according to the direction signal specifically includes: Inputting the direction signal of the I2C signal to be transmitted to the input end of the first inverter and the option card pass input end of the second tri-state buffer; Determining the working states of the first tri-state buffer and the second tri-state buffer according to the direction signal of the I2C signal to be transmitted; generating a transparent transmission route between the I2C master device and the I2C slave device according to the working states of the first tri-state buffer and the second tri-state buffer; Determining the working states of the first tri-state buffer and the second tri-state buffer according to the direction signal of the I2C signal to be transmitted specifically includes: When the direction signal of the I2C signal to be transmitted is the first direction, the first tri-state buffer is in a disabled state, wherein in the disabled state, the output end of the first tri-state buffer is in a high impedance state; When the direction signal of the I2C signal to be transmitted is the second direction, the second tri-state buffer is in a disabled state, wherein in the disabled state, the output end of the second tri-state buffer is in a high impedance state; Generating a transparent transmission route between the I2C master device and the I2C slave device according to the working states of the first tri-state buffer and the second tri-state buffer, specifically comprising: When the first tri-state buffer is in a disabled state, the transparent transmission route between the I2C master device and the I2C slave device is: the I2C signal to be transmitted of the I2C master device is input to the input end of the first buffer, the I2C signal to be transmitted is output through the output end of the first buffer, and the I2C signal to be transmitted is input to the input end of the second tri-state buffer, and is output to the I2C slave device through the output end of the second tri-state buffer; When the second tri-state buffer is in a disabled state, the transparent transmission route between the I2C slave device and the I2C master device is: the I2C signal to be transmitted of the I2C slave device is input to the input end of the second buffer, the I2C signal to be transmitted is output through the output end of the second buffer, and the I2C signal to be transmitted is input to the input end of the first tri-state buffer, and is output to the I2C master device through the output end of the first tri-state buffer.

2. According to a CPLD-based I2C signal transparent transmission method according to claim 1, it is characterized in that: Generating a direction signal of the I2C signal according to the reset signal by the direction determination module specifically includes: According to the reset signal, the state machine state of the I2C signal transparent transmission system is determined by the direction judgment module, and the state machine state of the I2C signal transparent transmission system includes an idle state, a device address transmission state, a read / write flag bit judgment state, a slave device response state, a first direction data transmission state, a second direction data transmission state, and a master device response state; The direction signal of the I2C signal to be transmitted is determined according to the state machine state of the I2C signal transparent transmission system.

3. According to a CPLD-based I2C signal transparent transmission method according to claim 2, it is characterized in that: The idle state is used to indicate a state where there is no signal transmission in the I2C signal transparent transmission system; The device address transmission state is used to indicate the state in which the I2C master device sequentially sends a device address of a specified number of bits to the I2C slave device; The read / write flag bit judgment state is used to indicate the state in which the I2C master device sends the read / write flag bit to the I2C slave device; The slave device response state is used to indicate the state of the I2C slave device sending a response bit or a negative response bit to the I2C master device; The first-direction data transmission state is used to indicate a state in which the I2C master device sequentially sends specified data to the I2C slave device, wherein the specified data includes a register address of the I2C slave device or data in a register to be transmitted to the I2C slave device; The second direction data transmission state is used to indicate a state in which the I2C slave device sequentially sends preset data to the I2C master device, wherein the preset data is data in a register to be transmitted to the I2C master device; The master device response state is used to indicate a state in which the I2C master device sends a response bit or a negative response bit to the I2C slave device.

4. According to a CPLD-based I2C signal transparent transmission method according to claim 3, it is characterized in that: Determining the direction signal of the I2C signal to be transmitted according to the state machine state of the I2C signal transparent transmission system specifically includes: When the state machine state of the I2C signal transparent transmission system is any one of the idle state, the device address transmission state, the first direction data transmission state and the master device response state, the direction signal of the I2C signal to be transmitted is determined to be the first direction.

5. According to a CPLD-based I2C signal transparent transmission method according to claim 3, it is characterized in that: Determining the direction signal of the I2C signal according to the state machine state of the I2C signal transparent transmission system specifically includes: When the state machine state of the I2C signal transparent transmission system is any one of the read / write flag determination state, the slave device response state and the second direction data transmission state, the direction signal of the I2C signal to be transmitted is determined to be the second direction.

6. An I2C signal transparent transmission device based on CPLD, characterized in that: The device comprises: at least one processor; and, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to: Based on the triggering of the reset signal of the I2C signal transparent transmission system, a direction signal of the I2C signal to be transmitted is generated according to the reset signal by the direction judgment module; The direction signal of the I2C signal to be transmitted is used to indicate the transmission direction of the I2C signal to be transmitted, including a first direction and a second direction, the first direction being the signal transmission direction output by the I2C master device and input by the I2C slave device, and the second direction being the signal transmission direction output by the I2C slave device and input by the I2C master device; By means of a direction control module, according to the direction signal of the I2C signal to be transmitted, controlling the I2C signal to be transmitted to be transparently transmitted according to the direction signal; The direction control module includes: a first inverter, a first tri-state buffer, a second tri-state buffer, a first buffer and a second buffer; Wherein, the input end of the first inverter is used to input the direction signal, and the output end of the first inverter is connected to the option card input end of the first tri-state buffer; The input end of the first tri-state buffer is used to receive a signal from the output end of the second buffer, and the output end of the first tri-state buffer is connected to the I2C master device; The input end of the first buffer is used to input the I2C signal to be transmitted of the I2C master device, and the output end of the first buffer is connected to the input end of the second tri-state buffer; The option card input terminal of the second tri-state buffer is used to input the direction signal, and the output terminal of the second tri-state is connected to the I2C slave device; The input end of the second buffer is used to input the I2C signal to be transmitted of the I2C slave device; By means of the direction control module, according to the direction signal of the I2C signal to be transmitted, controlling the I2C signal to be transmitted to be transparently transmitted according to the direction signal specifically includes: Inputting the direction signal of the I2C signal to be transmitted to the input end of the first inverter and the option card pass input end of the second tri-state buffer; Determining the working states of the first tri-state buffer and the second tri-state buffer according to the direction signal of the I2C signal to be transmitted; generating a transparent transmission route between the I2C master device and the I2C slave device according to the working states of the first tri-state buffer and the second tri-state buffer; Determining the working states of the first tri-state buffer and the second tri-state buffer according to the direction signal of the I2C signal to be transmitted specifically includes: When the direction signal of the I2C signal to be transmitted is the first direction, the first tri-state buffer is in a disabled state, wherein in the disabled state, the output end of the first tri-state buffer is in a high impedance state; When the direction signal of the I2C signal to be transmitted is the second direction, the second tri-state buffer is in a disabled state, wherein in the disabled state, the output end of the second tri-state buffer is in a high impedance state; Generating a transparent transmission route between the I2C master device and the I2C slave device according to the working states of the first tri-state buffer and the second tri-state buffer, specifically comprising: When the first tri-state buffer is in a disabled state, the transparent transmission route between the I2C master device and the I2C slave device is: the I2C signal to be transmitted of the I2C master device is input to the input end of the first buffer, the I2C signal to be transmitted is output through the output end of the first buffer, and the I2C signal to be transmitted is input to the input end of the second tri-state buffer, and is output to the I2C slave device through the output end of the second tri-state buffer; When the second tri-state buffer is in a disabled state, the transparent transmission route between the I2C slave device and the I2C master device is: the I2C signal to be transmitted of the I2C slave device is input to the input end of the second buffer, the I2C signal to be transmitted is output through the output end of the second buffer, and the I2C signal to be transmitted is input to the input end of the first tri-state buffer, and is output to the I2C master device through the output end of the first tri-state buffer.

7. A non-volatile computer storage medium storing computer executable instructions, wherein the computer executable instructions are configured to: Based on the triggering of the reset signal of the I2C signal transparent transmission system, a direction signal of the I2C signal to be transmitted is generated according to the reset signal by the direction judgment module; in, The direction signal of the I2C signal to be transmitted is used to indicate the transmission direction of the I2C signal to be transmitted, including a first direction and a second direction, the first direction being the signal transmission direction output by the I2C master device and input by the I2C slave device, and the second direction being the signal transmission direction output by the I2C slave device and input by the I2C master device; By means of a direction control module, according to the direction signal of the I2C signal to be transmitted, controlling the I2C signal to be transmitted to be transparently transmitted according to the direction signal; The direction control module includes: a first inverter, a first tri-state buffer, a second tri-state buffer, a first buffer and a second buffer; Wherein, the input end of the first inverter is used to input the direction signal, and the output end of the first inverter is connected to the option card input end of the first tri-state buffer; The input end of the first tri-state buffer is used to receive a signal from the output end of the second buffer, and the output end of the first tri-state buffer is connected to the I2C master device; The input end of the first buffer is used to input the I2C signal to be transmitted of the I2C master device, and the output end of the first buffer is connected to the input end of the second tri-state buffer; The option card input terminal of the second tri-state buffer is used to input the direction signal, and the output terminal of the second tri-state is connected to the I2C slave device; The input end of the second buffer is used to input the I2C signal to be transmitted of the I2C slave device; By means of the direction control module, according to the direction signal of the I2C signal to be transmitted, controlling the I2C signal to be transmitted to be transparently transmitted according to the direction signal specifically includes: Inputting the direction signal of the I2C signal to be transmitted to the input end of the first inverter and the option card pass input end of the second tri-state buffer; Determining the working states of the first tri-state buffer and the second tri-state buffer according to the direction signal of the I2C signal to be transmitted; generating a transparent transmission route between the I2C master device and the I2C slave device according to the working states of the first tri-state buffer and the second tri-state buffer; Determining the working states of the first tri-state buffer and the second tri-state buffer according to the direction signal of the I2C signal to be transmitted specifically includes: When the direction signal of the I2C signal to be transmitted is the first direction, the first tri-state buffer is in a disabled state, wherein in the disabled state, the output end of the first tri-state buffer is in a high impedance state; When the direction signal of the I2C signal to be transmitted is the second direction, the second tri-state buffer is in a disabled state, wherein in the disabled state, the output end of the second tri-state buffer is in a high impedance state; Generating a transparent transmission route between the I2C master device and the I2C slave device according to the working states of the first tri-state buffer and the second tri-state buffer, specifically comprising: When the first tri-state buffer is in a disabled state, the transparent transmission route between the I2C master device and the I2C slave device is: the I2C signal to be transmitted of the I2C master device is input to the input end of the first buffer, the I2C signal to be transmitted is output through the output end of the first buffer, and the I2C signal to be transmitted is input to the input end of the second tri-state buffer, and is output to the I2C slave device through the output end of the second tri-state buffer; When the second tri-state buffer is in a disabled state, the transparent transmission route between the I2C slave device and the I2C master device is: the I2C signal to be transmitted of the I2C slave device is input to the input end of the second buffer, the I2C signal to be transmitted is output through the output end of the second buffer, and the I2C signal to be transmitted is input to the input end of the first tri-state buffer, and is output to the I2C master device through the output end of the first tri-state buffer.

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