An etching method, LED chip and manufacturing method thereof

Abstract

The application provides an etching method, an LED chip and a manufacturing method thereof. A polymer layer and a negative photoresist are sequentially formed on the surface of a structure to be etched. An exposure and development are performed to form a mask plate with an inverted trapezoidal platform, i.e., the photoresist pattern is wide at the top and narrow at the bottom. Then, a sensitive source is used to cross-link the surfaces on both sides of the negative photoresist to realize photoresist pattern inversion, so that the photoresist pattern is narrow at the top and wide at the bottom. Finally, the etching selectivity of the structure to be etched relative to the etching enhancement layer is not less than 1, so that the etching area of the structure to be etched forms a preset pattern with a small inclination.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to an etching method, an LED chip and a manufacturing method thereof. Background Art

[0002] With the continuous development of semiconductor light-emitting technology, the application of LEDs is changing with each passing day, especially the development of LED in display technology. At the same time, due to the need for high resolution of LED displays, the spacing and size of LED chips are getting smaller and smaller, such as Mini-LED and other micro-light-emitting devices.

[0003] Mini-LEDs, with micron-scale dimensions, represent a new generation of LED technology. They inherit the high efficiency, reliability, brightness, and fast response times of fine-pitch LEDs, while also offering lower power consumption and costs. Currently, Mini-LEDs typically utilize a flip-chip structure, where deep trenches are etched using a positive photoresist mask, followed by an ICP etching process to separate the Mini-LEDs.

[0004] However, the inventors found during product testing that Figure 1 、 Figure 2 As shown in the dotted box, when a photoresist mask is used for deep etching to form a groove, the electromagnetic field will be distorted at the edge due to the influence of the edge effect, reducing the uniformity of the etching morphology on the entire surface. On the other hand, in the ICP etching process, the plasma will also tilt the etching angle under the action of the gas flow field. As a result, the size of the deep etching groove is too large relative to the size of the mini-LED chip, affecting the effective area and luminous area of ​​the Mini-LED chip of the same size. At the same time, as the size of the LED chip decreases, due to the thick thickness of the positive photoresist mask and the large exposure energy on the upper surface, there is severe diffraction and severe changes in the photoresist morphology after high-temperature baking, which brings about obvious edge effects in the deep etching channel. The pattern is severely deformed after etching, and the channel presents arc-shaped irregular lines. There is a risk of overlapping between the groove and the electrode groove in some areas, affecting the performance and appearance of the LED chip.

[0005] In view of this, the inventors specially designed an etching method, an LED chip and a manufacturing method thereof, which resulted in this case. Summary of the Invention

[0006] The object of the present invention is to provide an etching method, an LED chip and a manufacturing method thereof, so as to improve the deep etching morphology of the LED chip.

[0007] In order to achieve the above object, the technical solution adopted by the present invention is as follows:

[0008] An etching method, comprising:

[0009] providing a structure to be etched, the structure to be etched comprising a semiconductor material layer;

[0010] forming a preset pattern on the structure to be etched by etching the structure to be etched, the etching process comprising:

[0011] forming an etching enhancement layer on the surface of the structure to be etched, and the etching selectivity of the structure to be etched relative to the etching enhancement layer is not less than 1;

[0012] forming a sensitive negative photoresist on the surface of the etching enhancement layer, and after exposure and development to form a mask plate with a photoresist pattern, cross-linking the two side surfaces of the negative photoresist by a sensitive source to realize photoresist pattern inversion;

[0013] forming a preset pattern on the etching area of the structure to be etched by etching and de-gluing process.

[0014] Preferably, the negative photoresist comprises a heat-sensitive negative photoresist, and the etching enhancement layer comprises a polymer layer.

[0015] Preferably, after spin-coating a heat-sensitive negative photoresist on the surface of the polymer layer and performing exposure and development to form a mask plate with a photoresist pattern, the method further comprises:

[0016] Step one: using a baking plate to perform reverse baking on the side surface of the structure to be etched away from the negative photoresist, and heat the lower surface of the photoresist by heat conduction until the photoresist is hard and the polymer layer is glassy;

[0017] Step two: performing general exposure on the surface of the negative photoresist to shape the negative photoresist and improve its etching resistance;

[0018] Step three: baking the surface of the negative photoresist to heat the upper surface of the photoresist by heat convection; thereby, heat-crosslinking the two side surfaces of the negative photoresist by the step one and the step three to realize photoresist pattern inversion;

[0019] Step four: forming a preset pattern on the etching area of the structure to be etched by etching and de-gluing process.

[0020] Preferably, the glass transition temperature range of the polymer layer is equal to the baking temperature range of the baking plate.

[0021] Preferably, the baking temperature of the baking plate in the step one is not less than the surface baking temperature of the negative photoresist in the step three, so as to form a heat crosslinking temperature difference between the upper and lower surfaces of the negative photoresist to realize photoresist pattern inversion.

[0022] Preferably, the baking temperature of the baking plate in the step one and the surface baking temperature of the negative photoresist in the step two are in the range of 5-40℃, including the end point.

[0023] Preferably, the polymer layer has a polymerization temperature of 80-110℃, a glass transition temperature of 120-140℃, including the end point; the baking plate has a baking temperature of 120-140℃, including the end point; and the negative photoresist has a surface baking temperature of 90-105℃, including the end point.

[0024] Preferably, the polymer layer comprises one or more of organosiloxane and polyhydroxy polycyclic aromatic resin.

[0025] Preferably, the surface baking of the negative photoresist in the step three is performed in an oven in an air or nitrogen environment to form heating by thermal convection; and the baking plate in the step one is baked in a vacuum environment to form heating by thermal conduction.

[0026] Preferably, a surface modification layer is further provided between the polymer layer and the negative photoresist, and the surface modification layer is used to control the bonding strength of the contact surface between the polymer layer and the negative photoresist.

[0027] Preferably, the surface modification layer comprises hexamethyldisilazane, which is used as a surface modification layer to reduce the hydroxyl concentration when the surface of the negative photoresist is baked and heated, so as to control the bonding strength of the contact surface between the polymer layer and the negative photoresist.

[0028] The application further provides a manufacturing method of an LED chip, which uses the etching method in any one of the above embodiments to form a plurality of LED light emitting units separated by channels; specifically, the manufacturing method comprises the following steps:

[0029] S01, providing a substrate;

[0030] S02, growing an epitaxial stack, which comprises a first-type semiconductor layer, an active layer and a second-type semiconductor layer stacked in sequence on the surface of the substrate;

[0031] S03, etching the epitaxial stack to expose part of the first-type semiconductor layer, thereby forming a plurality of grooves and mesas, wherein the grooves and the mesas are arranged oppositely;

[0032] S04, using the etching method in any one of the above embodiments to etch the epitaxial stack to the surface of the substrate, thereby forming a plurality of epitaxial stacks arranged separately by channels;

[0033] S05, depositing a transparent conductive layer on the mesa of each of the independent epitaxial stacks.

[0034] S06, forming electrode extension strips on the surface of the transparent conductive layer and the bottom surface of the groove respectively;

[0035] Alternatively, the transparent conductive layer is etched to form a through hole, and the electrode extension strip is embedded in the transparent conductive layer through the through hole to form a connection with the second-type semiconductor layer;

[0036] S07, forming a composite reflective layer on the surface of the epitaxial stack, which at least includes a DBR reflective layer;

[0037] S08. Forming a first through hole and a second through hole in the composite reflective layer by an etching process, wherein the second through hole exposes a portion of the surface of the electrode extension strip located on the mesa, and the first through hole exposes a portion of the surface of the electrode extension strip located in the groove;

[0038] S09. Make a first electrode and a second electrode, wherein the first electrode is deposited in the first through hole and extends to the surface of the composite reflective layer, and the second electrode is deposited in the second through hole and extends to the surface of the composite reflective layer, and the first electrode and the second electrode are arranged far apart.

[0039] Preferably, the angle between the channel and the epitaxial stack is 55° to 90°, inclusive.

[0040] The present invention also provides an LED chip, which is obtained by the above-mentioned manufacturing method.

[0041] It can be seen from the above technical solution that the etching method provided by the present invention forms a polymer layer and a negative photoresist on the surface of the structure to be etched in sequence, and forms a mask plate with an inverted trapezoidal table through exposure and development, that is, the pattern of the photoresist is wide at the top and narrow at the bottom, and then uses a sensitive source to cross-link the surfaces of both sides of the negative photoresist to achieve the inversion of the photoresist pattern, so that the pattern of the photoresist is narrow at the top and wide at the bottom, and then combines the setting of the etching selectivity ratio of the structure to be etched relative to the etching enhancement layer to be not less than 1, so that the etching area of ​​the structure to be etched forms a preset pattern with a smaller inclination.

[0042] Furthermore, the negative photoresist includes a thermosensitive negative photoresist. After the thermosensitive negative photoresist is spin-coated on the surface of the polymer layer and exposed and developed to form a mask plate with a photoresist pattern, it also includes: first, the baking plate is reverse-baked to harden the film, and the polymer layer is vitrified to improve the etching resistance; then, the surface of the negative photoresist is exposed to the air to fix the negative photoresist and improve its etching resistance; then, the surface of the negative photoresist is baked, and the lower surface of the photoresist is heated by thermal conduction through the reverse baking and the upper surface of the photoresist is heated by thermal convection through the negative photoresist surface baking, so that the two sides of the negative photoresist are thermally cross-linked to different degrees to achieve reversal of the photoresist pattern; thereby achieving a photoresist pattern with reversed negative photoresist pattern and regular and smooth lines, which effectively solves the problems of edge jaggedness, pattern distortion and large inclination of the photoresist pattern.

[0043] At the same time, the negative photoresist in the present application is combined with the polymer layer as a deep etching mask, which is lower in cost and easier to operate than the traditional process of using silicon oxide or metal as a hard mask.

[0044] The present invention also provides an LED chip and a method for manufacturing the same. The etching method is used to form a plurality of LED light-emitting units isolated from each other by channels, thereby forming regular and smooth channels, thereby avoiding the risk of overlapping of the channels with the electrode grooves and affecting the performance of the LED chip. At the same time, the etching method can effectively solve the problem of large channel inclination of the LED chip, thereby obtaining a channel with steep sides, thereby effectively reducing the size of the channel and maximizing the effective area and light-emitting area of ​​the LED chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0046] Figure 1 This is a topography diagram of an LED chip after deep etching to form grooves in the prior art;

[0047] Figure 2 This is a FIB test image after deep etching of an LED chip to form grooves in the prior art;

[0048] Figure 3 Flowchart of the etching method provided in Example 1 of the present invention;

[0049] Figures 4.1 to 4.9A schematic structural diagram corresponding to the etching method provided in Example 1 of the present invention;

[0050] Figures 5.1 to 5.10 This is a structural schematic diagram corresponding to the method for manufacturing an LED chip provided in Example 2 of the present invention;

[0051] Figure 6 This is a morphology diagram of the LED chip provided in Example 2 of the present invention after deep etching to form grooves;

[0052] Figure 7 This is a FIB test image of the LED chip provided by Example 2 of the present invention after deep etching to form grooves;

[0053] Explanation of symbols in the figure: L1 structure to be etched, L2 polymer layer, L3 negative photoresist, 1 substrate, 2 first type semiconductor layer, 3 active layer, 4 second type semiconductor layer, 5.1 groove, 5.2 terrace, 6 transparent conductive layer, 7 electrode extension strip, 8.1 passivation layer, 8.2 DBR reflective layer, 8.3 second through hole, 8.4 first through hole, 9 metal filling layer, 10 second electrode, 11 first electrode. DETAILED DESCRIPTION

[0054] To make the content of the present invention clearer, the content of the present invention is further described below with reference to the accompanying drawings. The present invention is not limited to the specific embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts are within the scope of protection of the present invention.

[0055] Example 1

[0056] refer to Figure 3 The etching method shown is a flow chart, an etching method comprising:

[0057] like Figure 4.1 As shown, a structure L1 to be etched is provided, and the structure L1 to be etched includes a semiconductor material layer;

[0058] The structure to be etched L1 is etched to form a preset pattern. The etching process includes:

[0059] like Figure 2 As shown in .2, an etching enhancement layer is formed on the surface of the structure to be etched L1, and the etching selectivity ratio of the structure to be etched L1 to the etching enhancement layer is not less than 1;

[0060] A sensitive negative photoresist L3 is formed on the surface of the etching enhancement layer, and after exposure and development to form a mask having a photoresist pattern, a sensitive source is used to cross-link the surfaces of both sides of the negative photoresist L3 to achieve photoresist pattern inversion;

[0061] Through etching and stripping processes, the etched area of ​​the to-be-etched structure L1 forms a preset pattern.

[0062] On the basis of the above embodiments, in one embodiment of the present application, the negative photoresist L3 includes a thermosensitive negative photoresist L3, and the etching enhancement layer includes a polymer layer L2.

[0063] Based on the above embodiments, in one embodiment of the present application, Figure 4.3 As shown, after spin coating a thermosensitive negative photoresist L3 on the surface of the polymer layer L2, exposing and developing to form a mask having a photoresist pattern, the method further includes:

[0064] Step 1: Figure 4.4 As shown, the surface of the negative photoresist L3 on the side of the etched structure L1 is reversely baked using a baking plate to heat the lower surface of the photoresist L3 through heat conduction until the photoresist L3 is hardened and the polymer layer L2 is vitrified;

[0065] Step 2: Figure 4.5 As shown, a flood exposure is performed on the surface of the negative photoresist L3 to shape the negative photoresist L3 and improve its etching resistance;

[0066] Step 3: Figure 4.6 and 4.7 As shown, baking is performed on the surface of the negative photoresist L3 so that the upper surface of the photoresist is heated by thermal convection; thereby, through the steps 1 and 3, the surfaces on both sides of the negative photoresist L3 are thermally cross-linked to achieve inversion of the photoresist pattern;

[0067] Step 4: Figure 4.8 、 Figure 4.9 As shown, the etching area of ​​the to-be-etched structure L1 is formed into a preset pattern through etching and stripping processes.

[0068] Based on the above embodiment, in one embodiment of the present application, the glass transition temperature range of the polymer layer L2 is equivalent to the baking temperature range of the baking plate.

[0069] Based on the above embodiments, in one embodiment of the present application, the baking temperature of the baking plate in step one is not less than the surface baking temperature of the negative photoresist L3 in step two, so that a thermal cross-linking temperature difference is formed between the upper and lower surfaces of the negative photoresist L3 to achieve the reversal of the photoresist pattern.

[0070] Based on the above embodiments, in one embodiment of the present application, the difference between the baking temperature of the baking plate in step one and the surface baking temperature of the negative photoresist L3 in step three ranges from 5°C to 40°C, including endpoint values.

[0071] Based on the above embodiments, in one embodiment of the present application, the polymerization temperature of the polymer layer L2 is 80°C to 110°C, and its glass transition temperature is 120°C to 140°C, including endpoint values; the baking temperature of the baking plate is 120°C to 140°C, including endpoint values.

[0072] On the basis of the above embodiments, in one embodiment of the present application, the polymer layer L2 includes one or more of organic siloxane and polyhydroxy polyphenyl ring resin.

[0073] Based on the above embodiments, in one embodiment of the present application, the surface baking of the negative photoresist L3 in step three is performed in an oven in an air environment or a nitrogen environment to achieve heating by thermal convection; the baking plate baking in step one is performed in a vacuum environment to achieve heating by thermal conduction.

[0074] Based on the above embodiments, in one embodiment of the present application, a surface modification layer is further provided between the polymer layer L2 and the negative photoresist L3, and the surface modification layer is used to control the bonding strength of the contact surface between the polymer layer L2 and the negative photoresist L3.

[0075] Based on the above embodiments, in one embodiment of the present application, the surface modification layer includes hexamethyldisilazane, which is used as a surface modification layer. When the surface of the negative photoresist L3 is baked and heated, the hydroxyl concentration can be reduced to control the bonding strength between the contact surface of the polymer layer L2 and the negative photoresist L3.

[0076] On the basis of the above embodiment, in one embodiment of the present application, step four includes: forming a preset pattern in the etching area of ​​the to-be-etched structure L1 through a plasma (ICP) etching and a stripping process.

[0077] It can be seen from the above technical solution that the etching method provided by the present invention forms a polymer layer L2 and a negative photoresist L3 on the surface of the non-etched area of ​​the structure to be etched L1 in sequence, and forms a mask plate with an inverted trapezoidal table 5.2 through exposure and development, that is, the pattern of the photoresist is wide at the top and narrow at the bottom, and then the photoresist pattern is reversed by cross-linking the two sides of the negative photoresist L3 through a sensitive source, so that the pattern of the photoresist is narrow at the top and wide at the bottom, and then combined with the setting of the etching selectivity ratio of the structure to be etched L1 relative to the etching enhancement layer being not less than 1, the etching area of ​​the structure to be etched L1 forms a preset pattern with a smaller inclination.

[0078] Furthermore, the negative photoresist L3 includes a thermosensitive negative photoresist L3. After the thermosensitive negative photoresist L3 is spin-coated on the surface of the polymer layer L2 and exposed and developed to form a mask plate with a photoresist pattern, it also includes: first, the baking plate is reverse-baked to harden the film, and the polymer layer L2 is vitrified to improve the etching resistance; then, the surface of the negative photoresist L3 is exposed to the air to shape the negative photoresist L3 and improve its etching resistance; then, the surface of the negative photoresist L3 is baked, and the lower surface of the photoresist is heated by heat conduction through reverse baking and the upper surface of the photoresist is heated by heat convection through baking of the negative photoresist L3 surface, so that the two sides of the negative photoresist L3 are thermally cross-linked to different degrees to achieve reversal of the photoresist pattern; thereby achieving a photoresist pattern with reversed negative photoresist pattern and regular and smooth lines, which effectively solves the problems of edge jaggedness, pattern distortion and large inclination of the photoresist pattern.

[0079] At the same time, the negative photoresist L3 in the present application is combined with the polymer layer L2 as a deep etching mask, which is lower in cost and easier to operate than the traditional process of using silicon oxide or metal as a hard mask.

[0080] Example 2

[0081] An embodiment of the present invention provides a method for manufacturing an LED chip, which uses the etching method of Example 1 to form a plurality of LED light-emitting units isolated from each other by trenches. Specifically, the manufacturing method includes the following steps:

[0082] S01、 Figure 5.1 As shown, a substrate 1 is provided;

[0083] It should be noted that the type of the substrate 1 is not limited in the micro-light emitting element of this embodiment. For example, the substrate 1 can be, but is not limited to, a sapphire substrate 1 , a silicon substrate 1 , and the like.

[0084] S02, such as Figure 5.2 As shown, an epitaxial stack is grown, and the epitaxial stack includes a first-type semiconductor layer 2, an active layer 3, and a second-type semiconductor layer 4 stacked in sequence on the surface of a substrate 1;

[0085] It should be noted that the types of the epitaxial stacked first-type semiconductor layer 2, active region 3, and second-type semiconductor layer 4 may not be restricted in the micro-light-emitting element of this embodiment. For example, the first-type semiconductor layer 2 may be, but is not limited to, a gallium nitride layer, and correspondingly, the second-type semiconductor layer 4 may be, but is not limited to, a gallium nitride layer.

[0086] S03, such as Figure 5.3 As shown, by etching the epitaxial stack, part of the first type semiconductor layer 2 is exposed, thereby forming a plurality of grooves 5.1 and terraces 5.2, wherein the grooves 5.1 and terraces 5.2 are arranged opposite to each other;

[0087] In one embodiment of the present application, etching the epitaxial stack to form the plurality of grooves 5.15.1 and mesas 5.25.2 includes using an inductively coupled plasma (ICP) process with etching gases including Cl2, Ar, and O2. However, this application does not limit this, and the specific method may vary depending on the circumstances.

[0088] S04, such as Figure 5.4 As shown, the etching method shown in the above embodiment 1 is used to deeply etch the epitaxial stack to the surface of the exposed substrate 1, forming a plurality of epitaxial stacks spaced apart from each other by channels;

[0089] In one embodiment of the present application, the following steps are specifically included:

[0090] An etching enhancement layer is formed on the surface of the epitaxial stack, and an etching selectivity ratio of the epitaxial stack to the etching enhancement layer is not less than 1. In a specific embodiment of the present application, the etching enhancement layer includes a polymer layer L2, such as but not limited to one or more of organic siloxane and polyhydroxy polyphenyl ring resin;

[0091] forming a sensitive negative photoresist L3 on the surface of the etching enhancement layer. In a specific embodiment of the present application, the negative photoresist L3 includes a heat-sensitive negative photoresist L3;

[0092] Expose and develop the heat-sensitive negative photoresist L3 to form a mask having mutually intersecting isolation trenches;

[0093] A surface of the epitaxial stack facing away from the negative photoresist L3, i.e., the substrate 1 side, is reversely baked using a baking plate to heat the lower surface of the photoresist L3 by heat conduction until the photoresist L3 is hardened and the polymer layer L2 is vitrified. In a specific embodiment of the present application, the baking plate is performed in a vacuum environment to achieve heating by heat conduction, and the baking plate baking temperature is 120° C. to 140° C., inclusive.

[0094] Performing flood exposure on the surface of the negative photoresist L3 to shape the negative photoresist L3 and improve its etching resistance;

[0095] Baking is performed on the surface of the negative photoresist L3 so that the upper surface of the photoresist is heated by thermal convection; thereby, through the steps 1 and 3, the surfaces on both sides of the negative photoresist L3 are thermally cross-linked to achieve photoresist pattern inversion; in a specific embodiment of the present application, the surface of the negative photoresist L3 is baked in an oven in an air environment or a nitrogen environment to form heating by thermal convection, and the surface baking temperature of the negative photoresist L3 is 90 to 105° C., including end points;

[0096] Through etching and degumming processes, a number of epitaxial stacks spaced apart from each other through the channel are formed; in a specific embodiment of the present application, the channel area is exposed by ICP dry etching, preferably, Cl2 and BCl3 are used for deep etching, wherein the preferred Cl2 / BCl3 ratio is greater than 10:1, the upper electrode RF power is 250~400W, and the lower electrode RF power is 100~200W, but the present application does not limit this, and it depends on the specific situation.

[0097] S05, such as Figure 5.5 As shown, a transparent conductive layer 6 is deposited on each independent mesa 5.2 of the epitaxial stack;

[0098] It is worth mentioning that in the above embodiment, the material of the transparent conductive layer 66 can be ITO, and its formation process can be electron beam evaporation process, sputtering evaporation process, etc., depending on the specific situation, and this application does not limit this.

[0099] S06, such as Figure 5.6 As shown, electrode extension strips 7 are formed on the surface of the transparent conductive layer 6 and the bottom surface of the groove 5.1 respectively;

[0100] Alternatively, the transparent conductive layer 6 is etched to form a through hole, and the electrode extension strip 7 is embedded in the transparent conductive layer 6 through the through hole to form a connection with the second-type semiconductor layer 4;

[0101] It should be noted that the number of electrode extension strips 77 can be one or more; the formation process can be an electron beam evaporation process, which depends on the specific situation and is not limited in this application.

[0102] S07, such as Figure 5.7 As shown, a composite reflective layer is formed on the surface of the epitaxial stack, which includes at least a DBR reflective layer 8.2;

[0103] In one embodiment of the present application, the DBR reflective layer 8.2 includes a plurality of film layers with alternating high and low refractive indices, and the thickness of each film layer is one quarter of the wavelength of light emitted by the micro-light emitting element.

[0104] In another embodiment of the present application, the composite reflective layer includes a passivation layer 8.1 and a DBR reflective layer 8.2 stacked in sequence;

[0105] S08, such as Figure 5.8 As shown, a first through hole 8.4 and a second through hole 8.3 are formed in the composite reflective layer by an etching process, wherein the second through hole 8.3 exposes a portion of the surface of the electrode extension strip 7 located on the terrace 5.2, and the first through hole 8.4 exposes a portion of the surface of the electrode extension strip 7 located in the groove 5.1;

[0106] In another embodiment of the present application, Figure 5.9As shown, a metal filling layer 9 is deposited in the first through hole 8.4 and the second through hole 8.3, and the thickness of the metal filling layer 9 is equal to the thickness of the DBR reflective layer 8.2;

[0107] On the basis of the above embodiment, in one embodiment of the present application, the metal filling layer 9 includes an isolation layer and a filling layer stacked in sequence; wherein the isolation layer includes a Ti layer, and the filling layer includes an Al layer.

[0108] S10, such as Figure 5.10 As shown, a first electrode 11 and a second electrode 10 are manufactured. The first electrode 11 is deposited in the first through hole 8.4 and extends to the surface of the composite reflective layer. The second electrode 10 is deposited in the second through hole 8.3 and extends to the surface of the composite reflective layer. The first electrode 11 and the second electrode 10 are arranged far apart.

[0109] In one embodiment of the present application, the first electrode 11 and the second electrode 10 respectively include tin alloy electrodes;

[0110] In one embodiment of the present application, after the production of the first electrode 11 and the second electrode 10 is completed, RTA is used to perform multi-stage annealing and reflow; the temperature of each stage of the multi-stage annealing and reflow rises in a gradient, and the temperature does not exceed 280°C. After the multi-stage annealing and reflow, the surface of the tin alloy electrode is smooth and has no bumps, the overall height of the first and second electrodes 10 is consistent, and the film stress generated during the metal electrode evaporation process is gradually released.

[0111] Based on the above embodiment, the angle between the channel and the epitaxial stack is 55° to 90°, including the end values.

[0112] The present invention also provides an LED chip, which is obtained by the above-mentioned manufacturing method.

[0113] Through the above technical solution, it can be known that the method for manufacturing an LED chip provided by the present invention forms a polymer layer L2 and a negative photoresist L3 on the surface of the epitaxial stack in sequence, forms a mask plate with an inverted trapezoidal table 5.2 by exposure and development, that is, the pattern of the photoresist is wide at the top and narrow at the bottom, and then uses a sensitive source to cross-link the surfaces of both sides of the negative photoresist L3 to achieve the inversion of the photoresist pattern, so that the pattern of the photoresist is narrow at the top and wide at the bottom, and then combines the setting of the etching selectivity ratio of the etching enhancement layer relative to the epitaxial stack being not less than 1, so that the epitaxial stack forms an isolation channel with a smaller inclination.

[0114] Furthermore, the negative photoresist L3 includes a heat-sensitive negative photoresist L3. After the heat-sensitive negative photoresist L3 is spin-coated on the surface of the polymer layer L2 and exposed and developed to form isolation grooves with mutual intersections, the process also includes: first, performing a reverse baking on the substrate 1 side to harden the film while the polymer layer L2 is vitrified to improve the etching ability; then, performing a flood exposure on the surface of the negative photoresist L3 to fix the negative photoresist L3 and improve its etching resistance; then, baking the surface of the negative photoresist L3, and through reverse baking and baking the surface of the negative photoresist L3, the surfaces on both sides of the negative photoresist L3 are thermally cross-linked to achieve the inversion of the photoresist pattern. Thus, as Figure 6 、 Figure 7 As shown, a number of LED light-emitting units isolated from each other by channels are formed, which have regular and flat channels, avoiding the risk of the channels overlapping with the electrode grooves 5.1 and affecting the performance of the LED chip; at the same time, the above-mentioned etching method can effectively solve the problem of the large inclination of the LED chip channel, and obtain channels with steep sides, thereby effectively reducing the size of the channel and maximizing the effective area and light-emitting area of ​​the LED chip.

[0115] At the same time, the negative photoresist L3 in the present application is combined with the polymer layer L2 as a deep etching mask, which is lower in cost and easier to operate than the traditional process of using silicon oxide or metal as a hard mask.

[0116] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0117] It should also be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such article or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the article or device comprising the aforementioned elements.

[0118] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An etching method, characterized in that: include: Providing a structure to be etched, wherein the structure to be etched includes a semiconductor material layer; The structure to be etched is etched to form a preset pattern, and the etching process includes: forming an etching enhancement layer on the surface of the structure to be etched, wherein the etching selectivity ratio of the structure to be etched relative to the etching enhancement layer is not less than 1; After forming a sensitive negative photoresist on the surface of the etching enhancement layer, exposing and developing it to form a photoresist mask with an inverted trapezoidal shape; cross-linking the surfaces of both sides of the negative photoresist by a sensitive source to achieve photoresist pattern inversion, so that the pattern of the negative photoresist is narrow at the top and wide at the bottom; Through etching and stripping processes, the etching area of ​​the structure to be etched forms an inverted trapezoidal pattern with a smaller inclination than that of the mask plate.

2. The etching method according to claim 1, wherein: The negative photoresist comprises a thermally sensitive negative photoresist, and the etching enhancement layer comprises a polymer layer.

3. The etching method according to claim 2, wherein: After spin coating the thermosensitive negative photoresist on the surface of the polymer layer, exposing and developing the photoresist to form a mask having a photoresist pattern, the method further includes: Step 1: performing reverse baking on the surface of the structure to be etched, which is away from the negative photoresist, using a baking plate to heat the lower surface of the photoresist by heat conduction until the photoresist film is hardened and the polymer layer is vitrified; Step 2: performing flood exposure on the surface of the negative photoresist to fix the negative photoresist and improve its etching resistance; Step 3: baking the surface of the negative photoresist so that the upper surface of the photoresist is heated by thermal convection; thereby, through the steps 1 and 3, the surfaces on both sides of the negative photoresist are thermally cross-linked to achieve photoresist pattern inversion; Step 4: Form a preset pattern in the etched area of ​​the structure to be etched through etching and stripping processes.

4. The etching method according to claim 3, wherein: The glass transition temperature range of the polymer layer is equivalent to the baking temperature range of the baking plate.

5. The etching method according to claim 3, wherein: The baking temperature of the baking plate in step one is not less than the surface baking temperature of the negative photoresist in step three, so that a thermal cross-linking temperature difference is formed between the upper and lower surfaces of the negative photoresist to achieve reversal of the photoresist pattern.

6. The etching method according to claim 5, characterized in that: The difference between the baking temperature of the baking plate in step 1 and the baking temperature of the negative photoresist surface in step 2 is in the range of 5°C to 40°C, including the endpoint values.

7. The etching method according to claim 6, characterized in that: The polymerization temperature of the polymer layer is 80°C-110°C, and its glass transition temperature is 120°C-140°C, including endpoint values; the baking temperature of the baking plate is 120°C-140°C, including endpoint values; the baking temperature of the negative photoresist surface is 90-105°C, including endpoint values.

8. The etching method according to claim 2, wherein: The polymer layer includes one or more of organic siloxane and polyhydroxy polyphenyl ring resin.

9. The etching method according to claim 3, wherein: In an oven, in an air environment or a nitrogen environment, the negative photoresist surface baking described in step three is performed to form heating by heat convection; and the baking plate baking described in step one is performed in a vacuum environment to form heating by heat conduction.

10. The etching method according to claim 2, wherein: A surface modification layer is further provided between the polymer layer and the negative photoresist, and the surface modification layer is used to control the bonding strength between the contact surface of the polymer layer and the negative photoresist.

11. The etching method according to claim 10, characterized in that: The surface modification layer includes hexamethyldisilazane. The hexamethyldisilazane is used as a surface modification layer and can reduce the hydroxyl concentration when the negative photoresist surface is baked and heated to control the bonding strength between the polymer layer and the contact surface of the negative photoresist.

12. A method for manufacturing an LED chip, characterized in that: The etching method according to any one of claims 1 to 9 is used to form a plurality of LED light-emitting units isolated from each other by trenches; specifically, the manufacturing method comprises the following steps: S01, providing a substrate; S02, growing an epitaxial stack, wherein the epitaxial stack includes a first-type semiconductor layer, an active layer, and a second-type semiconductor layer sequentially stacked on the surface of the substrate; S03, exposing a portion of the first-type semiconductor layer by etching the epitaxial stack, thereby forming a plurality of grooves and mesas, wherein the grooves are arranged opposite to the mesas; S04. Using the etching method according to any one of claims 1 to 11, deeply etching the epitaxial stack until the substrate surface is exposed, to form a plurality of epitaxial stacks spaced apart from each other by channels; S05, depositing a transparent conductive layer on the mesas of each of the spaced-apart epitaxial stacks; S06, forming electrode extension strips on the surface of the transparent conductive layer and the bottom surface of the groove respectively; Alternatively, the transparent conductive layer is etched to form a through hole, and the electrode extension strip is embedded in the transparent conductive layer through the through hole to form a connection with the second-type semiconductor layer; S07, forming a composite reflective layer on the surface of the epitaxial stack, which comprises at least a DBR reflective layer; S08. Forming a first through hole and a second through hole in the composite reflective layer by an etching process, wherein the second through hole exposes a portion of the surface of the electrode extension strip located on the mesa, and the first through hole exposes a portion of the surface of the electrode extension strip located in the groove; S09. Make a first electrode and a second electrode, wherein the first electrode is deposited in the first through hole and extends to the surface of the composite reflective layer, and the second electrode is deposited in the second through hole and extends to the surface of the composite reflective layer, and the first electrode and the second electrode are arranged far apart.

13. The method for manufacturing an LED chip according to claim 12, wherein: The angle between the channel and the epitaxial stack is 55°ˉ90°, including the endpoint values.

14. An LED chip, characterized in that: The LED chip is obtained by the manufacturing method according to claim 12 or 13.

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