Method for manufacturing embedded package substrate and package substrate

Abstract

The application discloses a kind of embedded packaging substrate manufacturing method and packaging substrate, including providing a bottom plate, the surface of bottom plate is provided with finished product secondary outer layer circuit and is provided on finished product secondary outer layer circuit First via column;Provide a bearing plate, the surface of bearing plate is attached with electronic component, the connecting terminal of active surface of electronic component is in contact with bearing plate connection;Provide a packaging material, and the bottom plate, packaging material and bearing plate are laminated and compressed, wherein, packaging material is located between bottom plate and bearing plate and covers finished product secondary outer layer circuit and first via column, electronic component is located in one side of packaging material;Remove bearing plate, to expose the connecting terminal of active surface of electronic component, obtain semi-finished product.The application can simplify processing flow, reduce material waste, reduce the processing procedure after electronic component packaging, reduce the risk of electronic component scrapping.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a method for manufacturing an embedded packaging substrate and the packaging substrate. Background Technology

[0002] To increase the integration density of packaging substrates and achieve high-density interconnects, related technologies embed electronic components within the substrate. However, in these technologies, embedding electronic components typically requires machining or pre-machining cavities on the substrate to accommodate the components, then mounting the components within these cavities and encapsulating them with packaging materials. Because machining or pre-machining cavities on the substrate is necessary, the manufacturing process is lengthy and material costs are high. Furthermore, after the embedding and encapsulation of the electronic components, lengthy post-processing of the substrate is required, which can easily lead to product scrap due to the fragility of the electronic components. Summary of the Invention

[0003] The present invention aims to at least solve one of the technical problems existing in the prior art. To this end, the present invention proposes a method for manufacturing an embedded packaging substrate and a packaging substrate, which can simplify the processing flow.

[0004] On one hand, embodiments of the present invention provide a method for fabricating an embedded packaging substrate, comprising:

[0005] A base plate is provided, wherein the surface of the base plate is provided with a finished secondary outer layer circuit and a first through-hole post provided on the finished secondary outer layer circuit;

[0006] A carrier plate is provided, on the surface of which electronic components are mounted, and the connection terminals of the active surfaces of the electronic components are in contact with the carrier plate.

[0007] A packaging material is provided, and the base plate, the packaging material and the carrier plate are laminated together, wherein the packaging material is located between the base plate and the carrier plate and covers the finished product's second outer layer circuit and the first through-hole post, and the electronic components are located on one side of the packaging material;

[0008] Remove the carrier plate to expose the connection terminals of the active surface of the electronic component, thus obtaining a semi-finished product.

[0009] The embodiments of the present invention have at least the following beneficial effects:

[0010] By embedding and encapsulating electronic components on a base plate through a layered lamination process, no cavities need to be processed or pre-processed, which simplifies the processing flow and reduces material waste. Moreover, embedding and encapsulating electronic components on the outermost layer of the finished product shifts the embedding and encapsulation process of electronic components to a later stage, reducing the processing steps after electronic component encapsulation and lowering the risk of electronic component scrap.

[0011] According to some embodiments of the present invention, providing a support plate includes:

[0012] A support plate is provided, the support plate having at least one flat surface;

[0013] An adhesive zone is machined on the flat surface of the bearing plate;

[0014] The electronic components are mounted on the adhesive area of ​​the carrier plate.

[0015] According to some embodiments of the present invention, the step of machining an adhesive region on the flat surface of the bearing plate includes:

[0016] Adhesive is applied to the entire flat surface of the bearing plate;

[0017] Alternatively, adhesive can be applied to a localized area of ​​the flat surface of the carrier plate, the location of which is adapted to the mounting position of the electronic component.

[0018] According to some embodiments of the present invention, the encapsulation material is a pure resin sheet, and the step of laminating and pressing the base plate, the encapsulation material, and the carrier plate includes:

[0019] The pure resin material sheets are stacked on the base plate;

[0020] The carrier plate is stacked on the pure resin material sheet, wherein the side of the carrier plate on which the electronic components are attached faces the pure resin material sheet;

[0021] The stacked base plate, the pure resin material sheet, and the support plate are pressed together.

[0022] According to some embodiments of the present invention, after removing the carrier plate, the method further includes:

[0023] The semi-finished product is perforated to expose the first through-hole post;

[0024] The semi-finished product is electroplated to obtain the outermost layer of the finished product circuit, which is connected to the connection terminal of the first through-hole post and the active surface of the electronic component.

[0025] According to some embodiments of the present invention, the electroplating treatment of the semi-finished product includes:

[0026] Process the first seed layer onto the semi-finished product;

[0027] A first photosensitive masking film is processed on the first seed layer to obtain a circuit pattern corresponding to the outermost circuit of the finished product;

[0028] The semi-finished product is subjected to electroplating to form the outermost layer of the finished product through the circuit pattern;

[0029] Remove the first photosensitive masking film and etch the first seed layer.

[0030] According to some embodiments of the present invention, the electroplating treatment of the semi-finished product includes:

[0031] Process the first seed layer onto the semi-finished product;

[0032] The semi-finished product is subjected to whole-plate electroplating to form an electroplated metal layer on the first seed layer;

[0033] A second photosensitive masking film is processed on the electroplated metal layer to obtain a circuit pattern corresponding to the outermost circuit of the finished product;

[0034] The electroplated metal layer is etched to form the outermost circuit of the finished product through the circuit pattern;

[0035] Remove the second photosensitive masking film.

[0036] According to some embodiments of the present invention, the outermost layer of the finished product is provided with pads, and after obtaining the outermost layer of the finished product, the method further includes:

[0037] A solder resist layer is processed on the semi-finished product, and the solder resist layer is provided with solder resist openings corresponding to the solder pads;

[0038] The semi-finished product is subjected to metal surface treatment to form a surface treatment layer corresponding to the position of the solder resist opening.

[0039] According to some embodiments of the present invention, the base plate has multiple layers of wiring, and adjacent layers of wiring on the base plate are connected by a second through-hole post.

[0040] On the other hand, embodiments of the present invention provide a packaging substrate, which is prepared by the above-described embedded packaging substrate manufacturing method.

[0041] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0042] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0043] Figure 1 This is a flowchart illustrating the steps of the embedded packaging substrate fabrication method according to an embodiment of the present invention.

[0044] Figure 2 for Figure 1 One of the schematic diagrams of the finished product structure obtained by the embedded packaging substrate fabrication method is shown;

[0045] Figure 3 for Figure 1 The second schematic diagram shows the structure of the finished product prepared by the embedded packaging substrate fabrication method.

[0046] Figures 4 to 8 This is a schematic diagram of the intermediate process of the embedded packaging substrate fabrication method according to an embodiment of the present invention;

[0047] Figure 9 To Figure 8 The schematic diagram is obtained after the solder resist layer is processed and the metal surface is treated. Detailed Implementation

[0048] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0049] In the description of this invention, "several" means one or more, "multiple" means two or more, "greater than," "less than," "exceeding," etc. are understood to exclude the stated number, and "above," "below," "within," etc. are understood to include the stated number. If "first," "second," etc. are used in the description, they are only for the purpose of distinguishing technical features and should not be construed as indicating or implying relative importance or implicitly indicating the number of indicated technical features or the order of the indicated technical features.

[0050] In the description of this invention, unless otherwise explicitly defined, terms such as "setting" and "connection" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0051] Please refer to Figure 1 This embodiment discloses a method for fabricating an embedded packaging substrate, including steps S100 to S400. It should be noted that the consecutive numbering of the method steps in this embodiment is for ease of review and understanding. Adjusting the implementation order of some steps, considering the overall technical solution of this embodiment and the logical relationships between the steps, will not affect the technical effect achieved by the technical solution of this embodiment. The content of each step is discussed in detail below:

[0052] S100, a base plate 100 is provided, and the surface of the base plate 100 is provided with a finished secondary outer layer circuit 110 and a first through-hole post 120 provided on the finished secondary outer layer circuit 110.

[0053] In related technologies, one method for embedding electronic components 210 involves prefabricating a polymer frame with a cavity, then embedding and encapsulating the electronic components 210 within the cavity and fabricating a redistribution layer to connect the electronic components 210, followed by layer fabrication on the polymer frame. Since the process of embedding electronic components 210 is located early in the overall production process, and the electronic components 210 still require multiple processes after embedding and encapsulation, some processes (such as the lamination process) may damage the electronic components 210 and render them unusable. Other processes (such as the pattern plating process for the added-layer circuitry) may cause the encapsulation substrate containing the electronic components 210 to be scrapped due to circuit quality issues, thus resulting in waste of the electronic components 210.

[0054] Therefore, in this embodiment, the embedding and packaging process of electronic component 210 is moved backward, that is, electronic component 210 is embedded and packaged on a base plate 100. It should be noted that in this embodiment, the outermost layer circuit 110 and the outermost layer circuit 130 mentioned below refer to the finished product. For example, please refer to... Figure 2 Assuming the finished packaging substrate, after all processing steps, has four layers of circuitry, where L2 and L3 are inner layers and L1 and L4 are outer layers, then the second outermost layer 110 refers to the L2 and L3 layers, and the outermost layer 130 refers to the L1 and L4 layers. For example, please refer to... Figure 3 Assuming the finished packaging substrate, after all processing steps, has five layers of circuitry, where L2, L3, and L4 are inner layers and L1 and L5 are outer layers, then the second outermost layer 110 refers to the L2 and L4 layers, and the outermost layer 130 refers to the L1 and L5 layers. It is important to note that during processing, the product is in a semi-finished state (e.g., ...). Figure 4 As shown), for the base plate 100, the finished secondary outer layer circuit 110 is the outermost circuit of the base plate 100, and the first through-hole post 120 provided on the finished secondary outer layer circuit 110 is used as an interlayer connection structure to connect the finished secondary outer layer circuit 110 and the finished outermost circuit 130.

[0055] S200, please refer to Figure 5 A carrier plate 200 is provided, and electronic components 210 are mounted on the surface of the carrier plate 200. The connection terminals of the active surfaces of the electronic components 210 are in contact with the carrier plate 200.

[0056] In actual production, a base plate 100 may contain multiple identical units, each requiring the embedding of a corresponding electronic component 210. To achieve batch embedding and packaging of the electronic components 210, this embodiment mounts the electronic components 210 onto a carrier plate 200, allowing for independent arrangement of the electronic components 210. This means the electronic components 210 are arranged on the carrier plate 200 according to preset positions, eliminating the need to wait for the base plate 100 to be processed before arranging them one by one, thus improving processing efficiency. It should be understood that, for ease of description, this embodiment only illustrates one electronic component 210. The electronic component 210 can be an active device, such as a chip, or a passive device, such as a resistor or capacitor. The active surface of the electronic component 210 is provided with connection terminals. To facilitate subsequent wiring connections to these terminals, this embodiment connects the active surface of the electronic component 210 to the carrier plate 200. It should be noted that the electronic component 210 can be separated from the carrier plate 200 to facilitate the subsequent removal of the carrier plate 200.

[0057] S300, please refer to Figure 5 and Figure 6 A packaging material 300 is provided, and a base plate 100, a packaging material 300 and a carrier plate 200 are laminated and pressed together. The packaging material 300 is located between the base plate 100 and the carrier plate 200 and covers the outermost layer circuit 110 and the first through-hole post 120 of the finished product. The electronic component 210 is located on one side of the packaging material 300.

[0058] Unlike related technologies, this embodiment does not require machining or pre-machining cavities on the base plate 100. During the lamination process, the encapsulation material 300 can change from a solid state to a fluid state, filling the gap between the base plate 100 and the carrier plate 200, thereby covering the electronic components 210, the finished outermost layer circuit 110, and the first through-hole post 120. After lamination is completed, the encapsulation material 300 changes from a fluid state to a solid state, which can both embed and encapsulate the electronic components 210 and form an insulating dielectric layer, providing a basis for the subsequent fabrication of the finished outermost layer circuit 130.

[0059] S400, please refer to Figure 6 and Figure 7 Remove the carrier plate 200 to expose the connection terminals of the active surface of the electronic component 210, and obtain a semi-finished product.

[0060] In this embodiment, electronic components 210 are embedded and encapsulated on the base plate 100 by a layering and lamination method, eliminating the need for processing or pre-processing cavities. This simplifies the processing flow and reduces material waste. Furthermore, embedding and encapsulating electronic components 210 on the outermost layer of the finished product circuit 110 shifts the embedding and encapsulation process of electronic components 210 to a later stage, reducing the processing steps after encapsulation, lowering the risk of scrapping electronic components 210, and reducing waste of electronic components 210 due to production quality issues.

[0061] Please refer to Figure 5 In step S100 above, providing a support plate 200 includes:

[0062] S110. A support plate 200 is provided, the support plate 200 having at least one flat surface;

[0063] S120. An adhesive area is machined on the flat surface of the bearing plate 200;

[0064] S130. The electronic component 210 is mounted on the adhesive area of ​​the carrier plate 200.

[0065] Depending on the specific application requirements, the carrier plate 200 can be made of different materials. For example, in this embodiment, the carrier plate 200 is made of stainless steel. Stainless steel has high mechanical strength and is not easily deformed, ensuring that the carrier plate 200 has at least one flat surface. Furthermore, the flat surface of the stainless steel plate can be polished to obtain a smooth surface, facilitating subsequent processing of the adhesive area. The adhesive area allows electronic components 210 to be temporarily mounted on the carrier plate 200 and easily separated from it.

[0066] Step S120, which involves processing an adhesive area on the flat surface of the support plate 200, includes:

[0067] Adhesive 201 is applied to the entire flat surface of the bearing plate 200;

[0068] Alternatively, adhesive 201 can be applied to a localized area of ​​the flat surface of the carrier plate 200, with the location of the localized area matching the mounting position of the electronic component 210.

[0069] This embodiment allows for flexible adjustment of the adhesive area size according to actual application needs. For example, when the mounting positions of electronic components 210 are evenly distributed on the flat surface of the carrier plate 200, adhesive 201 can be applied to the entire flat surface of the carrier plate 200; when the mounting positions of electronic components 210 are concentrated in a local area of ​​the flat surface of the carrier plate 200, adhesive 201 can be applied to that local area, which helps save materials. The adhesive 201 can be double-sided tape or high-temperature adhesive, etc.

[0070] To better encapsulate the electronic component 210, the encapsulation material 300 is a pure resin sheet. A pure resin sheet refers to a material without any added strength, such as glass fiber. Because pure resin has good flowability, it can effectively surround the electronic component 210, reducing air bubbles or gaps in the encapsulation. For more details, please refer to [reference needed]. Figure 5 Step S300 involves laminating and pressing the base plate 100, the encapsulation material 300, and the carrier plate 200 together, including:

[0071] S310. Place the pure resin material sheet on the base plate 100;

[0072] S320. The carrier plate 200 is stacked on the pure resin material sheet, wherein the side of the carrier plate 200 on which the electronic components 210 are attached faces the pure resin material sheet.

[0073] S330, Press the stacked base plate 100, pure resin material sheet and bearing plate 200 together.

[0074] Please refer to Figure 7 and Figure 8 After step S400, removing the carrier plate 200, the method for fabricating the embedded packaging substrate in this embodiment further includes:

[0075] S510. The semi-finished product is perforated to expose the first through-hole column 120.

[0076] S520. Electroplating is performed on the semi-finished product to obtain the outermost circuit 130 of the finished product. The outermost circuit 130 of the finished product is connected to the connection terminal of the first through hole post 120 and the active surface of the electronic component 210.

[0077] After lamination, the encapsulation material 300 forms an insulating dielectric layer on the base plate 100. The thickness of the insulating dielectric layer is greater than the height of the first through-hole post 120, that is, the first through-hole post 120 is embedded in the insulating dielectric layer. Therefore, the semi-finished product needs to be opened, for example, the semi-finished product is laser-drilled to remove the encapsulation material 300 corresponding to the first through-hole post 120, thereby exposing the first through-hole post 120, and then the outermost circuit 130 of the finished product is processed. It should be noted that the outermost layer circuit 130 of the finished product has multiple traces. Some traces are connected to the first through-hole post 120, thereby realizing the interconnection between the outermost layer circuit 130 and the second outermost layer circuit 110 of the finished product; some traces are connected to the connection terminals of the active surface of the electronic component 210, thereby realizing the interconnection between the electronic component 210 and the outermost layer circuit 130 of the finished product; the two ends of some traces are respectively connected to the first through-hole post 120 and the connection terminals of the active surface of the electronic component 210, which can realize the interconnection between the electronic component 210 and the second outermost layer circuit 110 of the finished product.

[0078] In some application examples, step S520, electroplating the semi-finished product, includes:

[0079] S521. Process the first seed layer (not shown) on the semi-finished product;

[0080] S522. Process a first photosensitive masking film (not shown) on the first seed layer to obtain a circuit pattern corresponding to the outermost circuit 130 of the finished product.

[0081] S523. Electroplating is performed on the semi-finished product to form the outermost circuit 130 of the finished product through the circuit pattern;

[0082] S524, Remove the first photosensitive masking film and etch the first seed layer.

[0083] The first seed layer can be made of one or more of the following materials: copper, titanium, nickel, gold, silver, tungsten, aluminum, tin, etc. The first seed layer can be processed onto the semi-finished product using physical sputtering or chemical electroplating. Specifically, the material of the first seed layer adheres to the surface of the insulating dielectric layer, which can enhance the adhesion between the outermost layer of the finished product 130 and the insulating dielectric layer. The first photosensitive masking film can be processed by attaching a dry film to the first seed layer, or by coating a liquid photosensitive material onto the first seed layer, followed by exposure and development to obtain the circuit pattern. After electroplating, a preliminary finished outermost layer of the finished product 130 can be obtained. Removing the first photosensitive masking film and etching the first seed layer yields the complete finished outermost layer of the finished product 130.

[0084] In some other application examples, step S520, electroplating the semi-finished product, includes:

[0085] S525. Process the first seed layer on the semi-finished product;

[0086] S526. Electroplating is performed on the entire semi-finished product to form an electroplated metal layer (not shown) on the first seed layer;

[0087] S527. A second photosensitive masking film (not shown) is processed on the electroplated metal layer to obtain a circuit pattern corresponding to the outermost circuit 130 of the finished product.

[0088] S528. The electroplated metal layer is etched to form the outermost circuit 130 of the finished product through the circuit pattern.

[0089] S529, Remove the second photosensitive masking film.

[0090] Unlike the application example above, the circuit pattern obtained by processing with the first photosensitive masking film is a positive pattern, while the circuit pattern obtained by processing with the second photosensitive masking film is a negative pattern. During the etching process of the electroplated metal layer, the second photosensitive masking film protects the covered areas of the electroplated metal layer, while the uncovered areas are etched away, thus obtaining the outermost circuit 130 of the finished product.

[0091] Please refer to Figure 8 and Figure 9 In order to be soldered to other external components, the outermost circuit 130 of the finished product is provided with solder pads. After obtaining the outermost circuit 130 of the finished product, the embedding package substrate manufacturing method of this embodiment further includes:

[0092] S610. A solder resist layer 140 is processed on the semi-finished product. The solder resist layer 140 is provided with solder resist openings corresponding to the solder pads.

[0093] S620. Perform metal surface treatment on the semi-finished product to form a surface treatment layer 150 corresponding to the position of the solder resist opening.

[0094] The solder mask layer 140 protects the outermost circuit layer 130 of the finished product and exposes the areas to be soldered, forming solder mask openings. A surface treatment layer 150 is applied to the solder mask openings to protect the pads. The surface treatment can be anti-oxidation, nickel-palladium-gold plating, tin plating, or silver plating, etc.

[0095] Please refer to Figure 2 and Figure 4 In this embodiment, the embedding and packaging process of electronic component 210 is moved from an earlier stage to a later stage in the production process. Therefore, before embedding and packaging electronic component 210, the base plate 100 can be processed into a multi-layer board according to application requirements, so that the base plate 100 has multiple layers of circuitry. Adjacent layers of circuitry on the base plate 100 are connected by second through-hole posts 160. For example, the base plate 100 has three layers of circuitry, namely L1, L2, and L3 layers, where L1 or L3 layer circuitry is the finished outermost layer circuitry 110. In this way, even if the base plate 100 is scrapped during processing, the electronic component 210 will not be wasted, which helps to save material costs.

[0096] This embodiment provides a packaging substrate, which is prepared by the above-described embedding packaging substrate manufacturing method. In this embodiment, electronic components 210 are embedded and packaged on the base plate 100 through a lamination and pressing process, eliminating the need for machining or pre-machining cavities, thus simplifying the manufacturing process and reducing material waste. Furthermore, embedding and packaging electronic components 210 on the outermost layer of the finished circuit 110 shifts the embedding and packaging process of electronic components 210 to a later stage, reducing post-packaging processing steps, lowering the risk of scrapping electronic components 210, and reducing waste of electronic components 210 due to production quality issues.

[0097] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention.

Claims

1. A method for fabricating an embedded packaging substrate, characterized in that, include: A base plate (100) is provided, and the surface of the base plate (100) is provided with a finished secondary outer layer circuit (110) and a first through-hole post (120) provided on the finished secondary outer layer circuit (110); A carrier plate (200) is provided, on the surface of which electronic components (210) are mounted, and the connection terminals of the active surfaces of the electronic components (210) are in contact with the carrier plate (200); An encapsulation material (300) is provided, and the base plate (100), the encapsulation material (300) and the carrier plate (200) are laminated together, wherein the encapsulation material (300) is located between the base plate (100) and the carrier plate (200) and covers the finished outermost layer circuit (110) and the first through-hole post (120), and the electronic component (210) is located on one side of the encapsulation material (300); Remove the carrier plate (200) to expose the connection terminals of the active surface of the electronic component (210) to obtain a semi-finished product.

2. The method for fabricating an embedded packaging substrate according to claim 1, characterized in that, The provision of a support plate (200) includes: A support plate (200) is provided, the support plate (200) having at least one flat surface; An adhesive zone is machined on the flat surface of the bearing plate (200); The electronic component (210) is mounted in the adhesive area of ​​the carrier plate (200).

3. The method for fabricating an embedded packaging substrate according to claim 2, characterized in that, The process of machining an adhesive area on the flat surface of the bearing plate (200) includes: Adhesive (201) is applied to the entire flat surface of the support plate (200); Alternatively, adhesive (201) may be applied to a local area of ​​the flat surface of the carrier plate (200), the location of which is adapted to the mounting position of the electronic component (210).

4. The method for fabricating an embedded packaging substrate according to claim 1, characterized in that, The encapsulation material (300) is a pure resin sheet. The process of laminating and pressing the base plate (100), the encapsulation material (300), and the carrier plate (200) includes: The pure resin material sheets are stacked on the base plate (100); The carrier plate (200) is stacked on the pure resin material sheet, wherein the side of the carrier plate (200) on which the electronic component (210) is attached faces the pure resin material sheet; The stacked base plate (100), the pure resin material sheet, and the support plate (200) are pressed together.

5. The method for fabricating an embedded packaging substrate according to any one of claims 1 to 4, characterized in that, After removing the support plate (200), the method further includes: The semi-finished product is perforated to expose the first through-hole post (120); The semi-finished product is electroplated to obtain the outermost circuit (130) of the finished product. The outermost circuit (130) of the finished product is connected to the connection terminal of the first through hole post (120) and the active surface of the electronic component (210).

6. The method for fabricating an embedded packaging substrate according to claim 5, characterized in that, The electroplating treatment of the semi-finished product includes: Process the first seed layer onto the semi-finished product; A first photosensitive masking film is processed on the first seed layer to obtain a circuit pattern corresponding to the outermost circuit (130) of the finished product; The semi-finished product is electroplated to form the outermost layer of the finished product (130) through the circuit pattern; Remove the first photosensitive masking film and etch the first seed layer.

7. The method for fabricating an embedded packaging substrate according to claim 5, characterized in that, The electroplating treatment of the semi-finished product includes: Process the first seed layer onto the semi-finished product; The semi-finished product is subjected to whole-plate electroplating to form an electroplated metal layer on the first seed layer; A second photosensitive masking film is processed on the electroplated metal layer to obtain a circuit pattern corresponding to the outermost circuit (130) of the finished product; The electroplated metal layer is etched to form the outermost circuit (130) of the finished product through the circuit pattern; Remove the second photosensitive masking film.

8. The method for fabricating an embedded packaging substrate according to claim 5, characterized in that, The outermost layer of the finished product (130) is provided with pads. After obtaining the outermost layer of the finished product (130), the method further includes: A solder resist layer (140) is processed on the semi-finished product, and the solder resist layer (140) is provided with solder resist openings corresponding to the solder pads; The semi-finished product is subjected to metal surface treatment to form a surface treatment layer (150) corresponding to the position of the solder resist opening.

9. The method for fabricating an embedded packaging substrate according to claim 1, characterized in that, The base plate (100) has multiple layers of wiring, and adjacent layers of wiring are connected by a second through-hole post (160).

10. A packaging substrate, characterized in that, It is prepared by the embedding packaging substrate fabrication method according to any one of claims 1 to 9.

Images