Semiconductor processing tool and methods of use thereof

Abstract

A process tool includes a chamber housing defined by a process chamber and a wafer chuck structure disposed within the process chamber. The wafer chuck structure is configured to hold a wafer during a manufacturing process. The wafer chuck includes a lower portion and an upper portion disposed above the lower portion. The lower portion includes a plurality of grooves extending from a topmost surface toward a bottommost surface of the lower portion. The upper portion includes a plurality of openings that are holes extending completely through the upper portion and directly over the grooves of the lower portion. The plurality of openings directly overlie each of the grooves. Further, a cooling gas conduit is coupled to the grooves of the lower portion of the wafer chuck structure, and a cooling gas source is coupled to the cooling gas conduit.

Description

Technical Field

[0001] The embodiments of the present invention relate to a semiconductor processing machine and its method of use, and more particularly to a wafer chuck structure with holes in the upper surface to improve temperature uniformity and its method of use. Background Technology

[0002] Semiconductor device manufacturing is a process used to create integrated circuits found in everyday electronic devices. The manufacturing process is a multi-step sequence of steps including deposition, photolithography, and chemical processing, during which electronic circuits are gradually created on a wafer. Many integrated circuits are formed simultaneously on a semiconductor wafer, which then undergoes a dicing process to cut it into generally uniform chips. Summary of the Invention

[0003] According to some embodiments, a processing apparatus includes a chamber housing defining a processing chamber and a wafer chuck structure disposed within the processing chamber and configured to hold a wafer during a manufacturing process. The wafer chuck structure includes a lower portion, an upper portion, cooling gas conduits, and a cooling gas source. The lower portion includes a plurality of grooves extending from a topmost surface of the lower portion toward a bottommost surface of the lower portion, wherein the bottommost surface of the grooves is defined by an intermediate surface of the lower portion of the wafer chuck, the intermediate surface being disposed between the topmost and bottommost surfaces of the lower portion of the wafer chuck. The upper portion is disposed above the lower portion and includes a plurality of openings that extend completely through the upper portion of the wafer chuck and directly overlay the grooves of the lower portion of the wafer chuck. Cooling gas conduits are coupled to the grooves of the lower portion of the wafer chuck structure. A cooling gas source is coupled to the cooling gas conduit and configured to guide cooling gas toward the top of the wafer chuck structure during the manufacturing process through the cooling gas conduit, the grooves in the lower portion, and the openings in the upper portion. The openings in the upper portion of the wafer chuck structure are orifices, such that the plurality of openings in the upper portion of the wafer chuck structure directly cover each of the grooves in the lower portion of the wafer chuck structure.

[0004] According to some embodiments, a processing apparatus includes a chamber housing defining a processing chamber and a wafer chuck structure disposed within the processing chamber and configured to hold a wafer during a manufacturing process, wherein the wafer chuck structure includes a lower portion, an upper portion, and a cooling gas source. The lower portion includes a first material and includes a plurality of trenches extending from a topmost surface of the lower portion toward a bottommost surface of the lower portion. The upper portion is disposed above the lower portion, includes a second material different from the first material, and includes a plurality of orifice-like openings extending completely through the upper portion and directly overlying the trenches of the upper portion. The cooling gas source is coupled to the lower portion and configured to guide cooling gas at a specified temperature toward the upper portion of the wafer chuck structure through the trenches and orifice-like openings of the wafer chuck structure. The upper portion includes a first number of the openings, and the lower portion includes a second number of the trenches, wherein the first number is greater than the second number.

[0005] According to some embodiments, a method includes forming a layer over a wafer; forming a mask structure over the layer; conveying the wafer onto a wafer chuck structure disposed within a processing chamber, wherein the wafer chuck structure includes a lower portion having a plurality of trenches coupled to cooling gas conduits, the wafer chuck structure including an upper portion disposed over the lower portion and including a plurality of orifice openings extending completely through the upper portion and directly overlying the trenches of the lower portion; activating the wafer chuck structure during processing to electrostatically hold the wafer; activating a cooling gas source such that cooling gas flows through the cooling gas conduits, the trenches of the lower portion of the wafer chuck structure, and the orifice openings of the upper portion of the wafer chuck structure, thereby uniformly distributing the cooling gas toward the back side of the wafer; and performing a removal process according to the mask structure to remove portions of the layer while activating the cooling gas source. Attached Figure Description

[0006] The following detailed description, taken in conjunction with the accompanying drawings, will best convey the various aspects of this disclosure. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 Cross-sectional views of some embodiments of a processing chamber including a wafer chuck structure having a perforated upper portion to allow cooling gas to be uniformly distributed onto the wafer disposed on the upper portion of the wafer chuck structure during processing steps are shown.

[0008] Figure 2 and Figure 3A top view showing some embodiments of a wafer chuck structure, the wafer chuck structure including a perforated upper portion located above a lower portion having a trench connected to a hole.

[0009] Figure 4 and Figure 5 Cross-sectional views of some other embodiments of a wafer chuck structure are shown, the wafer chuck structure having a perforated upper portion to allow cooling gas to be uniformly distributed onto the wafer disposed on the upper portion of the wafer chuck structure during processing steps.

[0010] Figure 6A and Figure 6B A top view showing some other embodiments of the wafer chuck structure.

[0011] Figures 7 to 12 Various views illustrating some embodiments of a method for patterning layers on a wafer are shown, wherein the wafer is disposed on a wafer chuck structure having an upper portion with holes to allow cooling gas to be uniformly distributed to the wafer, thereby improving the uniformity of layer patterning on the wafer.

[0012] Figure 13 Showing with Figures 7 to 12 The flowcharts show some embodiments of the methods shown.

[0013] Explanation of icon numbers

[0014] 100, 400, 500, 700, 800, 900A, 900B, 900C, 1100, 1200: Sectional views;

[0015] 101: Chip chuck structure;

[0016] 102: Chamber shell;

[0017] 104: Lower part;

[0018] 104b: Bottom surface;

[0019] 104m: Intermediate surface;

[0020] 104t, 106t: Topmost surface;

[0021] 106: Upper part;

[0022] 106p: Peak;

[0023] 106v: Tanibe;

[0024] 108: Chip;

[0025] 110: Trench;

[0026] 112: Perforated opening;

[0027] 112a: lower part;

[0028] 112b: Upper part;

[0029] 116: Cooling gas pipeline;

[0030] 116a: First entrance;

[0031] 116b: Second entrance;

[0032] 118: Cooling gas source;

[0033] 120: Electrostatic chuck circuit;

[0034] 200, 300, 600A, 600B, 1000: Top view;

[0035] 502: Layer;

[0036] 504: Mask structure;

[0037] 702: Opening;

[0038] 802: Water source;

[0039] 804: Water pipe;

[0040] 902: Cooling gas;

[0041] 904: Removal process;

[0042] 1002: Legend;

[0043] 1004: Zone 1;

[0044] 1006: Second District;

[0045] 1008: Third District;

[0046] 1102: Conductive structure;

[0047] 1300: Method;

[0048] 1302, 1304, 1306, 1308, 1310, 1312, 1314: Actions;

[0049] d1: First distance;

[0050] d2: Second distance;

[0051] d3: Third distance;

[0052] d4: Fourth distance;

[0053] d5: Fifth distance;

[0054] d6: Sixth distance. Detailed Implementation

[0055] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features such that the first and second features are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0056] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein to describe the relationship between one element or feature and another element(s) shown in the diagrams. In addition to the orientations depicted in the diagrams, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein shall be interpreted accordingly.

[0057] Semiconductor devices typically comprise multiple layers (e.g., dielectric, semiconductor, and / or conductive layers / features) disposed above a substrate. These layers are formed through various deposition, photolithography, and removal processes. Temperature conditions during processing steps (e.g., deposition and removal processes) affect the control and predictability of these steps. For example, the etching rate (e.g., the amount of material per pass) can be primarily dependent on temperature conditions because etching processes are based on chemical reactions and / or atomic bombardment. Both chemical reactions and atomic bombardment can be accelerated by temperature. In some cases, conduits are integrated into the wafer chuck structure so that, during processing steps, cooling gases can be directed toward the bottom of the wafer on the wafer chuck structure to control the temperature of the wafer and the layers disposed on it.

[0058] For example, from a top perspective view, the wafer chuck structure may include trenches arranged in a ring structure, with conduits for cooling gas coupled to the trenches. Therefore, during the removal step, cooling gas is guided, for example, through the trenches of the wafer chuck structure to control the temperature of the wafer and layers to be patterned in the removal step. When the temperature of the layer to be patterned is more uniform throughout the wafer, the etching rate of the layer removal process is also more uniform. Subsequently, multiple portions of the layers on the wafer can be reliably patterned simultaneously.

[0059] However, when the trenches in the wafer chuck structure are annular, the uniformity of cooling gas distribution to the wafer and layers may be poor. For example, the region of the wafer and layers directly above the trench may be cooler than the region not directly above the trench. Therefore, the etching rate in the cooler regions of the layer may be faster or slower than the warmer regions. Due to the different etching rates, the resulting cavities in the layer may therefore have different depths.

[0060] Various embodiments of this disclosure relate to a wafer chuck including a lower portion having a plurality of trenches in an annular structure and an upper portion, the upper portion being disposed above the lower portion and having a plurality of aperture-like openings disposed above the trenches of the lower portion. During the removal process, the aperture-like openings provide a more uniform distribution of cooling gas throughout the wafer and across various layers on the wafer to reduce variability in etching rate and thus improve control and uniformity of etching depth throughout the patterned layer region.

[0061] Figure 1 A cross-sectional view 100 shows some embodiments of a processing unit, which includes a wafer chuck configured to hold a wafer during a removal process and includes trenches and orifice openings for allowing cooling gas to enter during the processing steps.

[0062] Figure 1 The processing unit includes a chamber housing 102 defining a processing chamber. In some embodiments, the processing chamber is configured for removal processes (e.g., etching), deposition processes, or similar processes. For example, in some embodiments where the processing chamber is configured for an etching process, a plasma gas source and corresponding circuitry (not shown) may be disposed within the chamber housing 102. In some embodiments, a wafer chuck structure 101 is disposed near the bottom of the processing chamber and within the chamber housing 102. The wafer chuck structure 101 is configured to hold a wafer 108 during manufacturing processes performed within the processing chamber.

[0063] In some embodiments, the wafer chuck structure 101 is an electrostatic chuck (ESC) and coupled to ESC circuitry 120. In some embodiments, ESC circuitry 120 is configured to "ON" the wafer chuck structure 101 to hold the wafer 108 using electrostatic force. For example, in some embodiments, the wafer chuck structure 101 includes electrostatic contacts that are "ON" by applying a voltage to the electrostatic contacts using ESC circuitry 120. In some embodiments, the electrostatic contacts provide an electrostatic force to hold the wafer 108 onto the wafer chuck structure 101.

[0064] In some embodiments, the wafer chuck structure 101 includes a lower portion 104 and an upper portion 106 disposed above the lower portion 104. In some embodiments, the lower portion 104 includes a first material, and the upper portion 106 includes a second material different from the first material. For example, in some embodiments, the lower portion 104 includes a metal, such as aluminum or the like. In some embodiments, the upper portion 106 includes a ceramic material or some other material different from the lower portion 104. In some embodiments, a wafer 108 is disposed directly above the upper portion 106 of the wafer chuck structure 101.

[0065] In some embodiments, the lower portion 104 of the wafer chuck structure 101 includes a plurality of trenches 110 extending from the topmost surface 104t of the lower portion 104 toward the bottommost surface 104b of the wafer chuck structure 101. In some embodiments, the trenches 110 have a lower surface defined by an intermediate surface 104m of the lower portion 104 of the wafer chuck structure 101, wherein the intermediate surface 104m is disposed between the topmost surface 104t and the bottommost surface 104b of the lower portion 104 of the wafer chuck structure 101. In some embodiments, the trenches 110 are coupled to a cooling gas conduit 116, which is coupled to a cooling gas source 118. In some embodiments, the cooling gas source 118 is disposed outside the chamber housing 102, while in some other embodiments, the cooling gas source 118 may be disposed inside the chamber housing 102. In some embodiments, as seen in cross-sectional view 100, the cooling gas conduit 116 is coupled only to some of the trenches 110, as can be seen from other cross-sectional perspective views, where the cooling gas conduit 116 is coupled to other portions of the trenches 110. In other embodiments, some of the trenches 110 in cross-sectional view 100 may also be coupled to each other. In other words, in some embodiments, each trench 110 is coupled to the cooling gas source 118.

[0066] In some embodiments, the upper portion 106 of the wafer chuck structure 101 includes a plurality of aperture-like openings 112 extending completely through the upper portion 106. In some embodiments, the aperture-like openings 112 of the upper portion 106 directly overlap the grooves 110 of the lower portion 104. (As will be...) Figure 2 As described in more detail below, in some embodiments, the groove 110 of the lower portion 104 may be a continuously connected annular structure, while the perforated opening 112 of the upper portion 106 is a small opening. Therefore, in some embodiments, the perforated opening 112 has a different pattern than the groove 110. In some embodiments, a plurality of perforated openings 112 directly cover the same groove 110.

[0067] In some embodiments, during the manufacturing process, a cooling gas source 118 is configured to supply cooling gas at a specified temperature through cooling gas conduits 116, trenches 110, and apertures 112 to guide the cooling gas toward the back side of the wafer 108. The cooling gas helps control and improve the reliability of the manufacturing process. For example, in some embodiments, if an etching process is performed to remove portions of the wafer 108 and / or layers (not shown) on it, the etching rate of the etching process depends on the temperature of the wafer 108 and / or the layers on it. Therefore, the cooling gas source 118 can be circuitically controlled to supply cooling gas to the wafer 108 and control the etching process. In some embodiments, due to the numerous apertures 112 disposed beneath the wafer 108, the cooling gas is more uniformly distributed on the wafer 108, improving the control and reliability of the manufacturing process.

[0068] Figure 2 A top view 200 showing some embodiments of an upper portion corresponding to a wafer chuck, including a perforated opening.

[0069] As illustrated in top view 200, in some embodiments, the upper portion 106 of the wafer chuck structure 101 includes a plurality of apertures 112. In some embodiments, the apertures 112 are circular as viewed from top view 200. In some other embodiments, the apertures 112 are square, elliptical, rhomboid, or some other shape as viewed from top view 200. In some embodiments, the apertures 112 are evenly distributed in the lower portion of the wafer chuck structure 101. Figure 1 Directly above groove 110 of (104). Figure 2 In the diagram, the groove 110 is shown in dashed lines because the groove 110 is located behind the upper portion 106 of the wafer chuck structure 101.

[0070] Figure 3 A top view 300 showing some embodiments of a lower portion of a wafer chuck, including grooves.

[0071] In some embodiments, the trenches 110 of the lower portion 104 of the wafer chuck structure 101 are annular, wherein each trench 110 extends through a larger surface area of ​​the lower portion 104 of the wafer chuck structure 101. In some embodiments, each trench 110 is coupled to a cooling gas source ( Figure 1 118). In some embodiments, the trench 110 is wider than the aperture 112. In some embodiments, because the trench 110 of the lower portion 104 covers more than the upper portion of the wafer chuck structure 101 ( Figure 1 The perforated opening 112 of the larger wafer chuck structure 101 covers the surface area of ​​the lower portion 104, allowing cooling gas to be rapidly distributed through the trench 110 and then through the perforated opening 112 toward the wafer. Figure 1 108) are evenly distributed for use on wafers ( Figure 1 More uniform temperature control (108).

[0072] Figure 4 A cross-sectional view 400 shows some other embodiments of a wafer chuck structure, which includes an upper portion having an orifice-like opening coupled to a cooling gas conduit, wherein the upper surface of the wafer chuck structure is roughened.

[0073] In some embodiments, the topmost surface 106t of the upper portion 106 of the wafer chuck structure 101 is rough, which may be described as including a plurality of peaks 106p and a plurality of valleys 106v, wherein the peaks 106p are disposed above the valleys 106v. In some embodiments, the average surface roughness of the topmost surface 106t of the upper portion 106 of the wafer chuck structure 101 is in the range of, for example, about 1 micrometer to about 100 micrometers. In some embodiments, the wafer 108 directly contacts the peaks 106p of the upper portion 106 of the wafer chuck structure 101, while the wafer 108 is spaced apart from the valleys 106v of the upper portion 106 of the wafer chuck structure 101. In some embodiments, the wafer 108 is spaced apart from the region of the upper portion 106 of the wafer chuck structure 101 by a fourth distance d4. In some embodiments, the fourth distance d4 is in the range of, for example, about 1 nanometer to about 1 millimeter.

[0074] In some embodiments, the topmost surface 106t is roughened to allow cooling gas to escape through the space between the wafer 108 and the valley 106v during the manufacturing process. As the cooling gas escapes through the space between the wafer 108 and the valley 106v during the manufacturing process, new cooling gas at a specified temperature can be directed toward the wafer 108. Therefore, the roughness of the topmost surface 106t of the wafer chuck structure 101 helps to continuously direct cooling gas toward the wafer 108 at a specified temperature to control the manufacturing process. Furthermore, in some embodiments, the cooling gas flow pressure generates a force between the wafer 108 and the wafer chuck structure 101, which helps to keep the wafer 108 on the wafer chuck structure 101 during the manufacturing process.

[0075] In some embodiments, the trench 110 has a width equal to a first distance d1. In some embodiments, the first distance d1 is in the range of, for example, about 1 mm to about 5 mm. In some embodiments, the aperture 112 has a width equal to a second distance d2. In some embodiments, the second distance d2 of the aperture 112 is smaller than the first distance d1 of the trench 110. In some embodiments, the second distance d2 is in the range of, for example, about 200 micrometers to about 1000 micrometers. In some other embodiments, the second distance d2 may be in the range of, for example, about 100 micrometers to about 500 micrometers. In some embodiments, cooling gas is more uniformly distributed onto the wafer 108 through the aperture 112 because the second distance d2 of the aperture 112 is smaller than the first distance d1 of the trench 110.

[0076] In some embodiments, the cooling gas conduit 116 is coupled to the trench 110 via the bottom or side of the lower portion 104 of the wafer chuck structure 101. In some embodiments, the cooling gas conduit 116 is coupled to the trench 110 at two locations, such as... Figure 4 The cross-sectional view 400 illustrates this. In some embodiments, the two inlets for the cooling gas conduit 116 into the trench 110 allow the cooling gas to be rapidly distributed throughout the trench 110 at a specified temperature. Then, in some embodiments, the cooling gas can be uniformly distributed toward the wafer 108 through a plurality of orifice openings 112. In some embodiments, the cooling gas conduit 116 has a width equal to a third distance d3. In some embodiments, the third distance d3 is in the range, for example, between about 100 mm and about 500 mm.

[0077] Figure 5 Cross-sectional view 500 shows some other embodiments of a wafer chuck structure including an upper portion with a hole-like opening, wherein the hole has different widths at various heights.

[0078] In some embodiments, the aperture 112 of the upper portion 106 of the wafer chuck structure 101 has two different widths, the width of which varies depending on where the width of the aperture 112 is measured. For example, in some embodiments, the aperture 112 has a lower portion 112a and an upper portion 112b, the lower portion 112a having a width equal to a second distance d2 and the upper portion 112b having a width equal to a fifth distance d5. In some embodiments, the fifth distance d5 is greater than the first distance d1. In some embodiments, the fifth distance d5 may be in the range of, for example, about 100 mm to about 500 mm. In some embodiments, the lower portion 112a is disposed below the upper portion 112b. In some other embodiments, the lower portion 112a (e.g., the narrower portion) is disposed above the upper portion 112b (e.g., the wider portion).

[0079] Furthermore, in some embodiments, layer 502 is disposed above wafer 108. In some embodiments, layer 502 may include a dielectric material, a metallic material, a semiconductor material, or some other suitable material. In some embodiments, mask structure 504 may be disposed above layer 502. In some embodiments, the cooling gas is also configured to control the temperature of layer 502 during the etching process, such that portions of layer 502 can be removed according to mask structure 504 at a predictable and controllable etching rate.

[0080] Figure 6A A top view 600A showing some other embodiments of the wafer chuck structure, including the upper portion of the perforated opening coupled to a cooling gas conduit.

[0081] In other embodiments, the groove 110 may be an annular structure, a rectangular structure, a curved structure, or a combination of other configurations. In some embodiments, for example Figure 5 The grooves 110 in the cross-sectional view 500 are all continuously connected to each other. In other words, in some embodiments, the lower portion of the wafer chuck structure 101 ( Figure 1 104) may actually include a single trench 110. However, multiple aperture-like openings 112 directly cover the respective trenches 110 of the wafer chuck structure 101. Furthermore, in some embodiments, the lower portion ( Figure 1 The first surface region of the upper portion 104 includes a trench 110, and the second surface region of the upper portion 106 includes a perforated opening 112. In some embodiments, the first surface region is larger than the second surface region, such that cooling gas guided through the perforated opening 112 can be directed toward the wafer. Figure 1 The 108) is more evenly distributed for temperature control.

[0082] Figure 6B A top view 600B showing some other embodiments of the wafer chuck structure, including the upper portion of the orifice-like opening 112 coupled to a cooling gas conduit.

[0083] The perforated opening 112 is in Figure 6B The circle is shown in shaded form. In some other embodiments, there may be substantially more perforated openings 112 near the outer edge of the upper portion 106 of the wafer chuck structure 101 than towards the center of the upper portion 106 of the chuck wafer structure 101. In some embodiments, this configuration can improve the wafer chuck structure 101's ability to hold the wafer (e.g., Figure 1 The ability of 108). It should be understood that, in Figure 6B The top view omits the grooves behind the perforated opening 112 and the upper portion 106 of the wafer chuck structure 101. Figure 1 The description of 110).

[0084] Figures 7 to 12 Various views 700 to 1200 illustrate some embodiments of a method for setting a wafer onto a wafer chuck structure, the wafer chuck structure including aperture-like openings for distributing cooling gas toward the wafer to perform etching processes and improve etching rate uniformity across the entire wafer. Although Figures 7 to 12 It's about describing a method, but it should be understood that... Figures 7 to 12 The structures disclosed herein are not limited to this method, but can be used independently of the method.

[0085] like Figure 7 As illustrated in cross-sectional view 700, a wafer 108 is provided. In some embodiments, wafer 108 may include any type of semiconductor body (e.g., silicon / CMOS bulk, germanium, SiGe, SOI, etc.), such as a semiconductor substrate or one or more dies on a wafer, and any other type of semiconductor and / or epitaxial layers formed thereon and / or otherwise associated with thereto. In some embodiments, layer 502 is formed over wafer 108 by means of, for example, deposition processes (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), sputtering, etc.). In some embodiments, layer 502 includes a dielectric material, such as a nitride (e.g., silicon nitride, silicon oxynitride), a carbide (e.g., silicon carbide), an oxide (e.g., silicon oxide), borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), a low-k oxide (e.g., carbon-doped oxide, SiCOH), or the like. In some other embodiments, layer 502 may include a metallic material, such as aluminum, copper, titanium, tungsten, or some other suitable metallic material. In still other embodiments, layer 502 may include a semiconductor material, such as silicon, germanium, or the like.

[0086] In some embodiments, a mask structure 504 may be formed over layer 502. In some embodiments, the mask structure 504 includes an opening 702 that exposes a portion of layer 502. In some embodiments, photolithography and removal (e.g., etching) processes may be used to form the mask structure 504. In some embodiments, the mask structure 504 includes a photoresist material or a hard mask material.

[0087] like Figure 8As illustrated in cross-sectional view 800, in some embodiments, a wafer 108 is fed into a processing chamber defined by a chamber housing 102. In some embodiments, the wafer 108 is fed onto a wafer chuck structure 101. In some embodiments, the wafer chuck structure 101 includes a lower portion 104 and an upper portion 106 disposed above the lower portion 104. In some embodiments, the lower portion 104 includes a groove 110 coupled to a cooling gas conduit 116. In some embodiments, the upper portion 106 includes a perforated opening 112 disposed directly above the groove 110 of the lower portion 104. In some embodiments, the cooling gas conduit 116 is coupled to a cooling gas source 118. In some embodiments, a water source 802 is coupled to the wafer chuck structure 101 via a water pipe 804 and configured to use cold water to cool the lower portion 104 of the wafer chuck structure 101 during the manufacturing process.

[0088] In some embodiments, wafer 108 is aligned with and positioned above wafer chuck structure 101 via a transport circuit (not shown). In some embodiments, wafer chuck structure 101 is coupled to electrostatic chuck (ESC) circuit 120. In some embodiments, ESC circuit 120 is "turned on" to apply voltage to electrostatic contacts on wafer chuck structure 101, which is configured to hold wafer 108 by electrostatic force.

[0089] Figure 9A , Figure 9B as well as Figure 9C Cross-sectional views 900A, 900B, and 900C are shown respectively, illustrating the removal process in which cooling gas 902 is guided through the wafer chuck structure 101 and toward the wafer 108 to control the temperature of the wafer 108 and thus also control the removal process. In some embodiments, Figure 9A The first time of the removal process is shown. Figure 9B The second time of the removal process is shown after the first time. Figure 9C The third time in the removal process is shown, following the first and second time points. It should be understood that... Figure 9A , Figure 9B as well as Figure 9C A single removal process is shown, but at different times during the removal process, it should be understood how the cooling gas 902 is distributed through the wafer chuck structure 101.

[0090] like Figure 9AAs illustrated in cross-sectional view 900A, in some embodiments, a cooling gas source 118 is "connected" to deliver cooling gas 902 at a specified temperature through a cooling gas conduit 116 and trenches 110 and orifice openings 112 of the wafer chuck structure 101. In some embodiments, the cooling gas conduit 116 has two inlet points into the trench 110. In some embodiments, a first inlet 116a is located near a trench 110 in an outer region near the lower portion 104 of the wafer chuck structure 101, and a second inlet 116b is located near a trench 110 near the center of the lower portion 104 of the wafer chuck structure 101. In some embodiments, the cooling gas 902 is helium or some other suitable inert gas. In some embodiments, the pressure of the cooling gas 902 on the wafer 108 helps keep the wafer 108 attached to the wafer chuck structure 101 and the electrostatic contacts.

[0091] In some embodiments, due to the wider trench 110, the cooling gas 902 is rapidly distributed through the trench 110, and due to the narrower orifice 112, the cooling gas 902 is evenly distributed toward the wafer through the orifice 112. In some embodiments, the cooling gas 902 is guided toward the wafer 108 and then flows outward and into a processing chamber away from the wafer 108 and the wafer chuck structure 101. In some embodiments, the cooling gas 902 passes through the upper portion 106 of the wafer 108 and the valley portion ( Figure 4 The cooling gas 902 can escape from the space between the wafer 108 and the wafer chuck structure 101. Therefore, new cooling gas 902 can be continuously pumped toward the wafer 108 to expose the wafer 108 to the cooling gas 902 at a specified temperature, thereby controlling the temperature of the wafer 108 and the layer 502.

[0092] In some embodiments, a water source 802 is also "connected" to deliver cooling water at a specified temperature into conduits in the lower portion 104 of the wafer chuck structure 101. The cooling water from the water source 802 controls the temperature of the lower portion 104 of the wafer chuck structure 101, thereby also controlling the temperature of the cooling gas 902 flowing through the lower portion 104 of the wafer chuck structure 101. For example, in some embodiments, the lower portion 104 of the wafer comprises a metal that can be readily heated. Therefore, in some embodiments, the water source 802 can lower the temperature of the lower portion 104 so that the temperature of the cooling gas 902 does not increase significantly as it flows through the trenches 110 of the lower portion 104.

[0093] In some embodiments, removal process 904 is performed when ESC circuit 120, cooling gas source 118, and water source 802 are "connected". In some embodiments, removal process 904 includes a wet etching process or a dry etching process. For example, in some embodiments, removal process 904 is a dry etching process that uses plasma gas to remove portions of layer 502 not covered by mask structure 504. In some embodiments, the etching rate of removal process 904 (e.g., the amount of material removed each time) is controlled by the temperature of layer 502, which is controlled by cooling gas 902. In some embodiments, because the aperture openings 112 of the upper portion 106 of wafer chuck structure 101 are small openings, with multiple aperture openings 112 disposed above each trench 110, cooling gas 902 is more uniformly distributed to wafer 108 to improve the temperature uniformity of layer 502 and thus improve the temperature uniformity of the etching rate of removal process 904.

[0094] like Figure 9B As illustrated in cross-sectional view 900B, in some embodiments, after a second time interval of removal process 904, a portion of layer 502 is removed according to the opening 702 of mask structure 504. In some embodiments, after the second time interval, removal process 904 removes a first number of layers 502 disposed below the opening 702 of mask structure 504. In some embodiments, the “first number” of layers 502 removed is quantified by the etching depth measured between the topmost surface of layer 502 and the new surface of layer 502 defined by removal process 904. In some embodiments, the etching depth after the second time interval is equal to a fifth distance d5. In some embodiments, the fifth distance d5 may vary throughout layer 502 due to variations in the temperature of layer 502 and therefore the etching rate of removal process 904. However, the aperture-like openings 112 distributed throughout the upper portion 106 of wafer chuck structure 101 significantly reduce the variation in the fifth distance d5.

[0095] The etching rate of removal process 904 is affected by the temperature of layer 502. For example, in some embodiments, layer 502 may include silicon nitride, which can be removed by removal process 904 using an exothermic reaction. For exothermic reactions, the higher the temperature of layer 502, the slower the etching rate of removal process 904, and therefore the longer it takes to remove the fifth distance d5 of layer 502. Therefore, when layer 502 includes a material that can be removed by an exothermic reaction, the etching rate of removal process 904 can be increased (e.g., accelerated) when cooling gas 902 is used to lower the temperature of layer 502. In some other embodiments, layer 502 may include silicon dioxide, which can be removed by removal process 904 using an endothermic reaction. For endothermic reactions, the higher the temperature of layer 502, the faster the etching rate of removal process 904, and therefore the faster it takes to remove the fifth distance d5 of layer 502. However, in some cases, the etching rate may be too fast and uncontrollable. Therefore, when layer 502 includes a material that can be removed by an endothermic reaction, the etching rate of layer 502 can be slowed down to increase the controllability of the removal process 904.

[0096] Therefore, the cooling gas 902 is uniformly distributed toward the wafer 108 and layer 502 to accelerate and / or slow down the etching rate of the removal process, thereby improving the uniformity of the fifth distance d5 throughout the wafer 108. In some other embodiments, the cooling gas 902 and the wafer chuck structure 101 can be used to control the temperature of the wafer 108 and / or layer 502 during deposition processes, thermal oxidation processes, or other suitable manufacturing processes, thereby improving the controllability of the thickness of the layer to be deposited, for example, on the wafer 108.

[0097] like Figure 9C As shown in the cross-sectional view 900C, after the third time of the removal process 904, the depth of the removed portion of layer 502 can be increased from the fifth distance ( Figure 9B The distance d5 is increased to a sixth distance d6. In some embodiments, since the etching rate of the removal process 904 is controllable by the distribution of cooling gas 902, an etch stop layer is not required within layer 502. Therefore, in some embodiments, time (e.g., the step of forming an etch stop layer) and material (e.g., the etch stop layer) are saved because the cooling gas 902 and the wafer chuck structure 101 can uniformly control the temperature of layer 502, which in turn controls the depth of layer 502 to be removed by the removal process 904 (e.g., the sixth distance d6).

[0098] Figure 10 The complete removal process is shown. Figure 9C Top view 1000 of some embodiments of layer 502 following layer 904, wherein different portions of layer 502 have different patterns to show the removal process based on the etching depth defined by the sixth distance d6. Figure 9CThe uniformity of 904). The variation in etching depth defined by the sixth distance d6 depends at least in part on the temperature of layer 502, which is affected by the cooling gas ( ) directed toward wafer 108. Figure 9C Distribution control (902). As illustrated in Figure 1002, in some embodiments, the first region 1004 of layer 502 has an etching depth (e.g., a sixth distance d6) within a range between a first value a and a second value b. In some embodiments, the second region 1006 of layer 502 has an etching depth (e.g., a sixth distance d6) within a range between a second value b and a third value c. In some embodiments, the third region 1008 of layer 502 has an etching depth (e.g., a sixth distance d6) within a range between a third value c and a fourth value d. This depends at least on the cooling gas ( Figure 9C The uniformity of the etching rate distribution (902) increases as the difference between the first value a and the fourth value d of the sixth distance d6 decreases. In some embodiments, the wafer chuck structure ( Figure 9C 101) of the pore-like opening ( Figure 9C 112) Increase cooling gas ( Figure 9C The uniformity of the 902) distribution reduces the difference between the first value a and the fourth value d of the sixth distance d6, allowing all regions of layer 502 to undergo the removal process. Figure 9C (904), while all regions of layer 502 have a significantly uniform etching depth.

[0099] like Figure 11 As shown in the cross-sectional view 1100, in some embodiments, after the removal process is completed ( Figure 9C After 904, you can start from Figure 9C The wafer 108 is removed from the processing chamber in the process. In some embodiments, the mask structure is then removed from layer 502. Figure 9C 504). In some embodiments, the mask structure ( Figure 9C The 504) is removed by an etching process (e.g., wet etching, dry etching). In some other embodiments, it can be removed while the wafer 108 is still located Figure 9C Removing the mask structure in the processing chamber ( Figure 9C (504).

[0100] like Figure 12 As shown in the cross-sectional view 1200, in some embodiments, the removal process ( Figure 9C(904) A conductive structure 1102 is formed within the openings of layer 502. In some embodiments, the conductive structure 1102 is formed by various steps of deposition (e.g., PVD, CVD, ALD, sputtering, etc.) and removal (e.g., etching, chemical mechanical planarization) processes. In some embodiments, the conductive structure 1102 comprises copper, aluminum, tungsten, titanium, cobalt, tantalum, or some other suitable conductive material. In some other embodiments, structures other than the conductive structure 1102 are formed in the openings of layer 502, such as dielectric isolation structures, semiconductor materials, or some other suitable features.

[0101] In some embodiments, due to the opening of layer 502, at least due to the cooling gas toward wafer 108 ( Figure 9C The 902) distribution results in a generally uniform etching depth (e.g. Figure 9C The sixth distance d6), therefore the conductive structure 1102 formed above layer 502 has a substantially the same structure (e.g., depth) throughout the wafer 108, so that multiple chips with the same structure can be formed on the wafer 108 at the same time.

[0102] Figure 13 Showing with Figures 7 to 12 The flowcharts show some embodiments of method 1300 corresponding to the method shown.

[0103] Although method 1300 is shown and described below as a series of actions or events, it should be understood that the order in which such actions or events are shown should not be interpreted in a limiting sense. For example, some actions may occur in a different order and / or simultaneously with other actions or events, in addition to those shown and / or described herein. Furthermore, not all shown actions may be required to implement one or more aspects or embodiments described herein. Moreover, one or more of the actions depicted herein may be performed in one or more separate actions and / or phases.

[0104] At action 1302, a wafer chuck structure is provided in the processing chamber. The wafer chuck structure includes a lower portion having multiple trenches coupled to cooling gas conduits. The wafer chuck structure also includes an upper portion disposed above the lower portion and including multiple orifice-like openings that extend completely through the upper portion and directly cover the trenches. Figure 1 and Figure 2 Cross-sectional view 100 and top view 200 are shown respectively, corresponding to some embodiments of action 1302.

[0105] At action 1304, a layer is formed on top of the wafer.

[0106] At action 1306, a mask structure is formed above the layer. Figure 7A cross-sectional view 700 is shown, corresponding to some embodiments of actions 1304 and 1306.

[0107] At action 1308, the wafer is transported into the processing chamber and onto the upper part of the wafer chuck structure.

[0108] At action 1310, the chip chuck structure is activated to electrostatically hold the chip during processing. Figure 8 Cross-sectional view 800 shows some embodiments corresponding to actions 1308 and 1310.

[0109] At action 1312, the cooling gas source is turned on so that the cooling gas flows through the cooling gas pipe, the groove of the lower part of the wafer chuck structure, and the hole-like opening of the upper part of the wafer chuck structure, thereby so that the cooling gas is evenly distributed on the back side of the wafer.

[0110] At action 1314, a removal process is performed to remove a portion of the layer according to the mask structure while the cooling gas source is turned on. Figures 9A to 9C Cross-sectional views 900A to 900C are shown corresponding to some embodiments of action 1314.

[0111] Therefore, this disclosure relates to a wafer chuck structure including a top surface with a perforated opening coupled to a cooling gas conduit and configured to uniformly distribute cooling gas to a wafer disposed above the wafer chuck structure during a removal process to improve the control and reliability of the removal process.

[0112] Therefore, in some embodiments, this disclosure relates to a processing apparatus including: a chamber housing defining a processing chamber; and a wafer chuck structure disposed within the processing chamber and configured to hold a wafer during a manufacturing process, wherein the wafer chuck structure includes: a lower portion including a plurality of grooves extending from a top surface of the lower portion toward a bottom surface of the lower portion, wherein the bottom surface of the grooves is defined by an intermediate surface of the lower portion of the wafer chuck, the intermediate surface being disposed between the top surface and the bottom surface of the wafer chuck; and an upper portion disposed above the lower portion and including a complete... Multiple openings extending through the upper portion of the wafer chuck and directly overlying the trenches of the lower portion of the wafer chuck; a cooling gas conduit coupled to the trenches of the lower portion of the wafer chuck structure; and a cooling gas source coupled to the cooling gas conduit, configured to guide cooling gas toward the top of the wafer chuck structure via the cooling gas conduit, the trenches of the lower portion, and the openings of the upper portion during the manufacturing process, wherein the openings of the upper portion of the wafer chuck structure are orifices, such that the multiple openings of the upper portion of the wafer chuck structure directly overlying each trench of the lower portion of the wafer chuck structure.

[0113] In some embodiments, the lower portion of the wafer chuck structure comprises a different material than the upper portion of the wafer chuck structure. In some embodiments, viewed from a top view of the wafer chuck structure, the grooves of the lower portion of the wafer chuck structure present a continuously connected annular structure. In some embodiments, the opening has a smaller width than the groove. In some embodiments, the wafer chuck structure is an electrostatic chuck configured to hold the wafer by electrostatic force during the manufacturing process. In some embodiments, the upper portion of the wafer chuck comprises a ceramic material. In some embodiments, the processing unit further includes a cold water source coupled to the lower portion of the wafer chuck structure and configured to deliver cooling water to the lower portion of the wafer chuck structure during the manufacturing process.

[0114] In other embodiments, this disclosure relates to a processing apparatus, including: a chamber housing defining a processing chamber; and a wafer chuck structure disposed within the processing chamber and configured to hold a wafer during a manufacturing process, wherein the wafer chuck structure includes: a lower portion comprising a first material and including a plurality of trenches extending from a top surface of the lower portion toward a bottom surface of the lower portion; an upper portion disposed above the lower portion, comprising a second material different from the first material, and including a plurality of orifice-like openings extending completely through the upper portion and directly overlying the trenches of the upper portion; and a cooling gas source coupled to the lower portion and configured to guide cooling gas at a specified temperature toward the upper portion of the wafer chuck structure through the trenches and openings of the wafer chuck structure, wherein the upper portion includes a first number of openings, the lower portion includes a second number of trenches, and the first number is greater than the second number.

[0115] In some embodiments, the first material is a metal and the second material is ceramic. In some embodiments, the topmost surface of the upper portion has a profile including peaks and valleys, wherein when a wafer is disposed on the upper portion of the wafer chuck structure, the wafer directly contacts the peaks of the topmost surface of the upper portion of the wafer chuck structure and is spaced apart from the valleys. In some embodiments, the wafer chuck structure is an electrostatic chuck. In some embodiments, the opening of the upper portion has multiple widths when measured at different locations along the thickness of the entire upper portion of the wafer chuck structure. In some embodiments, the opening has a smaller width than the trench. In some embodiments, the cooling gas source comprises helium.

[0116] In other embodiments, this disclosure relates to a method comprising: forming a layer over a wafer; forming a mask structure over the layer; conveying the wafer onto a wafer chuck structure disposed within a processing chamber, wherein the wafer chuck structure includes a lower portion having a plurality of trenches coupled to cooling gas conduits, wherein the wafer chuck structure includes an upper portion disposed over the lower portion and including a plurality of aperture openings extending completely through the upper portion and directly overlying the trenches of the lower portion; activating the wafer chuck structure to electrostatically hold the wafer during processing; activating a cooling gas source to allow cooling gas to flow through the cooling gas conduits, the trenches of the lower portion of the wafer chuck structure, and the aperture openings of the upper portion of the wafer chuck structure, thereby uniformly distributing the cooling gas toward the back side of the wafer; and performing a removal process to remove portions of the layer according to the mask structure while the cooling gas source is activated.

[0117] In some embodiments, the wafer is also held to the upper portion of the wafer chuck by pressure from the cooling gas. In some embodiments, the layer comprises a dielectric material, the removal process is an etching process, and the temperature of the cooling gas controls the etching rate of the etching process. In some embodiments, the topmost surface of the upper portion of the wafer chuck structure has a profile including peaks and valleys, the wafer directly contacts the peaks of the topmost surface of the upper portion of the wafer chuck structure and is spaced apart from the valleys, and the cooling gas travels between the valleys and the bottommost surface of the wafer. In some embodiments, the removal process is an etching process, and the etching rate of the etching process is controlled by the temperature of the cooling gas. In some embodiments, the aperture-like openings of the upper portion of the wafer chuck structure are disposed above each of the trenches of the lower portion of the wafer chuck structure.

[0118] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor processing machine, comprising: The chamber shell defines the processing chamber; as well as A wafer chuck structure disposed within the processing chamber and configured to hold a wafer during a manufacturing process, wherein the wafer chuck structure includes: The lower portion includes a plurality of grooves extending from the topmost surface of the lower portion toward the bottommost surface of the lower portion, wherein the bottommost surface of the grooves is defined by an intermediate surface of the lower portion of the wafer chuck, the intermediate surface being disposed between the topmost and bottommost surfaces of the lower portion of the wafer chuck, and the grooves having a first width at the topmost surface of the lower portion. An upper portion, disposed above the lower portion, includes multiple openings that extend completely through the upper portion of the wafer chuck and directly cover the grooves of the lower portion of the wafer chuck. The openings extend from the top surface of the wafer chuck structure to the top surface of the grooves. Each opening has a lower portion and an upper portion, the upper portion being adjacent to the top surface of the wafer chuck structure relative to the lower portion. The upper portion has a second width, and the lower portion has a third width, the second width being greater than the third width, and the first width being greater than the third width. The upper portion includes a rough, topmost surface comprising multiple peaks and multiple valleys, the peaks being disposed above the valleys. When a wafer is disposed on the upper portion of the wafer chuck structure, the wafer directly contacts the peaks of the rough, topmost surface of the upper portion of the wafer chuck structure and is spaced apart from the valleys. Cooling gas conduits are coupled to the trenches in the lower portion of the wafer chuck structure, and A cooling gas source, coupled to the cooling gas conduit, is configured to guide cooling gas toward the top of the wafer chuck structure during the manufacturing process through the cooling gas conduit, the trench in the lower portion, and the opening in the upper portion. The opening of the upper portion of the wafer chuck structure is a hole, such that the plurality of openings of the upper portion of the wafer chuck structure directly cover each of the grooves of the lower portion of the wafer chuck structure.

2. The semiconductor processing apparatus of claim 1, wherein the lower portion of the wafer chuck structure comprises a material different from the upper portion of the wafer chuck structure.

3. The semiconductor processing machine according to claim 1, wherein, viewed from a top view of the wafer chuck structure, the trenches of the lower portion of the wafer chuck structure present a continuously connected annular structure.

4. The semiconductor processing apparatus of claim 1, wherein the wafer chuck structure is an electrostatic chuck, the electrostatic chuck being configured to hold the wafer by electrostatic force during the manufacturing process.

5. The semiconductor processing apparatus of claim 1, wherein the upper portion of the wafer chuck comprises a ceramic material.

6. The semiconductor processing apparatus according to claim 1, further comprising: A cold water source is coupled to the lower portion of the wafer chuck structure and configured to deliver cooling water to the lower portion of the wafer chuck structure during the manufacturing process.

7. A semiconductor processing machine, comprising: The chamber shell defines the processing chamber; as well as A wafer chuck structure disposed within the processing chamber and configured to hold a wafer during a manufacturing process, wherein the wafer chuck structure includes: The lower portion includes a first material and includes a plurality of grooves extending from the topmost surface of the lower portion toward the bottommost surface of the lower portion, the grooves having a first width at the topmost surface of the lower portion. An upper portion, disposed above the lower portion, comprises a second material different from the first material and includes a plurality of aperture-like openings extending completely through the upper portion and directly covering the trench of the upper portion. The aperture-like openings extend from the top surface of the wafer chuck structure to the top surface of the trench. Each aperture-like opening has a lower portion and an upper portion, the upper portion being adjacent to the top surface of the wafer chuck structure relative to the lower portion. The upper portion has a second width, and the lower portion has a third width, the second width being greater than the third width, and the first width being greater than the third width. The upper portion includes a rough, topmost surface comprising a plurality of peaks and a plurality of valleys, the peaks being disposed above the valleys. When the wafer is disposed on the upper portion of the wafer chuck structure, the wafer directly contacts the peaks of the rough, topmost surface of the upper portion of the wafer chuck structure and is spaced apart from the valleys. A cooling gas source, coupled to the lower portion and configured to guide cooling gas at a specified temperature toward the upper portion of the wafer chuck structure via the trenches and orifices of the wafer chuck structure. The upper portion includes a first number of openings, the lower portion includes a second number of grooves, and the first number is greater than the second number.

8. The semiconductor processing apparatus according to claim 7, wherein the first material is a metal and the second material is ceramic.

9. The semiconductor processing apparatus of claim 7, wherein the average surface roughness of the roughest top surface of the upper portion of the wafer chuck structure is in the range of 1 micrometer to 100 micrometers.

10. The semiconductor processing machine according to claim 7, wherein the wafer chuck structure is an electrostatic chuck.

11. The semiconductor processing apparatus of claim 7, wherein the opening of the upper portion has a plurality of widths when measured at different locations along the thickness of the entire upper portion of the wafer chuck structure.

12. The semiconductor processing apparatus of claim 7, wherein the cooling gas source comprises helium.

13. A method for performing a semiconductor manufacturing process using a processing equipment, comprising: A layer is formed on top of the wafer; A mask structure is formed above the layer; The wafer is fed onto a wafer chuck structure disposed within a processing chamber, wherein the wafer chuck structure includes a lower portion having a plurality of trenches coupled to cooling gas conduits, the trenches having a first width at the topmost surface of the lower portion; the wafer chuck structure includes an upper portion disposed above the lower portion and including a plurality of orifice-like openings extending completely through the upper portion and directly overlying the trenches of the lower portion; the orifice-like openings extending from the top surface of the wafer chuck structure to the top surface of the trenches; the orifice-like openings having a lower portion and an upper portion, the upper portion... Compared to the lower portion adjacent to the top surface of the wafer chuck structure, the upper portion has a second width, the lower portion has a third width, the second width is greater than the third width, the first width is greater than the third width, the upper portion includes a rough top surface, the rough top surface includes a plurality of peaks and a plurality of valleys, the peaks are disposed above the valleys, when the wafer is disposed on the upper portion of the wafer chuck structure, the wafer directly contacts the peaks of the rough top surface of the upper portion of the wafer chuck structure and is spaced apart from the valleys; During processing, the wafer chuck structure is activated to electrostatically hold the wafer; The cooling gas source is turned on so that the cooling gas flows through the cooling gas pipe, the groove of the lower part of the wafer chuck structure and the hole-like opening of the upper part of the wafer chuck structure, thereby distributing the cooling gas evenly toward the back side of the wafer. as well as While the cooling gas source is switched on, a removal process is performed according to the mask structure to remove a portion of the layer.

14. The method of performing a semiconductor manufacturing process using a processing station according to claim 13, wherein the wafer is further held onto the upper portion of the wafer chuck by pressure from the cooling gas.

15. The method of semiconductor manufacturing process using a processing equipment according to claim 13, wherein the layer comprises a dielectric material, the removal process is an etching process, and the temperature of the cooling gas controls the etching rate of the etching process.

16. The method of semiconductor manufacturing process using a processing equipment according to claim 13, wherein the cooling gas travels between the valley and the bottommost surface of the wafer.

17. The method of semiconductor manufacturing process using a processing equipment according to claim 13, wherein the removal process is an etching process, and the etching rate of the etching process is controlled by the temperature of the cooling gas.

18. The method of performing a semiconductor manufacturing process using a processing station according to claim 13, wherein the aperture of the upper portion of the wafer chuck structure is disposed above each of the trenches of the lower portion of the wafer chuck structure.

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