Dynamic selection of cache coherency protocol in processor-based devices is provided

Abstract

Dynamic selection of cache coherency protocols provided in a processor-based device is disclosed. In this regard, the processor-based device includes a home PE and at least one snooper PE, as well as a central ordering point (COP). The COP dynamically selects, on a store-by-store basis, either a write-invalidate protocol or a write-update protocol as the cache coherency protocol to use for maintaining cache coherency for memory store operations by the home PE. This selection is made by the COP based on one or more protocol preference indicators that can be generated and provided by one or more of the home PE, the at least one snooper PE, and the COP itself. After selecting the cache coherency protocol to use, the COP sends a response message to each of the home PE and the at least one snooper PE indicating the selected cache coherency protocol.

Description

TECHNICAL FIELD

[0001] The technology of this disclosure relates to cache coherency protocols in processor-based devices, and more specifically to dynamic selection of cache coherency protocols. BACKGROUND

[0002] A processor-based device can include multiple processing elements (PEs) (e.g., processor cores as non-limiting examples), each providing one or more local caches for storing frequently accessed data. Because multiple PEs of a processor-based device can share memory resources (such as system memory), multiple copies of shared data read from a given memory address can simultaneously exist in system memory as well as in local caches of the PEs. Thus, to ensure that all of the PEs have a consistent view of the shared data, the processor-based device provides support for a cache coherency protocol to enable local changes to shared data within one PE to be propagated to other PEs. In this way, conflicts that can arise between the PEs due to inconsistencies between local copies of the shared data can be avoided.

[0003] Conventional cache coherency protocols include write-invalidate protocols and write-update protocols. Under a write-invalidate protocol, when one PE writes to a coherency granule (an aligned size of bytes of system memory on which cache coherency is managed), all copies of the coherency granule stored in local caches of other PEs are invalidated, where a dirty (i.e., modified) copy of the coherency granule is written to system memory prior to invalidation. PEs that lost a cached copy of the coherency granule in this way can subsequently reacquire a copy of the coherency granule via a memory load operation after completion of the memory store operation that triggered the invalidation. In contrast, under a write-update protocol, when one PE writes new data to a coherency granule, all other PEs receive a copy of the new data and use the new data to update their respective local copies of the coherency granule. Thus, write-update protocols do not require any local cached copies of the coherency granule to be invalidated, and thus do not require additional memory load operations to reacquire a lost coherency granule.

[0004] The relative efficiency of the write-invalidate protocol and the write-update protocol can depend on the circumstances of each PE operation. Generally, the write-invalidate protocol is more efficient than the write-update protocol in situations where many subsequent memory store operations to the same coherence granule are performed by the PE and the updated coherence granule is unlikely to be read by another PE in the short term. For example, when a software thread migrates from a first PE to a second PE, a memory store operation from the second PE to invalidate a local cache copy of a coherence granule in the first PE is more efficient than updating the value of the local cache copy of the coherence granule in the first PE. However, when a memory store operation to a coherence granule is followed by memory store operations to the same coherence granule by multiple PEs, the write-update protocol is more efficient than the write-invalidate protocol. In this situation, the write-update protocol ensures that all PEs holding a local cache copy of the coherence granule receive the updated copy, whereas the write-invalidate protocol in the same situation would require the PEs holding a local cache copy of the coherence granule to invalidate their stale copies and then perform a memory load operation by sending a separate read bus command to a central ordering point (COP) to read the updated value.

[0005] Thus, while the write-invalidate protocol and the write-update protocol each have advantages in certain situations, neither is equally efficient in all situations. Moreover, the information for determining which cache coherence protocol will be most efficient in a given situation can not be accessible by a single entity, such as the COP, but can be distributed among the home PE, the snooper PEs, and one or more of the COPs. Therefore, it is desirable to provide a mechanism by which the appropriate cache coherence protocol can be used in performing a memory store operation according to the existing circumstances. SUMMARY

[0006] The exemplary embodiments disclosed herein include providing dynamic selection of cache coherence protocols in a processor-based device. In this regard, in one exemplary embodiment, a processor-based device includes a plurality of processing elements (PEs) including a home PE and at least one snooper PE, and a central ordering point (COP). As used herein, the term "home PE" refers to a PE that performs a memory store operation and sends a cache coherence bus command to the COP. The term "snooper PE" refers to a PE that receives a snoop command associated with a memory store operation from the COP and then acts according to the snoop command to maintain cache coherence. Thus, a PE can operate as a home PE for one memory store operation and also operate as a snooper PE for a different memory store operation.

[0007] The COP of the processor-based device is configured to dynamically select, on a store-by-store basis, a write-invalidate protocol or a write-update protocol as the cache coherence protocol to be used for maintaining cache coherence for memory store operations by the home PE. This selection is made by the COP based on one or more protocol preference indicators that can be generated and provided by one or more of the home PE, the at least one snooper PE, and the COP itself. For example, in some embodiments, the home PE can predict that the write-update protocol has no advantage in its current situation based on conditions known to the home PE, and can prevent the write-update protocol from being used for memory store operations. Likewise, some embodiments can provide that one or more of the COP and the at least one snooper PE can indicate a preference for the write-update protocol based on each available knowledge, such as, by way of non-limiting example, the number of PEs holding local cache copies of the coherence granule, or the likelihood of a subsequent re-read of the coherence granule. After selecting the cache coherence protocol to be used based on the one or more protocol preference indicators, the COP sends a response message to each of the home PE and the at least one snooper PE indicating the cache coherence protocol selected for the memory store operation.

[0008] In another example embodiment, a processor-based device is provided. The processor-based device includes a plurality of PEs, including a home PE and at least one snooper PE. The processor-based device also includes a COP. The home PE is configured to send a cache coherence bus command to the COP as part of a memory store operation. The COP is configured to, in response to receiving the cache coherence bus command sent by the home PE, dynamically select, on a store-by-store basis, one of a write-invalidate protocol and a write-update protocol as the cache coherence protocol to be used for maintaining cache coherence based on one or more protocol preference indicators provided by one or more of the home PE, the at least one snooper PE, and the COP. The COP is also configured to send a response message to each of the home PE and the at least one snooper PE indicating the cache coherence protocol selected.

[0009] In another example embodiment, a method for dynamically selecting a cache coherency protocol in a processor-based device is provided. The method includes sending, by a master processing element (PE) of a plurality of PEs of the processor-based device, a cache coherency bus command to a central ordering point (COP) of the processor-based device as part of a memory store operation. The method also includes dynamically selecting, by the COP on a store-by-store basis, one of a write-invalidate protocol and a write-update protocol as the cache coherency protocol for maintaining cache coherency in response to receiving the cache coherency bus command based on one or more protocol preference indicators provided by one or more of the master PE, at least one snooper PE of the plurality of PEs, and the COP. The method further includes sending, by the COP, a response message indicating the selected cache coherency protocol to each of the master PE and the at least one snooper PE.

[0010] In another example embodiment, a non-transitory computer-readable medium having computer-executable instructions stored thereon is provided. The computer-executable instructions, when executed by a processor, cause the processor to send, by a master processing element (PE) of a plurality of processing elements of the processor, a cache coherency bus command to a central ordering point (COP) of the processor as part of a memory store operation. The computer-executable instructions also cause the processor to dynamically select, by the COP on a store-by-store basis, one of a write-invalidate protocol and a write-update protocol as the cache coherency protocol for maintaining cache coherency in response to receiving the cache coherency bus command based on one or more protocol preference indicators provided by one or more of the master PE, at least one snooper PE of the plurality of PEs, and the COP. The computer-executable instructions further cause the processor to send, by the COP, a response message indicating the selected cache coherency protocol to each of the master PE and the at least one snooper PE.

[0011] The scope of the disclosure and its additional embodiments will be understood by those skilled in the art upon reading the following detailed description of the preferred embodiments in conjunction with the drawings, which are incorporated in and form a part of this specification. BRIEF DESCRIPTION OF DRAWINGS

[0012] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure.

[0013] Figure 1 is a block diagram illustrating an example processor-based device configured to provide dynamic selection of a cache coherency protocol using protocol preference indicators provided by one or more of a master processing element (PE), at least one snooper PE, and a central ordering point (COP) of the processor-based device;

[0014] Figures 2A-2C This diagram illustrates, according to some embodiments, a method for dynamically selecting a cache coherence protocol. Figure 1 A message flow diagram illustrating the exemplary communication flow between the master PE, the listener PE, and the COP;

[0015] Figure 3 This is a flowchart illustrating an exemplary operation for providing dynamic selection of a cache coherence protocol according to one embodiment;

[0016] Figure 4 The illustration shows, according to one embodiment, that a protocol for predicting invalid writes is preferred and provides a protocol preference indicator to the COP. Figure 1 A flowchart of another exemplary operation of the main PE;

[0017] Figure 5 The illustration shows a preferred predictive write update protocol according to one embodiment. Figure 1 A flowchart illustrating an exemplary operation of COP;

[0018] Figure 6A and Figure 6B The illustration shows, according to one embodiment, a preferred write update protocol for predicting and providing a protocol preference indicator to the COP. Figure 1 A flowchart illustrating the exemplary operation of the eavesdropper PE; and

[0019] Figure 7 This is a block diagram of an exemplary processor-based device configured to provide dynamic selection of cache coherency protocols using protocol preference indicators, such as... Figure 1 Processor-based devices. Detailed Implementation

[0020] The exemplary embodiments disclosed herein include providing dynamic selection of cache coherency protocols in a processor-based device. In this regard, in one exemplary embodiment, a processor-based device includes a plurality of processing elements (PEs) including a home PE and at least one snooper PE, and a central ordering point (COP). The COP of the processor-based device is configured to dynamically select, on a store-by-store basis, a write-invalidate protocol or a write-update protocol as a cache coherency protocol for maintaining cache coherency for memory store operations by the home PE. The selection is made by the COP based on one or more protocol preference indicators that can be generated and provided by one or more of the home PE, the at least one snooper PE, and the COP itself. For example, in some embodiments, the home PE can predict, based on conditions known to the home PE, that the write-update protocol has no advantage in its current situation, and can prevent the write-update protocol from being used for memory store operations. Likewise, some embodiments can provide that one or more of the COP and the at least one snooper PE can indicate a preference for the write-update protocol based on knowledge available to each (e.g., as non-limiting examples, a number of PEs holding local cache copies of a coherency granule, a likelihood of a subsequent re-read of the coherency granule). After selecting the cache coherency protocol to use, the COP sends a response message to each of the home PE and the at least one snooper PE indicating the selected cache coherency protocol.

[0021] In this regard, Figure 1 An exemplary processor-based device 100 is illustrated that provides a plurality of processing elements (PEs) 102(0)-102(P) for processing executable instructions. Each of the PEs 102(0)-102(P) can include, for example, a separate processor core that includes a logical execution unit and associated cache and functional units. In the illustrated example, each of the PEs 102(0)-102(P) includes a corresponding execution pipeline 104(0)-104(P) that is configured to perform out-of-order execution of instruction streams that include computer executable instructions. As non-limiting examples, the execution pipelines 104(0)-104(P) can each include an extract stage for retrieving instructions for execution, a decode stage for converting the extracted instructions into control signals for instruction execution, a rename stage for allocating physical register file (PRF) registers, a dispatch stage for issuing execution instructions, an execution stage for sending instructions and operands to execution units, and / or a commit stage (P) for irrevocably updating the architectural state of the corresponding PE 102(0)-102(P) based on results of instruction execution. Figure 1

[0022] ​Figure 1 The PEs 102(0)-102(P) of the processor-based device 100 are interconnected to one another and to the system memory 106 by an interconnect bus 108. As shown in Figure 1 The system memory 106 is subdivided into a plurality of coherence granules 110(0)-110(G), each coherence granule representing the smallest unit of memory for which the processor-based device 100 maintains cache coherence (e.g., 64 bytes as a non-limiting example), as shown in Figure 1 The PEs 102(0)-102(P) also include corresponding caches 112(0)-112(P), which include cache lines 114(0)-114(C), 116(0)-116(C), and 118(0)-118(C), respectively. It should be understood that the PEs 102(0)-102(P) can also include caches other than the caches 112(0)-112(P) illustrated in Figure 1 The cache lines 114(0), 116(0), and 118(0) of the corresponding caches 112(0)-112(P) store local copies (“COGRAN COPY”) 120, 122, and 124, respectively, of one of the coherence granules 110(0)-110(G) (e.g., coherence granule 110(0) as a non-limiting example), as shown in

[0023] The processor-based device 100 also includes a central ordering point (COP) 126 configured to arbitrate between cache coherence bus commands received from a home PE of the PEs 102(0)-102(P), direct snoop commands to a snoop PE of the PEs 102(0)-102(P), and receive snoop replies from the snoop PE of the PEs 102(0)-102(P), and send response messages to both the home PE and the snoop PE of the PEs 102(0)-102(P). The COP 126 can work in conjunction with a snoop filter 128 configured to monitor traffic on the interconnect bus 108 to track the coherence state of the cache lines 114(0)-114(C), 116(0)-116(C), and 118(0)-118(C) of the PEs 102(0)-102(P).

[0024] Figure 1The processor-based device 100 of and constituent elements thereof can encompass any of known digital logic elements, semiconductor circuitry, processing cores and / or memory structures, and other elements, or combinations thereof. The embodiments described herein are not limited to any particular arrangement of elements, and the disclosed technology can be readily extended to various structures and layouts on semiconductor dies or packages. It should be appreciated that some embodiments of the processor-based device 100 can include other elements in addition to those shown in Figure 1 For example, each of the PEs 102(0)-102(P) can also include one or more functional units, instruction caches, unified caches, memory controllers, interconnect buses, and / or additional memory devices, cache and / or controller circuitry, which are omitted from Figure 1 for the sake of clarity.

[0025] As noted above, conventional processor-based devices provide support for cache coherency protocols, such as write-invalidate protocols and write-update protocols, to enable local changes to shared data within one PE 102(0)-102(P) to be propagated to other PEs 102(0)-102(P) to ensure that all of the PEs 102(0)-102(P) have a consistent view of the shared data. However, while write-invalidate protocols and write-update protocols each have advantages in particular scenarios, neither is equally efficient in all contexts. Moreover, information that can be used to determine which cache coherency protocol is most efficient in a given context can not be accessible by a single entity, such as the COP 126 of Figure 1 , but can be distributed among a home PE of the PEs 102(0)-102(P), a snooper PE of the PEs 102(0)-102(P), and one or more of the COP 126.

[0026] In this regard, Figure 2A-2C The processor-based device 100 of and constituent elements thereof can encompass any of known digital logic elements, semiconductor circuitry, processing cores and / or memory structures, and other elements, or combinations thereof. The embodiments described herein are not limited to any particular arrangement of elements, and the disclosed technology can be readily extended to various structures and layouts on semiconductor dies or packages. It should be appreciated that some embodiments of the processor-based device 100 can include other elements in addition to those shown in Figure 1In more detail, COP 126 is configured to dynamically select a cache coherence protocol (i.e., write invalidation protocol or write update protocol) for a given memory storage operation based on one or more protocol preference indicators provided by the master PE among PEs 102(0)-102(P), at least one snooping PE among PEs 102(0)-102(P), and one or more of COP 126 itself. The selection of the cache coherence protocol is performed by COP 126 on a per-store basis, allowing different cache coherence protocols to be selected for consecutive memory storage operations. Therefore, the processor-based device 100 is configured to support both write invalidation and write update protocols, rather than just one cache coherence protocol (as is the case with many conventional processor-based devices).

[0027] In some embodiments, PEs 102(0)-102(P) and COP 126 can be configured to provide one or more protocol preference indicators based on each available environmental knowledge. For example, when executing a memory store instruction (“MEM STOREINSTR”) 130, PE 102(0), acting as the master PE, can predict that a write invalidation protocol is preferred because PE 102(0) knows that it will perform multiple subsequent memory store operations on a coherent particle (such as coherent particle 110(0)). Similarly, COP 126 can determine that the number of PEs 102(0)-102(P) holding highly shared and disputed coherent particles in the local cache exceeds a proxy threshold 132, and therefore can predict that a write update protocol is preferred. Based on one or more protocol preference indicators received by COP 126, COP 126 dynamically selects a cache coherence protocol and then transmits the selected cache coherence protocol to PEs 102(0)-102(P). As a non-limiting example, the logic for generating, providing and evaluating such protocol preference indicators can be embodied in the prediction logic circuits 134(0)-134(P) of PE 102(0)-102(P) and / or in the prediction logic circuit 136 of COP 126.

[0028] To explain Figures 2A-2C The processor-based device 100 provides communication flows between its components for generating and providing protocol preference indicators and dynamically selecting cache coherence protocols. Figures 2A-2C For clarity, in the description Figure 1 Referenced at the time Figures 2A-2C Components. For example... Figures 2A-2CThe message flow diagram 200 is shown in FIG. 2, which illustrates the master PE 102(0), the snooper PEs 102(1) and 102(P), and the COP 126, represented by the vertical line, with the communications between these elements shown by the arrows with headings. It should be understood that the PE 102(0) is referred to as the "master PE" and the PEs 102(1) and 102(P) are referred to as "snooper PEs" for illustrative purposes only, and that each of the PEs 102(0)-102(P) can operate as a master PE or a snooper PE depending on its role in a particular memory store operation. It should also be understood that not all of the operations in the operations shown in FIG. 2 can be performed by all embodiments. Figure 2A All of the operations shown in FIG. 2 can be performed by all embodiments.

[0029] In Figure 1 In FIG. 2, the operations begin with the master PE 102(0) predicting whether a write- invalidate protocol is preferred in response to a memory store operation performed by the master PE 102(0), as indicated by block 202. In general, the master PE 102(0) can defer to other agents (such as, by way of non-limiting example, the snooper PEs 102(1) and 102(P), the COP 126, hints provided by software, and so on) to determine whether a write-update protocol is preferred. However, the master PE 102(0) can predict in some cases that a write-update protocol will be disadvantageous, and that a write-invalidate protocol is preferred. For example, in some embodiments, the master PE 102(0) can determine that the memory store operation will be one of multiple memory store operations to the same coherence granule (e.g., the coherence granule 110(0)), and thus a write-invalidate protocol is preferred. Some embodiments of the master PE 102(0) can further predict that a write-invalidate protocol is preferred by determining that the memory store operation will not include an atomic read-modify-write operation to the coherence granule 110(0). Note that if the memory store operation does involve an atomic read-modify-write operation, the master PE 102(0) can prefer a write-update protocol, as the master PE 102(0) can use a shared memory variable to communicate with other threads of execution. Figure 2A

[0030] ​In some embodiments, the home PE 102(0) can base its prediction on a software-provided hint (transmitted via, for example, an opcode hint added to a memory store instruction, a page table attribute, or an address range register, by way of non-limiting example). For example, the use of some high-level software constructs, such as C++ atomic variables and Java volatile variables, can indicate that the memory addresses associated with such constructs are used for shared memory communication between software threads. If the home PE 102(0) performs a memory store operation to a memory address associated with such a construct, it can infer that snooper PEs 102(1) and 102(P) can need to perform a subsequent memory load operation if the memory store operation causes local cache copies to be invalidated. Thus, if the home PE 102(0) detects a software-provided hint, the home PE 102(0) can predict that a write-invalidate protocol is not preferred in those cases.

[0031] Based on its prediction, the home PE 102(0) sends a cache coherency bus command 204 to the COP 126 to indicate its preferred cache coherency protocol, as indicated by arrow 206. The cache coherency bus command 204 includes a prevent-write-update attribute 208, which is asserted or de-asserted by the home PE 102(0) to indicate its preference to the COP 126. As shown in FIG. 2, the prevent-write-update attribute 208 represents one possible embodiment of a protocol preference indicator 210, and can be so referred to generally herein. In some embodiments, the prediction by the home PE 102(0) that a write-invalidate protocol is preferred will be treated as deterministic by the COP 126, allowing the home PE 102(0) to prohibit the use of a write-update protocol for a given memory store operation. Thus, as discussed in greater detail below, if the home PE 102(0) sends the cache coherency bus command 204 to the COP 126 and the prevent-write-update attribute 208 is asserted in such embodiments, the COP 126 sends a response message to the home PE 102(0) and to the snooper PEs 102(1) and 102(P) indicating that a write-invalidate protocol is selected. Figure 2B Figure 1 As discussed in greater detail below, if the home PE 102(0) sends the cache coherency bus command 204 to the COP 126 and the prevent-write-update attribute 208 is asserted in such embodiments, the COP 126 sends a response message to the home PE 102(0) and to the snooper PEs 102(1) and 102(P) indicating that a write-invalidate protocol is selected.

[0032] ​In some embodiments, the cache coherency bus command 204 can comprise a non-allocate write bus command sent by the home PE 102(0) in response to a cache miss on the cache 112(0), where the memory store operation is not write allocated in the cache 112(0) of the home PE 102(0). Some embodiments can provide that the cache coherency bus command 204 comprises a read and intent to write bus command sent by the home PE 102(0) in response to a cache miss on the cache 112(0), where the memory store operation is write allocated in the cache 112(0) of the home PE 102(0). According to some embodiments, the cache coherency bus command 204 can comprise an upgrade to writable bus command sent by the home PE 102(0) in response to a cache hit on the cache 112(0), where the cache line (e.g., as a non-limiting example, the cache line 114(0)) remains in a shared coherent state.

[0033] Upon receiving the cache coherency bus command 204 from the home PE 102(0), the COP 126 next makes its own prediction as to whether a write-update protocol is preferred, as indicated by block 212. Some embodiments can provide that this prediction by the COP 126 is based on whether the prevent-write-update attribute 208 of the cache coherency bus command 204 is asserted. In some embodiments, the COP 126 can base its prediction on how many of the PEs 102(0)-102(P) hold local cache copies of the coherent granule 110(0) (e.g., the local cache copies 120, 122, and 124) to be written by the memory store operation. If the number of PEs 102(0)-102(P) holding local cache copies 120, 122, and 124 exceeds a proxy threshold 132, then the COP 126 in such embodiments will predict that a write-update protocol is preferred for servicing the memory store operation. In some embodiments, the number of PEs 102(0)-102(P) holding local cache copies 120, 122, and 124 can be determined by the COP 126 consulting the snoop filter 128 or another snoop directory (not shown) of the processor-based device 100. Figure 1 Figure 2A

[0034] ​​After making its prediction, COP 126 sends snoop commands 214 to snooper PEs 102(l) and 102(P), as indicated by arrows 216 and 218, respectively. Snoop commands 214 include a write-update-request attribute 220 asserted or de-asserted by COP 126 to indicate its cache coherency protocol preference to snooper PEs 102(l) and 102(P). As noted above, in some embodiments, COP 126 can de-assert write-update-request attribute 220 if master PE 102(0) sends cache coherency bus command 204 and prevents write-update attribute 208 from being asserted. It will be appreciated that write-update-request attribute 220 represents another possible embodiment of protocol preference indicator 210, and thus can be so referred to generally herein, as shown in Figure 2B Operation then continues in Figure 2B

[0035] Referring now to Figure 2B , each of snooper PEs 102(l) and 102(P) can also independently predict whether the write-update protocol is preferred, as indicated by blocks 222 and 224, respectively. In this way, snooper PEs 102(l) and 102(P) can confirm participation or opt-out of the requested write-update (as indicated by the write-update-request attribute 220 of asserted snoop commands 214), or can request the write-update protocol if the write-update-request attribute 220 of snoop commands 214 is de-asserted. In the former case, each of snooper PEs 102(l) and 102(P) can default to using the write-update protocol if the write-update-request attribute 220 of snoop commands 214 is asserted by COP 126, unless it determines that there is a reason to opt-out. As non-limiting examples, a snooper PE such as snooper PEs 102(l) and 102(P) can decide to opt-out of using the write-update protocol because the snooper PE is not willing to receive write-update data due to resource constraints or due to being configured to be prohibited from receiving write-update data. Conversely, if the write-update-request attribute 220 of snoop commands 214 is de-asserted by COP 126, each of snooper PEs 102(l) and 102(P) can still request the write-update protocol based on its own prediction of the benefits of using the write-update protocol.

[0036] ​According to some embodiments, each of snooper PEs 102(1) and 102(P) can base their respective prediction of whether a write-update protocol is preferred on a likelihood of re-reading the coherence granule 110(0) to be written by the memory store operation. If so, snooper PEs 102(1) and 102(P) will indicate a preference for the write-update protocol. In some embodiments, snooper PEs 102(1) and 102(P) can each determine the likelihood of re-reading the coherence granule 110(0) based on a location of the local cache copy 122 and 124 in caches 112(1) and 112(P), respectively, as determined by a cache replacement policy of caches 112(1) and 112(P). For example, if cache 112(1) uses a least recently used (LRU) replacement policy, snooper PE 102(1) can determine that the coherence granule 110(0) is likely to be re-read if cache line 116(0) is installed between a midpoint between a least recently used cache line and a least recently used cache line in cache 112(1).

[0037] Some embodiments can provide that snooper PEs 102(1) and 102(P) can each determine the likelihood of re-reading the coherence granule 110(0) by determining whether the local cache copy 122 and 124 remains in an exclusive state at the time the snooping command 214 is received by the corresponding snooper PE 102(1) and 102(P) from COP 126. In some embodiments, snooper PEs 102(1) and 102(P) can each determine the likelihood of re-reading the coherence granule 110(0) by determining whether the local cache copy 122 and 124 remains in a modified or owned state, but the corresponding snooper PE 102(1) or 102(P) has not yet written the coherence granule 110(0). In either case, if true, snooper PEs 102(1) and 102(P) can be communicating with other software threads via shared memory variables, and thus will predict that a write-update protocol is the preferred cache coherence protocol.

[0038] After predicting whether a write-update protocol is preferred, snooper PEs 102(1) and 102(P) send snooping replies 226 and 228, respectively, to COP 126, as indicated by arrows 230 and 232. The snooping replies 226 and 228 include write-update request attributes 234 and 236, respectively, which are asserted or de-asserted depending on whether the corresponding snooper PE 102(1) and 102(P) predicted that a write-update protocol is preferred. It will be appreciated that, as described above, the write-update request attributes 234 and 236 can be asserted or de-asserted based on a variety of factors, such as whether the corresponding snooper PE 102(1) or 102(P) is likely to re-read the coherence granule 110(0), whether the corresponding snooper PE 102(1) or 102(P) is likely to write the coherence granule 110(0), and / or whether the corresponding snooper PE 102(1) or 102(P) is likely to be communicating with other software threads via shared memory variables. Figure 2CAs shown in FIG. 2, the write-update-request attributes 234 and 236 represent additional possible embodiments of the protocol preference indicator 210, and thus can be so referred to generally herein. Operation then continues in Figure 2C

[0039] Turning now to Figure 3 Upon receiving the snoop responses 226 and 228, the COP 126 can then determine in some embodiments whether either of the snoop responses 226 and 228 includes the asserted write-update-request attribute 234 or 236, respectively, as indicated by block 238. Assuming that the home PE 102(0) has not excluded use of the write-update protocol (i.e., has indicated that the write- invalidate protocol will be selected by asserting the prevent-write-update attribute 208), the COP 126 will generate a response message 240 that has a write-update-valid attribute 242 asserted based on the write-update-request attributes 234 and 236 being asserted or de-asserted, and send the response message 240 to the home PE 102(0) as well as the snooper PEs 102(1) and 102(P), as indicated by arrows 244, 246, and 248, respectively. Because the snooper PEs 102(1) and 102(P) independently determine whether the write-update protocol is preferred, either both of the write-update-request attributes 234 and 236 can be asserted, only one of the two can be asserted, or both of the two can be de-asserted. If either of the write-update-request attributes 234 and 236 is asserted (and the prevent-write-update attribute 208 of the cache-coherency bus command 204 sent by the home PE 102(0) is not asserted), the COP 126 will assert the write-update-valid attribute 242 of the response message 240. However, if both of the write-update-request attributes 234 and 236 are de-asserted (or, if the prevent-write-update attribute 208 of the cache-coherency bus command 204 sent by the home PE 102(0) is asserted), the COP 126 will de-assert the write-update-valid attribute 242 of the response message 240.

[0040] ​The write-update-valid attribute 242 of the response message 240 indicates to the home PE 102(0) as well as the snooping PEs 102(1) and 102(P) the cache coherency protocol that will be selected by the COP 126 for the memory store operation. Upon receiving the response message 240 with the write-update-valid attribute 242 asserted, the home PE 102(0) will perform the write-update by sending data to the snooping PEs 102(1), 102(P) respectively for updating their local cache copies 122 and 124. Likewise, upon receiving the response message 240 with the write-update-valid attribute 242 asserted, any of the snooping PEs 102(1), 102(P) whose snoop reply 226, 228 includes the asserted write-update-request attribute 234, 236 will be prepared to receive write-update data from the home PE 102(0). Any of the snooping PEs 102(1), 102(P) whose snoop reply 226, 228 includes the de-asserted write-update-request attribute 234, 236 will ignore the write-update-valid attribute 242 in the response message 240 and will perform a write-invalidate.

[0041] The mechanisms described herein for dynamically selecting a cache coherency protocol allow the COP 126 to select a write-invalidate protocol or a write-update protocol on a store-by-store basis based on input from one or more of the home PE 102(0), the snooping PEs 102(1) and 102(P), and the COP 126 itself. In this way, the cache coherency protocol that provides the best performance and / or lowest energy consumption can be used for each memory store operation that finds a cache copy of the coherency granule in another PE 102(0)-102(P).

[0042] To illustrate exemplary operations for providing dynamic selection of a cache coherency protocol according to some embodiments, Figure 3 a flowchart 300 is provided. For the sake of clarity, Figure 1 reference is made to the elements of Figures 2A-2C and Figure 3 as described above. Figure 4The operations in FIG. 10 begin, in some embodiments, when a master PE 102(0) of a plurality of PEs 102(0)-102(P) of a processor-based device 100 sends a cache coherency bus command 204 to a COP 126 of the processor-based device 100 as part of a memory store operation (block 302). In response to receiving the cache coherency bus command 204, the COP 126 dynamically selects one of a write-invalidate protocol and a write-update protocol as a cache coherency protocol for maintaining cache coherency on a store-by-store basis based on one or more protocol preference indicators 210 provided by one or more of the master PE 102(0), at least one snooper PE 102(1), 102(P) of the plurality of PEs 102(0)-102(P), and the COP 126 (block 304). The COP 126 then sends a response message 240 to the master PE 102(0) and each of the at least one snooper PE 102(1), 102(P) indicating the selected cache coherency protocol (block 306).

[0043] Figure 1 A flow diagram 400 of further exemplary operations of the master PE 102(0) of FIG. 10 is provided in accordance with one embodiment. For purposes of clarity, elements of FIG. 10 are referenced in describing Figures 2A-2C Figure 4 Figure 1 Figures 2A-2C Figure 4 Figure 1 In FIG. 10, the operations begin with the master PE 102(0) predicting that a write-invalidate protocol is preferred (block 402). In some embodiments, the operations for the block 402 of predicting that a write-invalidate protocol is preferred can include the master PE 102(0) predicting that the memory store operation will be one of a plurality of memory store operations to the same coherency granule (e.g., the coherency granule 110(0) as a non-limiting example) (block 404). Some embodiments can provide that the operations for the block 402 of predicting that a write-invalidate protocol is preferred include the master PE 102(0) predicting that the memory store operation will not include an atomic read-modify-write operation (block 406). In accordance with some embodiments, the operations for the block 402 of predicting that a write-invalidate protocol is preferred can be based on a hint provided by software (block 408).

[0044] ​​​​​In response to predicting that the write-invalidate protocol is preferred, the home PE 102(0) asserts the write-update-prevent attribute 208 of the cache coherency bus command 204 (block 410). In response to receiving the cache coherency bus command 204 and the write-update-prevent attribute 208 of the cache coherency bus command 204 being asserted, the COP 126 sends a response message 240 including a de-asserted write-update-valid attribute 242 to the home PE 102(0) and to each of the at least one snooper PE 102(1), 102(P) indicating that the write-invalidate protocol will be selected for the memory store operation (block 412).

[0045] To illustrate exemplary operations of a COP 126 for predicting that the write-update protocol is preferred Figure 5 according to one embodiment, Figure 5 a flowchart 500 is provided. For clarity, reference is made to the elements of Figure 1 and Figures 2A-2C and Figure 5 when describing Figure 6A the operations therein begin with the COP 126 predicting that the write-update protocol is preferred (block 502). In some embodiments, the operations for block 502 of predicting that the write-update protocol is preferred can include determining whether a count of the home PE 102(0) and the at least one snooper PE 102(1), 102(P) holding local cache copies 120, 122, 124 of the coherency granule 110(0) to be written by the memory store operation exceeds a proxy threshold 132 (block 504). In response to predicting that the write-update protocol is preferred, the COP 126 asserts the write-update-request attribute 220 of the snoop command 214 (block 506).

[0046] Figure 6B and Figure 1 a flowchart 600 illustrating exemplary operations of snooper PEs 102(1) and 102(P) for predicting that the write-update protocol is preferred and providing a protocol preference indicator 210 to the COP 126 according to one embodiment is provided. In aspects according to Figures 2A-2C and Figure 6A In aspects according to Figure 6B and Figure 6A the home PE 102(0) sending to the COP 126 the write-update-prevent attribute 208 of the cache coherency bus command 204 is de-asserted, thus allowing the COP 126 as well as the snooper PEs 102(1) and 102(P) to make their own prediction as to the preferred cache coherency protocol. For clarity, reference is made to Figure 6B and Figure 1 and Figures 2A-2C and Figure 6Aelement. In Figure 6B In the method 600, operation begins with a snooper PE (e.g., snooper PE 102(1)) predicting that a write-update protocol is preferred (block 602). In some embodiments, the operation to predict that a write-update protocol is preferred block 602 can include predicting that the snooper PE 102(1) is likely to re-read a coherency granule 110(0) to be written by a memory store operation (block 604). In some embodiments, the snooper PE 102(1) can predict that the snooper PE 102(1) is likely to re-read the coherency granule 110(0) based on a location of a local cache copy 122 in the cache 112(1) as determined by a cache replacement policy of the cache 112(1). Some embodiments can provide that the snooper PE 102(1) can predict that the snooper PE 102(1) is likely to re-read the coherency granule 110(0) by determining that the local cache copy 122 remains in an exclusive state when the snooper PE 102(1) receives a snoop command 214 from the COP 126, or by determining that the local cache copy 122 remains in a modified or owned state but that the snooper PE 102(1) has not written to the coherency granule 110(0).

[0047] In response to predicting that a write-update protocol is preferred, the snooper PE 102(1) asserts a write-update request attribute 234 of the snoop reply 226 (block 606). The COP 126 then receives at least one snoop reply 226, 228 corresponding to the at least one snooper PE 102(1), 102(P) (block 608). The COP 126 then determines whether any of the at least one snoop reply 226, 228 includes the asserted write-update request attribute 234, 236 (block 610). If not, the COP 126 sends a response message 240 including a de-asserted write-update valid attribute 242 to each of the home PE 102(0) and the at least one snooper PE 102(1), 102(P), the de-asserted write-update valid attribute 242 indicating that a write-invalidate protocol will be selected for the memory store operation (block 612). If the COP 126 determines at decision block 610 that any of the at least one snoop reply 226, 228 includes the asserted write-update request attribute 234, 236, processing continues at block 614 in Figure 6B

[0048] Reference is now made to Figure 7 ​COP 126 sends a response message 240 including an asserted write-update valid attribute 242 to each of the home PE 102(0) and the at least one snooper PE 102(1), 102(P), the asserted write-update valid attribute 242 indicating that a write-update protocol is to be selected for the memory store operation (block 614). In some embodiments, upon receiving the response message 240 including the asserted write-update valid attribute 242, each of the at least one snooper PE 102(1), 102(P) corresponding to a snooping reply in the snooping replies 226, 228 including the asserted write-update request attribute 234, 236 can perform a write-update operation (block 616). Likewise, in response to the response message 240 including the asserted write-update valid attribute 242, each of the at least one snooper PE 102(1), 102(P) corresponding to a snooping reply in the at least one snooping reply 226, 228 including the de-asserted write-update request attribute 234, 236 can perform a write-invalidate operation (block 618).

[0049] Figure 1 is a block diagram of an exemplary processor-based device 700 that provides dynamic selection of cache coherency protocols, such as Figure 1 the processor-based device 100. The processor-based device 700 can be one or more circuits included in an electronic board card, such as a printed circuit board (PCB), a server, a personal computer, a desktop computer, a laptop computer, a personal digital assistant (PDA), a computing pad, a mobile device, or any other device, and can represent, for example, a server or a user's computer. In this example, the processor-based device 700 includes a processor 702. The processor 702 represents one or more general-purpose processing circuits, such as a microprocessor, a central processing unit, etc., and can correspond to the PE 102(0)-102(P) of Figure 7 the processor-based device 100. The processor 702 is configured to execute processing logic in instructions to perform the operations and steps discussed herein. In this example, the processor 702 includes an instruction cache 704 for temporary fast access storage of instructions, and an instruction processing circuit 710. Instructions fetched or prefetched from memory, such as from a system memory 708 over a system bus 706, are stored in the instruction cache 704. The instruction processing circuit 710 is configured to process instructions fetched into the instruction cache 704 and process the instructions for execution.

[0050] Processor 702 and system memory 708 are coupled to system bus 706 and can be coupled to peripheral devices included in processor-based device 700. It is known that processor 702 communicates with these other devices by exchanging address, control, and data information via system bus 706. For example, processor 702 can transmit bus transaction requests to memory controller 712 in system memory 708, which is an example of a peripheral device. Although... Figure 7 Not shown, but multiple system buses 706 may be provided, each forming a different architecture. In this example, memory controller 712 is configured to provide memory access requests to memory array 714 in system memory 708. Memory array 714 includes an array of storage bit cells for storing data. As a non-limiting example, system memory 708 may be read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (such as synchronous DRAM (SDRAM), etc.), and static memory (e.g., flash memory, static random access memory (SRAM), etc.).

[0051] Other devices can be connected to system bus 706. For example... Figure 7 As shown, for example, these devices may include system memory 708, one or more input devices 716, one or more output devices 718, modem 724, and one or more display controllers 720. The input devices 716 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. The output devices 718 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. Modem 724 may be any device configured to allow data exchange with network 726. Network 726 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), BLUETOOTH™ networks, and the Internet. Modem 724 may be configured to support any type of desired communication protocol. Processor 702 may also be configured to access display controller 720 via system bus 706 to control information sent to one or more displays 722. Display 722 may include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, etc.

[0052] ​The processor-based device 700 may include an instruction set 728, which will be executed by the processor 702 according to the instructions for any desired application. The instructions 728 may be stored in system memory 708, the processor 702, and / or instruction cache 704 (as an example of non-transitory computer-readable medium 730). The instructions 728 may also reside wholly or at least partially in system memory 708 and / or in the processor 702 during their execution. The instructions 728 may also be transmitted or received via a network 726 via a modem 724, such that the network 726 includes the computer-readable medium 730.

[0053] Although the computer-readable medium 730 is shown as a single medium in the exemplary embodiments, the term "computer-readable medium" should be understood to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) storing one or more instruction sets 728. The term "computer-readable medium" should also be understood to include any medium capable of storing, encoding, or carrying an instruction set executable by a processing device and causing the processing device to perform any one or more methods of the embodiments disclosed herein. Therefore, the term "computer-readable medium" should be understood to include, but is not limited to, solid-state storage, optical media, and magnetic media.

[0054] The embodiments disclosed herein include various steps. These steps can be comprised of hardware components or embodied in machine-executable instructions that can be used to cause a general-purpose or special-purpose processor programmed with those instructions to perform these steps. Alternatively, these steps can be performed by a combination of hardware and software processes.

[0055] The embodiments disclosed herein can be provided as a computer program product or software process, which may include a machine-readable medium (or computer-readable medium) having instructions stored thereon, which can be used to program a computer system (or other electronic device) to perform processes according to the embodiments disclosed herein. A machine-readable medium includes any mechanism for storing or transmitting information in a machine-readable (e.g., computer-readable) form. For example, machine-readable media include machine-readable storage media (e.g., ROM, random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.).

[0056] Unless specifically stated otherwise and as is apparent from the preceding discussion, it is appreciated that, throughout the specification, discussions using terms such as "processing," "computing," "calculating," "determining," "displaying," or the like, refer to the action and processes of a computer system, or similar electronic

[0057] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct a more specialized apparatus to perform the required method steps. The required structure for a variety of these systems will be apparent from the description above. In addition, the embodiments described herein are not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the embodiments as described herein.

[0058] Those skilled in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the embodiments disclosed herein can be implemented as electronic hardware, instructions stored in memory or in another computer-readable medium and executed by a processor or other processing device, or combinations of both. The components of the distributed antenna system described herein can be employed in any circuit, hardware component, integrated circuit (IC), or IC chip, as examples. Memory disclosed herein can be any type and size of memory and can be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such

[0059] The various illustrative logical blocks, modules, and circuits described in connection with the embodiments disclosed herein can be implemented or performed with a processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. In addition, the controller can be a processor. The processor can be a microprocessor, but in the alternative, the processor can be any conventional processor, controller, microcontroller, or state machine. A processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0060] The embodiments disclosed herein can be embodied in hardware and in instructions stored in hardware, and can reside, for example, in RAM, flash memory, ROM, Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, hard disk, a removable disk, a CD-ROM, or any other form of computer-readable medium known in the art. The exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium can be integral to the processor. The processor and the storage medium can reside in an ASIC. The ASIC can reside in a remote station. In the alternative, the processor and the storage medium can reside as discrete components in a remote station, a base station, or a server.

[0061] It should also be noted that the operational steps described in any of the exemplary embodiments herein are described to provide examples and discussion. The operations described can be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step can actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary embodiments can be combined. Those of skill in the art will further appreciate that the information and signals described in this description can be represented using any of a variety of technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0062] Unless specifically stated otherwise, and as apparent from the preceding disclosure, it is not intended that any method described herein be construed as requiring its steps to be performed in a particular order. Accordingly, unless specifically stated otherwise, it is not intended that any particular order of steps be inferred from the disclosure.

[0063] It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Since modifications, combinations, sub-combinations and variations of the disclosed embodiments incorporating the spirit and substance of the application can occur to persons skilled in the art, the application should not be restricted to the precisely described embodiments and drawings, and it is therefore evident that the scope of the application should be determined not by the embodiments disclosed, but by the scope of the claims and their equivalents.

Claims

1. A processor-based device comprising: a plurality of processing elements (PEs) including a home PE and at least one snooper PE; and a central ordering point (COP); the home PE is configured to send a cache coherency bus command to the COP as part of a memory store operation; wherein a snooper PE is a PE that receives a snoop command from the COP associated with the memory store operation and then acts on the snoop command to maintain cache coherency; and the COP is configured to: in response to receiving the cache coherency bus command sent by the home PE, dynamically select one of a write-invalidate protocol and a write-update protocol as a cache coherency protocol for maintaining cache coherency on a store-by-store basis based on one or more protocol preference indicators provided by one or more of the home PE, the at least one snooper PE, and the COP; and send a response message to each of the home PE and the at least one snooper PE indicating the selected cache coherency protocol, wherein the response message sent to the at least one snooper PE is sent as a snoop command.

2. The processor-based device of claim 1, wherein the cache coherency bus command comprises one of: a non-allocate write bus command sent in response to a cache miss on a cache of the home PE, wherein the memory store operation does not write allocate in the cache of the home PE; an intent read and intent write bus command sent in response to a cache miss on the cache of the home PE, wherein the memory store operation write allocates in the cache of the home PE; and an upgrade-to-writeable bus command sent in response to a cache hit on a cache line in the cache of the home PE, wherein the cache line is held in a shared coherent state.

3. The processor-based device of claim 1, wherein: the one or more protocol preference indicators comprise a no-write-update attribute of the cache coherency bus command of the home PE; and the home PE is further configured to: predict whether the write-invalidate protocol is preferred; in response to predicting that the write-invalidate protocol is preferred, assert the no-write-update attribute of the cache coherency bus command; and in response to predicting that the write-invalidate protocol is not preferred, de-assert the no-write-update attribute of the cache coherency bus command.

4. The processor-based device of claim 3, wherein the home PE is configured to predict whether the write-invalidate protocol is preferred by being configured to predict whether the memory store operation is one of a plurality of memory store operations to a same coherence granule. ​ ​ ​ ​ 5. The processor-based device of claim 4, wherein the master PE is configured to predict whether the write-invalidate protocol is preferred by being further configured to predict whether the memory store operation does not include an atomic read-modify-write operation.

6. The processor-based device of claim 3, wherein the master PE is configured to predict whether the write-invalidate protocol is preferred based on a hint provided by software.

7. The processor-based device of claim 3, wherein the COP is configured to send the response message indicating the selected cache coherency protocol to each of the master PE and the at least one snooper PE by being configured to, in response to receiving the cache coherency bus command and the prevent-write-update attribute of the cache coherency bus command being asserted, send the response message including a de-asserted write-update-valid attribute to each of the master PE and the at least one snooper PE, the de-asserted write-update-valid attribute indicating that the write-invalidate protocol is selected for the memory store operation.

8. The processor-based device of claim 1, wherein: the one or more protocol preference indicators include a write-update-request attribute of a snoop command associated with the cache coherency bus command sent by the master PE and sent by the COP to the at least one snooper PE; and the COP is further configured to: predict whether the write-update protocol is preferred; in response to predicting that the write-update protocol is preferred, assert the write-update-request attribute of the snoop command; and in response to predicting that the write-update protocol is not preferred, de-assert the write-update-request attribute of the snoop command.

9. The processor-based device of claim 8, wherein the COP is configured to predict whether the write-update protocol is preferred by being configured to determine whether a count of the master PE and the at least one snooper PE holding local cache copies of a coherency granule to be written by the memory store operation exceeds a proxy threshold.

10. The processor-based device of claim 1, wherein: the one or more protocol preference indicators include a write-update-request attribute of a snoop reply associated with a snoop command sent by the COP and sent by a snooper PE of the at least one snooper PE to the COP; and the snooper PE is configured to: predict whether the write-update protocol is preferred; in response to predicting that the write-update protocol is preferred, assert the write-update-request attribute of the snoop reply; and in response to predicting that the write-update protocol is not preferred, de-assert the write-update-request attribute of the snoop reply.

11. The processor-based device of claim 10, wherein the snooper PE is configured to predict whether the write-update protocol is preferred by being configured to: determine whether a count of the master PE and the at least one snooper PE holding local cache copies of a coherency granule to be written by the memory store operation exceeds a proxy threshold; and in response to determining that the count of the master PE and the at least one snooper PE holding local cache copies of the coherency granule to be written by the memory store operation exceeds the proxy threshold, predict that the write-update protocol is preferred. determining whether a write-update-preferred attribute of the snoop command sent by the COP is asserted; and responsive to determining that the write-update-preferred attribute of the snoop command sent by the COP is asserted, predicting that the write-update protocol is preferred, unless the snoop PE is unwilling to receive write-update data.

12. The processor-based device of claim 10, wherein the snoop PE is configured to predict whether the write-update protocol is preferred by being configured to predict whether the snoop PE is likely to re-read a coherency granule to be written by the memory store operation.

13. The processor-based device of claim 12, wherein the snoop PE is configured to predict whether the snoop PE is likely to re-read the coherency granule to be written by the memory store operation based on a location of a local cache copy of the coherency granule in a local cache of the snoop PE as determined by a cache replacement policy of the local cache of the snoop PE.

14. The processor-based device of claim 12, wherein the snoop PE is configured to predict whether the snoop PE is likely to re-read the coherency granule to be written by the memory store operation by being configured to determine whether a local cache copy of the coherency granule is held in an exclusive state at the time the snoop PE receives the snoop command.

15. The processor-based device of claim 12, wherein the snoop PE is configured to predict whether the snoop PE is likely to re-read the coherency granule to be written by the memory store operation by being configured to determine whether a local cache copy of the coherency granule is held in a modified or owned state but the snoop PE has not made a write to the coherency granule.

16. The processor-based device of claim 1, wherein: the COP is further configured to: receive at least one snoop reply corresponding to the at least one snoop PE; and determine whether any of the at least one snoop reply includes an asserted write-update-request attribute; and the COP is configured to send the response message indicating the selected cache coherency protocol to each of the home PE and the at least one snoop PE by being configured to: responsive to determining that any of the at least one snoop reply includes an asserted write-update-request attribute, send the response message including an asserted write-update-valid attribute to each of the home PE and the at least one snoop PE, the asserted write-update-valid attribute indicating that the write-update protocol is to be selected for the memory store operation; and in response to determining that none of the at least one snoop reply includes the asserted write-update-request attribute, sending, to each of the home PE and the at least one snoop-er PE, the response message including a de-asserted write-update-valid attribute indicating that the write-invalidate protocol is selected for the memory store operation.

17. The processor-based device of claim 16, wherein: each of the at least one snoop-er PE corresponding to a snoop reply of the at least one snoop reply that includes the asserted write-update-request attribute is configured to perform a write-update operation in response to the response message including the asserted write-update-valid attribute; and each of the at least one snoop-er PE corresponding to a snoop reply of the at least one snoop reply that includes the de-asserted write-update-request attribute is configured to perform a write-invalidate operation in response to the response message including the asserted write-update-valid attribute.

18. A method for dynamically selecting a cache coherency protocol in a processor-based device, comprising: sending, by a home processing element (PE) of a plurality of PEs of a processor-based device, a cache coherency bus command to a central ordering point (COP) of the processor-based device as part of a memory store operation; in response to receiving the cache coherency bus command, dynamically selecting, by the COP on a store-by-store basis, one of a write-invalidate protocol and a write-update protocol as a cache coherency protocol for maintaining cache coherency based on one or more protocol preference indicators provided by one or more of the home PE, at least one snoop-er PE of the plurality of PEs, and the COP, wherein a snoop-er PE is a PE that refers to a PE that receives a snoop command from the COP associated with the memory store operation and then acts in accordance with the snoop command to maintain cache coherency; and sending, by the COP, a response message to each of the home PE and the at least one snoop-er PE indicating the selected cache coherency protocol, wherein the response message sent to the at least one snoop-er PE is sent as a snoop command.

19. The method of claim 18, wherein the cache coherency bus command comprises one of: a non-allocate write bus command sent in response to a cache miss on a cache of the home PE, wherein the memory store operation does not write allocate in the cache of the home PE; an intent read and intent write bus command sent in response to a cache miss on the cache of the home PE, wherein the memory store operation write allocates in the cache of the home PE; and an upgrade-to-writeable bus command sent in response to a cache hit on a cache line in the cache of the home PE, wherein the cache line is held in a shared coherent state. ​ 20. The method of claim 18, wherein: the one or more protocol preference indicators include a write-update-prevent attribute of the cache-coherent bus command by the home PE; and the method further comprises: predicting, by the home PE, that the write-invalidate protocol is preferred; and in response to predicting that the write-invalidate protocol is preferred, asserting, by the home PE, the write-update-prevent attribute of the cache-coherent bus command.

21. The method of claim 20, wherein predicting that the write invalidation protocol is preferred comprises: predicting, by the home PE, that the memory store operation is one of multiple memory store operations to a same coherence granule.

22. The method of claim 21, wherein predicting that the write invalidation protocol is preferred further comprises: predicting, by the home PE, that the memory store operation does not include an atomic read-modify-write operation.

23. The method of claim 20, wherein predicting that the write-invalidate protocol is preferred is based on a hint provided by software.

24. The method of claim 20, wherein sending, by the COP, the response message indicating the selected cache coherency protocol to each of the master PE and the at least one snooper PE comprises: in response to receiving the cache-coherent bus command and the write-update-prevent attribute of the cache-coherent bus command being asserted, sending, by the COP, the response message including a de-asserted write-update-valid attribute to each of the home PE and the at least one snooper PE, the de-asserted write-update-valid attribute indicating that the write-invalidate protocol is selected for the memory store operation.

25. The method of claim 18, wherein: the one or more protocol preference indicators include a write-update-request attribute of a snooping command associated with the cache-coherent bus command sent by the home PE and sent by the COP to the at least one snooper PE; and the method further comprises: predicting, by the COP, that the write-update protocol is preferred; in response to predicting that the write-update protocol is preferred, asserting, by the COP, the write-update-request attribute of the snooping command.

26. The method of claim 25, wherein predicting that the write-update protocol is preferred comprises: determining whether a count of the home PE and the at least one snooper PE holding a local cache copy of a coherence granule to be written by the memory store operation exceeds a proxy threshold.

27. The method of claim 18, wherein: the one or more protocol preference indicators include a write-update-request attribute of a snooping reply associated with a snooping command sent by the COP and sent by a snooper PE of the at least one snooper PE to the COP; and the method further comprises: predicting, by the snooper PE, that the write-update protocol is preferred; in response to predicting that the write-update protocol is preferred, asserting, by the snooper PE, the write-update-request attribute of the snooping reply.

28. The method of claim 27, wherein predicting that the write-update protocol is preferred comprises: determining that a write-update-preferred attribute of the snooping command sent by the COP is asserted; and in response to determining that the write-update-preferred attribute of the snooping command sent by the COP is asserted, predicting that the write-update protocol is preferred unless the snooper PE is unwilling to receive write-update data.

29. The method of claim 27, wherein predicting that the write-update protocol is preferred comprises predicting that the snooper PE can re-read a coherence granule to be written by the memory store operation.

30. The method of claim 29, wherein predicting that the snooper PE can re-read the coherence granule to be written by the memory store operation is based on a location of a local cache copy of the coherence granule in a local cache of the snooper PE as determined by a cache replacement policy of the local cache.

31. The method of claim 29, wherein predicting that the snooper PE is likely to re-read the coherency granule to be written by the memory store operation comprises: determining whether the local cache copy of the coherence granule was held in an exclusive state at a time the snooping command was received by the snooper PE.

32. The method of claim 29, wherein predicting that the snooper PE is likely to re-read the coherency granule to be written by the memory store operation comprises: determining whether the local cache copy of the coherence granule was held in a modified or owned state but the snooper PE did not write to the coherence granule.

33. The method of claim 18, further comprising: receiving, by the COP, at least one snoop reply corresponding to the at least one snooper PE; and determining, by the COP, that any snoop reply of the at least one snoop reply includes an asserted write-update request attribute; wherein sending, by the COP, the response message indicating the selected cache coherence protocol to each of the master PE and the at least one snooper PE comprises, in response to determining that any snoop reply of the at least one snoop reply includes an asserted write-update request attribute, sending, by the COP, the response message including an asserted write-update valid attribute to each of the master PE and the at least one snooper PE, the asserted write-update valid attribute indicating that the write-update protocol is to be selected for the memory store operation.

34. The method of claim 33, further comprising: performing, by each snooper PE of the at least one snooper PE corresponding to a snoop reply of the at least one snoop reply including an asserted write-update request attribute, a write-update operation in response to the response message including the asserted write-update valid attribute; and performing, by each snooper PE of the at least one snooper PE corresponding to a snoop reply of the at least one snoop reply including a de-asserted write-update request attribute, a write-invalidate operation in response to the response message including the de-asserted write-update valid attribute.

35. The method of claim 29, further comprising: receiving, by the COP, at least one snoop reply corresponding to the at least one snooper PE; and determining, by the COP, that no snoop reply of the at least one snoop reply includes an asserted write-update request attribute; wherein sending, by the COP, the response message indicating the selected cache coherency protocol to each of the master PE and the at least one snooper PE comprises sending, to each of the master PE and the at least one snooper PE, the response message including a de-asserted write-update-valid attribute indicating that the write-invalidate protocol is selected for the memory store operation in response to determining that none of the at least one snoop reply includes an asserted write-update-request attribute.

36. A non-transitory computer-readable medium having stored thereon computer- executable instructions that, when executed by a processor, cause the processor to: send, by a master PE of a plurality of processing elements (PEs) of the processor, a cache coherency bus command to a central ordering point (COP) of the processor as part of a memory store operation; in response to receiving the cache coherency bus command, dynamically select, by the COP on a store-by-store basis, one of a write-invalidate protocol and a write-update protocol as a cache coherency protocol for maintaining cache coherency based on one or more protocol preference indicators provided by one or more of the master PE, at least one snooper PE of the plurality of PEs, and the COP, wherein a snooper PE is a PE that receives a snoop command associated with the memory store operation from the COP and then acts in accordance with the snoop command to maintain cache coherency; and send, by the COP, a response message indicating the selected cache coherency protocol to each of the master PE and the at least one snooper PE, wherein the response message sent to the at least one snooper PE is sent as a snoop command.

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