Light-receiving element, imaging element, and imaging device

Abstract

The light-receiving element includes a sensor substrate (102) and a circuit board (101). The sensor substrate (102) is provided with a light-receiving region (103), a pair of voltage application electrodes, and an incident surface electrode (104). The light-receiving region (103) photoelectrically converts incident light into signal charges. The pair of voltage application electrodes alternately apply a voltage to generate an electric field that time-divides the signal charges in the light-receiving region (103) and distributes the signal charges to a pair of charge accumulation electrodes. The incident surface electrode (104) is provided on a light-incident surface of the light-receiving region and is applied with a voltage of a ground potential or lower. The circuit board (101) is provided on a surface of the sensor substrate (102) opposite to the light-incident surface. The circuit board (101) is provided with a pixel transistor of signal charges accumulated by the charge accumulation electrodes.

Description

Technical Field

[0001] The present disclosure relates to a light receiving element, an imaging element, and an imaging device. Background Art

[0002] The light receiving element used in the distance measurement system using the indirect time-of-flight (ToF) method includes a pixel array in which a plurality of light receiving pixels are arranged in a matrix. Each light receiving pixel includes: a light receiving area that photoelectrically converts incident light into a signal charge; and a pair of electrodes to which a voltage is alternately applied to generate an electric field in the light receiving area that time-divides the signal charge and distributes the signal charge to a pair of charge accumulation electrodes. (For example, see Patent Document 1).

[0003] Reference List

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2011-86904. Summary of the Invention

[0006] Problems to be solved by the present invention

[0007] However, as light-receiving pixels become thinner, charge collection efficiency decreases.

[0008] Therefore, the present disclosure proposes a light receiving element, an imaging element, and an imaging device capable of improving charge collection efficiency.

[0009] Solution to the problem

[0010] According to the present disclosure, a light receiving element is provided. The light receiving element includes a sensor substrate and a circuit board. The sensor substrate is provided with a light receiving area, a pair of voltage applying electrodes and an incident surface electrode. The light receiving area photoelectrically converts incident light into signal charge. The pair of voltage applying electrodes alternately apply voltage to generate an electric field in the light receiving area that time-divides the signal charge and distributes the signal charge to a pair of charge accumulation electrodes. The incident surface electrode is provided on the incident surface of light in the light receiving area and is applied with a voltage equal to or less than the ground potential. The circuit board is provided on the surface of the sensor substrate opposite to the incident surface of light. The circuit board is provided with pixel transistors that process the signal charge accumulated in the charge accumulation electrodes. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a diagram illustrating a configuration example of a solid-state imaging element as an example of a light receiving element according to the present disclosure.

[0012] Figure 2 is a diagram illustrating a configuration example of a pixel according to the present disclosure.

[0013] Figure 3 is a diagram illustrating a configuration example of a part of a signal extraction portion of a pixel according to the present disclosure.

[0014] Figure 4 is a diagram illustrating a circuit configuration example of a pixel according to the present disclosure.

[0015] Figure 5 is a diagram illustrating a connection mode between a circuit board and a sensor substrate according to the present disclosure.

[0016] Figure 6 It is an explanatory diagram of the incident surface electrode and the pixel separation area according to the present disclosure.

[0017] Figure 7A is a diagram illustrating a configuration example of a pixel separation area according to the present disclosure.

[0018] Figure 7B is a diagram illustrating a configuration example of a pixel separation area according to the present disclosure.

[0019] Figure 7C is a diagram illustrating a configuration example of a pixel separation area according to the present disclosure.

[0020] Figure 8 is an explanatory diagram of a pixel separation area according to the first modification of the present disclosure.

[0021] Figure 9 is an explanatory diagram of a pixel separation area according to a second modification of the present disclosure.

[0022] Figure 10 : is a diagram showing an arrangement example of pixel separation areas according to the present disclosure. DETAILED DESCRIPTION

[0023] Hereinafter, embodiments of the present disclosure will be described in detail based on the accompanying drawings. Note that in each of the following embodiments, the same reference numerals are used for the same parts, and repeated descriptions are omitted.

[0024] [1. Configuration Example of Solid-State Imaging Element]

[0025] For example, the present technology can be applied to a solid-state imaging element constituting a distance measurement system that performs distance measurement using an indirect time-of-flight (ToF) method, an imaging device including such a solid-state imaging element, and the like.

[0026] For example, the distance measurement system can be applied to an in-vehicle system that is installed on a vehicle and measures the distance to an object outside the vehicle, a gesture recognition system that measures the distance to an object such as a user's hand and recognizes the user's gesture based on the measurement result, etc.

[0027] In this case, the result of gesture recognition can be used, for example, to operate a car navigation system.

[0028] Figure 1 is a diagram illustrating a configuration example of a solid-state imaging element as an example of a light receiving element according to the present disclosure. Figure 1 The solid-state imaging element 11 shown is a back-illuminated current-assisted photon demodulator (CAPD) sensor, and is provided in an imaging device having a distance measurement function.

[0029] The solid-state imaging element 11 includes a circuit board 101 and a sensor substrate 102 stacked on the circuit board 101. The sensor substrate 102 is provided with a pixel array unit 21 in which a plurality of light receiving pixels (hereinafter, simply referred to as "pixels") are arranged in a matrix.

[0030] The circuit board 101 is provided with peripheral circuits. Examples of these peripheral circuits include a vertical drive unit 22, a column processing unit 23, a horizontal drive unit 24, and a system control unit 25. For example, the vertical drive unit 22 includes a pixel transistor that processes the signal charge photoelectrically converted at each pixel. Note that, to facilitate understanding of the connection relationship between the components of the circuit board 101 and the components of the sensor substrate 102, these components are shown on the same plane.

[0031] As described above, in the solid-state imaging element 11, the pixels of the pixel array unit 21 are provided on the sensor substrate 102, and the pixel transistors are provided on the circuit board 101, thereby improving the charge collection efficiency and reducing the power consumption. Figure 3 Describe this.

[0032] The solid-state imaging element 11 is further provided with a signal processing unit 26 and a data storage unit 27. Note that the signal processing unit 26 and the data storage unit 27 may be mounted on the same substrate as the solid-state imaging element 11, or may be provided on a substrate different from the solid-state imaging element 11 in the imaging device.

[0033] The pixel array unit 21 has a configuration in which pixels that generate electric charge according to the amount of light received and output signals based on the electric charge are arranged two-dimensionally in the row and column directions, that is, in a matrix. In other words, the pixel array unit 21 includes a plurality of pixels that photoelectrically convert incident light and output signals corresponding to the resulting electric charge.

[0034] Here, the row direction refers to the arrangement direction of pixels in a pixel row (i.e., the horizontal direction), and the column direction refers to the arrangement direction of pixels in a pixel column (i.e., the vertical direction). In other words, the row direction is the horizontal direction in the figure, and the column direction is the vertical direction in the figure.

[0035] In the pixel array unit 21, with respect to the pixel array in the matrix, the pixel drive line 28 is wired along the row direction of each pixel row, and two vertical signal lines 29 are wired along the column direction of each pixel column. For example, the pixel drive line 28 transmits a drive signal for performing drive when reading out a signal from a pixel. Note that in Figure 1 , the pixel driving line 28 is shown as one wiring, but the pixel driving line 28 is not limited to one wiring. One end of the pixel driving line 28 is connected to the output end corresponding to each row of the vertical driving unit 22.

[0036] The vertical drive unit 22 includes a shift register, an address decoder, and the like, and drives all pixels of the pixel array unit 21 simultaneously or in row units. In other words, the vertical drive unit 22, together with the system control unit 25 that controls the vertical drive unit 22, constitutes a drive unit that controls the operation of each pixel of the pixel array unit 21.

[0037] The signal output from each pixel of the pixel row according to the drive control of the vertical drive unit 22 is input to the column processing unit 23 through the vertical signal line 29. The column processing unit 23 performs predetermined signal processing on the signal output from each pixel through the vertical signal line 29 and temporarily stores the pixel signal after the signal processing.

[0038] Specifically, the column processing unit 23 performs noise removal processing, analog-to-digital (AD) conversion processing, and the like as signal processing.

[0039] The horizontal driving unit 24 includes a shift register, an address decoder, etc., and sequentially selects unit circuits corresponding to pixel columns of the column processing unit 23. Through selective scanning by the horizontal driving unit 24, pixel signals subjected to signal processing for each unit circuit in the column processing unit 23 are sequentially output.

[0040] The system control unit 25 includes a timing generator that generates various timing signals and the like, and performs drive control of the vertical drive unit 22 , the column processing unit 23 , the horizontal drive unit 24 and the like based on the various timing signals generated by the timing generator.

[0041] The signal processing unit 26 has at least an arithmetic processing function and performs various signal processes such as arithmetic processing based on the pixel signal output from the column processing unit 23. The data storage unit 27 temporarily stores data necessary for the signal processing in the signal processing unit 26.

[0042] [2. Example of pixel configuration]

[0043] Next, a configuration example of pixels provided in the pixel array unit 21 will be described. For example, the pixels provided in the pixel array unit 21 are configured as follows Figure 2 shown.

[0044] Figure 2 A cross section of one pixel 51 provided in the pixel array unit 21 is shown, and the pixel 51 receives and photoelectrically converts light (especially infrared light) incident on the light receiving area 103 from the outside and outputs a signal corresponding to the charge obtained as a result.

[0045] The pixel 51 includes, for example, a silicon substrate (ie, a sensor substrate 102 including a P-type semiconductor substrate having a P-type semiconductor region) and an on-chip lens 62 as an example of an imaging optical system formed on the sensor substrate 102. The sensor substrate 102 is stacked on the circuit board 101.

[0046] The circuit board 101 is provided with pixel transistors such as a transfer transistor, a reset transistor, an amplifying transistor, and a selection transistor which will be described later. Figure 4 An example of the circuit configuration of the circuit board 101 is described.

[0047] In the accompanying drawings, on the upper surface of the sensor substrate 102, that is, on the surface on the side of the light receiving area 103 on which light is incident from the outside (hereinafter also referred to as the incident surface), an on-chip lens 62 is formed, which collects light incident from the outside and allows the light to be incident on the light receiving area 103.

[0048] Furthermore, in the pixel 51 , an inter-pixel light shielding portion 63 - 1 and an inter-pixel light shielding portion 63 - 2 for preventing color mixture between adjacent pixels are formed at the end portion of the pixel 51 on the incident surface of the light receiving region 103 .

[0049] Furthermore, in the sensor substrate 102, an incident surface electrode 104 to which a voltage equal to or less than a ground potential is applied is provided on the incident surface in the light receiving region 103, thereby improving the charge collection efficiency. Figure 6 Describe this.

[0050] An oxide film 64 and signal extraction portions 65 - 1 and 65 - 2 called taps are formed on the surface side opposite to the incident surface in the light receiving region 103 , ie, at a portion inside the surface of the lower portion in the figure.

[0051] In this example, an oxide film 64 is formed in the central portion of the pixel 51 near the surface of the light receiving region 103 opposite to the incident surface, and a signal extraction portion 65 - 1 and a signal extraction portion 65 - 2 are formed at both ends of the oxide film 64 .

[0052] Here, the signal extraction portion 65 - 1 includes an N + semiconductor region 71 - 1 and an N − semiconductor region 72 - 1 as N-type semiconductor regions, and a P + semiconductor region 73 - 1 and a P − semiconductor region 74 - 1 as P-type semiconductor regions.

[0053] In other words, the N+ semiconductor region 71-1 is formed at a portion adjacent to the right side of the oxide film 64 in the drawing at an inner portion of the surface of the light receiving region 103 on the side opposite to the incident surface. In addition, the N- semiconductor region 72-1 is formed on the upper side of the N+ semiconductor region 71-1 in the drawing so as to cover (surround) the N+ semiconductor region 71-1.

[0054] Furthermore, a P+ semiconductor region 73-1 is formed at a portion adjacent to the right side in the drawing of the N+ semiconductor region 71-1 at an inner portion of the surface on the side opposite to the incident surface of the light receiving region 103. Furthermore, a P- semiconductor region 74-1 is formed on the upper side of the P+ semiconductor region 73-1 in the drawing so as to cover (surround) the P+ semiconductor region 73-1.

[0055] Note that although not shown here, more specifically, when the light receiving area 103 is observed from a direction perpendicular to the surface of the sensor substrate 102, the N+ semiconductor region 71-1 and the N- semiconductor region 72-1 are formed around the P+ semiconductor region 73-1 and the P- semiconductor region 74-1 to surround the P+ semiconductor region 73-1 and the P- semiconductor region 74-1.

[0056] Similarly, the signal extraction portion 65-2 includes an N- semiconductor region 72-2 having a lower donor impurity concentration than the N+ semiconductor region 71-2 and the N+ semiconductor region 71-2, which are N-type semiconductor regions, and a P- semiconductor region 74-2 having a lower acceptor impurity concentration than the P+ semiconductor region 73-2 and the P+ semiconductor region 73-2, which are P-type semiconductor regions. Here, examples of donor impurities include elements belonging to Group 5 of the periodic table, such as phosphorus (P) and arsenic (As) relative to Si. Examples of acceptor impurities include elements belonging to Group 3 of the periodic table, such as boron (B) relative to Si.

[0057] In other words, the N+ semiconductor region 71-2 is formed at a portion adjacent to the left side of the oxide film 64 in the drawing at an inner portion of the surface on the opposite side of the incident surface of the light receiving region 103. In addition, the N- semiconductor region 72-2 is formed on the upper side of the N+ semiconductor region 71-2 in the drawing so as to cover (surround) the N+ semiconductor region 71-2.

[0058] Furthermore, a P+ semiconductor region 73-2 is formed at a portion adjacent to the left side in the drawing of the N+ semiconductor region 71-2 at an inner portion of the surface on the side opposite to the incident surface of the light receiving region 103. Furthermore, a P- semiconductor region 74-2 is formed on the upper side of the P+ semiconductor region 73-2 in the drawing so as to cover (surround) the P+ semiconductor region 73-2.

[0059] Note that although not shown here, more specifically, when the light receiving area 103 is observed from a direction perpendicular to the surface of the sensor substrate 102, the N+ semiconductor region 71-2 and the N- semiconductor region 72-2 are formed around the P+ semiconductor region 73-2 and the P- semiconductor region 74-2 to surround the P+ semiconductor region 73-2 and the P- semiconductor region 74-2.

[0060] Hereinafter, in the case where there is no need to particularly distinguish the signal extraction section 65 - 1 and the signal extraction section 65 - 2 , the signal extraction section 65 - 1 and the signal extraction section 65 - 2 will also be simply referred to as the signal extraction section 65 .

[0061] In addition, in the following, when there is no need to specifically distinguish between the N+ semiconductor region 71-1 and the N+ semiconductor region 71-2, the N+ semiconductor region 71-1 and the N+ semiconductor region 71-2 will also be referred to as the N+ semiconductor region 71, and when there is no need to specifically distinguish between the N- semiconductor region 72-1 and the N- semiconductor region 72-2, the N- semiconductor region 72-1 and the N- semiconductor region 72-2 will also be referred to as the N- semiconductor region 72.

[0062] In addition, in the following, when there is no need to specifically distinguish between the P+ semiconductor region 73-1 and the P+ semiconductor region 73-2, the P+ semiconductor region 73-1 and the P+ semiconductor region 73-2 will also be referred to as the P+ semiconductor region 73, and when there is no need to specifically distinguish between the P- semiconductor region 74-1 and the P- semiconductor region 74-2, the P- semiconductor region 74-1 and the P- semiconductor region 74-2 will also be referred to as the P- semiconductor region 74.

[0063] Furthermore, in the light receiving region 103, a separation portion 75-1 is formed between the N+ semiconductor region 71-1 and the P+ semiconductor region 73-1 using an oxide film or the like to separate the N+ semiconductor region 71-1 and the P+ semiconductor region 73-1 from each other. Similarly, a separation portion 75-2 is also formed between the N+ semiconductor region 71-2 and the P+ semiconductor region 73-2 using an oxide film or the like to separate the N+ semiconductor region 71-2 and the P+ semiconductor region 73-2 from each other. Hereinafter, in the absence of a need to specifically distinguish between the separation portion 75-1 and the separation portion 75-2, the separation portion 75-1 and the separation portion 75-2 will also be referred to simply as the separation portion 75.

[0064] The N+ semiconductor region 71 provided in the light receiving region 103 serves as a detection unit for detecting the amount of light incident on the pixel 51 from the outside (that is, the amount of signal carrier generated by photoelectric conversion in the light receiving region 103). In addition, the P+ semiconductor region 73 serves as an injection contact portion for injecting a majority carrier current into the light receiving region 103 (that is, for generating an electric field in the light receiving region 103 by directly applying a voltage to the light receiving region 103).

[0065] In the pixel 51, the floating diffusion (FD) portion (hereinafter, also specifically referred to as the FD portion A) which is a floating diffusion region not shown is directly connected to the N+ semiconductor region 71-1, and the FD portion A is further connected to the vertical signal line 29 via an amplifying transistor, etc. (not shown).

[0066] Similarly, another FD portion different from the FD portion A (hereinafter, also particularly referred to as the FD portion B) is directly connected to the N + semiconductor region 71-2, and the FD portion B is further connected to the vertical signal line 29 via an amplifying transistor or the like (not shown). Here, the FD portion A and the FD portion B are connected to different vertical signal lines 29.

[0067] For example, when measuring the distance to an object using the indirect ToF method, infrared light is emitted toward the object from an imaging device provided with the solid-state imaging element 11. Then, when the infrared light is reflected by the object and returns to the imaging device as reflected light, the light receiving area 103 of the solid-state imaging element 11 receives and photoelectrically converts the incident reflected light (infrared light).

[0068] In this case, the vertical drive unit 22 drives the pixel 51 and distributes a signal corresponding to the charge obtained by the photoelectric conversion to the FD portion A and the FD portion B. Note that, as described above, the pixel 51 may be driven not by the vertical drive unit 22 but by a separately provided drive unit, the horizontal drive unit 24, or the like via the vertical signal line 29 or another control line extending in the vertical direction.

[0069] For example, at a specific timing, the vertical drive unit 22 applies a voltage to the two P+ semiconductor regions 73 via contacts, etc. Specifically, for example, the vertical drive unit 22 applies a voltage of 1.5V to the P+ semiconductor region 73-1 and a voltage of 0V to the P+ semiconductor region 73-2.

[0070] Then, an electric field is generated between the two P+ semiconductor regions 73 in the light receiving region 103, and current flows from the P+ semiconductor region 73-1 to the P+ semiconductor region 73-2. In this case, the holes (holes) in the light receiving region 103 move in the direction of the P+ semiconductor region 73-2, and the electrons move in the direction of the P+ semiconductor region 73-1.

[0071] Therefore, in this state, when infrared light (reflected light) from the outside is incident on the light receiving area 103 via the on-chip lens 62, and the infrared light is photoelectrically converted into electron and hole pairs in the light receiving area 103, the obtained electrons are guided in the direction of the P+ semiconductor region 73 through the electric field between the P+ semiconductor regions 73-1 and move to the N+ semiconductor region 71-1.

[0072] In this case, the electrons generated by the photoelectric conversion serve as signal carriers for detecting a signal corresponding to the amount of infrared light incident on the pixel 51 (ie, the amount of received infrared light).

[0073] Therefore, in the N+ semiconductor region 71-1, charges according to electrons moving into the N+ semiconductor region 71-1 are accumulated, and the charges are detected by the column processing unit 23 via the FD portion A, the amplifying transistor, the vertical signal line 29, and the like.

[0074] In other words, the charge accumulated in the N+ semiconductor region 71-1 is transferred to the FD portion A directly connected to the N+ semiconductor region 71-1, and a signal corresponding to the charge transferred to the FD portion A is read out by the column processing unit 23 via the amplifying transistor and the vertical signal line 29. Then, processing such as AD conversion processing is performed on the read signal in the column processing unit 23, and the obtained pixel signal is supplied as a result to the signal processing unit 26.

[0075] The pixel signal is a signal indicating the amount of charge according to electrons detected by the N+ semiconductor region 71-1 (ie, the amount of charge accumulated in the FD portion A). In other words, the pixel signal can also be said to be a signal indicating the amount of infrared light received by the pixel 51.

[0076] Furthermore, at the next timing, a voltage is applied to the two P+ semiconductor regions 73 via contacts or the like by the vertical drive unit 22, thereby generating an electric field in the opposite direction to the electric field generated so far in the light receiving region 103. Specifically, for example, a voltage of 1.5 V is applied to the P+ semiconductor region 73-2, and a voltage of 0 V is applied to the P+ semiconductor region 73-1.

[0077] Therefore, an electric field is generated between the two P + semiconductor regions 73 in the light receiving area 103 , and current flows from the P + semiconductor region 73 - 2 to the P + semiconductor region 73 - 1 .

[0078] In this state, when infrared light (reflected light) from the outside is incident on the light receiving area 103 via the on-chip lens 62, and the infrared light is photoelectrically converted into electron and hole pairs in the light receiving area 103, the obtained electrons are guided in the direction of the P+ semiconductor region 73 by the electric field between the P+ semiconductor regions 73-2 and move to the N+ semiconductor region 71-2.

[0079] Therefore, in the N+ semiconductor region 71-2, charges according to electrons moving into the N+ semiconductor region 71-2 are accumulated, and the charges are detected by the column processing unit 23 via the FD portion B, the amplifying transistor, the vertical signal line 29, and the like.

[0080] In other words, the charges accumulated in the N+ semiconductor region 71-2 are transferred to the FD portion B directly connected to the N+ semiconductor region 71-2, and a signal corresponding to the charges transferred to the FD portion B is read out by the column processing unit 23 via the amplifying transistor and the vertical signal line 29. Then, processing such as AD conversion processing is performed on the read signal in the column processing unit 23, and the obtained pixel signal is supplied as a result to the signal processing unit 26.

[0081] In this manner, when pixel signals obtained by photoelectric conversion of different periods are obtained in the same pixel 51 , the signal processing unit 26 calculates distance information indicating the distance to the object based on these pixel signals and outputs the distance information to the subsequent stage.

[0082] A method of allocating signal carrier waves to N+ semiconductor regions 71 different from each other in this manner and calculating distance information based on signals corresponding to the signal carrier waves is referred to as an indirect ToF method.

[0083] In addition, when Figure 2 When a portion of the signal extraction portion 65 in the pixel 51 is observed from top to bottom in FIG. 1 (ie, in a direction perpendicular to the surface of the light receiving region 103), for example, as Figure 3As shown, this portion has a structure in which a P+ semiconductor region 73 is surrounded by an N+ semiconductor region 71. Note that Figure 3 In, with Figure 2 The corresponding parts in FIG are denoted by the same reference numerals, and description thereof will be appropriately omitted.

[0084] exist Figure 3 In the example shown, an oxide film 64 (not shown) is formed in the center portion of the pixel 51, and a signal extraction portion 65 is formed in a portion slightly closer to the end of the pixel 51 from the center. Specifically, two signal extraction portions 65 are formed in the pixel 51.

[0085] Then, in each signal extraction portion 65, a P+ semiconductor region 73 is formed in a rectangular shape at the center position, and the P+ semiconductor region 73 is surrounded by an N+ semiconductor region 71 having a rectangular shape (more specifically, a rectangular frame shape) around the P+ semiconductor region 73. In other words, the N+ semiconductor region 71 is formed to surround the periphery of the P+ semiconductor region 73.

[0086] Furthermore, in the pixel 51, the on-chip lens 62 is formed so that infrared light incident from the outside is focused on the center portion of the pixel 51, that is, the portion indicated by the arrow A11. In other words, the infrared light incident on the on-chip lens 62 from the outside is focused by the on-chip lens 62 at the position indicated by the arrow A11, that is, Figure 2 The oxide film 64 Figure 2 The upper position in the middle.

[0087] Here, in a general pixel used for distance measurement using an indirect ToF method, the signal extraction section 65 and the pixel transistor are provided in the same layer in the sensor substrate 102. Therefore, as the pixel becomes thinner, the distance between the signal extraction section 65 and the pixel transistor becomes shorter, and current leaks from the signal extraction section 65 to the pixel transistor side, resulting in a decrease in charge collection efficiency.

[0088] Specifically, as described above, the pixel alternately applies a predetermined voltage to a pair of P+ semiconductor regions 73, sequentially causes bidirectional current to flow between the P+ semiconductor region 73-1 and the P+ semiconductor region 73-2, and distributes the charge obtained by photoelectric conversion to the FD portion A and the FD portion B.

[0089] However, when the pixel becomes thinner and the distance between the signal extraction section 65 and the pixel transistor becomes shorter, part of the current that should originally flow between the P+ semiconductor region 73-1 and the P+ semiconductor region 73-2 leaks to the Pwell region of the pixel transistor.

[0090] Therefore, not only does the power consumption of the pixel increase, but the intensity of the electric field generated in the light receiving area for guiding charges to the signal extraction part 65 decreases, which results in a decrease in the charges to be captured by the N+ semiconductor region 71, thereby resulting in a decrease in charge collection efficiency.

[0091] Therefore, in the pixel 51 according to the present disclosure, the pixel transistor is provided on the circuit board 101 , and the light receiving area 103 including the signal extraction portion 65 is provided on the sensor substrate 102 stacked on the circuit board 101 .

[0092] As described above, in the pixel 51 , the signal extraction portion 65 and the pixel transistor are provided on different stacked substrates, and therefore, even if the pixel 51 becomes thinner in the planar direction, the distance between the signal extraction portion 65 and the pixel transistor does not become shorter.

[0093] Therefore, in the case where the pixel 51 becomes thinner, power consumption can be reduced and charge collection efficiency can be improved by preventing current from leaking from the signal extraction portion 65 to the pixel transistor.

[0094] [3. Circuit Configuration Example of Pixel]

[0095] Next, we will refer to Figure 4 A circuit configuration example of a pixel according to the present disclosure is described. Figure 4 is a diagram illustrating a circuit configuration example of a pixel according to the present disclosure.

[0096] like Figure 4 As shown, in the pixel 51, the signal extraction portion 65-1 including the N+ semiconductor region 71-1, the P+ semiconductor region 73-1, etc. is provided on the sensor substrate 102. The circuit board 101 is provided with a transfer transistor 721A, an FD 722A, a reset transistor 723A, an amplifying transistor 724A, and a selecting transistor 725A as pixel transistors corresponding to the signal extraction portion 65-1.

[0097] Furthermore, in the pixel 51, a signal extraction portion 65-2 including an N+ semiconductor region 71-2, a P+ semiconductor region 73-2, and the like is provided on the sensor substrate 102. The circuit board 101 is provided with a transfer transistor 721B, an FD 722B, a reset transistor 723B, an amplifying transistor 724B, and a selecting transistor 725B as pixel transistors corresponding to the signal extraction portion 65-2.

[0098] The vertical drive unit 22 applies a predetermined voltage MIX0 to the P+ semiconductor region 73-1 and a predetermined voltage MIX1 to the P+ semiconductor region 73-2. In the above example, one of the voltages MIX0 and MIX1 is 1.5 V and the other is 0 V. The P+ semiconductor regions 73-1 and 73-2 are voltage applying electrodes to which the predetermined voltages are applied.

[0099] The N + semiconductor regions 71 - 1 and 71 - 2 are charge accumulation electrodes that detect and accumulate charges generated by photoelectric conversion of light incident on the light receiving region 103 .

[0100] When the drive signal TRG supplied to the gate electrode becomes active, the transfer transistor 721A is turned on in response thereto, thereby transferring the charge accumulated in the N+ semiconductor region 71-1 to the FD 722A. When the drive signal TRG supplied to the gate electrode becomes active, the transfer transistor 721B is turned on in response thereto, thereby transferring the charge accumulated in the N+ semiconductor region 71-2 to the FD 722B.

[0101] The FD 722A temporarily stores the charge supplied from the N+ semiconductor region 71-1. The FD 722B temporarily stores the charge supplied from the N+ semiconductor region 71-2. The FD 722A corresponds to the reference Figure 2 FD portion A is described, and FD 722B corresponds to FD portion B.

[0102] When the drive signal RST supplied to the gate electrode becomes active, the reset transistor 723A is turned on in response to this, thereby resetting the potential of the FD 722A to a predetermined level (reset voltage VDD). When the drive signal RST supplied to the gate electrode becomes active, the reset transistor 723B is turned on in response to this, thereby resetting the potential of the FD 722B to a predetermined level (reset voltage VDD). Note that when the reset transistors 723A and 723B are activated, the transfer transistors 721A and 721B are also simultaneously activated.

[0103] The source electrode of the amplifier transistor 724A is connected to the vertical signal line 29A via the selection transistor 725A, thereby forming a source-follower circuit having a load MOS electrode of a constant current source circuit unit 726A connected to one end of the vertical signal line 29A. The source electrode of the amplifier transistor 724B is connected to the vertical signal line 29B via the selection transistor 725B, thereby forming a source-follower circuit having a load MOS electrode of a constant current source circuit unit 726B connected to one end of the vertical signal line 29B.

[0104] The selection transistor 725A is connected between the source electrode of the amplifier transistor 724A and the vertical signal line 29A. When the selection signal SEL supplied to the gate electrode becomes active, the selection transistor 725A becomes conductive and outputs the pixel signal output from the amplifier transistor 724A to the vertical signal line 29A.

[0105] The selection transistor 725B is connected between the source electrode of the amplifier transistor 724B and the vertical signal line 29B. When the selection signal SEL supplied to the gate electrode becomes active, the selection transistor 725B becomes conductive and outputs the pixel signal output from the amplifier transistor 724B to the vertical signal line 29B.

[0106] The transfer transistors 721A and 721B, the reset transistors 723A and 723B, the amplification transistors 724A and 724B, and the selection transistors 725A and 725B of the pixel 51 are controlled by, for example, the vertical drive unit 22 .

[0107] As described above, in the pixel 51 , the signal extraction portion 65 is provided on the sensor substrate 102 , and the pixel transistor is provided on the circuit board 101 , which prevents current from leaking from the signal extraction portion 65 to the pixel transistor, thereby improving charge collection efficiency.

[0108] Furthermore, in pixel 51, light receiving region 103 including signal extraction section 65 is formed of, for example, a III-V semiconductor such as GaAs or InGaAs. Therefore, pixel 51 can improve quantum efficiency and sensitivity through a direct-transition band structure, and can also reduce sensor height by thinning the substrate.

[0109] Furthermore, the light receiving region 103 including the signal extraction portion 65 may be formed of, for example, Ge, GaSb, etc. In this case, the pixel 51 can improve electron collection efficiency through high electron mobility and reduce power consumption through low hole mobility.

[0110] [4. Connection mode between the circuit board and the sensor substrate]

[0111] Next, we will refer to Figure 5 Describe the connection pattern between the circuit board and the sensor substrate. Figure 5 is a diagram illustrating a connection mode between a circuit board and a sensor substrate according to the present disclosure.

[0112] Figure 5 A Cu-Cu joint MIX connecting the wiring on the sensor substrate 102 side and the wiring on the circuit board 101 side is indicated by a white circle. The wiring on the sensor substrate 102 side applies a predetermined voltage to the P+ semiconductor region 73 of the light receiving region 103. Figure 5A Cu-Cu joint DET connecting the wiring on the sensor substrate 102 side connected to the N + semiconductor region 71 of the light receiving region 103 and the wiring on the circuit board 101 side is indicated by a black circle.

[0113] like Figure 5 As shown, in pixel 51, Cu-Cu joints MIX are provided at two locations outside pixel array 21. In addition, Cu-Cu joints DET are provided at two locations for each pixel 51. In this way, compared with the case where a Cu-Cu joint MIX is provided for each pixel, the pixel 51 can be easily made thinner by reducing the number of Cu-Cu joints MIX. Note that the Cu-Cu joints MIX can be formed by through-chip vias (TCVs). In addition, the Cu-Cu joints MIX and DET can be formed by bumps.

[0114] [5. Incident surface electrode and pixel separation area]

[0115] Next, we will refer to Figure 6 The incident surface electrode and the pixel separation region according to the present disclosure are described. Figure 6 : is an illustration of the incident surface electrode and the pixel separation area according to the present disclosure. Figure 6 As shown, in the pixel 51, for example, when current flows from the signal extraction section 65-1 to the signal extraction section 65-2 in the light receiving area 103, the photoelectrically converted charge is induced from the signal extraction section 65-2 to the signal extraction section 65-1 as shown by the arrow by the electric field generated by the current.

[0116] Here, as the pixel 51 becomes thinner in the planar direction of the light incident surface, the interval between the signal extraction portion 65-1 and the signal extraction portion 65-2 becomes shorter, but the length of the light receiving region 103 in the thickness (depth) direction does not become shorter.

[0117] Therefore, in the case where the pixel 51 becomes thinner, even if current flows from the signal extraction portion 65-1 to the signal extraction portion 65-2, the electric field cannot sufficiently extend to the vicinity of the light incident surface in the light receiving area 103. Therefore, the pixel 51 cannot effectively guide the charge photoelectrically converted near the light incident surface in the light receiving area 103 to the signal extraction portion 65-2, resulting in a decrease in charge collection efficiency.

[0118] Therefore, in the pixel 51, the incident surface electrode 104 is provided on the light incident surface in the light receiving area 103. The incident surface electrode is connected to, for example, a ground (earthing) line or a negative voltage generating circuit provided on the circuit board 101, and 0 V or a negative voltage is applied thereto.

[0119] Therefore, in the pixel 51, when current flows from the signal extraction section 65-1 to the signal extraction section 65-2, current also flows from the signal extraction section 65-1 to the incident surface electrode 104. Therefore, the pixel 51 can effectively guide the charge photoelectrically converted near the light incident surface to the signal extraction section 65-1 as shown by the arrow by the electric field generated by the current flowing from the signal extraction section 65-2 to the incident surface electrode 104.

[0120] As described above, the pixel 51 includes an incident surface electrode 104 that applies a voltage equal to or less than the ground potential on the light incident surface, and therefore, even if the pixel becomes finer, the charge collection efficiency can be improved by guiding the charge photoelectrically converted near the light incident surface to the signal extraction part 65-1.

[0121] Note that the incident surface electrode 104 needs to transmit incident light and is therefore a transparent electrode. For example, the incident surface electrode 104 is a hole accumulation layer formed on the light incident surface of the light receiving region 103 by laminating a negative fixed charge film on the light incident surface.

[0122] Furthermore, the incident surface electrode 104 may be a P-type conductive layer doped with P-type impurities on the light incident surface in the light receiving region 103. Furthermore, the incident surface electrode 104 may be an inorganic electrode film, such as an indium tin oxide (ITO) film, laminated on the light incident surface in the light receiving region 103. Furthermore, the incident surface electrode 104 may be a metal film, such as a W film, having a light-transmitting film thickness (e.g., equal to or less than 50 nm) and laminated on the light incident surface in the light receiving region 103.

[0123] When any of the above-described incident surface electrodes 104 is provided, the pixel 51 can efficiently guide the charges photoelectrically converted near the light incident surface to the signal extraction portion 65 by the electric field generated by the current flowing from the signal extraction portion 65 to the incident surface electrode 104 .

[0124] Furthermore, the pixel 51 includes a pixel separation region 105 that electrically separates the light receiving region 103 from the light receiving region 103 of the adjacent pixel 51. The pixel separation region 105 is, for example, a deep trench isolation (DTI) formed between the pixels 51.

[0125] The pixel separation region 105 extends from the light incident surface in the light receiving region 103 to the middle portion toward the surface opposite to the light incident surface in the light receiving region 103. The pixel separation region 105 is provided to separate the pixel array 21 for each light receiving region 103, wherein a plurality of light receiving regions 103 provided for each pixel 51 are arranged in a matrix.

[0126] Therefore, each pixel 51 can confine the photoelectrically converted charge within the light receiving region 103 by the pixel separation region 105, thereby preventing the occurrence of electrical color mixing due to charge leakage to adjacent pixels 51. Next, a configuration example of the pixel separation region 105 will be described.

[0127] [6. Configuration Example of Pixel Separation Area]

[0128] 7A to 7C : is a diagram showing a configuration example of a pixel separation area according to the present disclosure. Figure 7A As shown, the pixel separation region 105A is composed of, for example, an insulator 106 such as SiO2. Therefore, in the pixel 51, as described above, the pixel separation region 105A can prevent electrical color mixing between the pixels 51. In addition, according to the pixel separation region 105A, by reflecting light incident on the light receiving region 103, optical color mixing caused by leakage of incident light to the adjacent pixel 51 can be prevented.

[0129] In addition, if Figure 7B As shown, the pixel separation region 105B may be composed of a metal 108 having an insulating film 107 such as SiO2 provided on its surface. According to the pixel separation region 105B, the metal 108 functions as a light shielding film, so that optical color mixing caused by incident light leaking to adjacent pixels 51 can be prevented.

[0130] In addition, if Figure 7C As shown, the pixel separation region 105C may be formed of an insulator 106 such as SiO2 with a negative fixed charge film 109 provided on the surface. According to the pixel separation region 105C, the negative fixed charge film 109 can reduce dark current and white spots generated on the surface of the pixel separation region 105C while maintaining the electric field distribution of the light receiving region 103.

[0131] In addition, you can 7A to 7C The pixel separation regions 105A, 105B, and 105C are shown in an electrically floating state. In this case, in the pixel 51, the current flowing from the signal extraction portion 65 to the incident surface electrode 104 flows more uniformly in the light receiving region 103, so that even if the pixel 51 becomes thinner, the desired electric field can be formed up to the vicinity of the incident surface electrode 104.

[0132] In addition, a voltage equal to or lower than the ground potential can be applied to the metal 108 in the pixel separation region 105B and the negative fixed charge film 109 in the pixel separation region 105C. In this case, in the pixel 51, Si in the light receiving region 103 near the pixel separation regions 105B and 105C is fixed to P type, so that dark current and white spots generated on the surfaces of the pixel separation regions 105B and 105C can be reduced.

[0133] As described above, in pixel 51, optical and electrical color mixing are prevented by pixel separation regions 105A, 105B, and 105C, thereby improving the resolution of luminance images and distance images and reducing noise caused by dark current, etc. Furthermore, in the case of strong background light, the sensitivity of pixel 51 can be reduced by making the voltage applied to incident surface electrode 104 close to 0V.

[0134] [7. Modification of pixel separation area]

[0135] Next, we will refer to Figures 8 to 10 Modifications and arrangement examples of pixel separation areas are described. Figure 8 is an explanatory diagram of a pixel separation area according to the first modification of the present disclosure. Figure 9 is an explanatory diagram of a pixel separation area according to a second modification of the present disclosure. Figure 10 : is a diagram showing an arrangement example of pixel separation areas according to the present disclosure.

[0136] like Figure 8 As shown, the pixel 51A according to the first modification includes a pixel separation region 110 that extends from the light incident surface of the light receiving region 103 to the surface of the sensor substrate 102 opposite to the light incident surface. The pixel separation region 110 is formed of, for example, an insulator such as SiO2. The pixel separation region 110 is provided so as to penetrate the front and rear surfaces of the sensor substrate 102, so that optical and electrical color mixing can be more reliably prevented from occurring between adjacent pixels 51A.

[0137] In addition, if Figure 9 As shown, the pixel separation region 110A included in the pixel 51B according to the second modification is provided to penetrate the front and rear surfaces of the sensor substrate 102, but has the same Figure 8 The pixel isolation regions 110 are shown in different configurations.

[0138] The pixel separation region 110A is composed of a metal 108 with an insulating film 107 such as SiO provided on the surface. Figure 10 As shown, the pixel separation region 110A is provided at a corner of a plurality of light receiving regions 103 having a rectangular shape in a plan view and arranged in a matrix, and connects the incident surface electrode 104 and a ground wiring or a negative voltage generating circuit.

[0139] In the pixel separation region 110A, for example, the ground (earthing) terminal of the sensor substrate 102 and each incident surface electrode 104 may be connected by a low-resistance wiring on the surface side opposite to the light incident surface in the light receiving region 103 or a low-resistance wiring on the circuit board 101. With this arrangement, a voltage drop due to wiring resistance is prevented in the incident surface electrode 104.

[0140] Furthermore, in the case where the pixel separation region 110A is provided at a corner portion of the light receiving region 103 having a rectangular shape in a plan view, for example, Figure 6 The pixel separation region 105 shown is provided on the periphery of the light receiving region 103 excluding corner portions in a plan view.

[0141] Therefore, in each light receiving region 103 , most of the periphery except for corners in a plan view is surrounded by the pixel separation region 105 extending from the light incident surface in the light receiving region 103 to the middle portion in the depth direction.

[0142] Therefore, most of the current flowing from the signal extraction section 65 to the incident surface electrode 104 flows uniformly in the light receiving area 103 , so that even if the pixel 51 becomes thinner, a desired electric field can be formed up to the vicinity of the incident surface electrode 104 .

[0143] Note that the effects described in this specification are merely examples and are not limiting, and other effects may be provided.

[0144] Note that the present technology can also have the following configurations. (1)

[0146] A light receiving element, comprising:

[0147] A sensor substrate is provided with:

[0148] The light receiving area converts the incident light into signal charges photoelectrically;

[0149] a pair of voltage applying electrodes to which voltage is alternately applied to generate an electric field that time-divides signal charges in the light receiving area and distributes the signal charges to the pair of charge accumulation electrodes; and

[0150] an incident surface electrode provided on the incident surface of light in the light receiving region and to which a voltage equal to or lower than a ground potential is applied; and

[0151] A circuit board is provided with:

[0152] The pixel transistor is provided on a surface of the sensor substrate opposite to the light incident surface and processes the signal charge accumulated in the charge accumulation electrode. (2)

[0154] The light receiving element according to (1), wherein

[0155] The incident surface electrode is a hole accumulation layer formed on the incident surface by laminating a negative fixed charge film on the incident surface of light. (3)

[0157] The light receiving element according to (1), wherein

[0158] The incident surface electrode is a P-type conductive layer doped with P-type impurities on the incident surface of light. (4)

[0160] The light receiving element according to (1), wherein

[0161] The incident surface electrode is an inorganic electrode film laminated on the light incident surface. (5)

[0163] The light receiving element according to (1), wherein

[0164] The incident surface electrode is a metal film having a light-transmitting film thickness and laminated on the light incident surface. (6)

[0166] The light receiving element according to any one of (1) to (6), further comprising:

[0167] The pixel separation region is provided between the plurality of light receiving regions arranged in a matrix and electrically separates adjacent light receiving regions. (7)

[0169] The light receiving element according to (6), wherein

[0170] The pixel separation region reaches from the incident surface of light to a middle portion of a surface opposite to the incident surface in the light receiving region. (8)

[0172] The light receiving element according to (7), wherein

[0173] The pixel separation region divides a pixel array in which a plurality of light receiving regions are arranged in a matrix for each of the light receiving regions, and electrically floats the pixel separation region. (9)

[0175] The light receiving element according to (6), wherein

[0176] The pixel separation region extends from the light incident surface to the surface of the sensor substrate opposite to the light incident surface. (10)

[0178] The light receiving element according to (9), wherein

[0179] The pixel separation region is provided at a corner portion of a plurality of light receiving regions having a rectangular shape in a plan view arranged in a matrix, and connects the incident surface electrode and a ground wiring or a negative voltage generating circuit. (11)

[0181] A light receiving element according to any one of (6) 55 (10), wherein

[0182] The pixel separation region is formed of an insulator. (12)

[0184] A light receiving element according to any one of (6) 55 (10), wherein

[0185] The pixel separation region is formed of a metal with an insulating film provided on the surface. (13)

[0187] A light receiving element according to any one of (6) 55 (10), wherein

[0188] The pixel separation region is composed of an insulator with a negative fixed charge film provided on the surface. (14)

[0190] An imaging element, comprising:

[0191] A sensor substrate is provided with:

[0192] a pixel array in which a plurality of light receiving regions that photoelectrically convert incident light into signal charges are arranged in a matrix;

[0193] a pair of voltage applying electrodes to which a voltage is alternately applied for each of the light receiving regions to generate an electric field that time-divides signal charge and distributes the signal charge to the pair of charge accumulation electrodes in each of the light receiving regions; and

[0194] an incident surface electrode provided on the incident surface of light in each of the light receiving regions and to which a voltage equal to or lower than a ground potential is applied; and

[0195] A circuit board is provided with:

[0196] The pixel transistor is provided on a surface of the sensor substrate opposite to the light incident surface and processes the signal charge accumulated in the charge accumulation electrode. (15)

[0198] An imaging device, comprising:

[0199] Imaging optical system;

[0200] A sensor substrate is provided with:

[0201] a pixel array in which a plurality of light receiving regions that photoelectrically convert incident light into signal charges are arranged in a matrix;

[0202] a pair of voltage applying electrodes to which a voltage is alternately applied for each of the light receiving regions to generate an electric field that time-divides signal charge and distributes the signal charge to the pair of charge accumulation electrodes in each of the light receiving regions; and

[0203] an incident surface electrode provided on the incident surface of light in each of the light receiving regions and to which a voltage equal to or lower than a ground potential is applied; and

[0204] A circuit board is provided with:

[0205] The pixel transistor is provided on a surface of the sensor substrate opposite to the light incident surface and processes the signal charge accumulated in the charge accumulation electrode.

[0206] Reference Mark List

[0207] 11 Solid-state imaging element

[0208] 21 pixel array unit

[0209] 22 vertical drive units

[0210] 51 pixels

[0211] 62 On-chip lens

[0212] 71-1, 71-2, 71 N+ semiconductor regions

[0213] 73-1, 73-2, 73 P+ semiconductor regions

[0214] 721A, 721B pass transistors

[0215] 722A, 722B FD

[0216] 723A, 723B reset transistors

[0217] 724A, 724B amplifier transistors

[0218] 725A, 725B select transistors.

Claims

1. A light receiving element, comprising: A sensor substrate is provided with: The light receiving area converts the incident light into signal charges photoelectrically; a pair of voltage applying electrodes to which voltage is alternately applied to generate an electric field in the light receiving area that time-divides the signal charge and distributes the signal charge to a pair of charge accumulation electrodes; as well as an incident surface electrode provided on the light incident surface of the light receiving region and to which a voltage equal to or lower than a ground potential is applied; as well as A circuit board is provided with: a pixel transistor provided on a surface of the sensor substrate opposite to the incident surface of the light and processing the signal charge accumulated in the charge accumulation electrode, wherein the light receiving area includes a signal extraction portion, and Wherein, the signal extraction part and the pixel transistor are arranged on different stacked substrates.

2. The light receiving element according to claim 1, in, The incident surface electrode is a hole accumulation layer formed on the incident surface by laminating a negative fixed charge film on the incident surface of the light.

3. The light receiving element according to claim 1, in, The incident surface electrode is a P-type conductive layer doped with P-type impurities on the incident surface of the light.

4. The light receiving element according to claim 1, in, The incident surface electrode is an inorganic electrode film laminated on the incident surface of the light.

5. The light receiving element according to claim 1, in, The incident surface electrode is a metal film having a light-transmitting film thickness and laminated on the incident surface of the light.

6. The light receiving element according to claim 1, further comprising: A pixel separation region is provided between the plurality of light receiving regions arranged in a matrix and electrically separates adjacent light receiving regions.

7. The light receiving element according to claim 6, in, The pixel separation region reaches a middle portion from the incident surface of the light toward a surface opposite to the incident surface in the light receiving region.

8. The light receiving element according to claim 7, in, The pixel separation region divides a pixel array in which the plurality of light receiving regions are arranged in a matrix for each of the plurality of light receiving regions, and electrically floats the pixel separation region.

9. The light receiving element according to claim 6, in, The pixel separation region reaches a surface of the sensor substrate opposite to the incident surface from the incident surface of the light.

10. The light receiving element according to claim 9, in, The pixel separation region is provided at a corner portion of the plurality of light receiving regions having a rectangular shape in a plan view arranged in a matrix, and connects the incident surface electrode and a ground wiring or a negative voltage generating circuit.

11. The light receiving element according to claim 6, in, The pixel separation region is formed of an insulator.

12. The light receiving element according to claim 6, in, The pixel separation region is formed of a metal with an insulating film provided on the surface.

13. The light receiving element according to claim 6, in, The pixel separation region is composed of an insulator with a negative fixed charge film provided on the surface.

14. An imaging element, comprising: A sensor substrate is provided with: a pixel array in which a plurality of light receiving regions that photoelectrically convert incident light into signal charges are arranged in a matrix; a pair of voltage applying electrodes to which a voltage is alternately applied for each of the plurality of light receiving regions to generate an electric field that time-divides the signal charge and distributes the signal charge to a pair of charge accumulation electrodes in each of the plurality of light receiving regions; as well as an incident surface electrode provided on a light incident surface in each of the plurality of light receiving regions and to which a voltage equal to or lower than a ground potential is applied; as well as A circuit board is provided with: a pixel transistor provided on a surface of the sensor substrate opposite to the incident surface of the light and processing the signal charge accumulated in the charge accumulation electrode, wherein the light receiving area includes a signal extraction portion, and Wherein, the signal extraction part and the pixel transistor are arranged on different stacked substrates.

15. An imaging device comprising: Imaging optical system; A sensor substrate is provided with: a pixel array in which a plurality of light receiving regions that photoelectrically convert incident light into signal charges are arranged in a matrix; a pair of voltage applying electrodes to which a voltage is alternately applied for each of the plurality of light receiving regions to generate an electric field that time-divides the signal charge and distributes the signal charge to a pair of charge accumulation electrodes in each of the plurality of light receiving regions; as well as an incident surface electrode provided on the incident surface of light in each of the plurality of light receiving regions and to which a voltage equal to or lower than a ground potential is applied; as well as A circuit board is provided with: a pixel transistor provided on a surface of the sensor substrate opposite to the incident surface of the light and processing the signal charge accumulated in the charge accumulation electrode, wherein the light receiving area includes a signal extraction portion, and Wherein, the signal extraction part and the pixel transistor are arranged on different stacked substrates.

Images