Electrostatic discharge protection circuit and integrated circuit having electrostatic discharge protection circuit

Abstract

The embodiment of the present application provides an ESD protection circuit across power domains, comprising: a first current discharge device connected between a first power terminal and a first ground terminal; a first trigger circuit configured to output a first trigger signal to trigger conduction of the first current discharge device when an ESD event occurs between the first power terminal and the first ground terminal; a second current discharge device connected between a second power terminal and a second ground terminal; a second trigger circuit configured to output a second trigger signal to trigger conduction of the second current discharge device when an ESD event occurs between the second power terminal and the second ground terminal; a third current discharge device connected between the first power terminal and the second power terminal; and a driving circuit connected to an output terminal of the first trigger circuit and an output terminal of the second trigger circuit, configured to trigger conduction of the third current discharge device when the first trigger signal and / or the second trigger signal is received. The embodiment of the present application also provides an integrated circuit comprising the ESD protection circuit.

Description

Technical Field

[0001] This application relates to an integrated circuit (IC), and more particularly to an integrated circuit with an electrostatic discharge protection circuit. Background Technology

[0002] Integrated circuit (IC) chips acquire electrical charges during transportation and packaging. When a charged chip comes into contact with a low-resistance object, a discharge process occurs, known as electrostatic discharge (ESD) in the charged device model (CDM).

[0003] Semiconductor devices in chips are easily damaged by ESD events, making ESD a problem that must be addressed in all chip designs. With the decreasing breakdown characteristics of semiconductor devices and the increasing size of chip packages, ESD protection design for chips has become extremely challenging.

[0004] Figure 1 This illustration shows a prior art chip with an ESD protection circuit 100. When the chip is negatively charged and its input / output (IO) pins are in contact with a low-resistance object, ESD current is injected from the IO pins and flows through... Figure 1 The current discharge path indicated by the middle arrow flows to different power supply terminals or ground terminals in the chip. For example... Figure 1 As shown by the middle arrow, in the event of an ESD incident in the CDM, the primary protection circuit 101, the secondary protection circuit 102, the first power clamping circuit 103, the back-to-back diode (B2B) 104, and the second power clamping circuit 105 constitute the ESD discharge path. When the voltage drop generated by the ESD current passing through the discharge path exceeds the breakdown voltage of the internal components, it will cause damage to the components, thus leading to the failure of the ESD protection design. Moreover, a long ESD discharge path is detrimental to ESD protection, for example... Figure 1 The discharge path from VDD1 to VDD2 needs to pass through multiple devices across power domains, which can easily cause ESD protection failure.

[0005] Therefore, designing effective ESD protection circuits is very important for integrated circuit chips. Summary of the Invention

[0006] This application provides an electrostatic discharge (ESD) protection circuit and an integrated circuit with ESD protection circuit, for effectively dealing with ESD events caused by electrostatic discharge (CDM).

[0007] According to a first aspect of this application, an electrostatic discharge (ESD) protection circuit is provided. The ESD protection circuit includes: a first current discharge device connected between a first power supply terminal and a first ground terminal; a first trigger circuit for outputting a first trigger signal to trigger the first current discharge device to conduct when an ESD event occurs between the first power supply terminal and the first ground terminal; a second current discharge device connected between a second power supply terminal and a second ground terminal; a second trigger circuit for outputting a second trigger signal to trigger the second current discharge device to conduct when an ESD event occurs between the second power supply terminal and the second ground terminal; a third current discharge device connected between the first power supply terminal and the second power supply terminal; and a drive circuit connected to the output terminals of the first and second trigger circuits for triggering the third current discharge device to conduct upon receiving the first trigger signal and / or the second trigger signal.

[0008] According to a first aspect of this application, the third current discharge device, the first trigger circuit, the second trigger circuit, and the drive circuit constitute a power-to-power ESD clamping circuit. The first current discharge device and the first trigger circuit constitute a first power-to-ground ESD clamping circuit, and the second current discharge device and the second trigger circuit constitute a second power-to-ground ESD clamping circuit. The advantage is that the power-to-power ESD clamping circuit shares a trigger circuit with both the first power-to-ground ESD clamping circuit and the second power-to-ground ESD trigger circuit. This design simplifies the ESD protection circuit and reduces its layout area.

[0009] According to a first aspect of this application, in a first implementation, the driving circuit includes: a first pull-up transistor and a second pull-up transistor connected in parallel, and a first pull-down transistor and a second pull-down transistor connected in series. The source of the first pull-up transistor is connected to the first power supply terminal, and its drain is connected to the gate of the third current discharge device. The source of the second pull-up transistor is connected to the second power supply terminal, and its drain is connected to the gate of the third current discharge device. The first pull-down transistor and the second pull-down transistor are connected in series between the gate of the third current discharge device and a first ground terminal or a second ground terminal.

[0010] Optionally, the gates of the first pull-up transistor and the first pull-down transistor are respectively connected to the output terminal of the first trigger circuit; the gates of the second pull-up transistor and the second pull-down transistor are respectively connected to the output terminal of the second trigger circuit. Optionally, the first pull-up transistor and the first pull-down transistor are of different transistor types, and the second pull-up transistor and the second pull-down transistor are of different transistor types. The advantage is that it avoids the problem of competition between the pull-up and pull-down paths of the drive circuit for the gate of the third current discharge device during an ESD event.

[0011] Optionally, the first current discharge device and the second current discharge device are PMOS transistors.

[0012] Optionally, the third current discharge device is an NMOS transistor.

[0013] Optionally, the first pull-up transistor and the second pull-up transistor are PMOS transistors, and the first pull-down transistor and the second pull-down transistor are NMOS transistors.

[0014] Optionally, the driving circuit further includes a first blocking transistor connected between the drain of the first pull-up transistor and the gate of the third current discharge device, and a second blocking transistor connected between the drain of the second pull-up transistor and the gate of the third current discharge device. The gate of the first blocking transistor is connected to its source, and the gate of the second blocking transistor is connected to its source.

[0015] Optionally, the first blocking transistor and the second blocking transistor are NMOS transistors.

[0016] Optionally, the first trigger circuit and the second trigger circuit include an RC flip-flop and an inverter, with the output of the RC flip-flop connected to the input of the inverter.

[0017] Optionally, it also includes a back-to-back diode device connected between the first ground terminal and the second ground terminal.

[0018] Optionally, at least one of the first current discharge device, the second current discharge device, and the third current discharge device is a large-size MOSFET.

[0019] According to a first aspect of this application, in a second implementation, the driving circuit includes: a first pull-up transistor and a second pull-up transistor connected in series, and a first pull-down transistor and a second pull-down transistor connected in parallel. The first pull-up transistor and the second pull-up transistor are connected in series between the gate of the third current discharge device and a first power supply terminal or a second power supply terminal. The source of the first pull-up transistor is connected to the first power supply terminal or the second power supply terminal, and the drain of the second pull-up transistor is connected to the gate of the third current discharge device. The drain of the first pull-down transistor is connected to the first ground terminal, and its source is connected to the gate of the third current discharge device. The drain of the second pull-down transistor is connected to the second ground terminal, and its source is connected to the gate of the third current discharge device.

[0020] Optionally, the gates of the first pull-up transistor and the first pull-down transistor are both connected to the output of the first trigger circuit. The gates of the second pull-up transistor and the second pull-down transistor are both connected to the output of the second trigger circuit. Optionally, the first pull-up transistor and the first pull-down transistor are of different transistor types, and the second pull-up transistor and the second pull-down transistor are of different transistor types. The advantage is that it avoids the problem of competition between the pull-up and pull-down paths of the drive circuit for the gate of the third current discharge device during an ESD event.

[0021] Optionally, the third current discharge device is a PMOS transistor.

[0022] Optionally, the first pull-up transistor and the second pull-up transistor are PMOS transistors, and the first pull-down transistor and the second pull-down transistor are NMOS transistors.

[0023] According to a second aspect of this application, an ESD protection circuit is provided as a power-to-power ESD clamping circuit, comprising: a current discharge device connected between a first power terminal and a second power terminal; a first trigger circuit connected between the first power terminal and a first ground terminal, for outputting a first trigger signal when an ESD event occurs between the first power terminal and the first ground terminal; a second trigger circuit connected between the second power terminal and the second ground terminal, for outputting a second trigger signal when an ESD event occurs between the second power terminal and the second ground terminal; and a driving circuit connected to the output terminals of the first trigger circuit and the second trigger circuit, for triggering the current discharge device to conduct upon receiving the first trigger signal and / or the second trigger signal, wherein the driving circuit employs a driving circuit according to a first or second implementation of the first aspect of the present invention described above.

[0024] According to a third aspect of this application, an integrated circuit having an ESD protection circuit according to any of the above aspects of the present invention is provided, comprising: a first power supply terminal and a second power supply terminal; a first ground terminal and a second ground terminal; and the ESD protection circuit.

[0025] Other features and advantages of the invention will become clear from the following detailed description of exemplary embodiments of the invention with reference to the accompanying drawings. Attached Figure Description

[0026] The accompanying drawings, which form part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0027] The invention will be more clearly understood with reference to the accompanying drawings and the following detailed description, wherein:

[0028] Figure 1 An ESD protection circuit in the prior art is shown.

[0029] Figure 2 A schematic diagram of a chip with ESD protection circuitry according to an embodiment of the present invention is shown.

[0030] Figure 3 It shows Figure 2 The embodiment shown illustrates a specific circuit implementation of the ESD protection circuit.

[0031] Figure 4 It shows Figure 2 Another specific circuit implementation of the ESD protection circuit in the illustrated embodiment.

[0032] Figure 5 It shows Figure 2 Another specific circuit implementation of the ESD protection circuit in the illustrated embodiment.

[0033] Figure 6 A schematic diagram of a power supply to power supply ESD clamping circuit according to an embodiment of the present invention is shown. Detailed Implementation

[0034] Figure 2 A schematic diagram of a chip with an ESD protection circuit 200 according to an embodiment of the present invention is shown.

[0035] Figure 2 The diagram specifically illustrates a block diagram of the ESD protection circuit 200 in the chip, as well as the first power supply terminal VDD1, the first ground terminal VDD1, the second power supply terminal VDD2, and the second ground terminal VDD2 in the chip. Other components in the chip are not shown to avoid obscuring the understanding of the invention.

[0036] The ESD protection circuit 200 provided in this embodiment of the invention is applicable to various integrated circuit chips, including but not limited to analog integrated circuits, digital integrated circuits, and mixed-signal integrated circuits.

[0037] Different power domains are a common application scenario in chips. For example Figure 2 As shown, there are different power domains, such as the first power domain containing the first power terminal VDD1 and the first ground terminal VDD1, and the second power domain containing the second power terminal VDD2 and the second ground terminal VDD2. For example, the first power domain containing the first power supply VDD1 can be an analog integrated circuit or a digital integrated circuit, and the second power domain containing the second power supply VDD2 can be of the same or different type as the first power domain, for example, it can be an analog integrated circuit or a digital integrated circuit.

[0038] like Figure 2 As shown, VDD1 and VDD2 can be one of various power supply terminals in the chip. VSS1 and VSS2 can be one of various ground terminals in the chip. Preferably, a back-to-back diode device is provided between VSS1 and VSS2, which can form a current discharge path between the two power domains in the event of an ESD event.

[0039] In this embodiment, as Figure 2 As shown, the ESD protection circuit 200 includes a first current discharge device 203 connected between the first power supply terminal VDD1 and the first ground terminal VSS1, and a first trigger circuit 204. The first trigger circuit 204 is used to output a first trigger signal to trigger the conduction of the first current discharge device 203 when an ESD event occurs between the first power supply terminal VDD1 and the first ground terminal VSS1, thereby forming a current discharge path. In fact, the first current discharge device 203 and the first trigger circuit 204 constitute a first power-to-ground ESD clamping circuit 201 between the first power supply terminal VDD1 and the first ground terminal VSS1.

[0040] like Figure 2 As shown, the first trigger circuit 204 is connected between the first power supply terminal VDD1 and the first ground terminal VSS1. The output terminal A1 of the first trigger circuit 204 is connected to the first current discharge device 203, and is used to output a first trigger signal to the first current discharge device 203 when an ESD event occurs between the first power supply terminal VDD1 and the first ground terminal VSS1.

[0041] Furthermore, the ESD protection circuit 200 also includes a second current discharge device 205 connected between the second power supply terminal VDD2 and the second ground terminal VSS2, and a second trigger circuit 206. The second trigger circuit 206 is used to output a second trigger signal to trigger the conduction of the second current discharge device 205 when an ESD event occurs between the second power supply terminal VDD2 and the second ground terminal VSS2, thereby forming a current discharge path. In fact, the second current discharge device 205 and the second trigger circuit 206 constitute a second power-to-ground ESD clamping circuit 202 between the second power supply terminal VDD2 and the second ground terminal VSS2.

[0042] like Figure 2 As shown, the second trigger circuit 206 is connected between the second power supply terminal VDD2 and the second ground terminal VSS2. The output terminal A2 of the second trigger circuit 206 is connected to the second current discharge device 205, and is used to output a second trigger signal to the second current discharge device 205 when an ESD event occurs between the second power supply terminal VDD2 and the second ground terminal VSS2.

[0043] Furthermore, the ESD protection circuit 200 also includes a third current discharge device 207 and a drive circuit 208, wherein the third current discharge device 207 is connected between the first power supply terminal VDD1 and the second power supply terminal VDD2.

[0044] The two input terminals of the driving circuit 208 are respectively connected to the output terminal A1 of the first trigger circuit 204 and the output terminal A2 of the second trigger circuit 206, and the output terminal of the driving circuit 208 is connected to the third current discharge device 207. When an ESD event occurs between the first power supply terminal VDD1 and the first ground terminal VSS1 or between the second power supply terminal VDD2 and the second ground terminal VSS2, the driving circuit 208 outputs a signal to the third current discharge device 207 to trigger the conduction of the third current discharge device 207.

[0045] In fact, in this embodiment, the third current discharge device 207, the first trigger circuit 204, the second trigger circuit 206, and the drive circuit 208 constitute a power-to-power ESD clamp circuit between the first power terminal VDD1 and the second power terminal VDD2.

[0046] compared to Figure 1In existing technology, when an ESD event occurs between the first power supply terminal VDD1 and the first ground terminal VSS1, or between the second power supply terminal VDD2 and the second ground terminal VSS2, the current discharge path of such a power-to-power ESD clamping circuit passes through the third current discharge device 207, thereby shortening the ESD discharge path across the power domain from VDD1 to VDD2. This design can improve the chip's ESD protection capability across power domains. Moreover, as Figure 2 As shown, the aforementioned power-to-power ESD clamping circuit shares the first trigger circuit 204 with the first power-to-ground ESD clamping circuit 201, and shares the second trigger circuit 206 with the second power-to-ground ESD clamping circuit 202. This embodiment reduces the number of independent trigger circuits by sharing trigger circuits, thereby reducing the chip layout area. Specifically, taking... Figure 2 For example, in the embodiment, this solution reduces the ESD trigger circuits for VDD1 to ground and VDD2 to ground that are designed separately for the power supply to power supply ESD clamping circuit, thereby reducing the layout area occupied by the two independently designed trigger circuits.

[0047] The ESD protection circuit 200 may further include other components as needed, and is not limited to those listed above.

[0048] Figure 3 yes Figure 2 The embodiment shown illustrates a specific circuit implementation of the ESD protection circuit 200.

[0049] The first trigger circuit 204 includes an RC flip-flop on the left and an inverter on the right as the output stage, wherein the output terminal B1 of the RC flip-flop is connected to the input terminal of the inverter. Figure 3 As shown, the second trigger circuit 206 can adopt the same configuration as the first trigger circuit 204.

[0050] The first trigger circuit 204 and the second trigger circuit 206 here may also employ other configurations of RC flip-flops and inverters known in the art, or other types of trigger circuits in the art.

[0051] Preferably, in this embodiment, the first current discharge device 203 or the second current discharge device 205 is a P-type metal-oxide-semiconductor (PMOS) transistor, which can reduce the leakage current from the corresponding power terminal to ground under normal chip operation.

[0052] The gate of the first current discharge device 203 is connected to the output terminal of the first trigger circuit 204, such as Figure 3As shown, the output terminal is A1. The gate of the second current discharge device 205 is connected to the output terminal of the second trigger circuit 206, as shown. Figure 3 As shown, the output terminal is A2.

[0053] like Figure 3 As shown, for example, when the chip is operating normally, the output terminal B1 of the RC flip-flop in the first trigger circuit 204 is grounded through the resistor in the RC flip-flop and is at a low potential. Therefore, the output of the inverter is at a high potential, and the PMOS transistor of the first current discharge device 203 is turned off. When an ESD event occurs between VDD1 and VSS1, the output terminal B1 of the RC flip-flop is pulled high, the output of the inverter is at a low potential, and the PMOS transistor of the first current discharge device 203 is turned on, thus forming a current discharge path from VDD1 to VSS1. Similarly, when an ESD event occurs between VDD2 and VSS2, the gate voltage of the second current discharge device 205 is pulled low, thus turning it on and forming a current discharge path from VDD2 to VSS2.

[0054] like Figure 3 As shown, the source of the third current discharge device 207 transistor is connected to the first power supply terminal VDD1, and its drain is connected to the second power supply terminal VDD2.

[0055] The output of the drive circuit 208 is connected to the gate of the third current discharge device 207, and is used to trigger the conduction of the third current discharge device 207 when an ESD event occurs between the first power supply terminal VDD1 and the first ground terminal VSS1 or between the second power supply terminal VDD2 and the second ground terminal VSS2.

[0056] Preferably, the first current discharge device 203, the second current discharge device 205, and the third current discharge device 207 can be large-size MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), such as BigFETs. When either of the two power supplies VDD1 or VDD2 is powered on or off before the other, a large current event will occur between VDD1 and VDD2. The large-size MOSFET can withstand such a large current. The third current discharge device 207 can be an NMOS transistor. For example, Figure 2 In the power supply to power supply ESD clamping circuit, when the chip is working normally, the voltage difference between VDD1 and VDD2 is usually significantly smaller than the voltage difference between the power supply and ground. The third current discharge device 207 NBigFET using NMOS transistors has very small leakage current.

[0057] Of course, the types of transistors used here are merely exemplary and not restrictive, and can be selected according to actual needs.

[0058] In this embodiment, as Figure 3 As shown, the driving circuit 208 includes: a first pull-up transistor MP1 and a second pull-up transistor MP2 connected in parallel, and a first pull-down transistor 209 and a second pull-down transistor 210 connected in series. The source of the first pull-up transistor MP1 is connected to the first power supply terminal VDD1, and its drain is connected to the gate of the third current discharge device 207; the source of the second pull-up transistor MP2 is connected to the second power supply terminal VDD2, and its drain is connected to the gate of the third current discharge device 207; the first pull-down transistor 209 and the second pull-down transistor 210 are connected in series between the gate of the third current discharge device 207 and a ground terminal, such as a first ground terminal VSS1 or a second ground terminal VSS2. The source of the first pull-down transistor 209 is connected to the gate of the third current discharge device, and the drain of the second pull-down transistor 210 is connected to a ground terminal, such as... Figure 3 The connection is shown to the first ground terminal VSS1. The drain of the second pull-down transistor 210 can also be connected to the second ground terminal VSS2.

[0059] Furthermore, the gates of the first pull-up transistor MP1 and the first pull-down transistor 209 are both connected to the output terminal of the first trigger circuit 204, such as... Figure 3 As shown, the gates of the second pull-up transistor MP2 and the second pull-down transistor 210 at output terminal A1 are both connected to the output terminal of the second trigger circuit 206, as follows: Figure 3 The output terminal A2 is shown.

[0060] Preferably, the first pull-up transistor MP1 and the first pull-down transistor 209 are of different transistor types. This ensures that when the output of the first trigger circuit 204 is input to the gates of the first pull-up transistor MP1 and the first pull-down transistor 209, one of them will be turned on while the other is turned off. In other words, the pull-up and pull-down operations of the first pull-up transistor MP1 and the first pull-down transistor 209 on the gate of the third current discharge device 207 will not occur simultaneously, avoiding the problem of competitive driving of the gate of the third current discharge device 207 by the pull-up and pull-down paths. Similarly, the second pull-up transistor MP2 and the second pull-down transistor 210 are of different transistor types, which can also avoid the problem of competitive driving of the gate of the third current discharge device 207 by the pull-up and pull-down paths.

[0061] In this embodiment, the first pull-up transistor and the second pull-up transistor are PMOS transistors, and the first pull-down transistor and the second pull-down transistor are NMOS transistors. Thus, the first pull-up transistor MP1, the second pull-up transistor MP2, the first pull-down transistor 209, and the second pull-down transistor 210 in the driving circuit 208 constitute a NAND logic circuit. This NAND logic circuit performs a NAND logic operation on the output of the first trigger circuit 204 and the output of the second trigger circuit 206. Therefore, when an ESD event occurs between the first power terminal VDD1 and the first ground terminal VSS1, or between the second power terminal VDD2 and the second ground terminal VSS2, the third current discharge device 207 is triggered to conduct; and during normal chip operation, the third current discharge device 207 is turned off.

[0062] When an ESD event occurs between the first power terminal VDD1 and the first ground terminal VSS1, or between the second power terminal VDD2 and the second ground terminal VSS2, the working principle of the ESD protection circuit 200 is as follows:

[0063] When an ESD event occurs between the first power terminal VDD1 and the first ground terminal VSS1 or between the second power terminal VDD2 and the second ground terminal VSS2, the gate voltage of the current discharge device in the corresponding clamping circuit is pulled low, the pull-up path in the drive circuit 208 is turned on, and the gate voltage of the third current discharge device 207 is pulled high, forming an ESD discharge path between VDD1 and VDD2.

[0064] Specifically, when an ESD event occurs between VDD1 and VSS1, the output terminal A1 of the first trigger circuit 204 is at a low potential, the gate voltage of the first current discharge device 203 is pulled low, and the gate voltage of the pull-up transistor MP1 in the drive circuit 208 is pulled low, MP1 is turned on, thereby pulling up the gate voltage of the NMOS transistor NBigFET of the third current discharge device 207, thus turning it on, forming a current discharge path between VDD1 and VDD2.

[0065] At this time, the gate voltage of the first pull-up transistor MP1 in the drive circuit 208 is pulled low, and MP1 is turned on, while the gate voltage of the NMOS of the first pull-down transistor 209 is low and thus turned off. Therefore, there is no competitive drive problem between the first pull-up transistor MP1 and the first pull-down transistor 209 for the gate of the third current discharge device 207.

[0066] Similarly, when an ESD event occurs between VDD2 and VSS2, the output terminal A2 of the second trigger circuit 206 is at a low potential, and the gate voltage of PBigFET2 of the second current discharge device 205 is pulled low. Likewise, the gate voltage of PMOS transistor MP2 in the drive circuit 208 is pulled low, and MP2 is turned on, thereby pulling up the gate voltage of NMOS transistor NBigFET of the third current discharge device 207, thus turning it on and forming a current discharge path between VDD1 and VDD2.

[0067] At this time, the gate voltage of the PMOS transistor of the second pull-up transistor MP2 in the driving circuit 208 is pulled low, MP2 is turned on, while the gate voltage of the NMOS transistor of the second pull-down transistor 210 is low and thus turned off. Therefore, there is no competitive driving problem between the second pull-up transistor MP2 and the second pull-down transistor 210 for the gate of the third current discharge device 207.

[0068] When the chip is working normally, such as Figure 3 As shown, the gate voltages of the PMOS transistor PBigFET1 of the first current discharge device 203 and the PMOS transistor PBigFET2 of the second current discharge device 205 are both pulled high. This causes the output of the driving circuit 208 to pull down the gate voltage of the NMOS transistor NBigFET of the third current discharge device 207, thus putting all three current discharge devices 203, 205, and 207 into a turned-off state. Specifically, the gate voltages of the PMOS transistor PBigFET1 of the first current discharge device 203 and the PMOS transistor PBigFET2 of the second current discharge device 205 are both pulled high, causing the first pull-down transistor 209 (NMOS transistor) and the second pull-down transistor 210 (NMOS transistor) in the driving circuit 208 to conduct, thereby pulling down the gate voltage of the third current discharge device 207, thus putting the third current discharge device 207 into a turned-off state.

[0069] The power-to-power ESD clamping circuit proposed in this embodiment does not require an additional independently designed trigger circuit, thereby reducing the layout area. Moreover, in the event of an ESD incident, there is no contention driving problem in the driving circuit 208 for the gate of the BigFET, the third current discharge device across the power domain.

[0070] Figure 2 The ESD protection circuit 200 of the illustrated embodiment should not be limited to Figure 3 The implementation method shown.

[0071] In another implementation, such as Figure 4 As shown, with Figure 3 The difference in implementation lies in the fact that the drive circuit 308 is compared to... Figure 3The driving circuit 208 further includes a first blocking transistor Mnb1 connected between the drain of the first pull-up transistor MP1 and the gate of the third current discharge device 207, and a second blocking transistor Mnb2 connected between the drain of the second pull-up transistor MP2 and the gate of the third current discharge device 207. In this embodiment, the first and second blocking transistors are NMOS transistors.

[0072] The gate of the first blocking transistor Mnb1 is connected to its source and then to the drain of the first pull-up transistor MP1. The drain of the first blocking transistor Mnb1 is connected to the gate of the third current discharge device 207. The gate of the second blocking transistor Mnb2 is connected to its source and then to the drain of the second pull-up transistor MP2. The drain of the second blocking transistor Mnb2 is connected to the gate of the third current discharge device 207.

[0073] These two blocking transistors can block the connection between the gate of the third current discharge device 207 and the parasitic diodes Dp1 and Dp2 of the pull-up transistors MP1 and MP2. In this embodiment, the pull-up path in the drive circuit adopts such a PMOS parasitic diode blocking technique to avoid the parasitic diodes pulling down the gate voltage of the third current discharge device 207 under any ESD event.

[0074] The specific principle is as follows: Figure 3 In the circuit, when an ESD event occurs between VDD1 and VSS1, the first pull-up transistor MP1 turns on, pulling the gate voltage of the third current discharge device 207 up to near VDD1, causing the third current discharge device 207 to conduct and discharge the current between VDD1 and VDD2. If there is no ESD event between VDD2 and VSS2 at this time, and the potential of VDD2 is significantly lower than that of VDD1, although MP2 is in the off state, the parasitic diode Dp2 will cause leakage from the gate of the third current discharge device 207 to VDD2, causing the gate voltage of the third current discharge device 207 to be pulled down, thus affecting the current discharge efficiency of the third current discharge device 207. Corresponding to this possible scenario, Figure 4 The embodiments in Figure 3 Based on this, a second blocking transistor Mnb2 is added. When Mp2 is in the off state, the second blocking transistor Mnb2 is also turned off to block the leakage current from the gate of the third current discharge device 207 to VDD2 through the parasitic diode Dp2, so that the gate voltage of the third current discharge device 207 is not pulled down in the above scenario, thus ensuring the current discharge efficiency of the third current discharge device 207.

[0075] Similarly, such as Figure 3In the circuit, when an ESD event occurs between VDD2 and VSS2, the second pull-up transistor MP2 turns on, pulling the gate voltage of the third current discharge device 207 up to near VDD2, causing the third current discharge device 207 to conduct and discharge the current between VDD2 and VDD1. If there is no ESD event between VDD1 and VSS1 at this time, and the potential of VDD1 is significantly lower than VDD2, although MP1 is in the off state, the parasitic diode Dp1 will cause leakage from the gate of the third current discharge device 207 to VDD1, causing the gate voltage of the third current discharge device 207 to be pulled down, thus affecting the current discharge efficiency of the third current discharge device 207. Corresponding to this possible scenario, Figure 4 The embodiments in Figure 3 Based on this, a first blocking transistor Mnb1 is added. When Mp1 is in the off state, the second blocking transistor Mnb1 is also turned off to block the leakage current from the gate of the third current discharge device 207 to VDD2 through the parasitic diode Dp1, so that the gate voltage of the third current discharge device 207 is not pulled down in the above scenario, thus ensuring the current discharge efficiency of the third current discharge device 207.

[0076] When the transistor type of the third current discharge device 207 changes, the logic circuit in the driving circuit 208 or the driving circuit 308 can be designed accordingly to achieve the above function, so that when an ESD event occurs between the first power supply terminal VDD1 and the first ground terminal VSS1 or between the second power supply terminal VDD2 and the second ground terminal VSS2, the third current discharge device 207 is triggered to conduct. Furthermore, the problem of competitive driving of the gate of the third current discharge device by the pull-up path and the pull-down path can be avoided.

[0077] Figure 5 It shows Figure 2 Another specific implementation of the ESD protection circuit 200 in the illustrated embodiment.

[0078] Specifically, such as Figure 5 As shown, with Figure 3 and Figure 4 The difference lies in the type of transistor in the third current discharge device 207. Figure 5 The PMOS transistor PBigFET is used. The logic circuit design of the driving circuit 408 is different from that of the driving circuits 208 and 308. In addition, the driving circuit 408 is connected to the output terminal B1 of the first trigger circuit 204 and the output terminal B2 of the second trigger circuit 206. In this embodiment, the output terminal B1 is the output terminal of the RC flip-flop in the first trigger circuit 204, and the output terminal B2 is the output terminal of the RC flip-flop in the second trigger circuit 206.

[0079] Specifically, the driving circuit 408 includes: a first pull-up transistor 501 and a second pull-up transistor 502 connected in series, and a first pull-down transistor 503 and a second pull-down transistor 504 connected in parallel.

[0080] The first pull-up transistor 501 and the second pull-up transistor 502 are connected in series between the gate of the third current discharge device 207 and a power supply terminal (e.g., the first power supply terminal VDD1 or the second power supply terminal VDD2). Specifically, the source of the first pull-up transistor 501 is connected to the first power supply terminal VDD1 or the second power supply terminal VDD2, such as... Figure 5 The source of the first pull-up transistor 501 is connected to VDD1, as follows: Figure 5 As shown. Here, the source of the first pull-up transistor 501 can be connected to VDD2. The drain of the second pull-up transistor 502 is connected to the gate of the third current discharge device 207.

[0081] The drain of the first pull-down transistor 503 is connected to the first ground terminal VSS1, and its source is connected to the gate of the third current discharge device 207; the drain of the second pull-down transistor 504 is connected to the second ground terminal VSS2, and its source is connected to the gate of the third current discharge device 207.

[0082] Furthermore, the gates of the first pull-up transistor 501 and the first pull-down transistor 503 are both connected to the output terminal of the first trigger circuit 204, such as... Figure 5 As shown, this could be the output terminal B1 of an RC flip-flop. The gates of the second pull-up transistor 502 and the second pull-down transistor 504 are both connected to the output terminal of the second trigger circuit, as shown below. Figure 5 As shown, it can be the output terminal B2 of the RC flip-flop in the second trigger circuit.

[0083] The first pull-up transistor 501 and the first pull-down transistor 503 are of different transistor types. Thus, in the event of an ESD event, one of the first pull-up transistor 501 and the first pull-down transistor 503 will be turned on while the other is turned off. The pull-up path containing the first pull-up transistor 501 and the pull-down path containing the first pull-down transistor 503 will not perform pull-up and pull-down operations on the gate of the third current discharge device 207 simultaneously, avoiding the problem of competitive driving of the gate of the third current discharge device 207 by the pull-up and pull-down paths. Similarly, the second pull-up transistor 502 and the second pull-down transistor 504 are of different transistor types, which can avoid the problem of competitive driving of the gate of the third current discharge device 207 by the pull-up and pull-down paths.

[0084] In this embodiment, the first pull-up transistor 501 and the second pull-up transistor 502 are PMOS transistors, and the first pull-down transistor 503 and the second pull-down transistor 504 are NMOS transistors.

[0085] Figure 5 The driving circuit 408 enables the third current discharge device 207 to be turned on when an ESD event occurs between the first power supply terminal VDD1 and the first ground terminal VSS1 or between the second power supply terminal VDD2 and the second ground terminal VSS2, and to be turned off when the chip is working normally.

[0086] The specific working principle is as follows:

[0087] When the chip is working normally, the output B1 of the RC flip-flop of the first trigger circuit 204 is grounded through a resistor and is at a low potential. Similarly, the output B2 of the RC flip-flop of the second trigger circuit 206 is also at a low potential. Therefore, the first pull-up transistor 501 and the second pull-up transistor 502 are both turned on, which pulls the gate of the third current discharge device 207 high, thereby turning off the PMOS transistor of the third current discharge device 207.

[0088] When an ESD event occurs between VDD1 and VSS1, the output terminal B1 of the RC flip-flop of the first trigger circuit 204 is pulled high, thereby turning on the first pull-down transistor 503. That is, the gate voltage of the PMOS transistor PBigFET of the third current discharge device 207 is pulled low, and the third current discharge device 207 is turned on, forming a current discharge path between VDD1 and VDD2.

[0089] At this time, the gate voltage of the first pull-up transistor 501 in the drive circuit 408 is pulled high, and the first pull-up transistor 501 is turned off. That is, the pull-up path where the first pull-up transistor 501 and the second pull-up transistor 502 are located is cut off. Therefore, there is no competitive drive problem between the pull-up path and the pull-down path for the gate of the third current discharge device 207.

[0090] Similarly, when an ESD event occurs between VDD2 and VSS2, the output B2 of the RC flip-flop of the second trigger circuit 206 is pulled high, thereby turning on the second pull-down transistor 504. That is, the gate voltage of the PMOS transistor PBigFET of the third current discharge device 207 is pulled low, and the third current discharge device 207 is turned on, forming a current discharge path between VDD1 and VDD2.

[0091] At this time, the gate voltage of the PMOS transistor of the second pull-up transistor 502 in the driving circuit 408 is pulled high, and the first pull-up transistor 501 is turned off, that is, the pull-up path containing the first pull-up transistor 501 and the second pull-up transistor 502 is cut off. Therefore, there is no competitive driving problem between the pull-up path and the pull-down path for the gate of the third current discharge device 207.

[0092] The above Figures 2 to 5 In any of the embodiments, a power-to-power ESD clamping circuit that shares a trigger circuit with the power-to-ground ESD clamping circuit helps to reduce the layout area. Furthermore, in any of the above embodiments, when an ESD event occurs, there is no contention for drive when the drive circuit triggers the current-discharging device across the power domain, which is beneficial for the formation of a low-resistance ESD path between power supplies.

[0093] Figure 6 A schematic diagram of a power supply to power supply ESD clamping circuit 300 according to another embodiment of the present invention is shown. Figure 5 The difference in the embodiments is that, in Figure 6 In the embodiments, such as Figure 6 As shown, the power supply ESD clamping circuit 300 can use a separate first trigger circuit 601 and a second trigger circuit 602 without limiting whether the first trigger circuit 601 and the second trigger circuit 602 are shared by other current discharge devices.

[0094] Specifically, such as Figure 6 As shown, the power supply to power supply ESD clamping circuit 300 includes: a current discharge device 607 connected between the first power terminal VDD1 and the second power terminal VDD2; a first trigger circuit 601 connected between the first power terminal VDD1 and the first ground terminal VSS1; a second trigger circuit 602 connected between the second power terminal VDD2 and the second ground terminal VSS2; and a drive circuit 608 for triggering the current discharge device 607 to conduct when an ESD event occurs between the first power terminal VDD1 and the first ground terminal VSS1 or between the second power terminal VDD2 and the second ground terminal VSS2.

[0095] The first trigger circuit 601 can be configured as the first trigger circuit 204 provided in any of the above embodiments. The second trigger circuit 602 can be configured as the second trigger circuit 206 provided in any of the above embodiments.

[0096] The driving circuit 608 can adopt the driving circuit configuration provided in any of the above embodiments, for example... Figure 3 , Figure 4 and Figure 5 The driver circuit provided is one of 208, 308 or 408.

[0097] The connection relationship between the driving circuit 608, the first trigger circuit 601, and the second trigger circuit 602 can be adopted as described in any of the above embodiments as needed. Further details are omitted here.

[0098] The ESD protection circuit and integrated circuit having such an ESD protection circuit according to embodiments of the present invention have been described in detail above. To avoid obscuring the concept of the invention, some details well-known in the art have not been described. Those skilled in the art can fully understand the technical solutions of the present invention based on the above description.

[0099] While specific embodiments of the invention have been described in detail by way of example, those skilled in the art should understand that the above examples are for illustrative purposes only and are not intended to limit the scope of the invention. Those skilled in the art should understand that modifications can be made to the above embodiments without departing from the scope of the invention. The scope of the invention is defined by the appended claims.

Claims

1. An electrostatic discharge (ESD) protection circuit, characterized in that, The ESD protection circuit includes: The first current discharge device is connected between the first power supply terminal and the first ground terminal; A first trigger circuit is configured to output a first trigger signal to trigger the conduction of the first current discharge device when an ESD event occurs between the first power supply terminal and the first ground terminal. The second current discharge device is connected between the second power supply terminal and the second ground terminal; The second trigger circuit is used to output a second trigger signal to trigger the conduction of the second current discharge device when an ESD event occurs between the second power supply terminal and the second ground terminal. The third current discharge device is connected between the first power supply terminal and the second power supply terminal; A driving circuit, connected to the output terminals of the first trigger circuit and the second trigger circuit, is used to trigger the conduction of the third current discharge device upon receiving the first trigger signal and / or the second trigger signal. The driving circuit includes: a first pull-up transistor and a second pull-up transistor connected in parallel, and a first pull-down transistor and a second pull-down transistor connected in series. The source of the first pull-up transistor is connected to the first power supply terminal, and its drain is connected to the gate of the third current discharge device. The source of the second pull-up transistor is connected to the second power supply terminal, and its drain is connected to the gate of the third current discharge device. The first pull-down transistor and the second pull-down transistor are connected in series between the gate of the third current discharge device and a first ground terminal or a second ground terminal.

2. The ESD protection circuit as described in claim 1, characterized in that, The gates of the first pull-up transistor and the first pull-down transistor are respectively connected to the output terminal of the first trigger circuit, and the gates of the second pull-up transistor and the second pull-down transistor are respectively connected to the output terminal of the second trigger circuit.

3. The ESD protection circuit as described in claim 1 or 2, characterized in that, The first pull-up transistor and the first pull-down transistor are of different transistor types, and the second pull-up transistor and the second pull-down transistor are of different transistor types.

4. The ESD protection circuit as described in claim 1 or 2, characterized in that, The first current discharge device and the second current discharge device are PMOS transistors.

5. The ESD protection circuit as described in claim 1 or 2, characterized in that, The third current discharge device is an NMOS transistor.

6. The ESD protection circuit as described in claim 1 or 2, characterized in that, The first pull-up transistor and the second pull-up transistor are PMOS transistors, and the first pull-down transistor and the second pull-down transistor are NMOS transistors.

7. The ESD protection circuit as described in claim 2, characterized in that, The first trigger circuit and the second trigger circuit include an RC flip-flop and an inverter, with the output of the RC flip-flop connected to the input of the inverter.

8. The ESD protection circuit as described in claim 1 or 2, characterized in that, It also includes a back-to-back diode device connected between the first ground terminal and the second ground terminal.

9. The ESD protection circuit as described in claim 1 or 2, characterized in that, The driving circuit further includes a first blocking transistor connected between the drain of the first pull-up transistor and the gate of the third current discharge device, and a second blocking transistor connected between the drain of the second pull-up transistor and the gate of the third current discharge device. The gate of the first blocking transistor is connected to its source, and its drain is connected to the gate of the third current discharge device. The gate of the second blocking transistor is connected to its source, and its drain is connected to the gate of the third current discharge device.

10. The ESD protection circuit as described in claim 1 or 2, characterized in that, At least one of the first current discharge device, the second current discharge device, and the third current discharge device is a large-size MOSFET.

11. The ESD protection circuit as described in claim 1, characterized in that, The driving circuit includes: a first pull-up transistor and a second pull-up transistor connected in series, and a first pull-down transistor and a second pull-down transistor connected in parallel. The first pull-up transistor and the second pull-up transistor are connected in series between the gate of the third current discharge device and a first power supply terminal or a second power supply terminal. The drain of the first pull-down transistor is connected to the first ground terminal, and its source is connected to the gate of the third current discharge device. The drain of the second pull-down transistor is connected to the second ground terminal, and its source is connected to the gate of the third current discharge device.

12. The ESD protection circuit as described in claim 11, characterized in that, The gates of the first pull-up transistor and the first pull-down transistor are respectively connected to the output terminal of the first trigger circuit, and the gates of the second pull-up transistor and the second pull-down transistor are respectively connected to the output terminal of the second trigger circuit.

13. The ESD protection circuit as described in claim 12, characterized in that, The first pull-up transistor and the first pull-down transistor are of different transistor types, and the second pull-up transistor and the second pull-down transistor are of different transistor types.

14. The ESD protection circuit as described in any one of claims 11-13, characterized in that, The third current discharge device is a PMOS transistor.

15. The ESD protection circuit as described in any one of claims 11-13, characterized in that, The first pull-up transistor and the second pull-up transistor are PMOS transistors, and the first pull-down transistor and the second pull-down transistor are NMOS transistors.

16. An integrated circuit having an electrostatic discharge protection circuit as described in any one of claims 1-15, characterized in that, include: The first power terminal and the second power terminal; The first grounding terminal and the second grounding terminal; as well as The ESD protection circuit.

17. An electrostatic discharge (ESD) protection circuit that serves as a power supply-to-power supply ESD clamping circuit, characterized in that, include: A current discharge device connected between the first power supply terminal and the second power supply terminal. A first trigger circuit connected between a first power supply terminal and a first ground terminal is used to output a first trigger signal when an ESD event occurs between the first power supply terminal and the first ground terminal; A second trigger circuit connected between a second power supply terminal and a second ground terminal is used to output a second trigger signal when an ESD event occurs between the second power supply terminal and the second ground terminal; as well as A driving circuit, connected to the output terminals of the first trigger circuit and the second trigger circuit, is used to trigger the current discharge device to conduct upon receiving the first trigger signal and / or the second trigger signal. The driving circuit includes: a first pull-up transistor and a second pull-up transistor connected in parallel, and a first pull-down transistor and a second pull-down transistor connected in series. The source of the first pull-up transistor is connected to the first power supply terminal, and its drain is connected to the gate of the current discharge device. The source of the second pull-up transistor is connected to the second power supply terminal, and its drain is connected to the gate of the current discharge device. The first pull-down transistor and the second pull-down transistor are connected in series between the gate of the current discharge device and a first ground terminal or a second ground terminal.

18. The ESD protection circuit as described in claim 17, characterized in that, The gates of the first pull-up transistor and the first pull-down transistor are respectively connected to the output terminal of the first trigger circuit, and the gates of the second pull-up transistor and the second pull-down transistor are respectively connected to the output terminal of the second trigger circuit.

19. The ESD protection circuit as described in claim 18, characterized in that, The first pull-up transistor and the first pull-down transistor are of different transistor types, and the second pull-up transistor and the second pull-down transistor are of different transistor types.

20. The ESD protection circuit as described in any one of claims 17-19, characterized in that, The current discharge device is an NMOS transistor.

21. The ESD protection circuit as described in any one of claims 17-19, characterized in that, The first pull-up transistor and the second pull-up transistor are PMOS transistors, and the first pull-down transistor and the second pull-down transistor are NMOS transistors.

22. The ESD protection circuit as described in any one of claims 17-19, characterized in that, The first trigger circuit and the second trigger circuit include an RC flip-flop and an inverter, with the output of the RC flip-flop connected to the input of the inverter.

23. The ESD protection circuit as described in any one of claims 17-19, characterized in that, It also includes a back-to-back diode device connected between the first ground terminal and the second ground terminal.

24. The ESD protection circuit as described in any one of claims 17-19, characterized in that, It includes a first blocking transistor connected between the drain of a first pull-up transistor and the gate of the current discharge device, and a second blocking transistor connected between the drain of a second pull-up transistor and the gate of the current discharge device. The gate of the first blocking transistor is connected to its source, and its drain is connected to the gate of the current discharge device. The gate of the second blocking transistor is connected to its source, and its drain is connected to the gate of the current discharge device.

25. An ESD protection circuit serving as a power supply-to-power supply ESD clamping circuit, comprising: A current discharge device connected between the first power supply terminal and the second power supply terminal. A first trigger circuit connected between a first power supply terminal and a first ground terminal is used to output a first trigger signal when an ESD event occurs between the first power supply terminal and the first ground terminal; A second trigger circuit connected between a second power supply terminal and a second ground terminal is used to output a second trigger signal when an ESD event occurs between the second power supply terminal and the second ground terminal; as well as A driving circuit, connected to the output terminals of the first trigger circuit and the second trigger circuit, is used to trigger the conduction of the current discharge device when receiving the first trigger signal and / or the second trigger signal. The driving circuit comprises: a first pull-up transistor and a second pull-up transistor connected in series, and a first pull-down transistor and a second pull-down transistor connected in parallel. The first pull-up transistor and the second pull-up transistor are connected in series between the gate of the third current discharge device and a first power supply terminal or a second power supply terminal. The drain of the first pull-down transistor is connected to the first ground terminal, and its source is connected to the gate of the current discharge device. The drain of the second pull-down transistor is connected to the second ground terminal, and its source is connected to the gate of the current discharge device.

26. The ESD protection circuit as described in claim 25, characterized in that, The gates of the first pull-up transistor and the first pull-down transistor are respectively connected to the output terminal of the first trigger circuit, and the gates of the second pull-up transistor and the second pull-down transistor are respectively connected to the output terminal of the second trigger circuit.

27. The ESD protection circuit as described in claim 26, characterized in that, The first pull-up transistor and the first pull-down transistor are of different transistor types, and the second pull-up transistor and the second pull-down transistor are of different transistor types.

28. The ESD protection circuit as described in any one of claims 25-27, characterized in that, The current discharge device is a PMOS transistor.

29. The ESD protection circuit as described in any one of claims 25-27, characterized in that, The first pull-up transistor and the second pull-up transistor are PMOS transistors, and the first pull-down transistor and the second pull-down transistor are NMOS transistors.

30. An integrated circuit having an ESD protection circuit as described in any one of claims 17-29, characterized in that, include: The first power terminal and the second power terminal; The first grounding terminal and the second grounding terminal; as well as The ESD protection circuit.

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