Diamond-based CMOS logic circuit for monolithic integration and preparation method thereof

Abstract

The diamond-based CMOS logic circuit and preparation method for monolithic integration of the present invention belong to the technical field of semiconductor monolithic integrated circuits. The structure includes a substrate (1), a diamond epitaxial layer (2), a hydrogen-terminated two-dimensional hole gas (3), an insulating dielectric layer (4), a semiconductor layer and an ohmic contact electrode in order from bottom to top; the preparation method includes the steps of growing a diamond epitaxial layer on a substrate, etching to form a groove structure, and forming a hydrogen-terminated two-dimensional hole gas. The present invention has a simple process, and the two-dimensional hole gas on the surface of the hydrogen-terminated diamond is used as a gate electrode to effectively shorten the gate length of the transistor, and the CMOS structure is formed by using p-type and n-type semiconductors, which is conducive to subsequent monolithic integration.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor monolithic integrated circuits, and more specifically, relates to a method for preparing a diamond-based CMOS logic circuit. Background Art

[0002] Wide bandgap semiconductor materials represented by diamond have a high critical breakdown electric field, which can achieve lower capacitance and on-resistance at the same breakdown voltage. They are core materials that support the innovation, development and transformation and upgrading of industries such as power electronics, 5G mobile communications, and new energy vehicles. The development of diamond power devices can meet major social needs such as industrial upgrading and energy conservation and emission reduction, and is becoming a technological commanding height for competition among countries around the world. In order to fully utilize the performance advantages of diamond transistors and reduce the power consumption of devices in circuit systems, integrating discrete power conversion circuits and drive circuits on the same chip is a very effective means to minimize parasitic inductance. The logic function of silicon-based power device IC driver chips is realized through complementary metal-oxide-semiconductor (CMOS) logic circuits. Mainly composed of PMOS (P-type MOSFET) and NMOS (N-type MOSFET) with complementary physical properties, CMOS logic circuits are expected to provide: (1) rail-to-rail output voltage (or input-to-output voltage level matching) for multi-level circuits, (2) suitable logic transition threshold voltage of about half the power supply voltage, (3) suppression of static power consumption; and (4) sufficient noise margin for both "low" and "high" logic. Existing diamond material dopants, especially n-type doping, have high activation energy and low doping efficiency, resulting in a significant decrease in material mobility when doped at high concentrations. On the other hand, Moore's Law of integrated circuit development requires smaller and smaller gate lengths for transistor devices. Hydrogen termination can form a two-dimensional hole gas with high hole concentration and high mobility on the surface of diamond. This two-dimensional hole gas is confined to a thin layer of several nanometers and can be used to realize p-channel MOSFET devices. However, research on n-channel devices is still facing challenges. Summary of the invention

[0003] In order to overcome the defects of the prior art, the present invention provides a diamond-based CMOS logic circuit for monolithic integrated circuit applications and a preparation method, which uses the two-dimensional hole gas channel on the surface of the hydrogen terminal as a gate to reduce its characteristic size. In addition, p-type and n-type semiconductor materials are deposited separately to realize n-channel and p-channel enhancement transistors to realize CMOS logic circuits.

[0004] The technical solution adopted by the present invention is as follows:

[0005] A diamond-based CMOS logic circuit that can be used for monolithic integration is characterized in that its structure includes, from bottom to top, a substrate 1, a diamond epitaxial layer 2, a hydrogen-terminated two-dimensional hole gas 3, an insulating dielectric layer 4, a semiconductor layer and an ohmic contact electrode, wherein the semiconductor layer includes a p-type semiconductor 5 and an n-type semiconductor 6, and the ohmic contact electrode includes a semiconductor ohmic electrode 7 and a hole gas ohmic electrode 8.

[0006] Furthermore, the substrate 1 is any one of diamond, silicon carbide substrate, sapphire, silicon and other materials obtained by high temperature and high pressure or chemical vapor deposition.

[0007] Furthermore, the diamond epitaxial layer 2 is unintentionally doped and has a dislocation density of less than 10 4 cm -2 ; The thickness of the diamond epitaxial layer is 1nm~100μm.

[0008] Furthermore, the hydrogen-terminated two-dimensional cavities 3 have a thickness of 0-10 nm and a concentration of 10 12 ~10 16 cm -2 , the concentration can be adjusted by plasma treatment conditions.

[0009] Furthermore, the insulating dielectric layer 4 is grown on one side of the groove etched in the diamond epitaxial layer 2, has a thickness of 1 to 100 μm, and is made of one or a combination of any of aluminum oxide, silicon nitride, hafnium oxide, silicon oxide and the like.

[0010] Furthermore, the material used for the semiconductor layer can be Si, nitride, oxide and two-dimensional material, etc.

[0011] Furthermore, the ohmic contact electrode may be a single layer or a stacked layer structure of metals such as Ti, Al, Ni, and Au.

[0012] A method for preparing a diamond-based CMOS logic circuit that can be used for monolithic integration comprises the following steps:

[0013] S1. Growing a diamond epitaxial layer 2 on a substrate 1 and etching to form a groove structure;

[0014] S2. In the diamond epitaxial layer 2, a region other than the groove is etched by plasma treatment to form a hydrogen-terminated two-dimensional hole gas 3;

[0015] S3. Depositing an insulating dielectric layer 4 on the surface of one side of the etched groove;

[0016] S4. Forming a p-type semiconductor layer 5 on one side of the groove;

[0017] S5. Forming an n-type semiconductor layer 6 on the other side of the groove;

[0018] S6. Forming a semiconductor ohmic electrode 7 on the surface of the semiconductor layer;

[0019] S7. Form an ohmic contact electrode 8 on the surface of the hydrogen-terminated two-dimensional hole gas 3.

[0020] In the step S1, the etching depth of the groove structure needs to be greater than the depth of the two-dimensional hole gas channel, so as to ensure that the two-dimensional hole gas can be used as the gate electrode of the semiconductor device on the sidewall of the groove. In the steps S4 and S5, the conductive properties of the semiconductor layer need to be complementary to form a subsequent CMOS logic circuit.

[0021] In addition, the present invention can also be expressed using the following method steps:

[0022] Step 1. growing an epitaxial layer on a substrate material and etching a groove;

[0023] Step 2. forming a two-dimensional hole gas channel;

[0024] Step 3. Depositing an insulating dielectric layer on the surface of the epitaxial material for subsequent preparation of a MOS structure;

[0025] Step 4. Depositing a p-type semiconductor to prepare an n-channel MOSFET;

[0026] Step 5. Depositing n-type semiconductor to prepare p-channel MOSFET;

[0027] Step 6. Depositing metal to prepare source and drain ohmic electrodes of the device;

[0028] Step 7. Depositing metal to prepare device gate electrode;

[0029] In the step 1, the substrate may be homogeneous diamond or other heterogeneous materials.

[0030] In the step 2, two-dimensional void gas is formed by hydrogen plasma treatment.

[0031] In the step 3, the etching method is inductively coupled plasma etching, reactive ion etching or ion milling.

[0032] In steps 4 and 5, the semiconductor can be prepared by CVD, sputtering, transfer, etc.

[0033] In steps 6 and 7, the electrode preparation method is magnetron sputtering, electron beam evaporation, thermal evaporation, etc.

[0034] Compared with the prior art, the beneficial effects are: the channel is set on the side wall based on the groove structure, thereby using the two-dimensional hole gas on the hydrogen terminal surface as the gate to reduce its characteristic size. In addition, p-type and n-type semiconductor materials are deposited separately to realize n-channel and p-channel enhancement transistors to realize CMOS logic circuits. At the same time, since the hydrogen terminal surface can be used to prepare diamond-based lateral conduction power devices, monolithic integration can be finally achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1-7 It is a process schematic diagram of the device manufacturing method of Example 1 of the present invention. DETAILED DESCRIPTION

[0036] The drawings are only for illustrative purposes and should not be construed as limiting the present invention. To better illustrate the present embodiment, some parts in the drawings may be omitted, enlarged or reduced, and do not represent the size of the actual product. For those skilled in the art, it is understandable that some well-known structures and their descriptions may be omitted in the drawings. The positional relationships described in the drawings are only for illustrative purposes and should not be construed as limiting the present invention.

[0037] Example 1

[0038] The structural schematic diagram of a diamond-based CMOS logic circuit that can be used for monolithic integration of the present invention is shown in FIG. Figure 7 From bottom to top, it includes a substrate 1, a diamond epitaxial layer 2, a hydrogen-terminated two-dimensional hole gas 3, an insulating dielectric layer 4, a semiconductor layer and an ohmic contact electrode, wherein the semiconductor layer includes a p-type semiconductor 5 and an n-type semiconductor 6, and the ohmic contact electrode includes a semiconductor ohmic electrode 7 and a hole gas ohmic electrode 8.

[0039] Example 2

[0040] See attached Figures 1 to 7 The method for preparing the diamond-based CMOS logic circuit that can be used for monolithic integration specifically comprises the following steps:

[0041] S1. Grow a diamond epitaxial layer 2 on a substrate 1 and etch a groove, such as Figure 1 As shown;

[0042] S2. forming a two-dimensional hole gas channel layer 3 on the diamond epitaxial layer 2, such as Figure 2 As shown;

[0043] S3. Depositing an insulating dielectric layer 4 on the diamond surface with a groove structure, such as Figure 3 As shown;

[0044] S4. Deposit p-type semiconductor 5 on the left side of the groove, such as Figure 4 As shown;

[0045] S5. Depositing n-type semiconductor 6 on the right side of the groove, such as Figure 5 As shown;

[0046] S6. Prepare source and drain electrodes for ohmic contact between p-type semiconductor and n-type semiconductor, such as Figure 6 shown.

[0047] S7. Prepare an electrode with a two-dimensional hole gas channel ohmic contact as the gate of the device, such as Figure 7 shown.

[0048] At this point, the entire device preparation process is completed. Figure 7 This is a schematic diagram of the device structure of Example 1.

[0049] Example 3

[0050] This embodiment is similar to the embodiment 2, except that the formation of the groove structure can also be achieved by first depositing metal or oxide as a mask in the groove region on the diamond epitaxial layer 2, and then performing a secondary epitaxial diamond layer growth.

[0051] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the embodiments here. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the claims of the present invention.

Claims

1. A diamond-based CMOS logic circuit for monolithic integration, characterized in that: The structure comprises, from bottom to top, a substrate (1), a diamond epitaxial layer (2), a hydrogen-terminated two-dimensional hole gas (3), an insulating dielectric layer (4), a semiconductor layer and an ohmic contact electrode, wherein the semiconductor layer comprises a p-type semiconductor (5) and an n-type semiconductor (6), and the ohmic contact electrode comprises a semiconductor ohmic electrode (7) and a hole gas ohmic electrode (8); A groove structure is etched on the side of the diamond epitaxial layer (2) facing the hydrogen-terminated two-dimensional hole gas (3), and the etching depth of the groove structure is greater than the depth of the two-dimensional hole gas channel, and the two-dimensional hole gas is used as the gate electrode of the semiconductor device on the side wall of the groove.

2. A diamond-based CMOS logic circuit for monolithic integration according to claim 1, characterized in that: The substrate (1) is any one of diamond, silicon carbide substrate, sapphire and silicon material obtained by high temperature and high pressure or chemical vapor deposition.

3. A diamond-based CMOS logic circuit for monolithic integration according to claim 1, characterized in that: The diamond epitaxial layer (2) is unintentionally doped and has a dislocation density of less than 10 4 cm -2 ; The thickness of the diamond epitaxial layer is 1nm~100μm.

4. A diamond-based CMOS logic circuit for monolithic integration according to claim 1, characterized in that: The hydrogen-terminated two-dimensional vacancy gas (3) has a thickness of 0 to 10 nm and a concentration of 10 12 ~10 16 cm -2 .

5. The diamond-based CMOS logic circuit for monolithic integration according to claim 1, characterized in that: The insulating dielectric layer (4) is grown on one side of the diamond epitaxial layer (2) where the groove is etched, has a thickness of 1 to 100 μm, and is made of one or a combination of any of aluminum oxide, silicon nitride, hafnium oxide, and silicon oxide.

6. A diamond-based CMOS logic circuit for monolithic integration according to claim 1, characterized in that: The materials used for the semiconductor layer are Si, nitride, oxide and two-dimensional material.

7. A diamond-based CMOS logic circuit for monolithic integration according to claim 1, characterized in that: The ohmic contact electrode is a single layer or stacked layer structure of Ti, Al, Ni, Au metal.

8. A method for preparing a monolithically integrated diamond-based CMOS logic circuit, comprising the following steps: S1. growing a diamond epitaxial layer (2) on a substrate (1) and etching to form a groove structure, wherein the etching depth of the groove structure is greater than the depth of the two-dimensional hole gas channel, and the two-dimensional hole gas is used as the gate electrode of the semiconductor device on the side wall of the groove; S2. Forming hydrogen-terminated two-dimensional cavities (3) by plasma treatment in the area other than the grooves on one side of the diamond epitaxial layer (2) where the grooves are etched; S3. Depositing an insulating dielectric layer (4) on the surface of one side of the etched groove; S4. forming a p-type semiconductor layer (5) on one side of the groove; S5. forming an n-type semiconductor layer (6) on the other side of the groove; S6. forming a semiconductor ohmic electrode (7) on the surface of the semiconductor layer; S7. Forming an ohmic contact electrode (8) on the surface of the hydrogen-terminated two-dimensional hole gas (3).

9. A method for preparing a monolithically integrated diamond-based CMOS logic circuit according to claim 8, wherein in steps S4 and S5, the conductive properties of the semiconductor layers are complementary to each other to form a subsequent CMOS logic circuit.

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