Electrostatic discharge circuit and method of operating the same

Abstract

Embodiments of the present invention provide an electrostatic discharge (ESD) circuit and a method of operating the same. The ESD circuit includes an ESD detection circuit, a clamping circuit, and an ESD assist circuit. The ESD detection circuit is coupled between a first node and a second node. The first node has a first voltage. The second node has a second voltage. The clamping circuit includes a first transistor having a first gate, a first drain, a first source, and a first body terminal. The first gate is coupled to the ESD detection circuit through a third node. The first drain is coupled to the second node. The first source and the first body terminal are coupled together at the first node. The ESD assist circuit is coupled between the first node and the third node and is configured to clamp a third voltage of the third node at the first voltage during an ESD event of the first node or the second node.

Description

Technical Field

[0001] Embodiments of the present invention relate to an electrostatic discharge circuit and its operation method. Background Technology

[0002] The latest trend in miniaturizing integrated circuits (ICs) has resulted in smaller devices that consume less power but offer more functionality at higher speeds than before. The miniaturization process has also increased the devices' sensitivity to electrostatic discharge (ESD) events due to various factors, such as thinner dielectric thickness and associated lower dielectric breakdown voltage. ESD is one of the causes of damage to electronic circuits and is a consideration in advanced semiconductor technologies. Summary of the Invention

[0003] According to one aspect of the present invention, an ESD circuit is provided, comprising: an ESD detection circuit coupled between a first node and a second node, the first node having a first voltage and the second node having a second voltage; a clamping circuit including a first transistor of a first type, the first transistor having a first gate, a first drain, a first source and a first body terminal, the first gate being coupled to the ESD detection circuit at least through a third node, the first drain being coupled to the second node, and the first source and the first body terminal being coupled together at the first node; and an ESD auxiliary circuit coupled between the first node and the third node and configured to clamp a third voltage of the third node at the first voltage during an ESD event at the first node or the second node.

[0004] According to another aspect of the present invention, an ESD circuit is provided, comprising: a first diode coupled between a first node and an input / output (I / O) pad; a second diode coupled between the I / O pad and a second node; internal circuitry coupled to the first diode, the second diode, and the I / O pad; and an ESD clamping circuit located between the first node and the second node; the ESD clamping circuit comprising: a first ESD detection circuit coupled between the first node and the second node, the first node having a first voltage and the second node having a second voltage; the first clamping circuit comprising a first transistor of a first type, the first transistor having a first gate, a first drain, a first source, and a first body terminal, the first gate being coupled to the first ESD detection circuit at least through a third node, the first drain being coupled to the second node, and the first source being coupled together with the first body terminal at the first node; and a first ESD auxiliary circuit coupled between the first node and the third node and configured to clamp a third voltage of the third node at the first voltage during an ESD event at the second node.

[0005] According to another aspect of the present invention, a method of operating an ESD circuit is provided, the method comprising: receiving a first ESD voltage at a first node, the first ESD voltage being greater than a reference supply voltage of a reference power source, the first ESD voltage corresponding to a first ESD event; activating an ESD auxiliary circuit in response to the first ESD event at the first node, such that the ESD auxiliary circuit clamps a first voltage at the gate of a first transistor of a discharge circuit at a second voltage at a second node, the discharge circuit being coupled between the first node and the second node, and the ESD auxiliary circuit being coupled at least between the first node and a third node, and the ESD auxiliary circuit including a body diode; activating the discharge circuit in response to the first ESD event, and the ESD auxiliary circuit clamping the first voltage at the gate of the first transistor at the second voltage; and discharging a first ESD current of the first ESD event through the first transistor in a first ESD direction from the first node to the second node. Attached Figure Description

[0006] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industrial practice, the various components are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1 This is a schematic block diagram of an integrated circuit according to some embodiments.

[0008] Figures 2A-2E These are corresponding circuit diagrams of corresponding integrated circuits according to some embodiments.

[0009] Figures 3A-3E These are cross-sectional views of corresponding integrated circuits according to some embodiments.

[0010] Figures 4A-4E These are corresponding circuit diagrams of corresponding integrated circuits according to some embodiments.

[0011] Figures 5A-5E These are cross-sectional views of corresponding integrated circuits according to some embodiments.

[0012] Figures 6A-6B These are corresponding circuit diagrams of corresponding integrated circuits according to some embodiments.

[0013] Figures 7A-7B These are corresponding circuit diagrams of corresponding integrated circuits according to some embodiments.

[0014] Figures 8A-8B This is a top view of the corresponding integrated circuit according to some embodiments.

[0015] Figure 9This is a flowchart of a method for operating an ESD circuit according to some embodiments.

[0016] Figure 10 This is a flowchart of a method for manufacturing an integrated circuit according to some embodiments. Detailed Implementation

[0017] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0018] Furthermore, for ease of description, this document may use spacing terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spacing terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spacing descriptors used herein may be interpreted accordingly.

[0019] In some embodiments, the electrostatic discharge (ESD) circuit includes an ESD detection circuit coupled between a first node and a second node. In some embodiments, the first node has a first voltage, and the second node has a second voltage.

[0020] In some embodiments, the ESD circuit further includes a clamping circuit comprising a first transistor of a first type. The first transistor has a first gate, a first drain, a first source, and a first body terminal. The first gate is coupled to the ESD detection circuit via a third node. The first drain is coupled to a second node. The first source and the first body terminal are coupled together at the first node.

[0021] The ESD circuitry also includes ESD auxiliary circuitry coupled between the first node and the third node. During an ESD event at the first or second node of this disclosure, the ESD auxiliary circuitry is configured to clamp a third voltage at the third node to a first voltage, thereby controlling the gate potential of the first transistor and causing the first transistor to turn on. According to some embodiments, in response to turning on, the first transistor is configured to discharge the ESD current of the ESD event from the second node to the first node in the forward ESD direction.

[0022] In some embodiments, by including an ESD auxiliary circuit in the integrated circuit of the present invention, the ESD auxiliary circuit is configured to reduce the capacitive coupling effect between the first node and the second node, and effectively reduce the on-resistance of the first transistor. In some embodiments, by reducing the on-resistance of the first transistor, the first transistor turns on faster and more strongly than other methods, resulting in improved ESD performance and improved ESD stability compared to other methods.

[0023] Figure 1 This is a schematic block diagram of an integrated circuit 100 according to some embodiments.

[0024] Integrated circuit 100 includes internal circuitry 102, a voltage supply node 104, a reference voltage supply node 106, input / output (IO) pads 108, diodes 110 and 112, and ESD clamping circuitry 120. In some embodiments, at least integrated circuit 100, 200A-200E ( Figures 2A-2E ), 300A-300E ( Figures 3A-3E ), 400A-400E ( Figures 4A-4E ), 500A-500E ( Figures 5A-5E ), 600A-600B ( Figures 6A-6B ), 700A-700B ( Figures 7A-7B ) or 800A-800B ( Figures 8A-8B The integrated circuits 100, 200A-200E are incorporated on a single integrated circuit (IC) or a single semiconductor substrate. In some embodiments, at least the integrated circuits 100, 200A-200E are integrated on a single semiconductor substrate. Figures 2A-2E ), 300A-300E ( Figures 3A-3E ), 400A-400E ( Figures 4A-4E ), 500A-500E ( Figures 5A-5E ), 600A-600B ( Figures 6A-6B ), 700A-700B ( Figures 7A-7B ) or 800A-800B ( Figures 8A-8B This includes one or more ICs that are integrated on one or more individual semiconductor substrates.

[0025] Internal circuitry 102 is coupled to I / O pads 108, diodes 110 and 112. Internal circuitry 102 is configured to receive I / O signals from I / O pads 108. In some embodiments, internal circuitry 102 is coupled to a voltage supply node 104 (e.g., VDD) and a reference voltage supply node 106 (e.g., VSS). In some embodiments, internal circuitry 102 is configured to receive a supply voltage VDD from voltage supply node 104 (e.g., VDD) and a reference voltage VSS from reference voltage supply node 106 (e.g., VSS).

[0026] Internal circuitry 102 includes circuitry configured to generate or process I / O signals received by or output to I / O pads 108. In some embodiments, internal circuitry 102 includes core circuitry configured to operate at a voltage lower than the supply voltage VDD of voltage supply node 104. In some embodiments, internal circuitry 102 includes at least one n-type transistor device or a p-type transistor device. In some embodiments, internal circuitry 102 includes at least logic gate units. In some embodiments, logic gate units include AND, OR, NAND, NOR, XOR, INV, AND-OR-Invert (AOI), OR-AND-Invert (OAI), MUX (multiplexer), Flip-flop, BUFF, Latch, delay, or clock units. In some embodiments, internal circuitry 102 includes at least memory units. In some embodiments, the memory cell includes static random access memory (SRAM), dynamic RAM (DRAM), resistive RAM (RRAM), magnetoresistive RAM (MRAM), or read-only memory (ROM). In some embodiments, the internal circuitry 102 includes one or more active or passive components. Examples of active components include, but are not limited to, transistors and diodes. Examples of transistors include, but are not limited to, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, p-channel and / or n-channel field-effect transistors (PFETs / NFETs), FinFETs, and planar MOS transistors with raised source / drain. Examples of passive components include, but are not limited to, capacitors, inductors, fuses, and resistors.

[0027] Voltage supply node 104 is coupled to diode 110 and ESD clamping circuit 120. Reference voltage supply node 106 is coupled to diode 112 and ESD clamping circuit 120. Voltage supply node 104 is configured to receive supply voltage VDD for normal operation of internal circuitry 102. Similarly, reference voltage supply node 106 is configured to receive reference supply voltage VSS for normal operation of internal circuitry 102. In some embodiments, at least voltage supply node 104 is a voltage supply pad. In some embodiments, at least reference voltage supply node 106 is a reference voltage supply pad. In some embodiments, the pad is at least a conductive surface, pin, node, or bus. Voltage supply node 104 or reference voltage supply node 106 is also referred to as a power supply voltage bus or rail. Figure 1 , Figures 2A-2E , Figures 3A-3E , Figures 4A-4E , Figures 5A-5E , Figures 6A-6B , Figures 7A-7B or Figures 8A-8B In the example configuration, the supply voltage VDD is the positive supply voltage, voltage supply node 104 is the positive power supply voltage, the reference supply voltage VSS is the ground supply voltage, and the reference voltage supply node 106 is the ground voltage terminal. Other power supply arrangements are within the scope of this disclosure.

[0028] IO pad 108 is coupled to internal circuitry 102. IO pad 108 is configured to receive IO signals from or output IO signals to internal circuitry 102. IO pad 108 is at least a pin coupled to internal circuitry 102. In some embodiments, IO pad 108 is a node, bus, or conductive surface coupled to internal circuitry 102.

[0029] Diode 110 is coupled between voltage supply node 104 and IO pad 108. The anode of diode 110 is coupled to internal circuitry 102, IO pad 108, and the cathode of diode 112. The cathode of diode 110 is coupled to voltage supply node 104 and ESD clamping circuit 120. In some embodiments, diode 110 is a pull-up diode, also referred to as a p+ diode. For example, in these embodiments, the p+ diode is formed between a p-well region (not shown) and an n-well region (not shown), and the n-well region is connected to VDD.

[0030] Diode 112 is coupled between reference voltage supply node 106 and IO pad 108. The anode of diode 112 is coupled to reference voltage supply node 106 and ESD clamping circuit 120. The cathode of diode 112 is coupled to internal circuitry 102, IO pad 108, and the anode of diode 110. In some embodiments, diode 112 is a pull-down diode or referred to as an n+ diode. For example, in these embodiments, an n+- diode is formed between an n+ junction (not shown) and a p-substrate (not shown), and the p-substrate is connected to ground or VSS.

[0031] Diodes 110 and 112 are configured to have minimal impact on the normal behavior of internal circuitry 102 or integrated circuit 100 (e.g., ESD-free conditions or ESD-free events). In some embodiments, an ESD event occurs when a voltage or current higher than the voltage or current level expected during normal operation of internal circuitry 102 is applied to at least voltage supply node 104, reference voltage supply node 106, or IO pad 108.

[0032] When no ESD event occurs, diodes 110 and 112 do not affect the operation of integrated circuit 100. During an ESD event, depending on whether diode 110 is forward-biased or reverse-biased, and the voltage level of voltage supply node 104 and IO pad 108, diode 110 is configured to transfer voltage or current between voltage supply node 104 and IO pad 108.

[0033] For example, during a Positive-to-VDD (PD) mode of ESD stress or event, diode 110 is forward biased and configured to transfer voltage or current from IO pad 108 to voltage supply node 104. In PD mode, positive ESD stress or positive ESD voltage (at least greater than the supply voltage VDD) is applied to IO pad 108, while voltage supply node 104 (e.g., VDD) is grounded, and reference voltage supply node 106 (e.g., VSS) is floating.

[0034] For example, during the negative-to-VDD (ND) mode of ESD stress or event, diode 110 is reverse biased and configured to transfer voltage or current from voltage supply node 104 to IO pad 108. In ND mode, negative ESD stress is received by IO pad 108, while voltage supply node 104 (e.g., VDD) is grounded and reference voltage supply node 106 (e.g., VSS) is floating.

[0035] During an ESD event, depending on whether diode 112 is forward-biased or reverse-biased, and the voltage levels of the reference voltage supply node 106 and the IO pad 108, diode 112 is configured to transfer voltage or current between the reference voltage supply node 106 and the IO pad 108.

[0036] For example, during a Positive-to-VSS (PS) mode of ESD stress or event, diode 112 is reverse biased and configured to transfer voltage or current from IO pad 108 to reference voltage supply node 106. In PS mode, positive ESD stress or ESD voltage (at least greater than the reference supply voltage VSS) is applied to IO pad 108, while voltage supply node 104 (e.g., VDD) is floating and reference voltage supply node 106 (e.g., VSS) is ground.

[0037] For example, during the negative-to-VSS (NS) mode of ESD stress or event, diode 112 is forward biased and configured to transfer voltage or current from reference voltage supply node 106 to IO pad 108. In NS mode, negative ESD stress is received by IO pad 108, while voltage supply node 104 (e.g., VDD) is floating and reference voltage supply node 106 (e.g., VSS) is ground.

[0038] At least diodes of other types, configurations, and arrangements, including diode 110 or 112, are within the scope of this disclosure.

[0039] ESD clamping circuit 120 is coupled between voltage supply node 104 (e.g., supply voltage VDD) and reference voltage supply node 106 (e.g., VSS). When no ESD event occurs, ESD clamping circuit 120 is off. For example, when no ESD event occurs, ESD clamping circuit 120 is off and therefore a non-conductive device or non-conductive circuit during normal operation of internal circuitry 102. In other words, ESD clamping circuit 120 is either off or non-conductive during normal operation of internal circuitry 102 in the absence of an ESD event.

[0040] If an ESD event occurs, the ESD clamping circuit 120 is configured to sense the ESD event and is configured to turn on and provide a current shunt path (e.g., VSS) between the voltage supply node 104 (e.g., supply voltage VDD) and the reference voltage supply node 106, thereby discharging the ESD current. For example, when an ESD event occurs, if the voltage difference across the ESD clamping circuit 120 is equal to or greater than the threshold voltage of the ESD clamping circuit 120, the ESD clamping circuit 120 is turned on to conduct current between the voltage supply node 104 (e.g., VDD) and the reference voltage supply node 106 (e.g., VSS).

[0041] During an ESD event, the ESD clamping circuit 120 is configured to turn on and discharge the ESD current (I1 or I2) in either the forward ESD direction (e.g., current I1) or the reverse ESD direction (e.g., current I2). The forward ESD direction (e.g., current I1) is from the reference voltage supply node 106 (e.g., VSS) to the voltage supply node 104 (e.g., VDD). The reverse ESD direction (e.g., current I2) is from the voltage supply node 104 (e.g., VDD) to the reference voltage supply node 106 (e.g., VSS).

[0042] During a positive ESD surge at reference voltage supply node 106, ESD clamping circuit 120 is configured to turn on and discharge ESD current I1 in the positive ESD direction from reference voltage supply node 106 (e.g., VSS) to voltage supply node 104 (e.g., VDD). In some embodiments, ESD clamping circuit 120 is configured to turn on after the PS mode of ESD (as described above) and discharge ESD current I1 in the positive ESD direction from reference voltage supply node 106 (e.g., VSS) to voltage supply node 104 (e.g., VDD).

[0043] During a positive ESD surge at voltage supply node 104, ESD clamping circuit 120 is configured to turn on and discharge ESD current I2 in the reverse ESD direction from voltage supply node 104 (e.g., VDD) to reference voltage supply node 106 (e.g., VSS). In some embodiments, ESD clamping circuit 120 is configured to turn on after the PD mode of ESD (as described above) and discharge ESD current I2 in the reverse ESD direction from voltage supply node 104 (e.g., VDD) to reference voltage supply node 106 (e.g., VSS).

[0044] In some embodiments, the ESD clamping circuit 120 is a transient clamping circuit. For example, in some embodiments, the ESD clamping circuit 120 is configured to handle transient or fast ESD events, such as rapid changes in voltage and / or current from an ESD event. During a transient or fast ESD event, the ESD clamping circuit 120 is configured to turn on very quickly to provide a shunt path between the voltage supply node 104 (e.g., supply voltage VDD) and the reference voltage supply node 106 (e.g., VSS) before an ESD event that could damage one or more components within the integrated circuit 100. In some embodiments, the ESD clamping circuit 120 is configured to turn off more slowly than it turns on.

[0045] In some embodiments, the ESD clamp 120 is a static clamping circuit. In some embodiments, the static clamping circuit is configured to provide a static or steady-state voltage and current response. For example, the static clamping circuit is turned on by a fixed voltage level.

[0046] In some embodiments, the ESD clamping circuit 120 includes a large NMOS transistor or PMOS transistor configured to carry ESD current without entering the avalanche breakdown region of the ESD clamping circuit 120. In some embodiments, the ESD clamping circuit 120 is implemented such that the ESD clamping circuit 120 does not have an avalanche junction inside, and is also referred to as a "non-snapback protection scheme".

[0047] Other types of clamping circuits, configurations, and arrangements of the ESD clamping circuit 120 are within the scope of this disclosure.

[0048] Other configurations or quantities of circuits in integrated circuit 100 are within the scope of this disclosure.

[0049] In some embodiments, according to certain implementations, during an ESD event at a first node or a second node, the ESD clamping circuit 120 is configured to discharge the ESD current of the ESD event in the forward ESD direction from the second node to the first node. Compared to other methods, the integrated circuit 100 has better ESD discharge capability and performance in the forward ESD direction while occupying less area.

[0050] Figure 2A This is a circuit diagram of an integrated circuit 200A according to some embodiments.

[0051] Integrated circuit 200A is an embodiment of ESD clamping circuit 120, and therefore a similar detailed description is omitted.

[0052] and Figure 1 , Figures 2A-2E , Figures 3A-3E , Figures 4A-4E , Figures 5A-5E , Figures 6A-6B , Figures 7A-7B and Figures 8A-8B Components that are the same or similar to those shown below are given the same reference numerals, and therefore their detailed descriptions are omitted.

[0053] Figures 2A-2E , Figures 3A-3E , Figures 4A-4E , Figures 5A-5E , Figures 6A-6B , Figures 7A-7B and Figures 8A-8B Node Nd1 in the middle corresponds to Figure 1 Voltage supply node 104. Figures 2A-2E , Figures 3A-3E , Figures 4A-4E , Figures 5A-5E , Figures 6A-6B , Figures 7A-7B and Figures 8A-8B The node Nd2 corresponds to Figure 1 The reference voltage supply node 106.

[0054] The integrated circuit 200A includes a control circuit 201, an ESD detection circuit 202, an ESD auxiliary circuit 204a, and a discharge circuit 210.

[0055] The control circuit 201 is coupled to the ESD detection circuit 202, the ESD auxiliary circuit 204a, and the discharge circuit 210 via nodes Nd1 and Nd2. The control circuit 201 is also coupled between nodes Nd1 and Nd2. The control circuit 201 is configured to control at least the ESD detection circuit 202.

[0056] ESD detection circuit 202 is coupled to control circuit 201, ESD auxiliary circuit 204a, discharge circuit 210, and node Nd3. ESD detection circuit 202 is also coupled between nodes Nd1 and Nd2. ESD detection circuit 202 is configured to detect an ESD event at node Nd2 (e.g., an ESD current I1 in the forward ESD direction) and, in response to the ESD event, charge node Nd3, thereby turning on discharge circuit 210. In some embodiments, in response to being turned on, discharge circuit 210 couples nodes Nd1 and Nd2, thereby providing an ESD discharge path between nodes Nd1 and Nd2. In some embodiments, ESD detection circuit 202 is configured to detect an ESD event at node Nd1 (e.g., an ESD current I2 in the reverse ESD direction).

[0057] ESD auxiliary circuit 204a is coupled to nodes Nd1, Nd3, ESD detection circuit 202, and discharge circuit 210. In response to an ESD event at node Nd2 (e.g., an ESD current I1 in the forward ESD direction), ESD auxiliary circuit 204a is configured to turn on and clamp the voltage at node Nd3 to be equal to the voltage at node Nd1 (e.g., VDD), thereby enabling discharge circuit 210 to turn on. In some embodiments, in response to being turned on, discharge circuit 210 couples nodes Nd2 and Nd1, thereby providing a forward ESD discharge path between nodes Nd2 and Nd1.

[0058] Discharge circuit 210 is coupled between node Nd1 and node Nd2. Discharge circuit 210 is also coupled to node Nd3, ESD detection circuit 202, and ESD auxiliary circuit 204a. Discharge circuit 210 is configured to couple nodes Nd1 and Nd2 during an ESD event at node Nd1 or node Nd2, thereby providing an ESD discharge path between nodes Nd1 and Nd2.

[0059] ESD detection circuit 202 includes resistor R1, capacitor C1, N-type metal-oxide-semiconductor (NMOS) transistor N1 and P-type metal-oxide-semiconductor (PMOS) transistor P1.

[0060] The discharge circuit 210 includes a PMOS transistor P2. The PMOS transistor P2 includes a gate, a drain, and a source (not labeled).

[0061] ESD auxiliary circuit 204a includes a PMOS transistor P3. In some embodiments, the PMOS transistor P3 is a ground-gate PMOS (ggPMOS) transistor. The PMOS transistor P3 includes a gate, a drain, and a source (not labeled).

[0062] Each of the following terminals is coupled together: the first terminal of resistor Rl, node Nd2, the source of NMOS transistor Nl, the body of NMOS transistor Nl, and the drain of PMOS transistor P2.

[0063] The second end of resistor R1, node Nd4, the first end of capacitor Cl, the gate of PMOS transistor Pl, and the gate of NMOS transistor N2 are all coupled together.

[0064] The second terminal of capacitor C1, node Ndl, source of PMOS transistor Pl, body of PMOS transistor Pl, source of PMOS transistor P2, body of PMOS transistor P2, source of PMOS transistor P3, gate of PMOS transistor P3, and body of PMOS transistor P3 are all coupled together.

[0065] Each of node Nd3, the drain of NMOS transistor N1, the drain of PMOS transistor P1, the source of PMOS transistor P3, and the gate of PMOS transistor P2 is coupled together.

[0066] In some embodiments, capacitor C1 is a transistor-coupled capacitor. For example, in some embodiments, capacitor C1 is a transistor having a drain and a source coupled together, thus forming a transistor-coupled capacitor.

[0067] Resistor R1 and capacitor C1 are configured as an RC network. Depending on the location of the RC network's output, the RC network can be configured as a low-pass filter or a high-pass filter.

[0068] NMOS transistor N1 and PMOS transistor P1 are configured as inverters (not labeled). Therefore, the slowly rising voltage at node Nd4 will be inverted by NMOS transistor N1 and PMOS transistor P1 (e.g., inverters), resulting in a rapid rise at node Nd3. Furthermore, the rapidly rising voltage at node Nd4 will be inverted by NMOS transistor N1 and PMOS transistor P1 (e.g., inverters), resulting in a slow rise at node Nd3. In some embodiments, NMOS transistor N1 and PMOS transistor P1 are configured to generate an inverted input signal (not shown) in response to an input signal (not shown).

[0069] When an ESD event occurs at node Nd2 (e.g., an ESD current I1 in the forward ESD direction), because the voltage at node Nd4 corresponds to the output voltage of the high-pass filter (e.g., the voltage across resistor R1 relative to node ND2), the rapidly rising ESD current or voltage at node Nd2 causes the voltage at node Nd4 (e.g., across resistor R2) to rise rapidly. In other words, resistor R1 is configured as a high-pass filter, and the rapidly changing voltage or current from the ESD event is not filtered or passes through resistor R1. In response to the rapidly rising voltage at node Nd4, NMOS transistor N1 and PMOS transistor P1 are configured as inverters, thereby inverting the voltage at node Nd4 to the voltage at node Nd3, and the voltage at Nd3 rapidly decreases. In other words, the voltage at node Nd3 is inverted from the voltage at node Nd4. In some embodiments, in response to the voltage at node Nd4, PMOS transistor P3 is turned on and configured to clamp the voltage at node Nd3 to be equal to the voltage at node Nd1 (e.g., VDD), thereby assisting ESD detection circuit 202 in turning on PMOS transistor P2. In response to being turned on, PMOS transistor P2 couples node Nd2 to node Nd1, and NMOS transistor N2 discharges ESD current I1 in the forward ESD direction from node Nd2 to Nd1.

[0070] In some embodiments, by including an ESD auxiliary circuit 204a in the integrated circuit 200A, the PMOS transistor P3 of the ESD auxiliary circuit 204a is configured to reduce the capacitive coupling effect between nodes Nd2 and Nd3 and effectively reduce the on-resistance of the PMOS transistor P2 by clamping the voltage of node Nd3 to be equal to the voltage of node Nd1 during an ESD event at node Nd2 (e.g., VDD). As a result, the PMOS transistor P2 turns on faster and stronger than other methods, thus improving ESD performance and ESD stability compared to other methods.

[0071] In some embodiments, in response to an ESD event at node Nd2 (e.g., an ESD current I1 in the forward ESD direction), the body diode of PMOS transistor P3 is configured to provide ESD protection for integrated circuit 200A by clamping the voltage at node Nd3. In some embodiments, the body diode of PMOS transistor P2 is configured to provide ESD protection for integrated circuit 200A by delivering an ESD current I1 in the forward ESD direction from node Nd2 to node Nd1.

[0072] In some embodiments, the ESD auxiliary circuit 204a has minimal impact on ESD events at node Nd1. For example, in some embodiments, the PMOS transistor P3 is turned off when an ESD event occurs at node Nd1.

[0073] At least other types of circuits, configurations, and arrangements of ESD detection circuit 202, ESD auxiliary circuit 204a, or discharge circuit 210 are within the scope of this disclosure.

[0074] Other configurations or quantities of circuits in integrated circuit 200A are within the scope of this disclosure.

[0075] Figure 2B This is a circuit diagram of integrated circuit 200B according to some embodiments.

[0076] Integrated circuit 200B is at least an embodiment of ESD clamping circuit 120, and therefore a similar detailed description is omitted.

[0077] Integrated circuit 200B is Figure 2A This is a variant of integrated circuit 200A, and therefore a similar detailed description is omitted. Compared to integrated circuit 200A, integrated circuit 200B uses ESD auxiliary circuit 204b instead of ESD auxiliary circuit 204a of integrated circuit 200A, and therefore a similar detailed description is omitted.

[0078] The integrated circuit 200B includes a control circuit 201, an ESD detection circuit 202, an ESD auxiliary circuit 204b, and a discharge circuit 210.

[0079] ESD auxiliary circuit 204b is Figure 2A This is a variant of the ESD auxiliary circuit 204a, and therefore a similar detailed description is omitted. Compared to the ESD auxiliary circuit 204a, the diode D1 of the ESD auxiliary circuit 204b replaces the PMOS transistor P3 of the ESD auxiliary circuit 204a, and therefore a similar detailed description is omitted.

[0080] ESD auxiliary circuit 204b includes diode D1. Diode D1 includes an anode and a cathode (not labeled).

[0081] and Figure 2A Compared to the ESD auxiliary circuit 204a, each of the following is coupled together: the anode of diode D1, node Nd3, the drain of NMOS transistor N1, the drain of PMOS transistor P1, and the gate of PMOS transistor P2.

[0082] and Figure 2A Compared to the ESD auxiliary circuit 204a, the cathode of diode D1, the second terminal of capacitor C1, node Nd1, the source of PMOS transistor P1, the body of PMOS transistor P1, the source of PMOS transistor P2, and the body of PMOS transistor P2 are coupled together.

[0083] use Figure 2B The description of the ESD auxiliary circuit 204b for an ESD event occurring at node Nd2 (e.g., an ESD current I1 in the positive ESD direction) is similar to... Figure 2A The description of an ESD event occurring at node Nd2 of the ESD auxiliary circuit 204a is omitted for brevity. In some embodiments, in response to an ESD event at node Nd2 (e.g., an ESD current I1 in the forward ESD direction), diode D1 is configured to be forward biased, thereby clamping the voltage at node Nd3 to be equal to the voltage at node Nd1 (e.g., VDD), thereby enabling the auxiliary ESD detection circuit 202 to turn on PMOS transistor P2. In response to being turned on, PMOS transistor P2 couples node Nd2 to node Nd1, and PMOS transistor P2 discharges the ESD current I1 in the forward ESD direction from node Nd2 to Nd1.

[0084] In some embodiments, by including an ESD auxiliary circuit 200B in the integrated circuit 200B, the integrated circuit 200B achieves at least the above-mentioned Figure 1 or Figure 2A One or more benefits discussed in the text.

[0085] At least other types of circuits, configurations, and arrangements of ESD detection circuit 202, ESD auxiliary circuit 204b, or discharge circuit 210 are within the scope of this disclosure.

[0086] Other configurations or quantities of circuits in integrated circuit 200B are within the scope of this disclosure.

[0087] Figure 2C This is a circuit diagram of an integrated circuit 200C according to some embodiments.

[0088] Integrated circuit 200C is at least an embodiment of ESD clamping circuit 120, and therefore a similar detailed description is omitted.

[0089] Integrated Circuit 200C is Figure 2A This is a variant of integrated circuit 200A, and therefore a similar detailed description is omitted. Compared to integrated circuit 200A, integrated circuit 200C uses ESD auxiliary circuit 204c instead of ESD auxiliary circuit 204a of integrated circuit 200A, and therefore a similar detailed description is omitted.

[0090] The integrated circuit 200C includes a control circuit 201, an ESD detection circuit 202, an ESD auxiliary circuit 204c, and a discharge circuit 210.

[0091] ESD auxiliary circuit 204c is Figure 2A This is a variant of the ESD auxiliary circuit 204a, and therefore a similar detailed description is omitted. Compared to the ESD auxiliary circuit 204a, the ESD auxiliary circuit 204c uses transistor B1 instead of the PMOS transistor P3 of the ESD auxiliary circuit 204a, and therefore a similar detailed description is omitted. Transistor B1 is a PNP bipolar junction transistor (BJT).

[0092] The ESD auxiliary circuit 204c includes transistor B1. Transistor B1 includes a base, a collector, and an emitter (not labeled).

[0093] and Figure 2A Compared to the ESD auxiliary circuit 204a, each of the collector of transistor B1, node Nd3, drain of NMOS transistor N1, drain of PMOS transistor P1, and gate of PMOS transistor P2 is coupled together.

[0094] and Figure 2A Compared to the ESD auxiliary circuit 204a, each of the following transistors is coupled together: the emitter of transistor B1, the base of transistor B1, the second terminal of capacitor C1, node Nd1, the source of PMOS transistor P1, the body of PMOS transistor P1, the source of PMOS transistor P2, and the body of PMOS transistor P2.

[0095] use Figure 2C The description of the ESD auxiliary circuit 204c for an ESD event occurring at node Nd2 (e.g., an ESD current I1 in the positive ESD direction) is similar to that of the circuit. Figure 2A The description of an ESD event occurring at node Nd2 of the ESD auxiliary circuit 204a is omitted for brevity. In some embodiments, in response to an ESD event at node Nd2 (e.g., an ESD current I1 in the forward ESD direction), transistor B1 is turned on and configured to clamp the voltage at node Nd3 to be equal to the voltage at node Nd1 (e.g., VDD), thereby enabling the auxiliary ESD detection circuit 202 to turn on PMOS transistor P2. In response to being turned on, PMOS transistor P2 couples node Nd2 to node Nd1, and PMOS transistor P2 discharges the ESD current I1 in the forward ESD direction from node Nd2 to Nd1.

[0096] In some embodiments, in response to an ESD event at node Nd2 (e.g., an ESD current I1 in the forward ESD direction), the body diode of transistor B1 is configured to provide ESD protection for integrated circuit 200C by clamping the voltage at node Nd3. In some embodiments, the body diode of PMOS transistor P2 is configured to provide ESD protection for integrated circuit 200C by delivering an ESD current I1 in the forward ESD direction from node Nd2 to node Nd1.

[0097] In some embodiments, by including an ESD auxiliary circuit 200C in the integrated circuit 200C, the integrated circuit 200C achieves at least the above-mentioned Figure 1 or Figure 2A One or more benefits discussed in the text.

[0098] At least other types of circuits, configurations, and arrangements of ESD detection circuit 202, ESD auxiliary circuit 204c, or discharge circuit 210 are within the scope of this disclosure.

[0099] Other configurations or quantities of circuits in the integrated circuit 200C are within the scope of this disclosure.

[0100] Figure 2D This is a circuit diagram of an integrated circuit 200D according to some embodiments.

[0101] Integrated circuit 200D is at least an embodiment of ESD clamping circuit 120, and therefore a similar detailed description is omitted.

[0102] Integrated Circuit 200D is Figure 2AThis is a variant of integrated circuit 200A, and therefore a similar detailed description is omitted. Compared to integrated circuit 200A, integrated circuit 200D has ESD auxiliary circuit 204d instead of ESD auxiliary circuit 204a of integrated circuit 200A, and therefore a similar detailed description is omitted.

[0103] The integrated circuit 200D includes a control circuit 201, an ESD detection circuit 202, an ESD auxiliary circuit 204d, and a discharge circuit 210.

[0104] ESD auxiliary circuit 204d is Figure 2A This is a variant of the ESD auxiliary circuit 204a, and therefore a similar detailed description is omitted. Compared to the ESD auxiliary circuit 204a, the NMOS transistor N2 of the ESD auxiliary circuit 204d replaces the PMOS transistor P3 of the ESD auxiliary circuit 204a, and therefore a similar detailed description is omitted.

[0105] ESD auxiliary circuit 204d includes an NMOS transistor N2. The NMOS transistor N2 includes a gate, drain, source, and body (not labeled).

[0106] and Figure 2A Compared to the ESD auxiliary circuit 204a, each of the gate, source, body, node Nd3, drain of NMOS transistor N1, drain of PMOS transistor P1, and gate of PMOS transistor P2 is coupled together.

[0107] and Figure 2A Compared to the ESD auxiliary circuit 204a, each of the following is coupled together: the drain of NMOS transistor N2, the second terminal of capacitor C1, node Nd1, the source of PMOS transistor P1, the body of PMOS transistor P1, the source of PMOS transistor P2, and the body of PMOS transistor P2.

[0108] use Figure 2D The description of the ESD auxiliary circuit 204d for an ESD event (e.g., an ESD current I1 in the positive ESD direction) occurring at node Nd2 is similar to... Figure 2AThe description of an ESD event occurring at node Nd2 of the ESD auxiliary circuit 204a is omitted for brevity. In some embodiments, in response to an ESD event at node Nd2 (e.g., an ESD current I1 in the forward ESD direction), NMOS transistor N2 is turned on and configured to clamp the voltage at node Nd3 to be equal to the voltage at node Nd1 (e.g., VDD), thereby enabling the auxiliary ESD detection circuit 202 to turn on PMOS transistor P2. In response to being turned on, PMOS transistor P2 couples node Nd2 to node Nd1, and PMOS transistor P2 discharges the ESD current I1 in the forward ESD direction from node Nd2 to Nd1.

[0109] In some embodiments, in response to an ESD event at node Nd2 (e.g., an ESD current I1 in the forward ESD direction), the body diode of NMOS transistor N2 is configured to provide ESD protection for integrated circuit 200D by clamping the voltage at node Nd3. In some embodiments, the body diode of PMOS transistor P2 is configured to provide ESD protection for integrated circuit 200D by delivering an ESD current I1 in the forward ESD direction from node Nd2 to node Nd1.

[0110] In some embodiments, by including an ESD auxiliary circuit 200D in the integrated circuit 200D, the integrated circuit 200D achieves at least the above-mentioned Figure 1 or Figure 2A One or more benefits discussed in the text.

[0111] At least other types of circuits, configurations, and arrangements of ESD detection circuit 202, ESD auxiliary circuit 204d, or discharge circuit 210 are within the scope of this disclosure.

[0112] Other configurations or quantities of circuits in the integrated circuit 200D are within the scope of this disclosure.

[0113] Figure 2E This is a circuit diagram of an integrated circuit 200E according to some embodiments.

[0114] Integrated circuit 200E is at least an embodiment of ESD clamping circuit 120, and therefore a similar detailed description is omitted.

[0115] Integrated circuit 200E is Figure 2A This is a variant of integrated circuit 200A, and therefore a similar detailed description is omitted. Compared to integrated circuit 200A, integrated circuit 200E has ESD auxiliary circuit 204e instead of ESD auxiliary circuit 204a of integrated circuit 200A, and therefore a similar detailed description is omitted.

[0116] The integrated circuit 200E includes a control circuit 201, an ESD detection circuit 202, an ESD auxiliary circuit 204e, and a discharge circuit 210.

[0117] ESD auxiliary circuit 204e is Figure 2A This is a variant of the ESD auxiliary circuit 204a, and therefore a similar detailed description is omitted. Compared to the ESD auxiliary circuit 204a, the ESD auxiliary circuit 204e uses transistor B2 instead of the PMOS transistor P3 of the ESD auxiliary circuit 204a, and therefore a similar detailed description is omitted. Transistor B2 is an NPN BJT.

[0118] The ESD auxiliary circuit 204e includes transistor B2. Transistor B2 includes a base, a collector, and an emitter (not labeled).

[0119] and Figure 2A Compared to the ESD auxiliary circuit 204a, each of the emitter of transistor B2, the base of transistor B2, node Nd3, the drain of NMOS transistor N1, the drain of PMOS transistor P1, and the gate of PMOS transistor P2 is coupled together.

[0120] and Figure 2A Compared to the ESD auxiliary circuit 204a, each of the collector of transistor B2, the second terminal of capacitor C1, node Nd1, the source of PMOS transistor P1, the body of PMOS transistor P1, PMOS transistor P2, and the body of PMOS transistor P2 is coupled together.

[0121] use Figure 2E The description of the ESD auxiliary circuit 204e for an ESD event occurring at node Nd2 (e.g., an ESD current I1 in the positive ESD direction) is similar to that of the corresponding circuit. Figure 2A and Figure 2C The description of the ESD auxiliary circuits 204a and 204c at node Nd2 when an ESD event occurs is omitted for brevity. In some embodiments, in response to an ESD event at node Nd2 (e.g., an ESD current I1 in the forward ESD direction), transistor B2 is turned on and configured to clamp the voltage at node Nd3 to be equal to the voltage at node Nd1 (e.g., VDD), thereby enabling the auxiliary ESD detection circuit 202 to turn on PMOS transistor P2. In response to being turned on, PMOS transistor P2 couples node Nd2 to node Nd1, and PMOS transistor P2 discharges the ESD current I1 in the forward ESD direction from node Nd2 to Nd1.

[0122] In some embodiments, in response to an ESD event at node Nd2 (e.g., an ESD current I1 in the forward ESD direction), the body diode of transistor B2 is configured to provide ESD protection for integrated circuit 200E by clamping the voltage at node Nd3. In some embodiments, the body diode of PMOS transistor P2 is configured to provide ESD protection for integrated circuit 200E by delivering an ESD current I1 in the forward ESD direction from node Nd2 to node Nd1.

[0123] In some embodiments, by including an ESD auxiliary circuit 200E in the integrated circuit 200E, the integrated circuit 200E achieves at least the above-mentioned Figure 1 or Figure 2A One or more benefits discussed in the text.

[0124] At least other types of circuits, configurations, and arrangements of ESD detection circuit 202, ESD auxiliary circuit 204e, or discharge circuit 210 are within the scope of this disclosure.

[0125] Other configurations or quantities of circuits in integrated circuit 200E are within the scope of this disclosure.

[0126] Figure 3A This is a cross-sectional view of integrated circuit 300A according to some embodiments.

[0127] Integrated circuit 300A is Figure 2A An embodiment of the PMOS transistor P3 of the ESD auxiliary circuit 204a is described, and therefore a similar detailed description is omitted.

[0128] Integrated circuit 300A includes substrate 302b.

[0129] Substrate 302b is an n-type substrate. In some embodiments, substrate 302b is a p-type substrate. In some embodiments, substrate 302b comprises: elemental semiconductors, including crystalline, polycrystalline, or amorphous silicon or germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable material; or combinations thereof. In some embodiments, the alloy semiconductor substrate has a gradient SiGe feature, wherein the Si and Ge composition changes from one ratio at one location of the gradient SiGe feature to another ratio at another location. In some embodiments, alloy SiGe is formed over a silicon substrate. In some embodiments, substrate 302b is a strained SiGe substrate. In some embodiments, the semiconductor substrate has a semiconductor-on-insulator structure, such as a silicon-on-insulator (SOI) structure. In some embodiments, the semiconductor substrate includes a doped epitaxial layer or a buried layer. In some embodiments, the compound semiconductor substrate has a multilayer structure, or the substrate includes a multilayer compound semiconductor structure.

[0130] In some embodiments, substrate 302b is replaced by an N-well formed inside a p-type substrate. In some embodiments, the N-well has an N-type dopant, and the p-type substrate has a p-type dopant.

[0131] The integrated circuit 300A also includes a gate structure 330 located above the substrate 302b. The gate structure 330 includes a gate dielectric 322 and a gate electrode 330a. The integrated circuit 300A also includes sidewalls 320a and 320b on opposite sides of the gate structure 330.

[0132] Integrated circuit 300A also includes a drain region 312a and a source region 314a. The source region 314a is a P+ active region having a P-type dopant in an implanted well (not shown) or in the substrate 302b. The drain region 312a is a P+ active region having a P-type dopant in an implanted well (not shown) or in the substrate 302b. In some embodiments, at least the source region 314a or the drain region 312a extends over the substrate 302b.

[0133] In some embodiments, Figure 3A The drain region 312a and source region 314a of transistor 360a or Figures 2B-2E and Figures 4A-4E The active regions of other devices are referred to as oxide-defined (OD) regions, which define the active regions of integrated circuits 300A-300E and 400A-400E (described below).

[0134] In some embodiments, integrated circuit 300A further includes a lightly doped drain (LDD) region 318 adjacent to the source region 314a and the drain region 312a and below the sidewall 320. In some embodiments, the first element and the second element being adjacent to each other includes a scenario where the first element and the second element are directly adjacent. In some embodiments, the first element and the second element being adjacent to each other includes a scenario where an intermediate element is located between the first element and the second element. In some embodiments, the LDD region 360 helps transistor 360a maintain a low leakage current.

[0135] In some embodiments, the drain region 312a, source region 314a, LDD region 318, sidewall 320, and gate structure 330 together form transistor 360a. Transistor 360a is a PMOS transistor.

[0136] Drain region 312a corresponds to Figure 2A The drain and source regions 314a of the PMOS transistor P3 correspond to Figure 2A The source and gate structure 330 of the PMOS transistor P3 corresponds to Figure 2A The gate, junction regions 316a and 317a of the PMOS transistor P3 correspond to Figure 2A The body of the PMOS transistor P3 is described, and therefore a similar detailed description is omitted.

[0137] Drain region 312a is coupled to node Nd3 (e.g. Figure 2A (As shown). Gate structure 330, source region 314a, and junction regions 316a and 316b are coupled to a supply voltage (e.g., voltage VDD) via node Nd1. In some embodiments, each of gate structure 330, source region 314a, and junction regions 316a and 316b is coupled together at node Nd1 and is also coupled to a supply voltage (e.g., voltage VDD).

[0138] In some embodiments, according to FinFET (Fin Field-Effect Transistor) Complementary Metal-Oxide-Semiconductor (CMOS) technology, the drain region 312a and source region 314a include fins. In some embodiments, the drain region 312a and source region 314a include nanosheets of a nanosheet transistor. In some embodiments, the drain region 312a and source region 314a include nanowires of a nanowire transistor. In some embodiments, according to planar CMOS technology, the drain region 312a and source region 314a do not have fins. Other types of transistors are also within the scope of this disclosure.

[0139] In some embodiments, drain region 312a is an extended drain region and has a larger size than source region 314a. In at least one embodiment, a silicide layer (not shown) covers a portion, but not all, of drain region 312a. This partial silicide configuration of drain region 312a improves the self-protection of transistor 360a against ESD events. In at least one embodiment, drain region 312a is fully silicided.

[0140] A gate structure 330 is disposed between a drain region 312a and a source region 314a. In some embodiments, the gate electrode 330a comprises a conductive material, such as metal or polysilicon (also referred to herein as “POLY”). In some embodiments, the gate structure 330 is coupled to a supply voltage terminal (e.g., voltage VDD) or a reference supply voltage terminal (e.g., voltage VSS).

[0141] Integrated circuit 300A also includes connector regions 316a and 317a and shallow trench isolation (STI) regions 308, 309, 310 and 311.

[0142] STI region 308 is configured to at least isolate drain region 312a and connector region 317a from each other. In some embodiments, STI region 308 is configured to isolate drain region 312a or connector region 317a from other portions (not shown) of integrated circuit 300A.

[0143] STI region 309 is configured to isolate connector region 317a from other parts of integrated circuit 300A.

[0144] STI region 310 is configured to at least isolate source region 316a and connector region 316a from each other. In some embodiments, STI region 310 is configured to isolate source region 316a or connector region 316a from other portions (not shown) of integrated circuit 300A.

[0145] STI region 311 is configured to isolate connector region 316a from other parts of integrated circuit 300A.

[0146] In some embodiments, connector regions 316a and 317a correspond to well connectors. In some embodiments, the well connector is a conductive material that couples the source / drain regions of the integrated circuit 300A to a voltage supply node (e.g., supply voltage VDD).

[0147] Connector regions 316a and 317a are heavily doped n-regions in a well (not shown) or substrate 302b. In some embodiments, connector regions 316a and 317a are heavily doped n-regions in an n-type well (not shown) on a p-type substrate. In some embodiments, the heavily doped n-regions are coupled to a voltage supply node (e.g., supply voltage VDD) via a well connector, thereby setting the potential of the n-type well or substrate 302b to prevent leakage from adjacent source / drain regions into the n-well / p-substrate.

[0148] Integrated circuit 300A also includes a body diode 340a. The body diode 340a is a parasitic element formed by a PN junction between a drain region 312a and at least a junction region 316a or 317a. In some embodiments, the body diode 340a is formed by a PN junction between a drain region 312a and a source region 314a. The body diode 340a is also referred to as a parasitic diode or an internal diode of integrated circuit 300A. In some embodiments, in response to a positive ESD event at node Nd2, the body diode 340a of PMOS transistor P3 is configured to provide ESD protection for integrated circuit 300A by clamping the voltage at node Nd3, and integrated circuit 300A thereby achieves at least the above-mentioned ESD protection. Figure 1 or Figure 2A One or more benefits discussed in the text.

[0149] Figure 3B This is a cross-sectional view of integrated circuit 300B according to some embodiments.

[0150] Integrated circuit 300B is Figure 2B An embodiment of diode D1 in the ESD auxiliary circuit 204b is described, and therefore a similar detailed description is omitted. Integrated circuit 300B is... Figure 3A A variant of the integrated circuit 300A, and therefore a similar detailed description is omitted.

[0151] Integrated circuit 300B includes substrate 302b, P-type region 352a, N-type region 356a, and STI regions 308, 310, and 311.

[0152] P-type region 352a is similar to Figure 3A The drain region 312a in the diagram is omitted here, and therefore a similar detailed description is omitted.

[0153] Substrate 302b is an n-type substrate with N-type dopant. P-type region 352a is a P+ active region having an implanted well (not shown) or P-type dopant in substrate 302b. N-type region 356a is an N+ active region having an implanted well (not shown) or N-type dopant in substrate 302b. STI region 310 is located between P-type region 352a and N-type region 356a.

[0154] STI region 308 is configured to isolate at least the P-type region 352a from other portions (not shown) of integrated circuit 300B. STI region 311 is configured to isolate at least the N-type region 356a from other portions (not shown) of integrated circuit 300B.

[0155] STI region 310 is configured to isolate at least P-type region 352a and N-type region 356a from each other. In some embodiments, STI region 310 is configured to isolate either P-type region 352a or N-type region 356a from other portions (not shown) of integrated circuit 300B.

[0156] P-type region 352a corresponds to Figure 2B The anode of diode D1, N-type region 356a corresponds to Figure 2B The cathode of diode D1 is described, and therefore a similar detailed description is omitted.

[0157] P-type region 352a is coupled to node Nd3 (e.g., ... Figure 2A (As shown). N-type region 356a is coupled to the supply voltage (e.g., voltage VDD) through node Nd1.

[0158] Integrated circuit 300B also includes a body diode 340b. The body diode 340b is a parasitic element formed by the PN junction between the P-type region 352a and the N-type region 356a. In some embodiments, in response to an ESD event in the forward direction at node Nd2, the body diode 340b is configured to provide ESD protection for integrated circuit 300B by clamping the voltage at node Nd3, thereby achieving at least the above-mentioned ESD protection. Figure 1 or Figure 2A The benefits are discussed in the text.

[0159] Figure 3C This is a cross-sectional view of an integrated circuit 300C according to some embodiments.

[0160] Integrated circuit 300C is Figure 2C An embodiment of transistor B1 in the ESD auxiliary circuit 204c is described, and therefore a similar detailed description is omitted. Integrated circuit 300C is Figure 3A A variant of the integrated circuit 300A, and therefore a similar detailed description is omitted.

[0161] Integrated circuit 300C includes a substrate 302a, a P-type region 362a, and an N-type region 366a. Substrate 302a is similar to substrate 302b, and P-type region 362a is similar to... Figure 3B The P-type region 352a and N-type region 366a are similar to Figure 3B The N-type region 356a in the text is omitted here, and therefore a similar detailed description is omitted.

[0162] exist Figure 3C In this design, substrate 302a is a p-type substrate with p-type dopant. N-type region 366a is an N+ active region with N-type dopant implanted in substrate 302a. P-type region 362a is a P+ active region with P-type dopant implanted in N-type region 366a.

[0163] P-type region 362a corresponds to Figure 2C The emitter of transistor B1, the N-type region 366a corresponds to Figure 2C The base of transistor B1, substrate 302a corresponds to Figure 2C The collector of transistor B1, and therefore a similar detailed description is omitted.

[0164] Each of the P-type region 362a and the N-type region 366a is coupled together and is also coupled to the supply voltage (e.g., voltage VDD) through node Nd1. Substrate 302a is coupled to node Nd3.

[0165] Integrated circuit 300C also includes a body diode 340c. The body diode 340c is a parasitic element formed by a PN junction between substrate 302a and N-type region 366a. In some embodiments, in response to an ESD event in the forward direction at node Nd2, the body diode 340c is configured to provide ESD protection for integrated circuit 300C by clamping the voltage at node Nd3, thereby achieving at least the above-ground ESD protection. Figure 1 or Figure 2A The benefits are discussed in the text.

[0166] Figure 3D This is a cross-sectional view of an integrated circuit 300D according to some embodiments.

[0167] Integrated circuit 300D is Figure 2D An embodiment of the NMOS transistor N2 in the ESD auxiliary circuit 204d is described, and therefore a similar detailed description is omitted. Integrated circuit 300D is... Figure 3A A variant of the integrated circuit 300A, and therefore a similar detailed description is omitted.

[0168] and Figure 3A Compared to the integrated circuit 300A, the drain region 312b replaces... Figure 3A The drain region 312a and the source region 314b are replaced. Figure 3A The source region 314a, junction regions 316b and 317b are replaced Figure 3A The corresponding junction areas 316a and 317a are replaced by transistor 360b, and therefore a similar detailed description is omitted.

[0169] The integrated circuit 300D includes a substrate 302a, a gate structure 330, a drain region 312b, a source region 314b, an LDD region 318, a sidewall 320, junction regions 316b and 317b, STI regions 308, 309, 310 and 311, and a body diode 340d.

[0170] exist Figure 3D In this context, substrate 302a is a p-type substrate with p-type dopant.

[0171] In some embodiments, the drain region 312b, source region 314b, LDD region 318, sidewall 320, and gate structure 330 together form transistor 360b. Transistor 360b is an NMOS transistor.

[0172] Drain region 312b corresponds to Figure 2D The drain and source regions 314b of the NMOS transistor N2 correspond to Figure 2D The source and gate structure 330 of the NMOS transistor N2 corresponds to Figure 2D The gate, junction regions 316b and 317b of the NMOS transistor N2 correspond to Figure 2D The body of the NMOS transistor N2, and therefore a similar detailed description is omitted.

[0173] The drain region 312b is coupled to the supply voltage (e.g., voltage VDD) through node Nd1. The gate structure 330, the source region 314b, and the junction region 316b are coupled to node Nd3.

[0174] STI region 308 is configured to at least isolate drain region 312b and connector region 317b from each other. In some embodiments, STI region 308 is configured to isolate drain region 312b or connector region 317b from other portions (not shown) of integrated circuit 300D.

[0175] STI region 309 is configured to isolate connector region 317b from other parts of integrated circuit 300D.

[0176] STI region 310 is configured to at least isolate source region 316b and connector region 316b from each other. In some embodiments, STI region 310 is configured to isolate source region 316b or connector region 316b from other portions (not shown) of integrated circuit 300D.

[0177] STI region 311 is configured to isolate connector region 316b from other parts of integrated circuit 300D.

[0178] In some embodiments, junction regions 316b and 317b correspond to substrate junctions. In some embodiments, the substrate junction is a conductive material that couples junction regions 316b and 317b to a reference voltage supply node (e.g., supply voltage VSS). For example, in some embodiments, junction regions 316b and 317b of substrate 302a include heavily doped p-regions formed in a p-type substrate. In some embodiments, the heavily doped p-regions are coupled to the reference voltage supply node (e.g., reference supply voltage VSS) through junction regions 316b and 317b, thereby setting the potential of substrate 302a to prevent leakage from adjacent source / drain regions.

[0179] Integrated circuit 300D also includes a body diode 340d. The body diode 340d is a parasitic element formed by a PN junction between at least the junction region 316b or 317b and the drain region 312b. In some embodiments, the body diode 340d is formed by a PN junction between the source region 314b and the drain region 312b. In some embodiments, in response to an ESD event in the forward direction at node Nd2, the body diode 340d of the NMOS transistor N2 is configured to provide ESD protection for integrated circuit 300D by clamping the voltage at node Nd3, and integrated circuit 300D thereby achieves at least the above-mentioned ESD protection. Figure 1 or Figure 2A One or more benefits discussed in the text.

[0180] Figure 3E This is a cross-sectional view of integrated circuit 300E according to some embodiments.

[0181] Integrated circuit 300E is Figure 2E An embodiment of transistor B2 in the ESD auxiliary circuit 204e is described, and therefore a similar detailed description is omitted. Integrated circuit 300E is Figure 3C A variant of the integrated circuit 300C, and therefore a similar detailed description is omitted.

[0182] Integrated circuit 300E includes a substrate 302b, an N-type region 362b, and a P-type region 366b. The N-type region 362b is similar to... Figure 3B The N-type region 366a and P-type region 366b are similar to Figure 3B The P-type region 362a in the text is omitted here, and therefore a similar detailed description is omitted.

[0183] Substrate 302b is an N-type substrate with N-type dopant. P-type region 366b is a P+ active region with P-type dopant implanted in substrate 302b. N-type region 362b is an N+ active region with N-type dopant implanted in P-type region 366b.

[0184] N-type region 362b corresponds to Figure 2EThe emitter of transistor B2, P-type region 366b corresponds to Figure 2E The base of transistor B2, substrate 302b corresponds to Figure 2E The collector of transistor B2, and therefore a similar detailed description is omitted.

[0185] Each of the N-type region 362b and the P-type region 366b is coupled together and also coupled to node Nd3. Substrate 302b is coupled to the supply voltage (e.g., voltage VDD) through node Nd1.

[0186] Integrated circuit 300E also includes a body diode 340e. The body diode 340e is a parasitic element formed by a PN junction between the P-type region 366b and the substrate 302b. In some embodiments, in response to an ESD event in the forward direction at node Nd2, the body diode 340e is configured to provide ESD protection for integrated circuit 300E by clamping the voltage at node Nd3, thereby achieving at least the above-mentioned ESD protection. Figure 1 or Figure 2A One or more benefits discussed in the text.

[0187] Figure 4A This is a circuit diagram of an integrated circuit 400A according to some embodiments.

[0188] Integrated circuit 400A is at least an embodiment of ESD clamping circuit 120, and therefore a similar detailed description is omitted.

[0189] Integrated circuit 400A is Figure 2A This is a variant of integrated circuit 200A, and therefore a similar detailed description is omitted. Compared to integrated circuit 200A, integrated circuit 400A has ESD detection circuit 402 instead of ESD detection circuit 202 of integrated circuit 200A, ESD auxiliary circuit 404a instead of ESD auxiliary circuit 204a of integrated circuit 200A, and discharge circuit 410 instead of discharge circuit 210 of integrated circuit 200A, and therefore a similar detailed description is omitted.

[0190] The integrated circuit 400A includes a control circuit 201, an ESD detection circuit 402, an ESD auxiliary circuit 404a, and a discharge circuit 410.

[0191] ESD detection circuit 402 is Figure 2A This is a variant of the ESD detection circuit 202, and therefore a similar detailed description is omitted. Compared to the ESD detection circuit 202, the resistor R2 of the ESD detection circuit 402 replaces the resistor R1 of the ESD detection circuit 202, and the capacitor C2 of the ESD detection circuit 402 replaces the capacitor C1 of the ESD detection circuit 202, and therefore a similar detailed description is omitted.

[0192] ESD discharge circuit 410 is Figure 2A This is a variant of the ESD discharge circuit 210, and therefore a similar detailed description is omitted. Compared to the ESD discharge circuit 210, the NMOS transistor N3 of the ESD discharge circuit 410 replaces the PMOS transistor P2 of the ESD discharge circuit 210, and therefore a similar detailed description is omitted.

[0193] ESD auxiliary circuit 404a is Figure 2A This is a variant of the ESD auxiliary circuit 204a, and therefore a similar detailed description is omitted. Compared to the ESD auxiliary circuit 204a, the NMOS transistor N4 of the ESD auxiliary circuit 404a replaces the PMOS transistor P3 of the ESD auxiliary circuit 204a, and therefore a similar detailed description is omitted.

[0194] ESD auxiliary circuit 404a includes an NMOS transistor N4. In some embodiments, the NMOS transistor N4 is a ground-gate NMOS (ggNMOS) transistor. The NMOS transistor N4 includes a gate, a drain, a source, and a body (not shown).

[0195] The ESD discharge circuit 410 includes an NMOS transistor N3. The NMOS transistor N3 includes a gate, drain, source, and body (not shown).

[0196] The first terminal of capacitor C2, node Nd2, source of NMOS transistor N1, body of NMOS transistor N1, source of NMOS transistor N3, body of NMOS transistor N3, gate of NMOS transistor N4, source of NMOS transistor N4, and body of NMOS transistor N4 are coupled together.

[0197] The first end of resistor R2, node Nd4, the second end of capacitor C2, the gate of PMOS transistor P1, and the gate of NMOS transistor N2 are all coupled together.

[0198] The second end of resistor R2, node Ndl, the source of PMOS transistor Pl, the body of PMOS transistor Pl, and the drain of NMOS transistor N3 are all coupled together.

[0199] Each of node Nd3, the drain of NMOS transistor N1, the drain of PMOS transistor P1, the drain of PMOS transistor N4, and the gate of NMOS transistor N3 is coupled together.

[0200] In some embodiments, capacitor C2 is a transistor coupling capacitor. For example, in some embodiments, capacitor C2 is a transistor having a drain and a source coupled together, thus forming a transistor coupling capacitor.

[0201] Resistor R2 and capacitor C2 are configured as an RC network. Depending on the location of the RC network's output, the RC network can be configured as a low-pass filter or a high-pass filter.

[0202] When an ESD event occurs at node Nd2 (e.g., an ESD current I1 in the forward ESD direction), the voltage at node Nd4 corresponds to the output voltage of the low-pass filter (e.g., the voltage across capacitor C2 relative to node ND2). The rapid increase in the ESD current or voltage at node Nd2 causes a slow increase in the voltage at node Nd4 (e.g., across capacitor C2). In other words, capacitor C2 is configured as a low-pass filter, and the rapidly changing voltage or current from the ESD event is filtered by capacitor C2. In some embodiments, the ESD detection circuit 402 has minimal impact on ESD events at node Nd2.

[0203] When an ESD event occurs at node Nd2 (e.g., ESD current Il flows in the forward ESD direction), the ESD current or voltage at node Nd2 rises rapidly, and the ESD auxiliary circuit 404a detects the rapidly rising current or voltage at node Nd2, causing the NMOS transistor N4 of the ESD auxiliary circuit 404a to turn on. In response to this turn-on, the NMOS transistor N4 couples node Nd2 to node Nd3, thereby charging the gate of node Nd3 and the gate of the NMOS transistor N3 of the discharge circuit 410 in response to the rising ESD voltage or current. In other words, the NMOS transistor N4 clamps the voltage of node Nd3 at the voltage (VSS) of node Nd2. In response to the charging by the NMOS transistor N4 of the ESD auxiliary circuit 404a, the NMOS transistor N3 of the discharge circuit 410 turns on and couples node Nd2 to node Nd1. By being turned on and coupled node Nd2 to node Nd1, NMOS transistor N3 discharges ESD current I1 in the positive ESD direction from node Nd2 to Nd1.

[0204] In some embodiments, in response to an ESD event at node Nd2 (e.g., an ESD current I1 in the forward ESD direction), the body diode of NMOS transistor N4 is configured to provide ESD protection for integrated circuit 400A by clamping the voltage at node Nd3. In some embodiments, the body diode of NMOS transistor N3 is configured to provide ESD protection for integrated circuit 400A by carrying an ESD current I1 in the forward ESD direction from node Nd2 to node Nd1.

[0205] In some embodiments, by including an ESD auxiliary circuit 404a in the integrated circuit 400A, the NMOS transistor N4 of the ESD auxiliary circuit 404a is configured to control the gate potential of the NMOS transistor N3 by clamping the voltage of node Nd3 to equal the voltage of node Nd2 (e.g., VSS) during an ESD event at node Nd2, thereby reducing the capacitive coupling effect between nodes Nd1 and Nd3 and effectively reducing the on-resistance of the NMOS transistor N3, and thus enabling the NMOS transistor N3 to turn on faster and stronger than other methods, resulting in improved ESD performance and improved ESD robustness compared to other methods.

[0206] At least other types of circuits, configurations, and arrangements of ESD detection circuit 402, ESD auxiliary circuit 404a, or discharge circuit 410 are within the scope of this disclosure.

[0207] Other configurations or quantities of circuits in integrated circuit 400A are within the scope of this disclosure.

[0208] Figure 4B This is a circuit diagram of an integrated circuit 400B according to some embodiments.

[0209] Integrated circuit 400B is at least an embodiment of ESD clamping circuit 120, and therefore a similar detailed description is omitted.

[0210] Integrated circuit 400B is Figure 4A This is a variant of integrated circuit 400A, and therefore a similar detailed description is omitted. Compared to integrated circuit 400A, integrated circuit 400B has ESD auxiliary circuit 404b instead of ESD auxiliary circuit 404a of integrated circuit 400A, and therefore a similar detailed description is omitted.

[0211] The integrated circuit 400B includes a control circuit 201, an ESD detection circuit 402, an ESD auxiliary circuit 404b, and a discharge circuit 410.

[0212] ESD auxiliary circuit 404b is Figure 4A This is a variant of the ESD auxiliary circuit 404a, and therefore a similar detailed description is omitted. Compared to the ESD auxiliary circuit 404a, the diode D2 of the ESD auxiliary circuit 404b replaces the NMOS transistor N4 of the ESD auxiliary circuit 404a, and therefore a similar detailed description is omitted.

[0213] The ESD auxiliary circuit 404b includes diode D2. Diode D2 includes an anode and a cathode (not labeled).

[0214] and Figure 4ACompared to the ESD auxiliary circuit 404a, each of the cathode of diode D2, node Nd3, drain of NMOS transistor N1, drain of PMOS transistor P1, and gate of NMOS transistor N3 is coupled together.

[0215] and Figure 4A Compared to the ESD auxiliary circuit 404a, each of the following components is coupled together: the anode of diode D2, the first terminal of capacitor C2, node Nd2, the source of NMOS transistor N1, the body of NMOS transistor N1, the source of NMOS transistor N3, and the body of NMOS transistor N3.

[0216] use Figure 4B The description of the ESD auxiliary circuit 404b for an ESD event occurring at node Nd2 (e.g., an ESD current I1 in the positive ESD direction) is similar to... Figure 4A The description of an ESD event occurring at node Nd2 of the ESD auxiliary circuit 404a is omitted for brevity. In some embodiments, in response to an ESD event at node Nd2 (e.g., an ESD current I1 in the forward ESD direction), diode D2 is configured to be forward biased, thereby clamping the voltage at node Nd3 to be equal to the voltage at node Nd2 (e.g., VSS), causing NMOS transistor N3 to turn on. In response to being turned on, NMOS transistor N3 couples node Nd2 to node Nd1, and NMOS transistor N3 discharges the ESD current I1 in the forward ESD direction from node Nd2 to Nd1.

[0217] In some embodiments, by including an ESD auxiliary circuit 400B in the integrated circuit 400B, the integrated circuit 400B achieves at least the above-mentioned Figure 1 or Figure 4A One or more benefits discussed in the text.

[0218] At least other types of circuits, configurations, and arrangements of ESD detection circuit 402, ESD auxiliary circuit 404b, or discharge circuit 410 are within the scope of this disclosure.

[0219] Other configurations or quantities of circuits in integrated circuit 400B are within the scope of this disclosure.

[0220] Figure 4C This is a circuit diagram of an integrated circuit 400C according to some embodiments.

[0221] Integrated circuit 400C is at least an embodiment of ESD clamping circuit 120, and therefore a similar detailed description is omitted.

[0222] Integrated circuit 400C is Figure 4AThis is a variant of integrated circuit 400A, and therefore a similar detailed description is omitted. Compared to integrated circuit 400A, integrated circuit 400C uses ESD auxiliary circuit 404c instead of ESD auxiliary circuit 404a of integrated circuit 400A, and therefore a similar detailed description is omitted.

[0223] The integrated circuit 400C includes a control circuit 201, an ESD detection circuit 402, an ESD auxiliary circuit 404c, and a discharge circuit 410.

[0224] ESD auxiliary circuit 404c is Figure 4A This is a variant of the ESD auxiliary circuit 404a, and therefore a similar detailed description is omitted. Compared to the ESD auxiliary circuit 404a, the ESD auxiliary circuit 404c uses transistor B3 instead of the NMOS transistor N4 of the ESD auxiliary circuit 404a, and therefore a similar detailed description is omitted. Transistor B3 is an NPN BJT.

[0225] The ESD auxiliary circuit 404c includes transistor B3. Transistor B3 includes a base, a collector, and an emitter (not labeled).

[0226] and Figure 4A Compared to the ESD auxiliary circuit 404a, each of the collector of transistor B3, node Nd3, drain of NMOS transistor N1, drain of PMOS transistor P1, and gate of NMOS transistor N3 is coupled together.

[0227] and Figure 4A Compared to the ESD auxiliary circuit 404a, the emitter of transistor B3, the base of transistor B3, the first terminal of capacitor C2, node Nd2, the source of NMOS transistor N1, the body of NMOS transistor N1, the source of NMOS transistor N3, and the body of NMOS transistor N3 are all coupled together.

[0228] The description of an ESD event occurring at node Nd2 (e.g., an ESD current I1 in the positive ESD direction) using the ESD auxiliary circuit 404c of Figure 4 is similar to that for... Figure 4A The description of an ESD event occurring at node Nd2 of the ESD auxiliary circuit 404a is omitted for brevity. In some embodiments, in response to an ESD event at node Nd2 (e.g., an ESD current I1 in the forward ESD direction), transistor B3 is turned on and configured to clamp the voltage at node Nd3 to be equal to the voltage at node Nd2 (e.g., VSS), thereby causing NMOS transistor N3 to turn on. In response to being turned on, NMOS transistor N3 couples node Nd2 to node Nd1, and NMOS transistor N3 discharges the ESD current I1 in the forward ESD direction from node Nd2 to Nd1.

[0229] In some embodiments, in response to an ESD event at node Nd2 (e.g., an ESD current I1 in the forward ESD direction), the body diode of transistor B3 is configured to provide ESD protection for integrated circuit 400C by clamping the voltage at node Nd3. In some embodiments, the body diode of NMOS transistor N3 is configured to provide ESD protection for integrated circuit 400B by delivering an ESD current I1 in the forward ESD direction from node Nd2 to Nd1.

[0230] In some embodiments, by including an ESD auxiliary circuit 400C in the integrated circuit 400C, the integrated circuit 400C achieves at least the above-mentioned Figure 1 or Figure 4A One or more benefits discussed in the text.

[0231] At least other types of circuits, configurations, and arrangements of ESD detection circuit 402, ESD auxiliary circuit 404c, or discharge circuit 410 are within the scope of this disclosure.

[0232] Other configurations or quantities of circuits in the integrated circuit 400C are within the scope of this disclosure.

[0233] Figure 4D This is a circuit diagram of an integrated circuit 400D according to some embodiments.

[0234] Integrated circuit 400D is at least an embodiment of ESD clamping circuit 120, and therefore a similar detailed description is omitted.

[0235] Integrated circuit 400D is Figure 4A This is a variant of integrated circuit 400A, and therefore a similar detailed description is omitted. Compared to integrated circuit 400A, integrated circuit 400D has ESD auxiliary circuit 404d instead of ESD auxiliary circuit 404a of integrated circuit 400A, and therefore a similar detailed description is omitted.

[0236] The integrated circuit 400D includes a control circuit 201, an ESD detection circuit 402, an ESD auxiliary circuit 404d, and a discharge circuit 410.

[0237] ESD auxiliary circuit 404d is Figure 4A This is a variant of the ESD auxiliary circuit 404a, and therefore a similar detailed description is omitted. Compared to the ESD auxiliary circuit 404a, the PMOS transistor P4 of the ESD auxiliary circuit 404d replaces the NMOS transistor N4 of the ESD auxiliary circuit 404a, and therefore a similar detailed description is omitted.

[0238] ESD auxiliary circuit 404d includes a PMOS transistor P4. The PMOS transistor P4 includes a gate, drain, source, and body (not labeled).

[0239] and Figure 4A Compared to the ESD auxiliary circuit 404a, each of the gate, source, body, node Nd3, drain of NMOS transistor N1, drain of PMOS transistor P1, and gate of NMOS transistor N3 is coupled together.

[0240] and Figure 4A Compared to the ESD auxiliary circuit 404a, each of the following is coupled together: the drain of PMOS transistor P4, the first terminal of capacitor C2, node Nd2, the source of NMOS transistor N1, the body of NMOS transistor N1, the source of NMOS transistor N3, and the body of NMOS transistor N3.

[0241] use Figure 4D The description of the ESD auxiliary circuit 404d for an ESD event occurring at node Nd2 (e.g., an ESD current I1 in the positive ESD direction) is similar to that for... Figure 4A The description of an ESD event occurring at node Nd2 of the ESD auxiliary circuit 404a is omitted for brevity. In some embodiments, in response to an ESD event at node Nd2 (e.g., an ESD current I1 in the forward ESD direction), PMOS transistor P4 is turned on and configured to clamp the voltage at node Nd3 to be equal to the voltage at node Nd2 (e.g., VSS), thereby causing NMOS transistor N3 to turn on. In response to being turned on, NMOS transistor N3 couples node Nd2 to node Nd1, and NMOS transistor N3 discharges the ESD current I1 in the forward ESD direction from node Nd2 to Nd1.

[0242] In some embodiments, in response to an ESD event at node Nd2 (e.g., an ESD current I1 in the forward ESD direction), the body diode of PMOS transistor P4 is configured to provide ESD protection for integrated circuit 400D by clamping the voltage at node Nd3. In some embodiments, the body diode of NMOS transistor N3 is configured to provide ESD protection for integrated circuit 400D by delivering an ESD current I1 in the forward ESD direction from node Nd2 to node Nd1.

[0243] In some embodiments, by including an ESD auxiliary circuit 400D in the integrated circuit 400D, the integrated circuit 400D achieves at least the above-mentioned Figure 1 or Figure 4A One or more benefits discussed in the text.

[0244] At least other types of circuits, configurations, and arrangements of ESD detection circuit 402, ESD auxiliary circuit 404d, or discharge circuit 410 are within the scope of this disclosure.

[0245] Other configurations or quantities of circuits in the integrated circuit 400D are within the scope of this disclosure.

[0246] Figure 4E This is a circuit diagram of an integrated circuit 400E according to some embodiments.

[0247] Integrated circuit 400E is at least an embodiment of ESD clamping circuit 120, and therefore a similar detailed description is omitted.

[0248] Integrated circuit 400E is Figure 4A This is a variant of integrated circuit 400A, and therefore a similar detailed description is omitted. Compared to integrated circuit 400A, integrated circuit 400E has ESD auxiliary circuit 404e instead of ESD auxiliary circuit 404a of integrated circuit 400A, and therefore a similar detailed description is omitted.

[0249] The integrated circuit 400E includes a control circuit 201, an ESD detection circuit 402, an ESD auxiliary circuit 404e, and a discharge circuit 410.

[0250] ESD auxiliary circuit 404e is Figure 4A This is a variant of the ESD auxiliary circuit 404a, and therefore a similar detailed description is omitted. Compared to the ESD auxiliary circuit 404a, the ESD auxiliary circuit 404e uses transistor B4 instead of the NMOS transistor N4 of the ESD auxiliary circuit 404a, and therefore a similar detailed description is omitted. Transistor B4 is a PNP BJT.

[0251] The ESD auxiliary circuit 404e includes transistor B4. Transistor B4 includes a base, a collector, and an emitter (not labeled).

[0252] and Figure 4A Compared to the ESD auxiliary circuit 404a, each of the emitter of transistor B4, the base of transistor B4, node Nd3, the drain of NMOS transistor N1, the drain of PMOS transistor P1, and the gate of NMOS transistor N3 is coupled together.

[0253] and Figure 4A Compared to the ESD auxiliary circuit 404a, each of the following is coupled together: the collector of transistor B4, the first terminal of capacitor C2, node Nd2, the source of NMOS transistor N1, the body of NMOS transistor N1, the source of NMOS transistor N3, and the body of NMOS transistor N3.

[0254] use Figure 4A The description of the ESD auxiliary circuit 404e for an ESD event occurring at node Nd2 (e.g., an ESD current I1 in the positive ESD direction) is similar to that for... Figure 4A The description of an ESD event occurring at node Nd2 of the ESD auxiliary circuit 404a is omitted for brevity. In some embodiments, in response to an ESD event at node Nd2 (e.g., an ESD current I1 in the forward ESD direction), transistor B4 is turned on and configured to clamp the voltage at node Nd3 to be equal to the voltage at node Nd2 (e.g., VSS), thereby causing NMOS transistor N3 to turn on. In response to being turned on, NMOS transistor N3 couples node Nd2 to node Nd1, and NMOS transistor N3 discharges the ESD current I1 in the forward ESD direction from node Nd2 to Nd1.

[0255] In some embodiments, in response to an ESD event at node Nd2 (e.g., an ESD current I1 in the forward ESD direction), the body diode of transistor B4 is configured to provide ESD protection for integrated circuit 400E by clamping the voltage at node Nd3. In some embodiments, the body diode of NMOS transistor N3 is configured to provide ESD protection for integrated circuit 400E by delivering an ESD current I1 in the forward ESD direction from node Nd2 to node Nd1.

[0256] In some embodiments, by including an ESD auxiliary circuit 400E in the integrated circuit 400E, the integrated circuit 400E achieves at least the above-mentioned Figure 1 or Figure 4A One or more benefits discussed in the text.

[0257] At least other types of circuits, configurations, and arrangements of ESD detection circuit 402, ESD auxiliary circuit 404e, or discharge circuit 410 are within the scope of this disclosure.

[0258] Other configurations or quantities of circuits in integrated circuit 400E are within the scope of this disclosure.

[0259] Figure 5A This is a cross-sectional view of an integrated circuit 500A according to some embodiments.

[0260] Integrated circuit 500A is Figure 4A This is an embodiment of the NMOS transistor N4 in the ESD auxiliary circuit 404a, and therefore a similar detailed description is omitted. Integrated circuit 500A is... Figure 3D A variant of the integrated circuit 300D, and therefore a similar detailed description is omitted.

[0261] and Figure 3D Compared to the 300D integrated circuit, the drain region 512b replaces... Figure 3D The drain region 312b and the source region 514b are replaced. Figure 3D The source region 314b, and the junction regions 516b and 517b are replaced. Figure 3D The corresponding junction areas 316b and 317b are replaced by transistor 560b, and therefore a similar detailed description is omitted.

[0262] The integrated circuit 500A includes a substrate 302a, a gate structure 330, a drain region 512b, a source region 514b, an LDD region 318, a sidewall 320, junction regions 516b and 517b, STI regions 308, 309, 310 and 311, and a body diode 540a.

[0263] exist Figure 5A In this context, substrate 302a is a p-type substrate with p-type dopant.

[0264] In some embodiments, the drain region 512b, source region 514b, LDD region 318, sidewall 320, and gate structure 330 together form transistor 560b. Transistor 560b is an NMOS transistor.

[0265] Drain region 512b corresponds to Figure 4A The drain and source regions 514b of the NMOS transistor N4 correspond to Figure 4A The source and gate structure 330 of the NMOS transistor N4 corresponds to Figure 4A The gate, junction regions 516b and 517b of the NMOS transistor N4 correspond to Figure 4A The body of the NMOS transistor N4, and therefore a similar detailed description is omitted.

[0266] Drain region 512b is coupled to node Nd3. Gate structure 330, source region 514b, and junction regions 516b and 517b are coupled to a reference supply voltage (e.g., voltage VSS) via node Nd2. In some embodiments, each of gate structure 330, source region 514a, and junction regions 516a and 516b is coupled together at node Nd2 and is also coupled to a reference supply voltage (e.g., voltage VSS).

[0267] Integrated circuit 500A also includes a body diode 540a. The body diode 540a is a parasitic element formed by a PN junction between at least the junction region 516b or 517b and the drain region 512b. In some embodiments, the body diode 540a is formed by a PN junction between the source region 514b and the drain region 512b. In some embodiments, in response to an ESD event in the forward direction at node Nd2, the body diode 540a of the NMOS transistor N4 is configured to provide ESD protection for integrated circuit 500A by clamping the voltage at node Nd3, and integrated circuit 500A thereby achieves at least the above-mentioned ESD protection. Figure 1 or Figure 4A One or more benefits discussed in the text.

[0268] Figure 5B This is a cross-sectional view of an integrated circuit 500B according to some embodiments.

[0269] Integrated circuit 500B is Figure 4B An embodiment of diode D2 in the ESD auxiliary circuit 404b is described, and therefore a similar detailed description is omitted. Integrated circuit 500B is... Figure 3B A variant of the integrated circuit 300B, and therefore a similar detailed description is omitted.

[0270] The integrated circuit 500B includes a substrate 302a, an N-type region 552a, a P-type region 556a, and STI regions 308, 310, and 311.

[0271] N-type region 552a is similar to Figure 3B The N-type region 356a and the P-type region 556a are similar to Figure 3B The N-type region 352a in the text is omitted here, and therefore a similar detailed description is omitted.

[0272] N-type region 552a is an N+ active region having an N-type dopant implanted into a well (not shown) or substrate 302a. P-type region 556a is a P+ active region having a P-type dopant implanted into a well (not shown) or substrate 302a.

[0273] N-type region 552a corresponds to Figure 4B The cathode of diode D2, P-type region 556a corresponds to Figure 4B The anode of diode D2, and therefore a similar detailed description is omitted.

[0274] N-type region 552a is coupled to node Nd3 (e.g., ... Figure 2A (As shown). P-type region 556a is coupled to the supply voltage (e.g., voltage VDD) through node ND2.

[0275] Integrated circuit 500B also includes a body diode 540b. The body diode 540b is a parasitic element formed by the PN junction between the P-type region 556a and the N-type region 552a. In some embodiments, in response to an ESD event in the forward direction at node Nd2, the body diode 540b is configured to provide ESD protection for integrated circuit 500B by clamping the voltage at node Nd3, and integrated circuit 500B thereby achieves at least the above-mentioned ESD protection. Figure 1 or Figure 4A One or more benefits discussed in the text.

[0276] Figure 5C This is a cross-sectional view of an integrated circuit 500C according to some embodiments.

[0277] Integrated circuit 500C is Figure 4C An embodiment of transistor B3 in the ESD auxiliary circuit 404c is described, and therefore a similar detailed description is omitted. Integrated circuit 500C is... Figure 3E A variant of the integrated circuit 300E, and therefore a similar detailed description is omitted.

[0278] The integrated circuit 500C includes a substrate 302b, an N-type region 362b, and a P-type region 366b.

[0279] N-type region 362b corresponds to Figure 4C The emitter of transistor B3, P-type region 366b corresponds to Figure 4C The base of transistor B3, substrate 302b corresponds to Figure 4C The collector of transistor B3, and therefore a similar detailed description is omitted.

[0280] Each of the N-type region 362b and the P-type region 366b is coupled together and is also coupled to a reference supply voltage (e.g., voltage VSS) through node Nd2. Substrate 302b is coupled to node Nd3.

[0281] Integrated circuit 500C also includes a body diode 540c. The body diode 540c is a parasitic element formed by a PN junction between the P-type region 366b and the substrate 302b. In some embodiments, in response to an ESD event in the forward direction at node Nd2, the body diode 540c is configured to provide ESD protection for integrated circuit 500C by clamping the voltage at node Nd3, and integrated circuit 500C thereby achieves at least the above-ground ESD protection. Figure 1 or Figure 4A One or more benefits discussed in the text.

[0282] Figure 5D This is a cross-sectional view of an integrated circuit 500D according to some embodiments.

[0283] Integrated circuit 500D is Figure 4DThis is an embodiment of the PMOS transistor P4 in the ESD auxiliary circuit 404d, and therefore a similar detailed description is omitted. Integrated circuit 500D is... Figure 3A A variant of the integrated circuit 300A, and therefore a similar detailed description is omitted.

[0284] and Figure 3A Compared to the 300A integrated circuit, the drain region 512a replaces... Figure 3D The drain region 312a and the source region 514a are replaced. Figure 3D The source region 314a, and the junction regions 516a and 517a are replaced. Figure 3D The corresponding junction areas 316a and 317a are replaced by transistor 560a, and therefore a similar detailed description is omitted.

[0285] The integrated circuit 500D includes a substrate 302b, a gate structure 330, a drain region 512a, a source region 514a, an LDD region 318, a sidewall 320, junction regions 516a and 517a, STI regions 308, 309, 310 and 311, and a body diode 540d.

[0286] exist Figure 5D In this context, substrate 302b is an n-type substrate with N-type dopant.

[0287] In some embodiments, the drain region 512a, source region 514a, LDD region 318, sidewall 320, and gate structure 330 together form transistor 560a. Transistor 560a is a PMOS transistor.

[0288] Drain region 512a corresponds to Figure 4A The drain and source regions 514a of the PMOS transistor P4 correspond to Figure 4A The source and gate structure 330 of the PMOS transistor P4 corresponds to Figure 4A The gate, junction regions 516a and 517a of the PMOS transistor P4 correspond to Figure 4A The body of the PMOS transistor P4 is described, and therefore a similar detailed description is omitted.

[0289] Drain region 512a is coupled to a reference supply voltage (e.g., voltage VSS) through node Nd2. Gate structure 330, source region 514a, and junction regions 516a and 517a are coupled to node Nd3.

[0290] Integrated circuit 500D also includes a body diode 540d. The body diode 540d is a parasitic element formed by a PN junction between at least the drain region 512a and the junction region 516a or 517a. In some embodiments, the body diode 540d is formed by a PN junction between the drain region 512a and the source region 514a. In some embodiments, in response to an ESD event in the forward direction at node Nd2, the body diode 540d of the PMOS transistor P4 is configured to provide ESD protection for integrated circuit 500D by clamping the voltage at node Nd3, and integrated circuit 500D thereby achieves at least the above-mentioned ESD protection. Figure 1 or Figure 4A One or more benefits discussed in the text.

[0291] Figure 5E This is a cross-sectional view of an integrated circuit 500E according to some embodiments.

[0292] Integrated circuit 500E is Figure 4E An embodiment of transistor B4 in the ESD auxiliary circuit 404e is described, and therefore a similar detailed description is omitted. Integrated circuit 500E is... Figure 3C A variant of the integrated circuit 300C, and therefore a similar detailed description is omitted.

[0293] The integrated circuit 500E includes a substrate 302a, a P-type region 362a, and an N-type region 366a.

[0294] exist Figure 5E In this context, substrate 302a is a p-type substrate with p-type dopant.

[0295] P-type region 362a corresponds to Figure 4E The emitter of transistor B4, N-type region 366a corresponds to Figure 4E The base of transistor B4, substrate 302a corresponds to Figure 4E The collector of transistor B4, and therefore a similar detailed description is omitted.

[0296] Each of the P-type region 362a and the N-type region 366a is coupled together and also coupled to node Nd3. Substrate 302a is coupled to a reference supply voltage (e.g., voltage VSS) through node Nd2.

[0297] Integrated circuit 500E also includes a body diode 540e. The body diode 540e is a parasitic element formed by the PN junction between substrate 302a and N-type region 366a. In some embodiments, in response to an ESD event in the forward direction at node Nd2, the body diode 540e is configured to provide ESD protection for integrated circuit 500E by clamping the voltage at node Nd3, thereby achieving at least the above-ground ESD protection. Figure 1 or Figure 4AOne or more benefits discussed in the text.

[0298] Figure 6A This is a circuit diagram of an integrated circuit 600A according to some embodiments.

[0299] Integrated circuit 600A is at least an embodiment of ESD clamping circuit 120, and therefore a similar detailed description is omitted. In some embodiments, integrated circuit 600A is a stack of two P-type power clamping circuits.

[0300] Integrated circuit 600A includes circuits 601a and 601b arranged in a stacked configuration. In some embodiments, each of circuits 601a and 601b corresponds to integrated circuits 200A, 200B, 200C, 200D, or 200E arranged in a stacked configuration, and therefore a similar detailed description is omitted. In some embodiments, the voltage of an ESD event is greater than the withstand voltage of a single ESD clamping circuit, therefore one or more ESD clamping circuits are arranged in a stacked configuration to withstand ESD events with voltages greater than the withstand voltage of a single ESD clamping circuit but less than the total withstand voltage of the plurality of ESD clamping circuits, thereby preventing failure during the ESD event.

[0301] Circuit 601a is coupled to circuit 601b at node Nd2.

[0302] Circuit 601a includes ESD detection circuit 602a, ESD auxiliary circuit 604a and discharge circuit 610a.

[0303] Circuit 601b includes ESD detection circuit 602b, ESD auxiliary circuit 604b and discharge circuit 610b.

[0304] Each of the ESD detection circuits 601a and 601b corresponds to Figures 2A-2E Each of the ESD detection circuit 202, ESD auxiliary circuits 604a and 604b corresponds to at least Figure 2A ESD auxiliary circuit 204a, Figure 2B ESD auxiliary circuit 204b Figure 2C ESD auxiliary circuit 204c, Figure 2D ESD auxiliary circuit 204d or Figure 2E The ESD auxiliary circuit 204e, and each of the ESD discharge circuits 610a and 610b corresponds to Figures 2A-2E The ESD discharge circuit 210 is described in detail hereafter, and therefore a similar detailed description is omitted.

[0305] Circuit 601a is coupled between nodes Nd1 and Nd2.

[0306] Circuit 601b is coupled between nodes Nd2 and Nd5.

[0307] ESD detection circuit 602a is coupled between nodes Nd1 and Nd2. ESD detection circuit 602b is coupled between nodes Nd2 and Nd5. Figures 2A-2E In contrast, node ND1 has a supply voltage VDD, and node Nd5 has a reference voltage VSS.

[0308] ESD discharge circuits 610a and 610b are coupled in series across nodes Nd1 and Nd5. ESD discharge circuit 610a is coupled between nodes Nd1 and Nd2. ESD discharge circuit 610b is coupled between nodes Nd2 and Nd5.

[0309] ESD auxiliary circuit 604a is coupled between nodes Nd1 and Nd3. ESD auxiliary circuit 604b is coupled between nodes Nd2 and Nd6. Figures 6A-6B The nodes Nd6 and Nd5 in the data are similar to Figures 2A-2E The corresponding nodes Nd3 and Nd2 in the table are omitted, and therefore similar detailed descriptions are omitted. Figures 2A-2E compared to, Figure 6A and Figure 7A The voltage at the middle node Nd5 (described below) corresponds to the reference supply voltage VSS, and Figure 6A and Figure 7A The voltage at the middle node Nd2 corresponds to the intermediate voltage V1a. In some embodiments, the intermediate voltage V1a is equal to (VDD-VSS) / 2.

[0310] The capacitive coupling effect between nodes Nd2 and Nd3 is represented by the equivalent capacitor C1a. In some embodiments, by including ESD auxiliary circuits 604a and 604b in the integrated circuit 600A, the capacitive coupling effect between nodes Nd2 and Nd3 (shown by the equivalent capacitor C1a) is reduced, thereby effectively reducing the on-resistance of the ESD discharge circuits 610a and 610b. This results in the ESD discharge circuits 610a and 610b conducting faster and more strongly than other methods, leading to improved ESD performance and improved ESD stability compared to other methods.

[0311] At least other types of circuits, configurations, and arrangements of ESD detection circuits 602a and 602b, ESD auxiliary circuits 604a and 604b, or discharge circuits 610a and 610b are within the scope of this disclosure.

[0312] Other configurations or quantities of circuits in integrated circuit 600A are within the scope of this disclosure.

[0313] Figure 6B This is a circuit diagram of integrated circuit 600B according to some embodiments.

[0314] Integrated circuit 600B is at least an embodiment of ESD clamping circuit 120, and therefore a similar detailed description is omitted. In some embodiments, integrated circuit 600B is a 3-stacked P-type power clamping circuit.

[0315] Integrated circuit 600B is Figure 6A This is a variant of integrated circuit 600A, and therefore a similar detailed description is omitted. Compared with integrated circuit 600A, integrated circuit 600B also includes circuit 601c, and therefore a similar detailed description is omitted.

[0316] Circuit 601c is coupled to circuit 601b at node Nd2.

[0317] Circuit 601c includes ESD detection circuit 602c, ESD auxiliary circuit 604c and discharge circuit 610c.

[0318] ESD detection circuit 601c corresponds to Figures 2A-2E The ESD detection circuit 202 and the ESD auxiliary circuit 604c correspond at least to Figure 2A ESD auxiliary circuit 204a, Figure 2B ESD auxiliary circuit 204b Figure 2C ESD auxiliary circuit 204c, Figure 2D ESD auxiliary circuit 204d or Figure 2E The ESD auxiliary circuit 204e and the ESD discharge circuit 610c correspond to Figures 2A-2E The ESD discharge circuit 210 is described in detail hereafter, and therefore a similar detailed description is omitted.

[0319] Circuit 601c is coupled between nodes Nd5 and Nd7.

[0320] The ESD detection circuit 602c is coupled between nodes Nd5 and Nd7. Figure 6A In contrast, the voltage at node Nd7 corresponds to the reference supply voltage VSS. Figure 6B and Figure 7B The voltage at node Nd2 (described below) corresponds to the intermediate voltage V1b, and Figure 6B and Figure 7B The voltage at node Nd5 corresponds to the intermediate voltage V2b. In some embodiments, the intermediate voltage V2b is equal to (VDD-VSS) / 3. In some embodiments, the intermediate voltage V1b is equal to 2*(VDD-VSS) / 3.

[0321] ESD discharge circuits 610a, 610b, and 610c are coupled in series across nodes Nd1 and Nd7. ESD discharge circuit 610c is coupled between nodes Nd5 and Nd7.

[0322] The ESD auxiliary circuit 604c is coupled between nodes Nd5 and Nd8. Figure 6B and Figure 7B The nodes Nd5 and Nd8 in the data are similar to Figures 2A-2E The corresponding nodes Nd3 and Nd2 in the table are omitted, and therefore similar detailed descriptions are omitted.

[0323] In some embodiments, by including ESD auxiliary circuits 604a, 604b, and 604c in the integrated circuit 600B, the capacitive coupling effect between nodes Nd2 and Nd3 (shown by the equivalent capacitor C1a) is reduced, thereby effectively reducing the on-resistance of the ESD discharge circuits 610a, 610b, and 610c. This results in the ESD discharge circuits 610a, 610b, and 610c conducting faster and more strongly than other methods, leading to improved ESD performance and improved ESD stability compared to other methods.

[0324] At least other types of circuits, configurations, and arrangements of ESD detection circuits 602a, 602b, and 602c, ESD auxiliary circuits 604a, 604b, and 604c, and discharge circuits 610a, 610b, and 610c are within the scope of this disclosure.

[0325] Other configurations or quantities of circuitry in integrated circuit 600B are within the scope of this disclosure. For example, in some embodiments, integrated circuit 600B includes a number of circuits 601a, 601b, or 601c other than three (e.g., three stacked P-type power clamping circuits).

[0326] Figure 7A This is a circuit diagram of an integrated circuit 700A according to some embodiments.

[0327] Integrated circuit 700A is at least an embodiment of ESD clamping circuit 120, and therefore a similar detailed description is omitted. In some embodiments, integrated circuit 700A is a stack of two N-type power clamping circuits.

[0328] Integrated circuit 700A is Figure 6A This is a variant of the integrated circuit 600A, and therefore a similar detailed description is omitted. Compared to integrated circuit 600A, integrated circuit 700A includes... Figures 4A-4E The characteristics of integrated circuits 400A-400E rather than Figures 2A-2E The integrated circuits 200A-200E are used, and therefore similar detailed descriptions are omitted.

[0329] Integrated circuit 700A includes circuits 701a and 701b arranged in a stacked configuration. In some embodiments, each of circuits 701a and 701b corresponds to integrated circuits 400A, 400B, 400C, 400D, or 400E arranged in a stacked configuration, and therefore similar detailed descriptions are omitted.

[0330] Circuit 701a is coupled to circuit 701b at node Nd2.

[0331] Circuit 701a includes ESD detection circuit 702a, ESD auxiliary circuit 704a and discharge circuit 710a.

[0332] Circuit 701b includes ESD detection circuit 702b, ESD auxiliary circuit 704b, and discharge circuit 710b.

[0333] Each of the ESD detection circuits 701a and 701b corresponds to Figures 4A-4E Each of the ESD detection circuit 402, ESD auxiliary circuits 704a and 704b corresponds to at least Figure 4A ESD auxiliary circuit 404a, Figure 4B ESD auxiliary circuit 404b Figure 4C ESD auxiliary circuit 404c, Figure 4D ESD auxiliary circuit 404d or Figure 4E The ESD auxiliary circuit 404e, and each of the ESD discharge circuits 710a and 710b corresponds to Figures 4A-4E The ESD discharge circuit 410 is described in detail below, and therefore a similar detailed description is omitted.

[0334] Circuit 701a is coupled between nodes Nd1 and Nd2.

[0335] Circuit 701b is coupled between nodes Nd2 and Nd5.

[0336] ESD detection circuit 702a is coupled between nodes Nd1 and Nd2. ESD detection circuit 702b is coupled between nodes Nd2 and Nd5. Figures 4A-4E In contrast, node ND1 has a supply voltage VDD, and node Nd5 has a reference voltage VSS.

[0337] ESD discharge circuits 710a and 710b are coupled in series across nodes Nd1 and Nd5. ESD discharge circuit 710a is coupled between nodes Nd1 and Nd2. ESD discharge circuit 710b is coupled between nodes Nd2 and Nd5.

[0338] ESD auxiliary circuit 704a is coupled between nodes Nd2 and Nd3. ESD auxiliary circuit 704b is coupled between nodes Nd5 and Nd6.

[0339] The capacitive coupling effect between nodes Nd1 and Nd3 is represented by the equivalent capacitor C1b. In some embodiments, by including ESD auxiliary circuits 704a and 704b in the integrated circuit 700A, the capacitive coupling effect between nodes Nd1 and Nd3 (shown by the equivalent capacitor C1b) is reduced, thereby effectively reducing the on-resistance of the ESD discharge circuits 710a and 710b. This results in the ESD discharge circuits 710a and 710b conducting faster and more strongly than other methods, leading to improved ESD performance and improved ESD stability compared to other methods.

[0340] At least other types of circuits, configurations, and arrangements of ESD detection circuits 702a and 702b, ESD auxiliary circuits 704a and 704b, or discharge circuits 710a and 710b are within the scope of this disclosure.

[0341] Other configurations or quantities of circuits in the integrated circuit 700A are within the scope of this disclosure.

[0342] Figure 7B This is a circuit diagram of integrated circuit 700B according to some embodiments.

[0343] Integrated circuit 700B is at least an embodiment of ESD clamping circuit 120, and therefore a similar detailed description is omitted. In some embodiments, integrated circuit 700B is a 3-stacked N-type power clamping circuit.

[0344] Integrated circuit 700B is Figure 6B Integrated circuit 600B and Figure 7A This is a variant of integrated circuit 700A, and therefore a similar detailed description is omitted. Compared to integrated circuit 600B, integrated circuit 700B includes... Figures 4A-4E The characteristics of integrated circuits 400A-400E rather than Figures 2A-2E The integrated circuits 200A-200E are described herein, and therefore similar detailed descriptions are omitted. Compared to integrated circuit 700A, integrated circuit 700B also includes circuit 701c, and therefore similar detailed descriptions are omitted.

[0345] Circuit 701c is coupled to circuit 701b at node Nd2.

[0346] Circuit 701c includes ESD detection circuit 702c, ESD auxiliary circuit 704c and discharge circuit 710c.

[0347] ESD detection circuit 701c corresponds to Figures 4A-4E The ESD detection circuit 402 and the ESD auxiliary circuit 704c correspond at least to Figure 4A ESD auxiliary circuit 404a, Figure 4B ESD auxiliary circuit 404b Figure 4C ESD auxiliary circuit 404c, Figure 4D ESD auxiliary circuit 404d or Figure 4E The ESD auxiliary circuit 404e and the ESD discharge circuit 710c correspond to Figures 4A-4E The ESD discharge circuit 410 is described in detail below, and therefore a similar detailed description is omitted.

[0348] Circuit 701c is coupled between nodes Nd5 and Nd7.

[0349] The ESD detection circuit 702c is coupled between nodes Nd5 and Nd7. Figure 7A In contrast, the voltage at node Nd7 corresponds to the reference supply voltage VSS.

[0350] ESD discharge circuits 710a, 710b, and 710c are coupled in series across nodes Nd1 and Nd7. ESD discharge circuit 710c is coupled between nodes Nd5 and Nd7.

[0351] The ESD auxiliary circuit 704c is coupled between nodes Nd7 and Nd8. Figure 6B and Figure 7B Nodes Nd7 and Nd8 in the data are similar to Figures 4A-4E The corresponding nodes Nd2 and Nd3 are omitted, and therefore similar detailed descriptions are omitted.

[0352] In some embodiments, by including ESD auxiliary circuits 704a, 704b, and 704c in the integrated circuit 700B, the capacitive coupling effect between nodes Nd1 and Nd3 (shown by the equivalent capacitor C1b) is reduced, thereby effectively reducing the on-resistance of the ESD discharge circuits 710a, 710b, and 710c. This results in the ESD discharge circuits 710a, 710b, and 710c conducting faster and more strongly than other methods, leading to improved ESD performance and improved ESD stability compared to other methods.

[0353] At least other types of circuits, configurations, and arrangements of ESD detection circuits 702a, 702b, and 702c, ESD auxiliary circuits 704a, 704b, and 704c, and discharge circuits 710a, 710b, and 710c are within the scope of this disclosure.

[0354] Other configurations or quantities of circuitry in integrated circuit 700B are within the scope of this disclosure. For example, in some embodiments, integrated circuit 700B includes a number of circuits 701a, 701b, or 701c other than three (e.g., three stacked N-type power clamping circuits).

[0355] Figures 8A-8BThis is a top view of the corresponding integrated circuits 800A-800B according to some embodiments.

[0356] Integrated circuits 800A-800B are at least embodiments of ESD clamping circuit 120, and therefore similar detailed descriptions are omitted.

[0357] According to some embodiments, integrated circuit 800A is a top-level view of at least integrated circuits 200A, 200B, 200C, 200D, or 200E.

[0358] According to some embodiments, integrated circuit 800B is a top-level view of at least integrated circuits 400A, 400B, 400C, 400D, or 400E.

[0359] Integrated circuits 800A and 800B are manufactured using a layout design similar to that of their counterparts 800A and 800B. For the sake of simplicity, Figures 8A-8B Described as integrated circuits 800A-800B, but in some embodiments, Figures 8A-8B Corresponding to the layout design, the structural elements of integrated circuits 800A-800B also correspond to the layout pattern, as well as the structural relationships including alignment, length and width. The configuration and layers of the layout design of the corresponding integrated circuit 800A- are similar to the structural relationships, configuration and layers of the corresponding integrated circuits 800A-800B, and similar detailed descriptions are omitted for brevity.

[0360] The integrated circuit 800A includes regions 801, 802a, 802b, 804a and 810a, and conductive structures 820a, 822a, 824a, 826a, 828a, 830a and 840a.

[0361] Region 801 corresponds to Figures 2A-2E and Figures 4A-4E The control circuit 201, region 802a corresponds to the PMOS transistor P1 of the ESD detection circuit 202, region 802b corresponds to the NMOS transistor N1 of the ESD detection circuit 202, and region 804a corresponds to at least Figure 2A ESD auxiliary circuit 204a, Figure 2B ESD auxiliary circuit 204b Figure 2C ESD auxiliary circuit 204c, Figure 2D ESD auxiliary circuit 204d or Figure 2E The ESD auxiliary circuit 204e, region 810a corresponds to Figures 2A-2E The ESD discharge circuit 210 is described in detail below, and therefore a similar detailed description is omitted.

[0362] Conductive structure 822a or conductive structure 828a corresponds to at least Figure 2AESD auxiliary circuit 204a, Figure 2B ESD auxiliary circuit 204b Figure 2C ESD auxiliary circuit 204c, Figure 2D ESD auxiliary circuit 204d or Figure 2E The node Nd2 of the ESD auxiliary circuit 204e is omitted here, and therefore a similar detailed description is omitted.

[0363] Conductive structure 824a or conductive structure 826a corresponds to at least Figure 2A ESD auxiliary circuit 204a, Figure 2B ESD auxiliary circuit 204b Figure 2C ESD auxiliary circuit 204c, Figure 2D ESD auxiliary circuit 204d or Figure 2E The node Ndl of the ESD auxiliary circuit 204e is omitted here, and therefore a similar detailed description is omitted.

[0364] Conductive structure 840a corresponds to at least Figure 2A ESD auxiliary circuit 204a, Figure 2B ESD auxiliary circuit 204b Figure 2C ESD auxiliary circuit 204c, Figure 2D ESD auxiliary circuit 204d or Figure 2E The node Nd3 of the ESD auxiliary circuit 204e is omitted here, and therefore a similar detailed description is omitted.

[0365] At least conductive structures 820a, 824a, 826a, or 830a are configured to provide a supply voltage VDD. In some embodiments, at least conductive structures 820a, 824a, 826a, or 830a are power rails.

[0366] At least conductive structure 822a or 828a is configured to provide a reference supply voltage VSS. In some embodiments, at least conductive structure 822a or 828a is a reference power rail.

[0367] Each of the conductive structures 820a, 822a, 824a, 826a, 828a, 830a, and 840a extends in a first direction X and is separated from each other in a second direction Y, which is different from the first direction X. In some embodiments, each of the plurality of conductive structures 820a, 822a, 824a, 826a, 828a, 830a, and 840a is at the same level of integrated circuit 800A. In some embodiments, at least one of the conductive structures 820a, 822a, 824a, 826a, 828a, 830a, or 840a is at a different level of integrated circuit 800A from another of at least one of the conductive structures 820a, 822a, 824a, 826a, 828a, 830a, or 840a.

[0368] In some embodiments, at least one of the conductive structures 820a, 822a, 824a, 826a, 828a, 830a, and 840a comprises one or more layers of a conductive material, a metal, a metal compound, or a doped semiconductor. In some embodiments, the conductive material comprises tungsten, cobalt, ruthenium, copper, or combinations thereof. In some embodiments, the metal comprises at least Cu (copper), Co, W, Ru, Al, etc. In some embodiments, the metal compound comprises at least AlCu, W-TiN, TiSix, NiSix, TiN, TaN, etc. In some embodiments, the doped semiconductor comprises at least doped silicon, etc.

[0369] Conductive structure 824a is located between conductive structure 804a and conductive structure 822a. Conductive structures 804a and 822a are spaced apart from each other by a distance D1 in the second direction Y.

[0370] Conductive structure 826a is located between conductive structure 804a and conductive structure 828a. Conductive structures 804a and 828a are spaced apart from each other by a distance D1 in the second direction Y.

[0371] In some embodiments, conductive structure 824a is located between conductive structure 804a and conductive structure 822a, which causes conductive structure 804a and conductive structure 822a to be spaced apart from each other in the second direction Y by a distance D1 greater than in other methods, thereby resulting in a smaller coupling capacitance between conductive structure 804a and conductive structure 822a than in other methods.

[0372] In some embodiments, conductive structure 826a is located between conductive structure 804a and conductive structure 828a, which causes conductive structure 804a and conductive structure 828a to be spaced apart from each other in the second direction Y by a distance D1 greater than in other methods, thereby resulting in a smaller coupling capacitance between conductive structure 804a and conductive structure 828a than in other methods.

[0373] Other circuit configurations or quantities in the integrated circuit 800A are within the scope of this disclosure.

[0374] According to some embodiments, integrated circuit 800B is a top-level view of at least integrated circuits 400A, 400B, 400C, 400D, or 400E.

[0375] The 800B integrated circuit is Figure 8A This is a variant of the 800A integrated circuit, and therefore a similar detailed description is omitted. Compared to the 800A integrated circuit, Figure 8B Region 804b replaces region 804a. Figure 8BRegion 810b replaces region 810a, and conductive structures 820b, 822b, 824b, 826b, 828b, 830b and 840b replace the corresponding conductive structures 820a, 822a, 824a, 826a, 828a, 830a and 840a, and therefore similar detailed descriptions are omitted.

[0376] The integrated circuit 800B includes regions 801, 802a, 802b, 804b and 810b, and conductive structures 820b, 822b, 824b, 826b, 828b, 830b and 840b.

[0377] Region 804b corresponds to at least the corresponding Figures 4A-4E The ESD auxiliary circuits 404a, 404b, 404c, 404d, or 404e, with region 810b corresponding to... Figures 4A-4E The ESD discharge circuit 410 is described in detail below, and therefore a similar detailed description is omitted.

[0378] Conductive structure 822b or conductive structure 828b corresponds to the corresponding Figures 4A-4E The node Nd1 of at least the ESD auxiliary circuits 404a, 404b, 404c, 404d or 404e, and therefore a similar detailed description is omitted.

[0379] Conductive structure 824b or conductive structure 826b corresponds to the corresponding Figures 4A-4E The node Nd2 of at least the ESD auxiliary circuits 404a, 404b, 404c, 404d or 404e, and therefore a similar detailed description is omitted.

[0380] Conductive structure 840b corresponds to the corresponding Figures 4A-4E The node Nd3 of at least the ESD auxiliary circuits 404a, 404b, 404c, 404d or 404e, and therefore a similar detailed description is omitted.

[0381] At least conductive structures 820b, 824b, 826b, or 830b are configured to provide a reference supply voltage VSS. In some embodiments, at least conductive structures 820b, 824b, 826b, or 830b are reference power rails.

[0382] At least conductive structure 822b or 828b is configured to provide a supply voltage VDD. In some embodiments, at least conductive structure 822b or 828b is a power rail.

[0383] In some embodiments, each of conductive structures 820b, 822b, 824b, 826b, 828b, 830b, and 840b is on the same level of integrated circuit 800B. In some embodiments, at least one of conductive structures 820b, 822b, 824b, 826b, 828b, 830b, or 840b is on a different level of integrated circuit 800B from another of at least one of conductive structures 820b, 822b, 824b, 826b, 828b, 830b, or 840b.

[0384] Conductive structure 824b is located between conductive structure 804b and conductive structure 822b. Conductive structures 804b and 822b are spaced apart from each other by a distance D1 in the second direction Y.

[0385] Conductive structure 826b is located between conductive structure 804b and conductive structure 828b. Conductive structures 804b and 828b are spaced apart from each other by a distance D1 in the second direction Y.

[0386] In some embodiments, conductive structure 824b is located between conductive structure 804b and conductive structure 822b, which results in conductive structure 804b and conductive structure 822b being spaced apart from each other in the second direction Y by a distance D1 greater than in other methods, thereby resulting in a smaller coupling capacitance between conductive structure 804b and conductive structure 822b than in other methods.

[0387] In some embodiments, conductive structure 826b is located between conductive structure 804b and conductive structure 828b, which causes conductive structure 804b and conductive structure 828b to be spaced apart from each other in the second direction Y by a distance D1 greater than in other methods, thereby resulting in a smaller coupling capacitance between conductive structure 804b and conductive structure 828b than in other methods.

[0388] Other circuit configurations or quantities in the 800B integrated circuit are within the scope of this disclosure.

[0389] Figure 9 This is a flowchart of a method 900 for operating an ESD circuit according to some embodiments.

[0390] In some embodiments, the ESD circuit of method 900 includes at least integrated circuits 100, 200A-200E, 300A-300E, 400A-400E, 500A-500E, 600A-600B, 700A-700B, and 800A-800B. Figure 1 , Figures 2A-2E , Figures 3A-3E , Figures 4A-4E , Figures 5A-5E , Figures 6A-6B , Figures 7A-7B and Figures 8A-8BIt should be understood that it is possible to... Figure 9 Additional operations are performed before, during, and / or after the method 900 described herein, and some other processes are described only briefly. It should be understood that method 900 utilizes one or more features of integrated circuits 100, 200A-200E, 300A-300E, 400A-400E, 500A-500E, 600A-600B, 700A-700B, and 800A-800B. Further operational sequences of method 900 with respect to at least integrated circuits 100, 200A-200E, 300A-300E, 400A-400E, 500A-500E, 600A-600B, 700A-700B, or 800A-800B are within the scope of this disclosure.

[0391] At operation 902 of method 900, a first ESD voltage is received at a first node. In some embodiments, the first node of method 900 includes node Nd2. In some embodiments, the first ESD voltage is greater than the reference supply voltage VSS of node Nd2. In some embodiments, the first ESD voltage corresponds to a first ESD event.

[0392] At operation 904, the detection circuit detects the first ESD event at the first node, thereby causing the detection circuit to charge the first gate of the first transistor of the discharge circuit.

[0393] In some embodiments, the detection circuit of method 900 includes at least detection circuit 202 or 402. In some embodiments, the discharge circuit of method 900 includes at least discharge circuit 210 or 410. In some embodiments, the first transistor of the discharge circuit of method 900 includes at least PMOS transistor P2 or NMOS transistor N3.

[0394] In some embodiments, the discharge circuit is coupled between the first node and the second node. In some embodiments, the detection circuit is coupled to the first node, the second node, and the third node.

[0395] In some embodiments, the second node of method 900 includes node Nd1. In some embodiments, the third node of method 900 includes node Nd3 or Nd4.

[0396] At operation 906, the ESD auxiliary circuit is turned on in response to a first ESD event at the first node, thereby causing the ESD auxiliary circuit to clamp the first voltage of the first gate of the first transistor of the discharge circuit to the second voltage of the second node or the third voltage of the first node.

[0397] In some embodiments, the ESD auxiliary circuit of method 900 includes at least ESD auxiliary circuits 204a, 204b, 204c, 204d, 204e, 404a, 404b, 404c, 404d, or 404e. In some embodiments, the ESD auxiliary circuit of method 900 includes at least the ESD auxiliary circuit of method 1000, including at least ESD auxiliary circuits 300A, 300B, 300C, 300D, 300E, 500A, 500B, 500C, 500D, or 500E.

[0398] In some embodiments, the first voltage of method 900 is the voltage of node Nd3. In some embodiments, the second voltage of the second node of method 900 is the voltage of node Nd1 (e.g., VDD). In some embodiments, the third voltage of the first node of method 900 is the voltage of node Nd2 (e.g., VSS).

[0399] In some embodiments, the ESD auxiliary circuit is coupled at least between the first node and the third node.

[0400] In some embodiments, the ESD auxiliary circuit includes a body diode. In some embodiments, the body diode of method 900 includes at least body diodes 340a, 340b, 340c, 340d, 340e, 540a, 540b, 540c, 540d, or 540e.

[0401] At operation 908, the first transistor of the discharge circuit is turned on at least in response to a first ESD event at the first node, and the ESD auxiliary circuit clamps the first voltage of the first gate at a second voltage or a third voltage. In some embodiments, operation 908 further includes turning on the first transistor of the discharge circuit in response to the first gate of the first transistor being charged.

[0402] At operation 910, in response to the first transistor of the discharge circuit being turned on, the first node is coupled to the second node.

[0403] At operation 912, the first ESD current of the first ESD event at the first node is discharged through the first transistor in the first ESD direction from the first node to the second node. In some embodiments, operation 912 further includes discharging the first ESD current of the first ESD event at the first node in the first ESD direction from the first node to the second node through at least the channel of the first transistor or the body diode of the first transistor.

[0404] In some embodiments, the first ESD current corresponds to the forward ESD direction. In some embodiments, the first ESD current includes an ESD current I1 in the forward ESD direction from node Nd2 to node Nd1.

[0405] In some embodiments, one or more operations of method 900 are not performed. In some embodiments, one or more operations of method 900 are repeated. In some embodiments, method 900 is repeated.

[0406] In some embodiments, methods 900 and 1000 (discussed below) thereby achieve at least in Figure 1 , Figures 2A-2E , Figures 3A-3E , Figures 4A-4E , Figures 5A-5E , Figures 6A-6B , Figures 7A-7B or Figures 8A-8B One or more benefits discussed in the text.

[0407] Figure 10 This is a flowchart of a method 1000 for manufacturing an integrated circuit according to some embodiments.

[0408] In some embodiments, method 1000 can be used to fabricate or manufacture at least integrated circuits 100, 200A-200E, 300A-300E, 400A-400E, 500A-500E, 600A-600B, 700A-700B, and 800A-800B. Figure 1 , Figures 2A-2E , Figures 3A-3E , Figures 4A-4E , Figures 5A-5E , Figures 6A-6B , Figures 7A-7B and Figures 8A-8B ).

[0409] It should be understood that it is possible Figure 10 Additional operations are performed before, during, and / or after the method 1000 described herein, and some other processes are described only briefly. It should be understood that method 1000 utilizes one or more features of integrated circuits 100, 200A-200E, 300A-300E, 400A-400E, 500A-500E, 600A-600B, 700A-700B, and 800A-800B.

[0410] Method 1000 relates to other operational sequences of at least integrated circuits 100, 200A-200E, 300A-300E, 400A-400E, 500A-500E, 600A-600B, 700A-700B, or 800A-800B, within the scope of this disclosure.

[0411] Method 1000 is applicable at least to integrated circuits 500A, 500B, or 500C. Method 1000 is described with respect to integrated circuits 500A, 500B, or 500C. However, Method 1000 is also applicable to integrated circuits 100-100B, 200A-200B, 300A-300B, or 400A-400C. Other operational sequences of Method 1000 with respect to integrated circuits 500A, 500B, or 500C are within the scope of this disclosure.

[0412] In operation 1002 of method 1000, an ESD auxiliary circuit is fabricated on a wafer. In some embodiments, the ESD auxiliary circuit of method 1000 includes at least ESD auxiliary circuits 204a, 204b, 204c, 204d, 204e, 404a, 404b, 404c, 404d, or 404e. In some embodiments, the ESD auxiliary circuit of method 1000 includes at least ESD auxiliary circuits 300A, 300B, 300C, 300D, 300E, 500A, 500B, 500C, 500D, or 500E. In some embodiments, the wafer of method 1000 includes a substrate 302a or 302b.

[0413] In some embodiments, operation 1002 includes manufacturing at least one integrated circuit 300A, 300B, 300C, 300D, 300E, 500A, 500B, 500C, 500D, or 500E.

[0414] In some embodiments, operation 1002 includes fabricating at least an integrated circuit 300A or 500D, wherein a first well is fabricated in a substrate, a drain region and a source region of a transistor are fabricated in the first well, and a first gate structure is fabricated. In these embodiments, the substrate is a substrate 302a comprising p-type dopant, the first well (not shown) comprises n-type dopant, the drain region is a drain region 312a or 512a comprising p-type dopant, the source region is a source region 314a or 514a comprising p-type dopant, and the first gate structure is a gate 330. In some embodiments, the p-type dopant comprises boron, aluminum, or other suitable p-type dopant.

[0415] In some embodiments, the first well includes an n-type dopant. In some embodiments, the n-type dopant includes phosphorus, arsenic, or other suitable n-type dopant. In some embodiments, the first well includes an epitaxial layer grown over a substrate 302a or 302b. In some embodiments, the epitaxial layer is doped by adding a dopant during the epitaxial process. In some embodiments, the epitaxial layer is doped by ion implantation after its formation. In some embodiments, the first well is formed by doping the substrate 302a or 302b. In some embodiments, doping is performed by ion implantation. In some embodiments, the first well has a range from 1 × 10⁻⁶. 12atoms / cm 3 Up to 1×10 14 atoms / cm 3 The dopant concentration. Other dopant concentration values ​​or ranges for the first well are within the scope of this disclosure.

[0416] In some embodiments, the drain region of transistor 360a or 560a is formed in the first well. In these embodiments, the drain region extends in the second direction Y and has a p-type dopant. In some embodiments, the source region of transistor 360a or 560a is formed in the first well. In these embodiments, the source region extends in the second direction Y and has a p-type dopant.

[0417] In some embodiments, operation 1002 includes fabricating at least an integrated circuit 300D or 500A, wherein drain and source regions of a transistor are fabricated in a substrate, and a first gate structure is fabricated. In these embodiments, the substrate is a substrate 302a comprising p-type dopant, the drain region is a drain region 312b or 512b comprising n-type dopant, the source region is a source region 314b or 514b comprising n-type dopant, and the first gate structure is a gate 330.

[0418] In some embodiments, forming source / drain components of at least transistor 360b or 560b in a substrate includes removing a portion of the substrate to form a groove at the edge of each spacer 320a, 320b, and then performing a fill process by filling the groove in the substrate. In some embodiments, the groove is etched (e.g., wet or dry etching) after removing the pad oxide layer or sacrificial oxide layer. In some embodiments, an etching process is performed to remove the top surface portion of the active region adjacent to the isolation region (e.g., STI regions 308, 309, 310, or 311). In some embodiments, the fill process is performed by an epitaxial or epitaxial (epi) process. In some embodiments, the groove is filled using a growth process concurrent with the etching process, wherein the growth rate of the growth process is greater than the etching rate of the etching process. In some embodiments, a combination of a growth process and an etching process is used to fill the groove. For example, a layer of material is grown in the groove, and then the grown material is etched to remove a portion of the material. A subsequent growth process is then performed on the etched material until the desired thickness of the material in the groove is reached. In some embodiments, the growth process continues until the top surface of the material is above the top surface of the substrate. In some embodiments, the growth process continues until the top surface of the material is coplanar with the top surface of the substrate.

[0419] In some embodiments, portions of the substrate are removed by isotropic or anisotropic etching processes. The etching process selectively etches the substrate without etching the gate structure 230 and the spacer 220. In some embodiments, the etching process is performed using reactive ion etching (RIE), wet etching, or other suitable techniques. In some embodiments, semiconductor material is deposited in a trench to form source / drain components. In some embodiments, an epitaxial process is performed to deposit semiconductor material in the trench. In some embodiments, the epitaxial process includes selective epitaxial growth (SEG), CVD, molecular beam epitaxy (MBE), other suitable processes, and / or combinations thereof. The epitaxial process uses gaseous and / or liquid precursors that interact with the composition of the substrate 302a or 302b. In some embodiments, the source / drain components comprise epitaxially grown silicon (epi Si), silicon carbide, or silicon-germanium. In some cases, the source / drain components of the IC device associated with the gate structure 330 are either in-situ doped or undoped during the epitaxial process. When the source / drain components are undoped during the epitaxial process, they are in some cases doped during subsequent processes. These subsequent doping processes are achieved through ion implantation, plasma immersion ion implantation, gas and / or solid source diffusion, other suitable processes, and / or combinations thereof. In some embodiments, the source / drain components are also exposed to an annealing process after formation and / or after subsequent doping processes.

[0420] In some embodiments, manufacturing at least the gate region of operations 1002, 1004, or 1006 (described below) includes manufacturing a gate structure 330. In some embodiments, manufacturing at least the gate region of operations 1002, 1004, or 1006 (described below) includes performing one or more deposition processes to form one or more dielectric material layers. In some embodiments, the deposition processes include chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or other processes suitable for depositing one or more material layers. In some embodiments, manufacturing the gate region includes performing one or more deposition processes to form one or more conductive material layers. In some embodiments, manufacturing the gate region includes forming a gate electrode or a dummy gate electrode. In some embodiments, manufacturing the gate region includes depositing or growing at least one dielectric layer, such as a gate dielectric. In some embodiments, the gate region is formed using doped or undoped polysilicon (or polysilicon). In some embodiments, the gate region includes metals (such as Al, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi), other suitable conductive materials, or combinations thereof. Other materials for the gate region are also within the scope of this invention.

[0421] In some embodiments, operation 1002 includes fabricating integrated circuit 300B, wherein a P-type region 352a and an N-type region 356a are formed in a substrate 302a, and the formation of the P-type region 352a and the N-type region 356a is similar to the formation of the source / drain regions of at least integrated circuit 300A, 300D, 500A or 500D, and therefore such detailed descriptions are omitted.

[0422] In some embodiments, operation 1002 includes fabricating integrated circuit 500B, wherein an N-type region 552a and a P-type region 556a are formed in a substrate 302a, and the formation of the N-type region 552a and the P-type region 556a is similar to the formation of the source / drain regions of at least integrated circuit 300A, 300D, 500A or 500D, and therefore a similar detailed description is omitted.

[0423] In some embodiments, operation 1002 includes fabricating an integrated circuit 300C or 500E, wherein an N-type region 366a is formed in a substrate 302a, a P-type region 362a is formed in the N-type region 366a, and the formation of the P-type region 362a and the N-type region 366a is similar to the formation of the source / drain regions of at least the integrated circuit 300A, 300D, 500A or 500D, and therefore such detailed descriptions are omitted.

[0424] In some embodiments, operation 1002 includes fabricating an integrated circuit 300E or 500C, wherein a P-type region 366b is formed in a substrate 302b, an N-type region 362b is formed in the P-type region 366b, and the formation of the N-type region 362b and the P-type region 366b is similar to the formation of the source / drain regions of at least the integrated circuit 300A, 300D, 500A or 500D, and therefore such detailed descriptions are omitted.

[0425] In some embodiments, the regions of the source / drain, junction region, and p-type region containing P-type dopant have a range from 1x10. 12 atoms / cm 3 Up to 1x10 14 atoms / cm 3 The dopant concentration. Other dopant concentration values ​​or ranges for p-type dopant are within the scope of this invention. In some embodiments, the regions of the source / drain, junction region, and N-type region containing n-type dopant have a range from 1 × 10⁻⁶. 12 atoms / cm 3 Up to 1×10 14 atoms / cm 3 The dopant concentration. Other dopant concentration values ​​or ranges for n-type dopants are within the scope of this invention.

[0426] In some embodiments, at least operations 1002, 1004, or 1006 further include fabricating a signal connector region on the front side of the wafer. In some embodiments, the signal connector region of method 1000 includes at least connector regions 316a, 316b, 317a, 317b, 516a, 516b, 517a, or 517b.

[0427] In some embodiments, at least the junction regions 316a, 316b, 317a, 317b, 516a, 516b, 517a, or 517b are heavily doped p-regions. In some embodiments, at least the junction regions 316a, 316b, 317a, 317b, 516a, 516b, 517a, or 517b are heavily doped n-regions.

[0428] In some embodiments, at least junction regions 316a, 316b, 317a, 317b, 516a, 516b, 517a, or 517b are formed by ion implantation. The power range of ion implantation is from about 1500 keV to about 8000 keV. Other power values ​​or ranges for ion implantation are within the scope of this disclosure.

[0429] In some embodiments, the junction regions 316a, 316b, 317a, 317b, 516a, 516b, 517a, or 517b are epitaxially grown. In some embodiments, the junction regions 316a, 316b, 317a, 317b, 516a, 516b, 517a, or 517b comprise an epitaxial layer grown over a substrate 302a or 302b. In some embodiments, the epitaxial layer is doped by adding a dopant during the epitaxial process. In some embodiments, the epitaxial layer is doped by ion implantation after its formation. In some embodiments, the junction regions 316a, 316b, 317a, 317b, 516a, 516b, 517a, or 517b are formed over a doped substrate 302a or 302b. In some embodiments, doping is performed by ion implantation. In some embodiments, connector areas 316a, 316b, 317a, 317b, 516a, 516b, 517a, or 517b have a range from 1 × 10 12 atoms / cm 3 Up to 1×10 14 atoms / cm 3 The dopant concentration. Other values ​​or ranges of dopant concentration for junction regions 316a, 316b, 317a, 317b, 516a, 516b, 517a, or 517b are within the scope of this disclosure.

[0430] In operation 1004 of method 1000, a discharge circuit is fabricated on a wafer. In some embodiments, the discharge circuit of method 1000 includes at least discharge circuit 210 or 410. In some embodiments, the discharge circuit of method 1000 includes at least NMOS transistor N3 or PMOS transistor P2.

[0431] In some embodiments, operation 1004 includes fabricating a second well in a substrate, fabricating a second source region in the second well, fabricating a second drain region in the second well, and fabricating a second gate structure. In some embodiments, operation 1004 includes fabricating a second source region in a substrate, fabricating a second drain region in a substrate, and fabricating a second gate structure.

[0432] In some embodiments, at least the second source / drain region or second gate structure of operation 1004 is formed in a manner similar to the formation of the first source / drain region or first gate structure of operation 1002 (as described above), and similar detailed descriptions are omitted.

[0433] In operation 1006 of method 1000, a detection circuit is fabricated on a wafer. In some embodiments, the detection circuit of method 1000 includes at least detection circuit 202 or 402. In some embodiments, the detection circuit of method 1000 includes at least capacitor C1 or C2, resistor R1 or R2, and NMOS transistor N1 or PMOS transistor P1.

[0434] In some embodiments, operation 1006 includes fabricating a third well in a substrate, fabricating a third source region in the third well, fabricating a third drain region in the third well, and fabricating a third gate structure. In some embodiments, operation 1006 includes fabricating a third source region in a substrate, fabricating a third drain region in a substrate, and fabricating a third gate structure.

[0435] In some embodiments, at least the third source / drain region or third gate structure of operation 1006 is formed in a manner similar to the formation of the first source / drain region or first gate structure of operation 1002 (as described above), and similar detailed descriptions are omitted.

[0436] In some embodiments, the capacitor C1 or C2 in method 1000 is a transistor coupling capacitor, and the manufacture of the transistor coupling capacitor is similar to the manufacture of an NMOS transistor N1 or a PMOS transistor P1, except that the drain, source, and body are coupled together, and such detailed descriptions are omitted. In some embodiments, operation 1006 is repeated to form an NMOS transistor N1, a PMOS transistor P1, and at least a capacitor C1 or C2.

[0437] In operation 1008 of method 1000, a conductive structure assembly is fabricated on the front side of a wafer. In some embodiments, operation 1008 includes depositing the conductive structure assembly on the front side of the wafer. In some embodiments, the conductive structure assembly of method 1000 includes at least a conductive structure 390. In some embodiments, the conductive structure assembly of method 1000 includes components configured to connect... Figures 3A-3B , Figure 3D , Figures 5A-5B or Figure 5D The conductive structure (not shown) of one or more of the gate, drain, source, body, node Nd1, node Nd2 or node Nd3 is similar to conductive structure 390, and therefore a similar detailed description is omitted.

[0438] In some embodiments, the conductive structure group of forming method 1000 uses a combination of photolithography and material removal processes to form openings in an insulating layer (not shown) above a substrate. In some embodiments, the photolithography process includes patterning a photoresist, such as a positive or negative photoresist. In some embodiments, the photolithography process includes forming a hard mask, an anti-reflective structure, or other suitable photolithographic structure. In some embodiments, the material removal process includes a wet etching process, a dry etching process, a RIE process, laser drilling, or other suitable etching process. The openings are then filled with a conductive material, such as copper, aluminum, titanium, nickel, tungsten, or other suitable conductive materials. In some embodiments, CVD, PVD, sputtering, ALD, or other suitable formation processes are used to fill the openings.

[0439] In some embodiments, one or more operations of method 1000 are not performed. In some embodiments, one or more operations of method 1000 are repeated. In some embodiments, method 1000 is repeated.

[0440] At least corresponding Figure 1 , Figures 2A-2E , Figures 3A-3E , Figures 4A-4E , Figures 5A-5E , Figures 6A-6B , Figures 7A-7B and Figures 8A-8B Other diode types or quantities, transistor types, or other quantities of diodes in the integrated circuits 100, 200A-200E, 300A-300E, 400A-400E, 500A-500E, 600A-600B, 700A-700B, and 800A-800B are within the scope of this disclosure.

[0441] In addition, for illustrative purposes, Figures 2A-2E and Figures 4A-4EThe various NMOS or PMOS transistors shown have specific dopant types (e.g., N-type or P-type). The embodiments of this disclosure are not limited to specific transistor types, and... Figures 2A-2E and Figures 4A-4E One or more of the PMOS or NMOS transistors shown can be replaced by corresponding transistors of different transistor / dopant types. Similarly, the low or high logic values ​​of the various signals used in the above description are also for illustrative purposes. The embodiments of this disclosure are not limited to specific logic values ​​when signals are activated and / or deactivated. Different logic values ​​are chosen within the range of various embodiments. Figures 2A-2E and Figures 4A-4E Different numbers of NMOS / PMOS transistors are selected within the range of various embodiments.

[0442] One aspect of this specification relates to an electrostatic discharge (ESD) circuit. In some embodiments, the ESD circuit includes an ESD detection circuit, a clamping circuit, and an ESD auxiliary circuit. In some embodiments, the ESD detection circuit is coupled between a first node and a second node. In some embodiments, the first node has a first voltage, and the second node has a second voltage. In some embodiments, the clamping circuit includes a first transistor of a first type. In some embodiments, the first transistor has a first gate, a first drain, a first source, and a first body terminal. In some embodiments, the first gate is coupled to the ESD detection circuit at least through a third node. In some embodiments, the first drain is coupled to the second node, and the first source and the first body terminal are coupled together at the first node. In some embodiments, the ESD auxiliary circuit is coupled between the first node and the third node and is configured to clamp a third voltage of the third node at the first voltage during an ESD event at the first node or the second node.

[0443] In some embodiments, the ESD auxiliary circuit includes: a diode coupled between a first node and a third node, the diode having an anode coupled to the third node, a first gate and an ESD detection circuit, and a cathode coupled to the first node, a first source and a first body terminal.

[0444] In some embodiments, the ESD auxiliary circuit includes: a second transistor of a first type having a second gate, a second drain, a second source, and a second body terminal, the second drain being coupled to a third node, a first gate, and an ESD detection circuit, and each of the first node, the first source, the first body terminal, the second gate, the second source, and the second body terminal being coupled together.

[0445] In some embodiments, the second transistor includes: a first active region located in a substrate, the first active region corresponding to a second drain of the second transistor; a second active region located in the substrate, the second active region corresponding to a second source of the second transistor; and a third active region located in the substrate, the third active region corresponding to a second body terminal of the second transistor, wherein the second active region and the third active region are coupled together, and the first active region and the third active region are configured as a body diode of the second transistor.

[0446] In some embodiments, the ESD auxiliary circuit includes: a first bipolar junction transistor having a first base, a first collector, and a first emitter, the first collector being coupled to a third node, a first gate, and an ESD detection circuit, and each of the first node, the first base, the first emitter, the first source, and the first body terminal being coupled together.

[0447] In some embodiments, the ESD auxiliary circuit includes: a second transistor of a second type different from the first type, having a second gate, a second drain, a second source, and a second body terminal, the second drain being coupled to a first node, a first source, and a first body terminal, and each of the second gate, the second source, the second body terminal, the third node, the first gate, and the ESD detection circuit being coupled together.

[0448] In some embodiments, the second transistor includes: a first active region located in a substrate, the first active region corresponding to a second drain of the second transistor; a second active region located in the substrate, the second active region corresponding to a second source of the second transistor; and a third active region located in the substrate, the third active region corresponding to a second body terminal of the second transistor, wherein the second active region and the third active region are coupled together, and the first active region and the third active region are configured as a body diode of the second transistor.

[0449] In some embodiments, the ESD auxiliary circuit includes: a first bipolar junction transistor having a first base, a first collector and a first emitter, the first collector being coupled to a first node, a first source and a first body terminal, and each of the first emitter, the first base, the third node, the first gate and the ESD detection circuit being coupled together.

[0450] In some embodiments, the ESD auxiliary circuit includes: a diode coupled between a first node and a third node, the diode having a cathode coupled to the third node, a first gate and an ESD detection circuit, and an anode coupled to the first node, a first source and a first body terminal.

[0451] In some embodiments, the ESD circuit further includes: a first conductor extending in a first direction and configured to provide a first voltage; a second conductor extending in the first direction and configured to provide a second voltage; a third conductor extending in the first direction, and the third conductor including a third node; a fourth conductor extending in the first direction and configured to provide the first voltage; and a fifth conductor extending in the first direction and configured to provide the second voltage; wherein the first node is a portion of the first conductor or the fourth conductor; the second node is a portion of the second conductor or the fifth conductor; each of the first conductor, the second conductor, the third conductor, the fourth conductor, and the fifth conductor is separated from each other in a second direction different from the first direction; the third conductor is located between the first conductor and the fourth conductor; the first conductor is located between the third conductor and the second conductor; and the fourth conductor is located between the third conductor and the fifth conductor.

[0452] Another aspect of this specification relates to ESD circuitry. ESD circuitry includes a first diode, a second diode, internal circuitry, and ESD clamping circuitry. In some embodiments, the first diode is coupled between a first node and an input / output (I / O) pad. In some embodiments, the second diode is coupled between the I / O pad and the second node. In some embodiments, internal circuitry is coupled to the first diode, the second diode, and the I / O pad. In some embodiments, the ESD clamping circuitry is located between the first node and the second node. In some embodiments, the ESD clamping circuitry includes a first ESD detection circuit, a first clamping circuit, and a first ESD auxiliary circuit. In some embodiments, the first ESD detection circuitry is coupled between the first node and the second node. In some embodiments, the first node has a first voltage and the second node has a second voltage. In some embodiments, the first clamping circuitry includes a first transistor of a first type. In some embodiments, the first transistor has a first gate, a first drain, a first source, and a first body terminal. In some embodiments, the first gate is coupled to at least the first ESD detection circuitry via a third node, the first drain is coupled to the second node, and the first source and the first body terminal are coupled together at the first node. In some embodiments, a first ESD auxiliary circuit is coupled between a first node and a third node and is configured to clamp a third voltage of the third node at a first voltage during an ESD event at the second node.

[0453] In some embodiments, the ESD clamping circuit further includes: a second ESD detection circuit coupled between a second node and a fourth node, the fourth node having a fourth voltage; a second clamping circuit including a second transistor of a first type, the second transistor having a second gate, a second drain, a second source, and a second body terminal, the second gate being coupled to the second ESD detection circuit at least through a fifth node, the second drain being coupled to the fourth node, and the second source and the second body terminal being coupled together at the second node; and a second ESD auxiliary circuit coupled between the second node and the fifth node and configured to clamp the fifth voltage of the fifth node at the second voltage during an ESD event at the fourth node.

[0454] In some embodiments, the ESD clamping circuit further includes: a third ESD detection circuit coupled between the fourth node and the sixth node, the sixth node having a sixth voltage; a third clamping circuit including a third transistor of the first type, the third transistor having a third gate, a third drain, a third source, and a third body terminal, the third gate being coupled to the third ESD detection circuit at least through the seventh node, the third drain being coupled to the sixth node, and the third source and the third body terminal being coupled together at the fourth node; and a third ESD auxiliary circuit coupled between the fourth node and the seventh node, and configured to clamp the seventh voltage of the seventh node to the fourth voltage during an ESD event at the sixth node.

[0455] In some embodiments, the first ESD detection circuit includes: a resistor coupled between a second node and an input node; a capacitor coupled between an input node and a first node; and an inverter coupled to the first node, the second node, the third node, the input node, the first gate, and the first ESD auxiliary circuit.

[0456] In some embodiments, the inverter includes: a third transistor of a first type, the third transistor having a third gate, a third drain, a third source, and a third body terminal; and a fourth transistor of a second type, different from the first type, the fourth transistor having a fourth gate, a fourth drain, a fourth source, and a fourth body terminal, wherein each of the third gate, the fourth gate, and the input node is coupled together; each of the third source, the third body terminal, the first node, the first source, and the first body terminal is coupled together; each of the fourth source, the fourth body terminal, the second node, and the first drain is coupled together; and each of the third drain, the fourth drain, the first gate, and the third node is coupled together.

[0457] In some embodiments, the first ESD auxiliary circuit includes: a second transistor of a first type having a second gate, a second drain, a second source, and a second body terminal, the second drain being coupled to a third node, a first gate, and a first ESD detection circuit, and each of the first node, the first source, the first body terminal, the second gate, the second source, and the second body terminal being coupled together.

[0458] In some embodiments, the second transistor includes: a first active region located in a substrate, the first active region corresponding to a second drain of the second transistor; a second active region located in the substrate, the second active region corresponding to a second source of the second transistor; and a third active region located in the substrate, the third active region corresponding to a second body terminal of the second transistor, wherein the second active region and the third active region are coupled together, and the first active region and the third active region are configured as a body diode of the second transistor.

[0459] In some embodiments, the first ESD auxiliary circuit includes: a first bipolar junction transistor having a first base, a first collector and a first emitter, the first collector being coupled to a third node, a first gate and a first ESD detection circuit, and each of the first node, the first base, the first emitter, the first source and the first body terminal being coupled together.

[0460] In some embodiments, the first ESD auxiliary circuit includes: a diode coupled between a first node and a third node, the diode having an anode coupled to the third node, a first gate and a first ESD detection circuit, and a cathode coupled to the first node, a first source and a first body terminal.

[0461] Another aspect of this specification relates to a method of operating an ESD circuit. The method includes receiving a first ESD voltage at a first node, the first ESD voltage being greater than a reference supply voltage of a reference power source, the first ESD voltage corresponding to a first ESD event. In some embodiments, the method further includes turning on an ESD auxiliary circuit in response to the first ESD event at the first node, such that the ESD auxiliary circuit clamps a first voltage at the gate of a first transistor of a discharge circuit at a second voltage at a second node, the discharge circuit being coupled between the first node and the second node, and the ESD auxiliary circuit being coupled at least between the first node and a third node, and the ESD auxiliary circuit including a body diode. In some embodiments, the method further includes turning on the discharge circuit in response to the first ESD event, and the ESD auxiliary circuit clamping the first voltage at the first gate at the second voltage. In some embodiments, the method further includes discharging a first ESD current of the first ESD event through the first transistor in a first ESD direction from the first node to the second node.

[0462] Many embodiments have been described. However, it should be understood that various modifications can be made without departing from the spirit and scope of this disclosure. For example, various transistors shown as having a specific dopant type (e.g., N-type or P-type metal-oxide-semiconductor (NMOS or PMOS)) are for illustrative purposes. Embodiments of this disclosure are not limited to a specific type. Different dopant types are selected for a particular transistor within the scope of various embodiments. The low or high logic values ​​of the various signals used in the above description are also for illustrative purposes. When a signal is activated and / or deactivated, the various embodiments are not limited to specific logic values. Different logic values ​​are selected within the scope of various embodiments. In various embodiments, the transistor is used as a switch. Switching circuits used instead of transistors are within the scope of various embodiments. In various embodiments, the source of the transistor can be configured as the drain, and the drain can be configured as the source. Therefore, the terms source and drain are used interchangeably. Various signals are generated by corresponding circuits, but for simplicity, the circuits are not shown.

[0463] The accompanying figures illustrate capacitor circuits using discrete capacitors. Equivalent circuits can be used. For example, capacitor devices, circuits, or networks (e.g., combinations of capacitors, capacitor elements, devices, circuits, etc.) can be used instead of discrete capacitors. The above description includes exemplary steps, but these steps are not necessarily performed in the order shown. Steps may be appropriately added, substituted, rearranged, and / or removed according to the spirit and scope of the disclosed embodiments.

[0464] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made within the invention without departing from its spirit and scope.

Claims

1. An electrostatic discharge circuit, comprising: A first electrostatic discharge detection circuit is coupled between a first node and a second node, wherein the first node has a first voltage and the second node has a second voltage. The first clamping circuit includes a first transistor of a first type, the first transistor having a first gate, a first drain, a first source and a first body terminal, the first gate being coupled to the first electrostatic discharge detection circuit through a third node, the first drain being coupled to a second node, and the first source and the first body terminal being coupled together at the first node. A first electrostatic discharge auxiliary circuit is coupled between the first node and the third node and is configured to clamp the third voltage of the third node at the first voltage during an electrostatic discharge event of the first node or the second node. A second electrostatic discharge detection circuit is coupled between the second node and the fourth node, the fourth node having a fourth voltage; The second clamping circuit includes a second transistor of the first type, the second transistor having a second gate, a second drain, a second source, and a second body terminal, the second gate being coupled to the second electrostatic discharge detection circuit at least through a fifth node, the second drain being coupled to the fourth node, and the second source and the second body terminal being coupled together at the second node. and A second electrostatic discharge auxiliary circuit is coupled between the second node and the fifth node and is configured to clamp the fifth voltage of the fifth node to the second voltage during an electrostatic discharge event at the fourth node.

2. The electrostatic discharge circuit according to claim 1, wherein, The first electrostatic discharge auxiliary circuit includes: A diode coupled between the first node and the third node, the diode having an anode coupled to the third node, the first gate and the first electrostatic discharge detection circuit, and a cathode coupled to the first node, the first source and the first body terminal.

3. The electrostatic discharge circuit according to claim 1, wherein, The first electrostatic discharge auxiliary circuit includes: The third transistor of the first type has a third gate, a third drain, a third source, and a third body terminal, the third drain being coupled to the third node, the first gate, and the first electrostatic discharge detection circuit, and each of the first node, the first source, the first body terminal, the third gate, the third source, and the third body terminal being coupled together.

4. The electrostatic discharge circuit according to claim 3, wherein, The third transistor includes: A first active region is located in the substrate, and the first active region corresponds to the third drain of the third transistor; A second active region is located in the substrate, and the second active region corresponds to the third source of the third transistor; and A third active region is located in the substrate, and the third active region corresponds to the third body terminal of the third transistor. The second active region and the third active region are coupled together, and the first active region and the third active region are configured as the body diodes of the third transistor.

5. The electrostatic discharge circuit according to claim 1, wherein, The first electrostatic discharge auxiliary circuit includes: A first bipolar junction transistor has a first base, a first collector, and a first emitter, the first collector being coupled to the third node, the first gate, and the first electrostatic discharge detection circuit, and each of the first node, the first base, the first emitter, the first source, and the first body terminal being coupled together.

6. The electrostatic discharge circuit according to claim 1, wherein, The first electrostatic discharge auxiliary circuit includes: Unlike the first type, the second type of third transistor has a third gate, a third drain, a third source, and a third body terminal, the third drain being coupled to the first node, the first source, and the first body terminal, and each of the third gate, the third source, the third body terminal, the third node, the first gate, and the first electrostatic discharge detection circuit is coupled together.

7. The electrostatic discharge circuit according to claim 6, wherein, The third transistor includes: A first active region is located in the substrate, and the first active region corresponds to the third drain of the third transistor; A second active region is located in the substrate, and the second active region corresponds to the third source of the third transistor; and A third active region is located in the substrate, and the third active region corresponds to the third body terminal of the third transistor. The second active region and the third active region are coupled together, and the first active region and the third active region are configured as the body diodes of the third transistor.

8. The electrostatic discharge circuit according to claim 1, wherein, The first electrostatic discharge auxiliary circuit includes: A first bipolar junction transistor has a first base, a first collector, and a first emitter, the first collector being coupled to the first node, the first source, and the first body terminal, and each of the first emitter, the first base, the third node, the first gate, and the first electrostatic discharge detection circuit being coupled together.

9. The electrostatic discharge circuit according to claim 1, wherein, The first electrostatic discharge auxiliary circuit includes: A diode coupled between the first node and the third node, the diode having a cathode coupled to the third node, the first gate and the first electrostatic discharge detection circuit, and an anode coupled to the first node, the first source and the first body terminal.

10. The electrostatic discharge circuit according to claim 1, further comprising: A first conductor extends in a first direction and is configured to provide the first voltage; A second wire extends in the first direction and is configured to provide the second voltage; A third conductor extends in the first direction, and the third conductor includes the third node; A fourth wire extends in the first direction and is configured to provide the first voltage; A fifth conductor extends in the first direction and is configured to provide the second voltage; Wherein, the first node is a portion of the first wire or the fourth wire; The second node is a portion of the second conductor or the fifth conductor; Each of the first wire, the second wire, the third wire, the fourth wire, and the fifth wire is separated from each other in a second direction different from the first direction; The third conductor is located between the first conductor and the fourth conductor; The first conductor is located between the third conductor and the second conductor; and The fourth conductor is located between the third conductor and the fifth conductor.

11. An electrostatic discharge circuit, comprising: The first diode is coupled between the first node and the input / output pads; A second diode is coupled between the input / output pads and the second node; Internal circuitry, coupled to the first diode, the second diode, and the input / output pads; as well as Electrostatic discharge clamping circuit, the electrostatic discharge clamping circuit comprising: A first electrostatic discharge detection circuit is coupled between a first node and a second node, wherein the first node has a first voltage and the second node has a second voltage. The first clamping circuit includes a first transistor of a first type, the first transistor having a first gate, a first drain, a first source and a first body terminal, the first gate being coupled to the first electrostatic discharge detection circuit through a third node, the first drain being coupled to a second node, and the first source and the first body terminal being coupled together at the first node. A first electrostatic discharge auxiliary circuit is coupled between the first node and the third node and is configured to clamp the third voltage of the third node at the first voltage during an electrostatic discharge event at the second node. A second electrostatic discharge detection circuit is coupled between the second node and the fourth node, the fourth node having a fourth voltage; The second clamping circuit includes a second transistor of the first type, the second transistor having a second gate, a second drain, a second source, and a second body terminal. The second gate is coupled to the second electrostatic discharge detection circuit via a fifth node, the second drain is coupled to the fourth node, and the second source and the second body terminal are coupled together at the second node. A second electrostatic discharge auxiliary circuit is coupled between the second node and the fifth node and is configured to clamp the fifth voltage of the fifth node at the second voltage during an electrostatic discharge event at the fourth node.

12. The electrostatic discharge circuit according to claim 11, wherein, The internal circuitry includes logic gate units.

13. The electrostatic discharge circuit according to claim 11, wherein, The electrostatic discharge clamping circuit also includes: A third electrostatic discharge detection circuit is coupled between the fourth node and the sixth node, the sixth node having a sixth voltage; The third clamping circuit includes a third transistor of the first type, the third transistor having a third gate, a third drain, a third source, and a third body terminal, the third gate being coupled to the third electrostatic discharge detection circuit via a seventh node, the third drain being coupled to the sixth node, and the third source and the third body terminal being coupled together at the fourth node; and A third electrostatic discharge auxiliary circuit is coupled between the fourth node and the seventh node and is configured to clamp the seventh voltage of the seventh node at the fourth voltage during an electrostatic discharge event at the sixth node.

14. The electrostatic discharge circuit according to claim 11, wherein, The first electrostatic discharge detection circuit includes: A resistor is coupled between the second node and the input node; A capacitor, coupled between the input node and the first node; and An inverter is coupled to the first node, the second node, the third node, the input node, the first gate, and the first electrostatic discharge auxiliary circuit.

15. The electrostatic discharge circuit according to claim 14, wherein, The inverter includes: A third transistor of the first type, the third transistor having a third gate, a third drain, a third source, and a third body terminal; and Unlike the first type of second type of fourth transistor, the fourth transistor has a fourth gate, a fourth drain, a fourth source, and a fourth body terminal. Each of the third gate, the fourth gate, and the input node is coupled together; Each of the third source electrode, the third body terminal, the first node, the first source electrode, and the first body terminal is coupled together; Each of the fourth source, the fourth body terminal, the second node, and the first drain is coupled together; and Each of the third drain, the fourth drain, the first gate, and the third node is coupled together.

16. The electrostatic discharge circuit according to claim 11, wherein, The first electrostatic discharge auxiliary circuit includes: The third transistor of the first type has a third gate, a third drain, a third source, and a third body terminal, the third drain being coupled to the third node, the first gate, and the first electrostatic discharge detection circuit, and each of the first node, the first source, the first body terminal, the third gate, the third source, and the third body terminal being coupled together.

17. The electrostatic discharge circuit according to claim 16, wherein, The third transistor includes: A first active region is located in the substrate, and the first active region corresponds to the third drain of the third transistor; A second active region is located in the substrate, and the second active region corresponds to the third source of the third transistor; and A third active region is located in the substrate, and the third active region corresponds to the third body terminal of the third transistor. The second active region and the third active region are coupled together, and the first active region and the third active region are configured as the body diodes of the third transistor.

18. The electrostatic discharge circuit according to claim 11, wherein, The first electrostatic discharge auxiliary circuit includes: A first bipolar junction transistor has a first base, a first collector, and a first emitter, the first collector being coupled to the third node, the first gate, and the first electrostatic discharge detection circuit, and each of the first node, the first base, the first emitter, the first source, and the first body terminal being coupled together.

19. The electrostatic discharge circuit according to claim 11, wherein, The first electrostatic discharge auxiliary circuit includes: A diode coupled between the first node and the third node, the diode having an anode coupled to the third node, the first gate and the first electrostatic discharge detection circuit, and a cathode coupled to the first node, the first source and the first body terminal.

20. A method of operating an electrostatic discharge circuit, the method comprising: A first electrostatic discharge voltage is received at the first node, the first electrostatic discharge voltage being greater than the reference supply voltage of the reference power source, and the first electrostatic discharge voltage corresponding to a first electrostatic discharge event. In response to the first electrostatic discharge event at the first node, a first electrostatic discharge auxiliary circuit is turned on, such that the first electrostatic discharge auxiliary circuit clamps the first voltage of the first gate of the first transistor of the first discharge circuit at the second voltage of the second node. The first discharge circuit is coupled between the first node and the second node, and the first electrostatic discharge auxiliary circuit is coupled at least between the first node and the third node. The first gate of the first transistor is coupled to the third node, and the first electrostatic discharge auxiliary circuit includes a first body diode. In response to the first electrostatic discharge event, the first discharge circuit is turned on, and the first electrostatic discharge auxiliary circuit clamps the first voltage of the first gate at the second voltage; The first electrostatic discharge current of the first electrostatic discharge event is discharged through the first transistor in a first electrostatic discharge direction from the first node to the second node; The second electrostatic discharge auxiliary circuit is turned on in response to the first electrostatic discharge current of the first electrostatic discharge event at the second node, such that the second electrostatic discharge auxiliary circuit clamps the third voltage of the second gate of the second transistor of the second discharge circuit to the fourth voltage of the fourth node, the second discharge circuit is coupled between the second node and the fourth node, the second electrostatic discharge auxiliary circuit is coupled at least between the fourth node and the fifth node, the second gate of the second transistor is coupled to the fifth node, and the second electrostatic discharge auxiliary circuit includes a second body diode; The second discharge circuit is turned on in response to the first electrostatic discharge current at the second node, and the second electrostatic discharge auxiliary circuit clamps the third voltage of the second gate to the fourth voltage. as well as The first electrostatic discharge current of the first electrostatic discharge event is discharged from the second node to the fourth node along the first electrostatic discharge direction via the second transistor.

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