GOA circuit and display panel

Abstract

The present invention provides a GOA circuit and a display panel. The output end of the first GOA unit of each level of the GOA module realizes the pull-up of the input end of the first GOA unit of the lower level GOA module and the input ends of multiple second GOA units, so that the multiple second GOA units of the lower level GOA module are uniformly turned on and sequentially output multiple scanning drive signals. At the same time, the first GOA unit of each level of the GOA module also realizes the pull-down of the pull-down end of the first GOA unit of the upper level GOA module, so that the multiple second GOA units of the upper level GOA module are uniformly turned off. Therefore, the first GOA unit of each level of the GOA module realizes the uploading and downloading of signals, thereby reducing the number of thin film transistors used, simplifying the structure of the GOA circuit, and being more conducive to realizing the narrow frame design of the display panel.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a GOA circuit and a display panel. Background Art

[0002] The GOA circuit can reduce the border of the display panel. The common GOA circuit includes multiple cascaded GOA units. The structure diagram and timing diagram of each level of GOA unit are as follows: Figure 1 and Figure 2 As shown, the working principle is: ST (n-4) and G (n-4) are both high potential, so that T110 is turned on, Q (n) is charged, and T210 and T220 are turned on. At this time, the periodic square wave of CK is synchronously output to ST (n) and G (n), where G (n) is the gate output signal (scan drive signal) input to the scan line inside the panel to turn on the TFT of each row of pixels. Since ST (n) has no load, it can be used as a good level transfer signal. Subsequently, when G (n + 4) is high potential, it turns on T410 and T310 as a pull-down signal, pulls Q (n) and G (n) down, turns off T210 and T220, and the inverter INV outputs a high level, turns on T420, T710 and T320, and maintains Q (n), ST (n) and G (n) at a low level.

[0003] Although the above-mentioned GOA circuit can already play a role in reducing the border of the display panel, since a large number of TFTs are still used, some repeated components of each level of GOA units can be streamlined and merged to achieve the purpose of reducing the number of TFTs per level, thereby further reducing the border of the display panel. Summary of the invention

[0004] In order to solve the above problems, an embodiment of the present invention provides a GOA circuit, including a multi-stage cascaded GOA module, each stage of the GOA module includes: a first GOA unit, a pull-up unit, a pull-down unit and a plurality of second GOA units, the first GOA unit includes an input end, a pull-down end and an output end, the second GOA unit includes an input end and an output end, wherein,

[0005] The input end of the first GOA unit of the n-th level GOA module is connected to the output end of the first GOA unit of the n-1-th level GOA module, so that the output end of the first GOA unit of the n-1-th level GOA module is used to pull up the input ends of the multiple second GOA units of the n-th level GOA module through the input end of the pull-up unit of the n-th level GOA module, thereby making the output ends of the multiple second GOA units of the n-th level GOA module output multiple scan drive signals in sequence;

[0006] The output end of the first GOA unit of the n-th level GOA module is connected to the input end of the first GOA unit of the n+1-th level GOA module and the pull-down end of the first GOA unit of the n-1-th level GOA module;

[0007] The pull-down end of the first GOA unit of the n-th level GOA module is connected to the output end of the first GOA unit of the n+1-th level GOA module, so that the output end of the first GOA unit of the n+1-th level GOA module is used to pull down the input end and output end of multiple second GOA units of the n-th level GOA module through the pull-down unit of the n-th level GOA module.

[0008] In some embodiments, the first GOA unit further includes a first clock signal terminal, and the first GOA units of the multi-stage cascaded GOA modules sequentially output signals according to a first clock signal inputted from the first clock signal terminal.

[0009] In some embodiments, the second GOA unit further includes a second clock signal terminal, and the plurality of second GOA units of each level of the GOA module sequentially output a plurality of scan drive signals according to a second clock signal inputted from the second clock signal terminal.

[0010] In some embodiments, the first GOA unit of the n-th stage GOA module includes a thirteenth transistor, a twenty-second transistor, a thirty-first transistor, and a forty-third transistor, wherein:

[0011] The gate and source of the thirteenth transistor are both connected to the input end of the first GOA unit of the n-th level GOA module, and the drain of the thirteenth transistor is connected to the input end of the first GOA unit of the n-th level GOA module;

[0012] A gate of the 22nd transistor is connected to the first pull-up node, a source of the 22nd transistor is connected to the first clock signal terminal, and a drain of the 22nd transistor is connected to the output terminal of the first GOA unit of the nth stage GOA module;

[0013] The gate of the thirty-first transistor and the gate of the forty-third transistor are connected to the pull-down end of the first GOA unit of the n-th level GOA module, the source of the thirty-first transistor and the source of the forty-third transistor are connected to a constant low voltage potential, the drain of the thirty-first transistor is connected to the output end of the first GOA unit of the n-th level GOA module, and the drain of the forty-third transistor is connected to the first pull-up node.

[0014] In some embodiments, any second GOA unit of the n-th stage GOA module includes a twenty-first transistor, a thirty-second transistor, a forty-second transistor, and an inverter, wherein:

[0015] The gate of the 21st transistor is connected to the pull-up end of the second GOA unit of the n-th level GOA module, the drain of the 42nd transistor and the input end of the inverter, the source of the 21st transistor is connected to the second clock signal end, and the drain of the 21st transistor is connected to the output end of any second GOA unit of the n-th level GOA module;

[0016] The gate of the thirty-second transistor and the gate of the forty-second transistor are connected to the output end of the inverter, the source of the thirty-second transistor and the source of the forty-second transistor are connected to a constant low voltage potential, the drain of the thirty-second transistor is connected to the output end of any second GOA unit of the n-th level GOA module, and the drain of the forty-second transistor is connected to the pull-up end of the second GOA unit of the n-th level GOA module.

[0017] In some embodiments, the inverter includes a fifty-first transistor, a fifty-second transistor, a fifty-third transistor, and a fifty-fourth transistor, wherein:

[0018] The gate and source of the fifty-first transistor are connected to the low-frequency control signal, and the drain of the fifty-first transistor, the drain of the fifty-second transistor and the gate of the fifty-third transistor are connected;

[0019] The gate of the fifty-second transistor and the gate of the fifty-fourth transistor are connected to the pull-up terminal CQ(n) of the second GOA unit, and the source of the fifty-second transistor and the source of the fifty-fourth transistor are connected to a constant voltage low potential;

[0020] The source of the fifty-third transistor is connected to the low-frequency control signal, and the drain of the fifty-third transistor and the drain of the fifty-fourth transistor are connected and connected to the output end of the inverter.

[0021] In some embodiments, the pull-up unit of the n-th level GOA module includes an eleventh transistor, the gate and drain of the eleventh transistor are connected to the first pull-up node, and the drain of the eleventh transistor is connected to the pull-up ends of multiple second GOA units of the n-th level GOA module.

[0022] In some embodiments, the pull-down unit of the n-th level GOA module includes a forty-first transistor, the gate of the forty-first transistor is connected to the pull-down end of the first GOA unit of the n-th level GOA module, the source of the forty-first transistor is connected to a constant voltage low potential, and the drain of the forty-first transistor is connected to the pull-up ends of multiple second GOA units of the n-th level GOA module.

[0023] In some embodiments, the first clock signal terminal uses 8 clock cycle signals, and every two consecutive clock cycle signals are separated by half a clock cycle.

[0024] On the other hand, an embodiment of the present invention further provides a display panel, comprising the GOA circuit as described above.

[0025] In the GOA circuit and display panel provided by the embodiments of the present invention, the output end of the first GOA unit of each level of the GOA module realizes the pull-up of the input end of the first GOA unit of the lower-level GOA module and the input ends of multiple second GOA units, so that the multiple second GOA units of the lower-level GOA module are uniformly opened and output multiple scan drive signals in sequence. At the same time, the first GOA unit of each level of the GOA module also realizes the pull-down of the pull-down end of the first GOA unit of the upper-level GOA module, so that the multiple second GOA units of the upper-level GOA module are uniformly closed. Therefore, the first GOA unit of each level of the GOA module realizes the uploading and downloading of signals, thereby reducing the number of thin-film transistors used, simplifying the structure of the GOA circuit, and being more conducive to realizing the narrow frame design of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The technical solutions and other beneficial effects of the present invention will be made apparent by describing in detail the specific embodiments of the present invention in conjunction with the accompanying drawings.

[0027] Figure 1 It is a structural schematic diagram of a common GOA circuit in the prior art;

[0028] Figure 2 It is a timing diagram of a common GOA circuit in the prior art;

[0029] Figure 3 A schematic diagram of the structure of a GOA circuit provided in an embodiment of the present invention;

[0030] Figure 4 A schematic structural diagram of a first GOA unit of a GOA circuit provided in an embodiment of the present invention;

[0031] Figure 5 A schematic diagram of the structure of a second GOA unit of a GOA circuit provided in an embodiment of the present invention;

[0032] Figure 6 A schematic diagram of the structure of an 8-stage second GOA unit with an 8CK cycle of a GOA circuit provided in an embodiment of the present invention;

[0033] Figure 7 A timing diagram of a first GOA unit of a GOA circuit provided in an embodiment of the present invention;

[0034] Figure 8 A timing diagram of a second GOA unit of a GOA circuit provided in an embodiment of the present invention;

[0035] Fig. 9 A schematic diagram of reducing the duty cycle of a second clock signal of a GOA circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0037] like Figure 3 As shown, an embodiment of the present invention provides a GOA circuit, including a multi-stage cascaded GOA module, each stage of the GOA module includes: a first GOA unit (sGOA), a pull-up unit 10, a pull-down unit 20 and a plurality of second GOA units (pGOA), the first GOA unit (sGOA) includes an input terminal (Start), a pull-down terminal (pull down) and an output terminal sG (n), the second GOA unit (pGOA) includes an input CQ (n) and an output terminal G (n), wherein,

[0038] The input terminal (Start) of the first GOA unit of the n-th level GOA module is connected to the output terminal sG (n-1) of the first GOA unit of the n-1-th level GOA module, so that the output terminal sG (n-1) of the first GOA unit of the n-1-th level GOA module is used to pull up the input terminals CQ (n) of the multiple second GOA units of the n-th level GOA module through the input terminal (Start) of the pull-up unit 10 of the n-th level GOA module, thereby making the output terminals G (n) of the multiple second GOA units of the n-th level GOA module output multiple scan driving signals in sequence;

[0039] The output terminal sG(n) of the first GOA unit of the n-th level GOA module is connected to the input terminal (Start) of the first GOA unit of the n+1-th level GOA module and the pull-down terminal (pull down) of the first GOA unit of the n-1-th level GOA module;

[0040] The pull-down end (pull down) of the first GOA unit of the n-th level GOA module is connected to the output end sG(n-1) of the first GOA unit of the n+1-th level GOA module, so that the output end sG(n+1) of the first GOA unit of the n+1-th level GOA module is used to pull down the input end CQ(n) and output end G(n) of multiple second GOA units of the n-th level GOA module through the pull-down unit 20 of the n-th level GOA module.

[0041] In the GOA circuit provided by the embodiment of the present invention, the output end of the first GOA unit of each level of the GOA module realizes the pull-up of the input end of the first GOA unit of the lower-level GOA module and the input ends of multiple second GOA units, so that the multiple second GOA units of the lower-level GOA module are uniformly opened and output multiple scan drive signals in sequence. At the same time, the first GOA unit of each level of the GOA module also realizes the pull-down of the pull-down end of the first GOA unit of the upper-level GOA module, so that the multiple GOA units of the upper-level GOA module are uniformly closed, thereby realizing the uploading and downloading of signals with one first GOA unit.

[0042] That is to say, in the GOA circuit provided by the embodiment of the present invention, the first GOA unit of each level of GOA module is cascaded, and the first GOA unit itself does not output a scan signal, but only outputs a pull-down signal to the upper-level GOA module and a pull-up signal to the lower-level GOA module. In this way, the pull-down unit 20 of the upper-level GOA module turns off the multiple scan drive signals outputted in sequence by the multiple second GOA units of the upper-level GOA module, and the pull-up unit 10 of the lower-level GOA module turns on the multiple scan drive signals outputted by the multiple GOA units of the lower-level GOA module. As a result, each level of the GOA module outputs multiple scan drive signals in sequence through the common first GOA unit, pull-up unit and pull-down unit, and multiple second GOA units output multiple scan drive signals in sequence, thereby reducing the number of thin-film transistors used, simplifying the structure of the GOA circuit, and being more conducive to realizing the narrow frame design of the display panel.

[0043] It should be noted that the input end (start) of the pull-up unit 10 of the first-stage GOA module is connected to the initial pull-up signal (sSTV).

[0044] Combination Figure 4 and Figure 7 As shown, the first GOA unit (sGOA) further includes a first clock signal terminal (sCK / sCKX), and the first GOA unit (sGOA) of the multi-stage cascaded GOA module sequentially outputs a signal sG(n) according to the first clock signal input by the first clock signal terminal (sCK / sCKX). That is, the first GOA unit of the continuous GOA module can set two clock signals sCK and sCKX with the same period and width, the width of the high potential is 1H, and the total period is 8H, so the duty cycle is 12.5%.

[0045] like Figure 5 As shown, the second GOA unit (pGOA) also includes a second clock signal terminal (CK / CKX), and multiple second GOA (pGOA) units of each level of GOA module sequentially output multiple scan drive signals according to the second clock signal input by the second clock signal terminal (CK / CKX).

[0046] Combination Figure 3 and Figure 4 As shown, the first GOA unit (sGOA) of the n-th level GOA module includes a thirteenth transistor S13, a twenty-second transistor S22, a thirty-first transistor S31 and a forty-third transistor S43, wherein:

[0047] The gate and source of the thirteenth transistor S13 are both connected to the input terminal (Start) of the first GOA unit of the nth stage GOA module, and the drain of the thirteenth transistor S13 is connected to the first pull-up node sQ(n);

[0048] The gate of the 22nd transistor S22 is connected to the first pull-up node sQ(n), the source of the 22nd transistor S22 is connected to the first clock signal terminal (sCK / sCKX), and the drain of the 22nd transistor S22 is connected to the output terminal sG(n) of the first GOA unit of the nth stage GOA module;

[0049] The gate of the thirty-first transistor S31 and the gate of the forty-third transistor S43 are connected to the pull-down end (pull down) of the first GOA unit of the n-th level GOA module, the source of the thirty-first transistor S31 and the source of the forty-third transistor S43 are connected to the constant low voltage potential VSS, the drain of the thirty-first transistor S31 is connected to the output end sG(n) of the first GOA unit of the n-th level GOA module, and the drain of the forty-first transistor is connected to the first pull-up node.

[0050] Specifically, at the rising edge of the sSTV signal, sQ(1) is raised by sSTV, and due to the unidirectional conduction function of the thirty-first transistor S13, when sSTV drops, sQ(1) remains in a high potential state. sQ(1) is in a high potential state, and the gate of the twenty-second transistor S22 is turned on. At this time, sG(1) is synchronized with the sCK signal.

[0051] Depend on Figure 3 As shown, the sG(1) signal will serve as the start signal of sGX(1). After sG(1) is synchronized to a high level of sCK, sQ(1) maintains a high level after the rising edge of sG(1). At this time, sGX(1) synchronizes the signal of sCKX, and the signals of sGX(1) and sCKX remain consistent. When sGX(1) is synchronized to the high level signal of sCKX, sGX(1) is transmitted back to the gates of S31 and S43 of sGOA(1). At this time, sQ(1) is pulled down, and sG(1) loses synchronization with sCK. The level transmission relationship between the first GOA unit (sGOA) of the subsequent GOA module, such as the level transmission relationship between sGOA(2) and sGOAX(1), is similar to this and will not be repeated here.

[0052] Combination Figure 3 , Figure 5 and Figure 6 As shown, any second GOA unit (pGOA) of the nth level GOA module ( Figure 6 8 cascaded pGOAs are used as an example) including a twenty-first transistor T21, a thirty-second transistor T32, a forty-second transistor T42 and an inverter 30, wherein:

[0053] The gate of the 21st transistor T21 is connected to the pull-up terminal CQ(n) of the second GOA unit of the n-th level GOA module, the drain of the 42nd transistor T42 and the input terminal of the inverter 30, the source of the 21st transistor T21 is connected to the second clock signal terminal (CK / CKX), and the drain of the 21st transistor T21 is connected to the output terminal G(n) of any second GOA unit of the n-th level GOA module;

[0054] The gate of the thirty-second transistor T32 and the gate of the forty-second transistor T42 are connected to the output end of the inverter 30, the source of the thirty-second transistor T32 and the source of the forty-second transistor T42 are connected to the constant low potential VSS, the drain of the thirty-second transistor T32 is connected to the output end G(n) of any second GOA unit of the n-th level GOA module, and the drain of the forty-second transistor T42 is connected to the pull-up end CQ(n) of the second GOA unit of the n-th level GOA module.

[0055] Specifically, sGOA can independently generate sequentially delayed single H timing control signals such as sG(1), sGX(1), sG(2), and sGX(2). Figure 3In the connection relationship shown, the high potential signal of sG (1) activates the high potential signal of CQ (1), and the pulse of sG (2) restores the signal of CQ (1) to a low potential. During the high potential time of CQ (1), G (1)-G (4) synchronize the signals of CK (1) to CK (4) respectively, and then are uniformly closed by the CQ (1) signal to synchronize with CK. In terms of timing, the high potentials of sG (1) and sG (2) always occur one H before the rising delay of CK, so the high potential of CQ (1) just crosses the high potential period of CK1~CK4, so PGOA (1)-PGOA (4) can just synchronize to a complete CK high potential square wave waveform. Similarly, for other PGOAs, their synchronous opening and closing processes follow the same timing logic. For example, the synchronization period corresponding to sCK (1) and sCK (2) is the time between the two rising delays of the two square wave signals. During this period, XQ (1) is a high-voltage signal. Therefore, PGOA (5) to PGOA (8) can synchronize the waveforms of CKX (1) to CKX (4) during this period, thereby outputting Gate waveforms such as G (5) to G (8).

[0056] Further, the inverter 30 includes a fifty-first transistor T51, a fifty-second transistor T52, a fifty-third transistor T53 and a fifty-fourth transistor T54, wherein:

[0057] The gate and source of the fifty-first transistor T51 are connected to the low-frequency control signal LC, and the drain of the fifty-first transistor T51, the drain of the fifty-second transistor T51 and the gate of the fifty-third transistor T53 are connected;

[0058] The gate of the fifty-second transistor T52 and the gate of the fifty-fourth transistor T54 are connected to the pull-up terminal CQ(n) of the second GOA unit, and the source of the fifty-second transistor T52 and the source of the fifty-fourth transistor T54 are connected to a constant voltage low potential;

[0059] The source of the fifty-third transistor T53 is connected to the low-frequency control signal, and the drain of the fifty-third transistor T53 and the drain of the fifty-fourth transistor T54 are connected and connected to the output end of the inverter 30 .

[0060] In some embodiments, the pull-up unit 10 of the n-th level GOA module includes an eleventh transistor T11, the gate and drain of the eleventh transistor T11 are connected to the input end (Start) of the first GOA unit of the n-th level GOA module, and the drain of the thirteenth transistor T11 is connected to the pull-up end CQ (n) of multiple second GOA units of the n-th level GOA module.

[0061] In some embodiments, the pull-down unit 20 of the n-th level GOA module includes a forty-first transistor T41, a gate of the forty-first transistor T41 is connected to the pull-down end (pull down) of the first GOA unit of the n-th level GOA module, a source of the forty-first transistor T41 is connected to a constant low voltage potential VSS, and a drain of the forty-first transistor T41 is connected to the pull-up end CQ(n) of multiple second GOA units of the n-th level GOA module.

[0062] It should be noted that compared with Figure 1 In the structure of the common GOA circuit shown in FIG. 1 , in the GOA circuit of the embodiment of the present invention, the second GOA unit (pGOA) and the eleventh transistor T11 and the forty-first transistor T41 of each stage of the GOA module are omitted as a whole. Figure 1 T310 in the design is mainly based on the fact that the pull-down of the output signal G(n) of the second GOA unit is driven by the falling delay of CK. T31 does not really pull down the G(n) signal, but is only used to make G(n) and VSS conductive for a period of time after G(n) is pulled down. Therefore, it is omitted here, and only the pull-down of the inverter is maintained to further reduce the number of thin-film transistors used in the GOA module, thereby simplifying the structure of the GOA circuit.

[0063] In some embodiments, the first clock signal terminal (sCK / sCKX) uses an 8-clock cycle signal, and every two consecutive clock cycle signals are separated by half a clock cycle.

[0064] It should be noted that the above embodiment is only described by taking 8CK as an example. For example, for the driving mode of 2N CK, the period of sCK and sCKX is 2N*H, and its duty cycle is 1 / 2N, and its phase still differs by N*H time. In addition, the number of PGOAs sharing a CQ or CQX is N, and the high potential time in the period of CK and XCK and the time of the entire period are N*H and 2N*H respectively. It needs to be ensured that Figure 8 As shown, the square wave pulses of sG and sGX always lead the corresponding rise of CK and XCK by one H time.

[0065] Furthermore, the above is a logic timing with CK and XCK as 1 / 2 duty cycle. It should be pointed out that the premise of the above pGOA normal output G (n) is that within one H after the 42nd transistor T42 receives the pull-down signal rising delay, the 42nd transistor T42 must complete the pull-down of the CQ and CQX signals. Otherwise, the CQ and CQX signals that have not been fully pulled down will cause the 21st transistor T21 to synchronize the CK signal of the next cycle, causing output abnormality. Considering that in actual situations, CQ and CQX drop very slowly due to load reasons, and may not be able to complete the signal pull-down within one H, the high potential duty cycle of CK and XCK can be appropriately reduced, that is, the high potential time can be reduced to extend the time allowed for T41 to perform pull-down. Fig. 9 As shown, at this time, CK and XCK no longer produce STV signals, so the duty cycle can be reduced on both the rising and falling sides of CK and XCK, that is, Fig. 9 All three ways of reducing the duty cycle shown are possible.

[0066] Based on the above embodiments, an embodiment of the present invention further provides a display panel, including the GOA circuit as described above. The display panel has the same structure and beneficial effects as the GOA circuit. Since the above embodiments have described the GOA circuit in detail, it will not be repeated here.

[0067] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0068] The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present invention. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A GOA circuit, characterized in that: A multi-stage cascaded GOA module is provided, wherein each stage of the GOA module comprises: a first GOA unit, a pull-up unit, a pull-down unit and a plurality of second GOA units, wherein the first GOA unit comprises an input terminal, a pull-down terminal and an output terminal, and the second GOA unit comprises an input terminal and an output terminal, wherein: The input end of the first GOA unit of the n-th level GOA module is connected to the output end of the first GOA unit of the n-1-th level GOA module, so that the output end of the first GOA unit of the n-1-th level GOA module is used to pull up the input ends of the multiple second GOA units of the n-th level GOA module through the input end of the pull-up unit of the n-th level GOA module, thereby making the output ends of the multiple second GOA units of the n-th level GOA module output multiple scan drive signals in sequence; The output end of the first GOA unit of the n-th level GOA module is connected to the input end of the first GOA unit of the n+1-th level GOA module and the pull-down end of the first GOA unit of the n-1-th level GOA module; The pull-down end of the first GOA unit of the n-th level GOA module is connected to the output end of the first GOA unit of the n+1-th level GOA module, so that the output end of the first GOA unit of the n+1-th level GOA module is used to pull down the input end and output end of multiple second GOA units of the n-th level GOA module through the pull-down unit of the n-th level GOA module.

2. The GOA circuit according to claim 1, characterized in that: The first GOA unit also includes a first clock signal terminal, and the first GOA units of the multi-stage cascaded GOA modules sequentially output signals according to the first clock signal input by the first clock signal terminal.

3. The GOA circuit according to claim 1, wherein: The second GOA unit also includes a second clock signal terminal, and the multiple second GOA units of each level of the GOA module sequentially output multiple scan drive signals according to the second clock signal input by the second clock signal terminal.

4. The GOA circuit according to claim 2, characterized in that: The first GOA unit of the n-th level GOA module includes a thirteenth transistor, a twenty-second transistor, a thirty-first transistor and a forty-third transistor, wherein: The gate and source of the thirteenth transistor are both connected to the input end of the first GOA unit of the nth-stage GOA module, and the drain of the thirteenth transistor is connected to the first pull-up node; A gate of the 22nd transistor is connected to the first pull-up node, a source of the 22nd transistor is connected to the first clock signal terminal, and a drain of the 22nd transistor is connected to the output terminal of the first GOA unit of the nth stage GOA module; The gate of the thirty-first transistor and the gate of the forty-third transistor are connected to the pull-down end of the first GOA unit of the n-th level GOA module, the source of the thirty-first transistor and the source of the forty-third transistor are connected to a constant low voltage potential, the drain of the thirty-first transistor is connected to the output end of the first GOA unit of the n-th level GOA module, and the drain of the forty-third transistor is connected to the first pull-up node.

5. The GOA circuit according to claim 3, characterized in that: Any second GOA unit of the n-th level GOA module includes a twenty-first transistor, a thirty-second transistor, a forty-second transistor and an inverter, wherein: The gate of the 21st transistor is connected to the pull-up end of the second GOA unit of the n-th level GOA module, the drain of the 42nd transistor and the input end of the inverter, the source of the 21st transistor is connected to the second clock signal end, and the drain of the 21st transistor is connected to the output end of any second GOA unit of the n-th level GOA module; The gate of the thirty-second transistor and the gate of the forty-second transistor are connected to the output end of the inverter, the source of the thirty-second transistor and the source of the forty-second transistor are connected to a constant low voltage potential, the drain of the thirty-second transistor is connected to the output end of any second GOA unit of the n-th level GOA module, and the drain of the forty-second transistor is connected to the pull-up end of the second GOA unit of the n-th level GOA module.

6. The GOA circuit according to claim 5, characterized in that: The inverter includes a fifty-first transistor, a fifty-second transistor, a fifty-third transistor and a fifty-fourth transistor, wherein: The gate and source of the fifty-first transistor are connected to the low-frequency control signal, and the drain of the fifty-first transistor, the drain of the fifty-second transistor and the gate of the fifty-third transistor are connected; The gate of the fifty-second transistor and the gate of the fifty-fourth transistor are connected to the pull-up terminal CQ(n) of the second GOA unit, and the source of the fifty-second transistor and the source of the fifty-fourth transistor are connected to a constant voltage low potential; The source of the fifty-third transistor is connected to the low-frequency control signal, and the drain of the fifty-third transistor and the drain of the fifty-fourth transistor are connected and connected to the output end of the inverter.

7. The GOA circuit according to claim 4, characterized in that: The pull-up unit of the n-th level GOA module includes an eleventh transistor, the gate and drain of the eleventh transistor are connected to the input end of the first GOA unit of the n-th level GOA module, and the drain of the eleventh transistor is connected to the pull-up ends of multiple second GOA units of the n-th level GOA module.

8. The GOA circuit according to claim 1, wherein: The pull-down unit of the n-th level GOA module includes a forty-first transistor, a gate of the forty-first transistor is connected to the pull-down end of the first GOA unit of the n-th level GOA module, a source of the forty-first transistor is connected to a constant voltage low potential, and a drain of the forty-first transistor is connected to the pull-up ends of multiple second GOA units of the n-th level GOA module.

9. The GOA circuit according to claim 2, characterized in that: The first clock signal end uses 8 clock cycle signals, and every two consecutive clock cycle signals are separated by half a clock cycle.

10. A display panel, characterized in that: The GOA circuit comprises the GOA circuit described in any one of claims 1 to 9.

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