Apparatus, system, and method for multi-pump error correction

Abstract

Apparatus, systems, and methods for multi-pump error correction. An error correction code (ECC) circuit can receive a plurality of data bits and provide one or more parity bits. The parity bits can be used to locate and / or correct errors in the data bits. The ECC circuit can split the plurality of data bits into a plurality of portions and then sequentially process the portions to generate preliminary parity bits. Once the portions of the data have been sequentially processed, the preliminary parity bits can be combined to generate the parity bits.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to semiconductor devices, such as semiconductor memory devices. BACKGROUND

[0002] Semiconductor memory devices can include a plurality of memory cells to store information. The stored information can be encoded as binary data, and each memory cell can store a single bit of information. Information in a memory cell can deteriorate or change due to a variety of different errors, which can result in one or more bits of incorrect information being read out from the memory device (e.g., bits having a different state than the originally written bits).

[0003] There can be many applications where it is useful to ensure a high fidelity of information read out from a memory. A memory device can include error correction circuitry that can be used to determine whether information read out from a memory cell contains any errors compared to the data written into the memory cell, and can correct the discovered errors. SUMMARY

[0004] One embodiment of the present disclosure provides an apparatus comprising: error correction code (ECC) circuitry configured to receive a plurality of data bits and provide a plurality of parity bits based on the plurality of data bits, wherein the ECC circuitry is configured to generate a first set of preliminary parity bits based on a first portion of the plurality of data bits at a first time, generate a second set of preliminary parity bits based on a second portion of the plurality of data bits at a second time after the first time, and generate the plurality of parity bits based on the first and second sets of preliminary parity bits.

[0005] Another embodiment of the present disclosure provides error correction code (ECC) circuitry comprising: a multiplexer configured to receive a plurality of data bits and provide a first portion of the plurality of data bits as pump bits at a first time and a second portion of the plurality of data bits as the pump bits at a second time after the first time; a logic tree configured to provide preliminary parity bits based on pump bits; and a logic gate configured to generate parity bits from a first preliminary parity bit based on the first portion of the plurality of data bits and a second preliminary parity bit based on the second portion of the plurality of data bits.

[0006] Yet another embodiment of the present disclosure provides a method comprising: dividing a plurality of data bits into a first portion and a second portion; generating a first preliminary parity bit based on the first portion at a first time; generating a second preliminary parity bit based on the second portion at a second time after the first time; and combining the first and second preliminary parity bits to generate parity bits. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a block diagram of a semiconductor device according to embodiments of the present disclosure.

[0008] Figure 2 is a block diagram of a memory device according to some embodiments of the present disclosure.

[0009] Figure 3 is a schematic diagram of error correction code (ECC) control circuitry according to some embodiments of the present disclosure.

[0010] Figure 4 is a chart showing a representation of the operation of a logic tree according to some embodiments of the present disclosure.

[0011] Figure 5 is a block diagram of a syndrome generator according to some embodiments of the present disclosure.

[0012] Figure 6 is a block diagram of a syndrome generator according to some embodiments of the present disclosure.

[0013] Figure 7 is a timing diagram of an example operation of ECC circuitry according to some embodiments of the present disclosure.

[0014] Figure 8 is a chart showing a representation of the operation of a logic tree according to some embodiments of the present disclosure.

[0015] Figure 9 is a block diagram of a syndrome generator according to some embodiments of the present disclosure.

[0016] Figure 10 is a block diagram of a method according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0017] The following description of certain examples is merely exemplary in nature and is in no way intended to limit the scope of the disclosure, its application, or uses. In the following detailed description of embodiments of the application, reference is made to the accompanying drawings that form a part hereof, and in which are shown by way of illustration specific embodiments in which the described systems and methods can be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the presently disclosed systems and methods, and it is to be understood that other embodiments can be utilized, and that structural and logical changes can be made without departing from the spirit and scope of the present disclosure. Furthermore, to the extent that the terms "includes" and "including" are used in the detailed description and claims, these terms are intended to be inclusive in a manner similar to the term "comprising" as that term is interpreted in the appended claims. Additionally, for clarity, certain detailed descriptions have not been discussed with respect to certain features in order not to obscure the descriptions of the embodiments of the present disclosure. Thus, the following detailed description is not to be understood in a restrictive sense and the scope of the present disclosure is defined by the appended claims.

[0018] A memory device can include a memory array having a number of memory cells, each memory cell located at an intersection of a word line (row) and a digit line (column). During an access operation, such as a read or write operation, a row can be activated and data can be read from or written to the memory cells along the activated row. Each row can include memory cells storing a number of bits of data and a number of bits of parity information (e.g., data bits and parity bits) that can be used to correct up to a certain number of errors in the data bits. During a write operation, an error correction code circuit can generate parity bits based on the data written to the memory cells of the row. During a read operation, the error correction code circuit can use the parity bits to determine whether the read data bits are correct, locate errors, and can correct any errors found.

[0019] An error correction code (ECC) circuit can be used to generate parity bits based on data written during a write operation and compare read data to read parity bits to locate errors. The ECC circuit can include a logic tree, such as a tree of XOR gates, that can be used to combine a set of write data or read data into parity bits. The logic tree can include a large number of logic gates and can occupy a relatively large amount of space. The number of logic gates can be based in part on the number of bits that the logic tree needs to process at one time. It can be useful to reduce the size of the logic tree by reducing the number of bits that the logic tree needs to process at one time.

[0020] The present disclosure is directed to apparatuses, systems, and methods for multi-pump error correction. An ECC circuit can receive a data block as part of an access operation. The ECC circuit can split the data block into a plurality of portions, each of which can be sequentially processed by a logic tree at different times (e.g., as part of different pumps). For example, the data block can be split into a first portion that can be processed by the logic tree in response to a first pump to generate a first set of preliminary parity bits, and the logic tree can sequentially process a second portion in response to a second pump to generate a second set of preliminary parity bits. The first and second sets of preliminary parity bits can then be combined to generate an overall set of parity bits associated with the data block. Because the data is split into a plurality of portions that are sequentially processed, the logic tree can process a smaller number of bits each time, which can allow for a reduction in the size of the logic tree.

[0021] In some embodiments, the logic tree can have different operations between different pumps. For example, in some embodiments, the logic tree can have different sections, some of which can receive only a subset of bits in a given pump to change the operation of the overall logic tree between pumps. For example, in some embodiments, the logic tree can have different sections, some of which can be used to process all portions and some of which can be used only by some portions of the data.

[0022] Figure 1 is a block diagram of a semiconductor device according to an embodiment of the present disclosure. The semiconductor device 100 can be a semiconductor memory device, such as a DRAM device integrated on a single semiconductor chip.

[0023] The semiconductor device 100 includes a memory array 118. The memory array 118 is shown to include a plurality of memory banks. In Figure 1 In an embodiment, the memory array 118 is shown to include eight memory banks BANK0 to BANK7. More or fewer banks can be included in the memory array 118 of other embodiments. Each memory bank includes a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC arranged at intersections of the plurality of word lines WL and the plurality of bit lines BL. Selection of the word lines WL is performed by a row decoder 108, and selection of the bit lines BL is performed by a column decoder 110. In Figure 1 In an embodiment, the row decoder 108 includes a respective row decoder for each memory bank, and the column decoder 110 includes a respective column decoder for each memory bank. The bit lines BL are coupled to respective sense amplifiers (SAMP). Read data from the bit lines BL is amplified by the sense amplifiers SAMP and transferred to an error correction code (ECC) control circuit 120 through a complementary local data line (LIOT / B), a transfer gate (TG), and a complementary main data line (MIOT / B) coupled to the ECC control circuit 120. Conversely, write data output from the ECC control circuit 120 is transferred to the sense amplifiers SAMP through the complementary main data line MIOT / B, the transfer gate TG, and the complementary local data line LIOT / B, and written in the memory cells MC coupled to the bit lines BL.

[0024] The semiconductor device 100 can employ a plurality of external terminals, including command and address (C / A) terminals coupled to a command and address bus to receive commands and addresses, and a CS signal clock terminal for receiving a clock CK and / CK; data terminals DQ for providing data; and power terminals for receiving power supply potentials VDD, VSS, VDDQ, and VSSQ.

[0025] An external clock CK and / CK is supplied to clock terminals, which are provided to input circuitry 112. The external clock can be complementary. Input circuitry 112 generates an internal clock ICLK based on the CK and / CK clock. The ICLK clock is provided to command decoder 106 and internal clock generator 114. Internal clock generator 114 provides various internal clocks LCLK based on the ICLK clock. The LCLK clock can be used for timing operations of various internal circuitry. An internal data clock LCLK is provided to input / output circuitry 122 to time operations of circuitry included in input / output circuitry 122, such as to a data receiver to time reception of write data.

[0026] The C / A terminals can be supplied with memory addresses. The memory addresses supplied to the C / A terminals are transferred to address decoder 104 via command / address input circuitry 102. Address decoder 104 receives the addresses and supplies a decoded row address XADD to row decoder 108 and a decoded column address YADD to column decoder 110. Address decoder 104 can also supply a decoded bank address BADD, which can indicate a bank of memory array 118 that contains the decoded row address XADD and column address YADD. Commands can be supplied to the C / A terminals. Examples of commands include timing commands to control timing of various operations, access commands to access memory, such as read commands to perform read operations and write commands to perform write operations, as well as other commands and operations. An access command can be associated with one or more row addresses XADD, column addresses YADD, and bank addresses BADD to indicate memory cells to be accessed.

[0027] Commands can be provided to command decoder 106 as internal command signals via command / address input circuitry 102. Command decoder 106 includes circuitry to decode the internal command signals to generate various internal signals and commands to perform operations. For example, command decoder 106 can provide row command signals to select word lines and column command signals to select bit lines.

[0028] The device 100 can receive access commands as read commands. When a read command is received and the bank address, row address, and column address are supplied in time with the read command, read data is read from the memory cells of the memory array 118 corresponding to the row and column addresses. The read command is received by the command decoder 106, which provides internal commands to cause the read data from the memory array 118 to be provided to the ECC control circuit 120. The read command can also cause one or more parity bits associated with the read data to be provided to the ECC control circuit 120 along the MIOT / B. The ECC control circuit 120 can use the parity bits to determine if the read data includes any errors, and if any errors are detected, can correct them to produce corrected read data. The corrected read data is output from the data terminals DQ to the outside of the device 100 via the input / output circuit 122.

[0029] The device 100 can receive access commands as write commands. When a write command is received and the bank address, row address, and column address are supplied in time with the write command, write data is supplied to the ECC control circuit 120 through the DQ terminals. The write data supplied to the data terminals DQ is written to the memory cells of the memory array 118 corresponding to the row and column addresses. The write command is received by the command decoder 106, which provides internal commands to cause the write data to be received by the data receivers in the input / output circuit 122. A write clock can also be provided to the external clock terminals for use in timing the reception of the write data by the data receivers of the input / output circuit 122. The write data is supplied to the ECC control circuit 120 via the input / output circuit 122. The ECC control circuit 120 can generate a number of parity bits based on the write data, and can provide the write data and the parity bits to the memory array 118 for writing to the memory cells MC.

[0030] The ECC control circuit 120 can be used to ensure fidelity of data read from a particular group of memory cells to data written to the group of memory cells. In some embodiments, the device 100 can include several different ECC control circuits 120, each of which is responsible for a different portion of the memory cells MC of the memory array 118. For example, there can be one or more ECC control circuits 120 for each bank of the memory array 118.

[0031] Each ECC control circuit 120 can receive a number of data bits (from the IO circuit 122 or the memory array 118) and can use a number of parity bits to correct potential errors in the number of data bits based on the number of data bits. For example, as part of a write operation, the ECC control circuit 120 can receive 128 data bits from the IO circuit 122 and can generate 8 parity bits based on the 128 data bits. The 128 data bits and 8 parity bits (e.g., a total of 136 bits) can be written to the memory array 118. As part of an example read operation, the ECC control circuit 120 can receive 128 data bits and 8 parity bits from the memory cell array 118. The ECC control circuit 120 can use the 8 parity bits to determine whether there are any errors in the 128 read data bits and, if any errors are found, can correct them. For example, the ECC control circuit 120 can be capable of locating and correcting up to one error bit in the 128 data bits based on the 8 parity bits. While various embodiments can be discussed with reference to an ECC circuit that uses 8 parity bits to find one error in 128 data bits, it should be understood that this is for explanatory purposes only and that other numbers of data bits, error bits, and parity bits can be used in other example embodiments. In Figure 3 Example ECC circuits are discussed in more detail.

[0032] Each ECC control circuit 120 can receive a data set as part of an access operation (e.g., a read or write operation) and can split the data set into multiple portions that are sequentially processed to generate parity bits associated with the data set. For example, the ECC control circuit 120 can split the data into halves and sequentially process each half. The ECC control circuit 120 can be coupled to various command and timing signals (e.g., a clock signal such as ICLK, a command signal such as R / W) and can generate various internal timing signals used to control the sequential processing of the portions of the data set.

[0033] The device 100 can also receive a command to perform one or more refresh operations as part of a self-refresh mode. In some embodiments, a self-refresh mode command can be externally issued to the memory device 100. In some embodiments, a self-refresh mode command can be periodically generated by a component of the device. In some embodiments, a refresh signal AREF can also be activated when an external signal indicates a self-refresh entry command. The refresh signal AREF can be a pulsed signal that is activated when the command decoder 106 receives a signal indicating entry into a self-refresh mode. The refresh signal AREF can be activated immediately following the command input, and thereafter can be activated in a desired internal timing cycle. The refresh signal AREF can be used to control the timing of refresh operations during the self-refresh mode. Thus, refresh operations can continue automatically. A self-refresh exit command can stop the automatic activation of the refresh signal AREF and return to an idle state. The refresh signal AREF is supplied to the refresh control circuit 116. The refresh control circuit 116 supplies a refresh row address RXADD to the row decoder 108, which can refresh one or more word lines WL indicated by the refresh row address RXADD.

[0034] The supply terminals are also supplied with supply potentials VDDQ and VSSQ. The supply potentials VDDQ and VSSQ are supplied to the input / output circuit 122. In some embodiments of the present disclosure, the supply potentials VDDQ and VSSQ supplied to the supply terminals can be the same potentials as the supply potentials VDD and VSS supplied to the supply terminals. In another embodiment of the present disclosure, the supply potentials VDDQ and VSSQ supplied to the supply terminals can be different potentials from the supply potentials VDD and VSS supplied to the supply terminals. The supply potentials VDDQ and VSSQ supplied to the supply terminals are used for the input / output circuit 122 so that supply noise generated by the input / output circuit 122 does not propagate to other circuit blocks.

[0035] The supply terminals are also supplied with supply potentials VDDQ and VSSQ. The supply potentials VDDQ and VSSQ are supplied to the input / output circuit 122. In some embodiments of the present disclosure, the supply potentials VDDQ and VSSQ supplied to the supply terminals can be the same potentials as the supply potentials VDD and VSS supplied to the supply terminals. In another embodiment of the present disclosure, the supply potentials VDDQ and VSSQ supplied to the supply terminals can be different potentials from the supply potentials VDD and VSS supplied to the supply terminals. The supply potentials VDDQ and VSSQ supplied to the supply terminals are used for the input / output circuit 122 so that supply noise generated by the input / output circuit 122 does not propagate to other circuit blocks.

[0036] Figure 2 is a block diagram of a memory device according to some embodiments of the present disclosure. The memory device 200 shows an example layout of certain components used as part of access operations in the memory device 200. Other components can be omitted for clarity. In some embodiments, the memory device 200 can be included in a memory sub-system, such as the memory sub-system 100 of FIG. 1. Figure 1memory device 100.

[0037] The memory device 200 includes a number of bank groups 240 as part of a memory array. The bank groups 240 can be divided into a first portion of bank groups 240a and a second portion of bank groups 240b, with a row decoder 208 located between the sections. Two sections of a given bank group 240 and the row decoder 208 can be arranged along a first direction (e.g., the y-axis). Each bank group 240 can be separated from another bank group by a column decoder 210 associated with a first bank group, an error correction region 220, and a column decoder 210 associated with a second bank. The bank groups, column decoders 210, and error correction regions 220 can be arranged along a second axis (e.g., the x-axis) that is orthogonal to the first axis. The bank groups of the memory device 200 can be arranged in an array along the x-y plane.

[0038] There can be an error correction region 220 and a column decoder 210 for each portion of a given bank group 240. The error correction region 220 can be coupled to one or more DQ pads 226 (e.g., through I / O circuitry) to send and receive data external to the device 200. The DQ pads 226 (and I / O circuitry, etc.) can be located in a PERIDQ region between the memory bank groups 240, and other components of the memory device 200 (e.g., command address input circuitry) can be located in a PERICA region between the memory bank groups 240.

[0039] The ECC region 220 includes one or more ECC control circuits to correct data bits stored in the memory bank groups 240 associated with the ECC region 220. For example, each ECC region 220 can include ECC control circuitry that manages the portions of the bank groups on either side of the ECC region 220. For example, a first ECC region 220 can be associated with portion 240a and a second ECC region 220 can be associated with portion 240b. In some embodiments, the ECC region 220 can include ECC control circuitry that corrects data for any of the bank groups associated with the ECC region 220 depending on which bank group is active. In some embodiments, the ECC region 220 can extend (e.g., along the y direction) and can include one or more ECC control circuits that can manage both portions of a bank group (e.g., 240a and 240b).

[0040] Figure 3 is a schematic diagram of an error correction code (ECC) control circuit according to some embodiments of the present disclosure. In some embodiments, Figure 3 The ECC control circuit 300 of the memory device 100 can be included in Figure 1 The ECC control circuit 120 and / or Figure 2ECC control circuit 220. As part of a write operation, ECC control circuit 300 can receive write data bits WD and can generate write parity bits WP. These can be provided as data bits D and parity bits P to the memory array and can be stored in the memory array for later retrieval. As part of a read operation, ECC control circuit 300 can receive data D from the memory array as read data RD and parity bits P as read parity PR, and can generate corrected data bits CRD based on bits RD and PR. Corrected data bits CRD can then be provided to I / O circuitry (e.g., Figure 1 from the device.

[0041] During an example read operation, read amplifiers 301 are activated to amplify read parity PR and read data RD. Amplified bits PR and RD are provided to encoder / syndrome generator circuit 315. Encoder / syndrome generator circuit 315 provides syndrome bits S based on read bits RD and PR. In some embodiments, the number of syndrome bits S can match the number of parity bits PR. Syndrome bits S are provided to error locator circuit 330. Syndrome bits S can represent parity bits that would have been written as part of a write operation (e.g., WP), or can represent syndrome information for read parity PR and RD based on indicating a mismatch between read parity information and syndrome bits generated from read parity.

[0042] As part of a read operation, error locator circuits 330 and 340 can determine the location of errors in read data RD based on syndrome information S. Error locator circuit 330 provides a first set of error determination signals EBST and a second set of error determination bits EDQ based in part on syndrome bits S. In some embodiments, data provided to / at the DQ terminals can be organized into bursts on several different DQ terminals (e.g., a burst of 8 bits on each of 16 different DQ terminals, totaling 128 bits). The first set of error determination signals EBST can indicate the location of error bits within a burst. In some embodiments, there can be a bit for each of the bits in a burst, and signals EBST can be provided collectively to the DQ terminals. The second set of error determination signals EDQ can indicate which of the DQ terminals an error bit is being provided to. In some embodiments, there can be a bit for each DQ terminal, and signals EDQ can be provided collectively with the burst bits.

[0043] Error determination signals EBST and EDQ can be provided to a second error locator circuit 340. The second error locator circuit 340 can decode the signals EBST and EDQ to identify the location of the error bits in the read data RD. The location of the error bits can be specified by an error location signal EL. In some embodiments, there can be a number of bits of the error location signal EL based on the number of bits of the read data RD, where each bit of the error location signal EL is associated with a bit of the read data RD.

[0044] The error location signal EL is provided to an error correction circuit 350. The error correction circuit 350 also receives the read data RD and corrects one or more error bits in RD based on the error location signal EL. For example, if the nth bit of the error location signal EL is at a high logic level, then the error correction circuit 350 can change the state of the nth read bit RD. The error correction circuit 350 can provide corrected read data CRD. The corrected read data CRD can be provided to the DQ pads and read out from the device.

[0045] In an example write operation to a memory device, the ECC control circuit 300 can receive write data WD and a data mask signal DM. The first multiplexer 303 can synthesize the write data WD and the corrected read data CRD based on the data mask signal DM. The first multiplexer 303 can provide data D to the write amplifiers 302, which provide amplified data D to the memory array. In some embodiments, the data mask signal DM can be associated with different burst bits received at the data terminals. When one (or more) of the data mask bits DM is active, then the write data WD associated with that data mask bit can be replaced by the corrected read data CRD in the data D.

[0046] Write parity WP information can be synthesized based on WD. The write data can pass through the write amplifiers 302 to become data D, and then fed through the syndrome generator 315 to generate syndrome information S. The syndrome information S can be used along with the write parity WP' to generate write parity WP, which is written to the memory array as parity bits P. The second multiplexer 304 can synthesize the write data WD and the read data RD based on the data mask signal. The second multiplexer 304 can provide parity write data PWD. The parity write data PWD can be provided to the encoder / syndrome generator circuit 315, which can encode the parity write data PWD to write parity WP'. The write parity WP' is provided to the converter circuit 305, which generates write parity WP, which is written to the memory array as parity bits P.

[0047] The converter circuit 305 includes an XOR logic gate 305a and a third multiplexer 305b. The XOR logic gate 305a has input terminals coupled to the syndrome bit S and the write parity bit WP'. The XOR logic gate 305a provides an output that is at a high logic level when the syndrome bit S is different from the associated write parity bit WP'. The third multiplexer 305b provides the output of the XOR logic gate 305a or the write parity WP' as the write parity WP. The multiplexer 305b selects the source of the write parity WP bit based on the conversion signal EDM. When the conversion signal EDM is active, the write parity WP is the output of the XOR gate 305a. When the conversion signal EDM is inactive, the signal WP' is provided as the signal WP.

[0048] The mask error detector circuit 360 provides the signal EDM based on the syndrome bit S and the data mask DM. The mask error detector circuit 360 can determine whether the error bit belongs to the same burst of data as the data masked by the data mask signal DM. If they are the same, the signal EDM can be activated. If they are not the same, the signal EDM can remain inactive.

[0049] The encoder / syndrome generator circuit 315 includes a logic tree that receives read data RD (as part of a read operation) or write data WD (as part of a write operation). The logic tree can encode the received data into one or more syndrome bits S. The read data RD and the parity write data WD can have a number of bits. In some embodiments, the read data RD and the parity write data WD can have the same number of bits. The number of bits of RD and WD can be based on the read / write word length of the memory. For example, the read data RD and the parity write data WD can each include 128 bits. The encoded parity bits can include a number of bits. In some embodiments, the number of syndrome bits S can be substantially less than the number of input data bits (e.g., WD or RD). For example, if the input data WD or RD includes 128 bits, there can be 8 syndrome bits. More or fewer syndrome bits can be used in other example embodiments. In some embodiments, the number of syndrome bits S can be based on the number of bits of the input data WD or RD. For example, if the input data WD or RD includes 128 bits, there can be 8 syndrome bits. More or fewer syndrome bits can be used in other example embodiments. Figures 4 to 6 The operation of an example syndrome generator is discussed in more detail in

[0050] The syndrome generator 315 can split the received read data RD (or write data WD) into a number of groups, each of which can be processed by the logic tree in response to activation of a pump signal (pump). For example, the data can be split into a first group and a second group, each of which can be processed to generate a respective set of preliminary parity bits, which can then be combined to generate the syndrome bits S.

[0051] Although the operations of the syndrome generator 315 are described in terms of Figure 3not shown, but various components can be activated by one or more timing and control signals, which can help indicate whether a write or read operation is being performed. For example, the encoder / syndrome generator circuit 315 can receive a write state signal, which can be at a first level if a write operation is being performed and at a second level if a read operation is being performed. The components of the ECC circuit 300 can also receive various timing signals, which can be provided to the various components in sequence to trigger activation of the various components in the proper order to ensure that write and read operations are performed correctly. For example, the syndrome generator 315 can receive pump signals that manage the processing of different portions of the read or write data. In Figure 7 The timing of an example ECC circuit is discussed in more detail in the background.

[0052] Figure 4 is a chart showing a representation of the operation of a logic tree according to some embodiments of the present disclosure. The chart 400 depicts the logical operations of a particular example embodiment of a logic tree. For example, the chart can represent the operation of one or more logic trees in the syndrome generator 315 of Figure 3 .

[0053] The chart 400 shows the index of the bytes across the first row and the index of the bits within the bits across the second row. Thus, the list of the chart 400 represents the data bits input to the logic tree (e.g., the RD or PWD of Figure 3 . In an example embodiment of Figure 4 , the logic tree receives 128 data bits and generates 8 parity bits. More or fewer data bits and / or parity bits can be used in other example embodiments.

[0054] The rows of the chart 400 (except for the first two index rows) represent different parity bits generated by the logic tree. In an example embodiment of Figure 4 , 8 parity bits (S0 through S7) are generated from 128 data bits. More or fewer parity bits can be used in other example embodiments.

[0055] Each entry in the chart 400 represents whether the data bit is used to generate the corresponding parity bit. An entry of one in the chart can represent that the data bit is used, while an entry of zero can represent that the data bit is not used to generate the parity bit. Thus, reading across a row of the chart 400, an entry with a one can represent that all of the data bits are logically combined (e.g., via an XOR gate) to generate the parity bit.

[0056] The chart 400 is divided into a first portion 410 and a second portion 420. The two portions can represent portions of the data that are processed by separate pumps (e.g., sequentially). In an example embodiment of Figure 4In one embodiment, there are two pumps, each of which can receive a portion of data, which in this case is divided in half. Therefore, since the data in this embodiment contains 128 bits, 64 bits are processed during the first pump and 64 bits are processed during the second pump. Other arrangements can be used to divide several data bits into other portions, such as one-third, one-quarter, etc. In some embodiments, different portions may contain different numbers of bits (e.g., a first portion may have a first number of bits, a second portion may have a second number of bits different from the first number, etc.).

[0057] Boxes 412, 414, 416, 422, 424, and 426 represent sections of parts 410 and 420, respectively, which can be used for the layout of the logic tree to help manage the input to the logic tree during different pumps. For example, note that boxes 412 and 422 contain entries that are the same as each other, boxes 416 and 426 contain entries that are the same as each other, and boxes 414 and 424 contain logically complementary rows.

[0058] Ensuring that there is at least one difference between the first portion 410 and the second portion 420 can be useful. This helps ensure that one or more pieces of information in the data bits are not lost during the generation of the parity bit. For example, at least one row (e.g., at least one parity bit) may have different entries in the first portion 410 and the second portion 420. Figure 4 In the example embodiment, boxes 414 and 424 highlight two rows (parity bits) that are calculated differently between the two sections 410 and 420, respectively. In other example embodiments, there may be differences in the number of parity bits.

[0059] Figure 5 This is a block diagram of a checksum generator according to some embodiments of the present disclosure. In some embodiments, the checksum generator 500 may represent Figure 4 An example implementation of the logic tree logic arranged in the middle. In some embodiments, the check generator 500 may be included in Figure 3 In the checksum generator 315. The checksum generator 500 shows the components of the logic tree used for the write operation. Figure 6 A more detailed description of the checksum generator used for the read operation (which may be checksum generator 500, but has...) Figure 5 (Additional components omitted from the diagram). Figure 5 and 6 This illustrates a specific implementation of Figure 400. Other implementations may be used in other example embodiments.

[0060] The check generator 500 shows several logic trees (e.g., XOR trees) 510-516, each containing several logic gates that combine bits. Logic trees 510-516 can be as follows:Figure 4 The bits are combined in the manner described in Figure 400. For example, logic tree 510 can be configured using... Figure 4 The 64 bits of the input are combined in the manner shown in boxes 412 and 422 to produce four parity bits (e.g., the first parity bit S0 may involve XORing every other input bit, etc.). Logic tree 516 can be implemented. Figure 4 Boxes 416 and 426. Logic trees 512 and 514 can be implemented in more detail as described herein. Figure 4 Boxes 414 and 424.

[0061] The checksum generator 500 includes multiplexers 502-506, whose management splits the input data (BUS0-127) into two parts, each of which can be provided as pump positions D0-63. For simplicity, the timing signals (e.g., pump signals) used to control the multiplexers 502-506 (and latch 520) are omitted. The timing of operations of instance logic trees, such as the checksum generator 500, will be... Figure 7 The following is a more detailed discussion.

[0062] Multiplexer 502 receives data along the input data bus, for example Figure 3 Write data PWD (or Figure 3 Reading data RD, such as in Figure 6 (Discussed in more detail below). Figure 5 In an example embodiment, the input data bus BUS contains 128 data bits (e.g., BUS0-BUS127). Multiplexer 502 can provide a first portion of the data on the bus or a second portion of the data on the bus as pump bits D0-63 based on the state of the pump signal. Therefore, multiplexer 502 can provide a first portion of the data at a first time (e.g., pump bits D0-63 are BUS0-63) and a second portion of the data at a second time (e.g., D0-63 is BUS64-127).

[0063] Since logic trees 510 and 516 represent operations on the logic tree that do not change between pumps (e.g., Figure 4 Boxes 412, 422, 416, and 426) can therefore receive selected portions from multiplexer 502. Since logic trees 512 and 514 represent portions of the logic tree that change between pumps (e.g., ...), Figure 4 (Boxes 414 and 424), so further modifications to parts of the data may be required subsequently.

[0064] exist Figure 5 In the example embodiment, logic trees 512 and 514 represent logically complementary operations. Specifically, during the first pump, Figure 4Block 414 shows that parity bit S5 is generated using the first 32 bits of a portion, and parity bit S6 is generated using the second 32 bits of the portion, and block 424 shows that parity bit S5 is generated using the second 32 bits, and parity bit S6 is generated using the first 32 bits. Thus, additional multiplexers 504 and 506 are used, which split the pump bits D0-D63 into a first half and a second half. In response to a first pump signal, multiplexer 504 can provide the first half of the selected portion (e.g., pump bits D0 through D31) to logic tree 512, while multiplexer 506 can provide the second half of the selected portion (e.g., bits D32 through D63) to logic tree 514. Thus, during a first pump, logic tree 512 can receive data bus bits BUS0-31, while XOR tree 514 can receive data bus bits BUS32-63. During a second pump, multiplexers 504 and 506 can be reversed, and multiplexer 504 can provide bits D32 through D63 to logic tree 512, while multiplexer 506 can provide bits D0 through D31 to XOR tree 514. Thus, during a second pump, logic tree 512 can receive data bus bits BUS96-BUS127, while logic tree 514 can receive data bus bits BUS64-95. Multiplexers 504 and 506 can be responsive to the same signals as multiplexer 502, or one or more different signals.

[0065] Logic trees 510-516 can each generate one or more partial parity bits N0 through N7 based on received input data (e.g., D0-D63 or a portion thereof). For example, logic tree 510 generates five partial parity bits N0 through N4, while XOR trees 512-516 each generate one bit N5 through N7, respectively. A set of latches 520 can store partial parity bits generated in response to a first portion of bus data (e.g., during a first pump). A first pump signal (and / or a signal having timing related to the first pump signal) can cause latches 520 to store values N0 through N7 generated during the first pump. The values stored in latches 520 can be one input to each of a respective plurality of XOR gates 530. A second input to the XOR gates can be directly tied to one of values N0 through N7. Thus, during a second pump, XOR gates 530 can each combine the second pump values of N0 through N7 with the first pump values of N0 through N7 stored in a respective one of latches 520. The outputs of XOR gates 530 can represent parity bits P0 through P7. Thus, each parity bit P0 through P7 is made by combining partial parity bits generated during a first pump with partial parity bits generated during a second pump.

[0066] Figure 6is a block diagram of a syndrome generator according to some embodiments of the disclosure. In some embodiments, syndrome generator 600 can represent Figure 4 an example implementation of the logic tree logic arranged in. In some embodiments, syndrome generator 600 can be included in Figure 3 syndrome generator 315 of. Syndrome generator 600 shows components of a logic tree used as part of a read operation. Syndrome generator 600 can be generally similar to Figure 5 syndrome generator 500, except that Figure 6 additional components are shown to generate syndrome bits S0-S7 as part of a read operation.

[0067] For brevity, since logic tree 600 includes many of the same components as syndrome generator 500, components and operations already described with respect to Figure 5 will not be repeated with respect to Figure 6 again.

[0068] During a read operation, additional logic gates such as XOR gates 640 can be used to compare parity bits generated based on read data (e.g., BUS0-BUS127) and read parity bits associated with the data (e.g., BUS128-BUS135). Each XOR gate 640 can compare a parity bit generated from read data (e.g., an output of XOR gate 530) with a respective one of read parity bits BUS128-BUS135. Read parity bits BUS128-BUS135 can be provided to XOR gates 640 in any timing, such as as part of a first pump or a second pump.

[0069] Figure 7 is a timing diagram of example operations of an ECC circuit according to some embodiments of the disclosure. In some embodiments, timing diagram 700 can represent Figures 4 to 6 operations of an ECC circuit represented in. As in those embodiments, in timing diagram 700, 128 data bits are read / written and 8 parity bits are generated based on those data bits.

[0070] The timing diagram generally starts at an initial time to, at which read or write data (Rd / Wr data) is provided along buses BUS0-127. The read or write data can be provided as part of an access operation (e.g., a read or write operation). The read / write data can be provided to an ECC circuit (e.g., Figure 3 ECC circuit 300 of).

[0071] At a first time ti, the data is divided into a first portion. Just before time ti, a multiplexer signal MUX can be activated in a first state to indicate a multiplexer coupled to the read / write data (e.g., multiplexer 610 of) to provide the first portion of the data to a first pump (e.g., first pump 620 of).Figures 5 to 6 The first portion of read / write data should be provided by the multiplexers 502) in the first state. For example, in the first state, the multiplexer signal MUX can cause the multiplexers to provide the first half of the bits of the read / write data as the pump bits D0-63 (e.g., Bus0-63).

[0072] At a second time t2, the various logic trees (e.g., 510-516) can provide various preliminary parity bits N0-7. At this same time, the latch clock Lat clock can activate, which can cause the preliminary parity bits N0-7 to be latched in the corresponding latches (e.g., 520). This can set the latch outputs to the preliminary parity bits N0-7 for the data portion Bus0-63. Figure 5 Figure 5 Just before a third time t3, the multiplexer signal MUX can change to a second state, which can cause the multiplexers to provide a second portion of the data BUS0-127 as the pump bits D0-63. In other words, at time t3, the values of D0-63 can change to BUS64-127. At time t4, the various logic trees can complete processing the second portion of data, and the preliminary parity bits N0-7 can change to new values based on the second portion of data BUS64-127. At this point, the logic gates (e.g., XOR gates 530) can combine the preliminary parity bits for the first portion of data (e.g., BUS0-63) stored in the latches with the preliminary parity bits for the second portion of data (e.g., BUS64-127) to generate the overall parity bits P0-7.

[0073] Just before a third time t3, the multiplexer signal MUX can change to a second state, which can cause the multiplexers to provide a second portion of the data BUS0-127 as the pump bits D0-63. In other words, at time t3, the values of D0-63 can change to BUS64-127. At time t4, the various logic trees can complete processing the second portion of data, and the preliminary parity bits N0-7 can change to new values based on the second portion of data BUS64-127. At this point, the logic gates (e.g., XOR gates 530) can combine the preliminary parity bits for the first portion of data (e.g., BUS0-63) stored in the latches with the preliminary parity bits for the second portion of data (e.g., BUS64-127) to generate the overall parity bits P0-7. Figures 5 to 6

[0074] Although not shown in FIG. 5, it should be understood that additional signals can be used. For example, the multiplexers 504 and 506 of FIG. 5 can be operated by additional multiplexer signals, not shown. Figure 7 Figures 5 to 6

[0075] Figure 8 is a chart showing a representation of the operation of a logic tree according to some embodiments of the present disclosure. Figure 8 The chart 800 of FIG. 8 can be generally similar to the chart 400 of FIG. 4, except that Figure 4 The chart 800 of FIG. 8 depicts an embodiment in which the input data is divided into four pumps (rather than two, as depicted in FIG. 4). For the sake of brevity, features similar to those described in FIG. 4 will not be repeated with respect to FIG. 8. Figure 8 Figure 4 Figure 4 Figure 8

[0076] ​​​​​​​​In diagram 800, the 128 bits are split into four distinct pumps, each 32 bits long. Each pump represents a portion of the data shown in boxes 810, 820, 830, and 840, respectively. Each portion has a box representing logic that remains unchanged between pumps. For example, boxes 812, 822, 832, and 842 all have the same entries as each other. Each portion also has boxes that change between pumps. For example, box 814 is different from box 824.

[0077] Figure 9 This is a block diagram of a checksum generator according to some embodiments of the present disclosure. In some embodiments, the checksum generator 900 may represent Figure 8 An example implementation of the logic tree logic arranged in Figure 800. In some embodiments, the checksum generator 900 may be included in... Figure 3 In the checksum generator 315. The checksum generator 900 can be broadly similar to Figure 5 The difference between the check generator 500 and the check generator 900 is that the check generator 900 uses four pumps (e.g., the data is divided into four parts) instead of... Figure 5 The two pumps (and two sections) shown are illustrated. For simplicity, the check generator 900 can be broadly represented as... Figure 5 The checksum generator 500 is therefore similar to the previous one relative to... Figure 5 The features and operations already described will not be relative to Figure 9 repeat.

[0078] The check generator 900 shows several logic trees 910-916, each containing several logic gates (e.g., XOR gates) arranged in a tree manner, the tree arrangement in this example being based on... Figure 8 The input patterns are shown in Figure 800. Therefore, logic tree 910 can implement blocks 812, 822, 832, and 842; logic trees 912 and 914 can implement blocks 814, 824, 834, and 844; and logic tree 916 can implement blocks 816, 826, 836, and 846. It should be noted that, due to... Figure 5 Compared to logic trees 510-516 (each of which processes 64 bits at a time), each of logic trees 910-916 processes fewer bits at a time (e.g., 32). Therefore, logic trees 910-916 can contain fewer logic gates and thus occupy less space (and draw less power).

[0079] Multiplexer 902 can split the received data BUS0-127 into four portions and sequentially provide each portion as pump bits D0-31. Thus a first pump can include BUS0-31, a second pump can include BUS32-63, a third pump can include BUS63-95, and a fourth pump can include BUS96-127. Thus a multiplexer control signal that operates multiplexer 902 can have four states. A timing generator (not shown) can control the timing of signals such as the multiplexer control signal (and a latch signal that operates latches 920). The timing generator can be activated by various command signals such as signals associated with read and write operations.

[0080] Rather than splitting the pump bits into different portions (e.g., a first half and a second half) as in Figure 5 , logic trees 912 and 914 can only receive data during certain pumps. Multiplexers 904 and 906 can control when pump bits D0-31 are provided to logic trees 912 and 914, respectively. In Figure 9 , a first multiplexer 904 can pass pump bits through first and fourth pumps (e.g., BUS0-31 and BUS96-127) but block the pump bits during second and third pumps (e.g., data BUS32-63 and BUS63-95). A second multiplexer 906 can pass pump bits during second and third pumps but block the pump bits during first and fourth pumps. Multiplexers 904 and 906 can be operated by the same multiplexer signal as multiplexer 902 or can be operated by different multiplexer control signals.

[0081] Although not shown in Figure 9 , additional features can be used in syndrome generator 900 during read operations similar to the differences between Figure 5 and 6 .

[0082] Figure 10 is a block diagram of a method in accordance with some embodiments of the disclosure. In some embodiments, method 1000 can be implemented by one or more of the systems or devices described in Figures 1 to 9 .

[0083] Method 1000 can generally begin with block 1010, which describes dividing a plurality of data bits into a first portion and a second portion. The data bits can be associated with an access operation such as a read or write operation, for example. For example, there can be 128 data bits. The data bits can be received by a multiplexer that can sequentially provide the portions. For example, the first portion can be provided in response to a multiplexer signal being in a first state while the second portion can be provided in response to the multiplexer signal being in a second state.

[0084] Block 1010 can be generally followed by block 1020, which describes generating first preliminary parity bits based on the first portion at a first time. The first preliminary parity bits can be generated by a logic tree (e.g., 510-516 of Figure 5 FIG. 1). The first preliminary parity bits can be stored in latches.

[0085] Block 1020 can be generally followed by block 1030, which describes generating second preliminary parity bits based on the second portion at a second time. In some embodiments, the second preliminary parity bits can be generated by the same logic tree as the first preliminary parity bits.

[0086] Block 1030 can be generally followed by block 1040, which describes combining the first preliminary parity bits and the second preliminary parity bits to generate parity bits. For example, a logic gate such as an XOR gate can combine the first and second preliminary parity bits. In some embodiments, the first preliminary parity bits can be received from latches.

[0087] In some embodiments, the method 1000 can include generating additional parity bits. In some embodiments, these further include generating third preliminary parity bits based on a first half of the first portion, generating fourth preliminary parity bits based on a second half of the first portion, and combining the third and fourth preliminary parity bits to generate second parity bits.

[0088] It should be appreciated that any of the examples, embodiments, or processes described herein can be combined or separated into other examples, embodiments and / or processes according to the systems, apparatuses and methods of the present invention.

[0089] Finally, the above discussion is meant to be illustrative only of the systems of the present invention and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Thus, while the systems of the present invention have been described in detail with respect to exemplary embodiments, it will be apparent to those skilled in the art that numerous modifications and variations of the systems described herein can be made without departing from the spirit and scope of the systems of the present invention as set forth in the following claims. The specification and drawings should thus be considered in all respects to be illustrative and not restrictive.

Claims

1. A semiconductor device comprising: An error correction code (ECC) circuit configured to receive multiple data bits and provide multiple parity bits based on the multiple data bits, wherein the ECC circuit is configured to: Based on the first portion of the multiple data bits, a preliminary set of parity bits is generated using a logic tree. At a second time following the first time, a second set of preliminary parity bits is generated using the same logic tree based on the second portion of the plurality of data bits, and The first and second sets, based on the initial parity bits, generate the plurality of parity bits using corresponding gates that are separate from the logic tree.

2. The semiconductor device of claim 1, wherein the ECC circuit comprises: A multiplexer configured to split the plurality of data bits into a first portion and a second portion; as well as The logic tree is configured to generate at least one preliminary parity bit in the first set and at least one preliminary parity bit in the second set.

3. The semiconductor device of claim 2, wherein the ECC circuit further comprises: A latch configured to store the first set of preliminary parity bits; as well as A logic gate configured to combine a second set of preliminary parity bits with a first set of preliminary parity bits stored in the latch.

4. The semiconductor device of claim 2, wherein the ECC circuit further comprises: A second logic tree is configured to provide at least one preliminary parity bit in a first set of preliminary parity bits based on a first half of the first portion of the plurality of data bits, and is configured to provide at least one preliminary parity bit in a second set of preliminary parity bits based on a second half of the second portion of the plurality of data bits.

5. The semiconductor device of claim 1, further comprising a memory array, wherein, as part of a write operation, the plurality of data bits and the plurality of parity bits are written into the memory array.

6. The semiconductor device of claim 1, further comprising a memory array, wherein, as part of a read operation, the plurality of data bits are read from the memory array together with a plurality of read parity bits.

7. The semiconductor device of claim 6, wherein the ECC circuit is further configured to combine the plurality of read parity bits with the plurality of parity bits to generate a plurality of parity sub-bits, and wherein the ECC circuit is further configured to locate errors in the plurality of data bits based on the plurality of parity sub-bits.

8. An error correction code (ECC) circuit, comprising: A multiplexer configured to receive multiple data bits, and to provide a first portion of the multiple data bits as a pump position at a first time and to provide a second portion of the multiple data bits as a pump position at a second time after the first time; A logic tree configured to provide initial parity bits based on pump positions; as well as A logic gate, separate from the logic tree and configured to generate a parity bit based on a first preliminary parity bit of a first portion of the plurality of data bits and a second preliminary parity bit of a second portion of the plurality of data bits, wherein the first preliminary parity bit is generated based on the logic tree and the second preliminary parity bit is generated based on the same logic tree.

9. The ECC circuit according to claim 8, further comprising: A second multiplexer is configured to receive the pump position and provide a first half of the input bit at the first time and a second half of the pump position at the second time. as well as A second logic tree is configured to provide another preliminary parity bit based on the first half or the second half of the pump position received from the second multiplexer, wherein the second parity bit is based on the other preliminary parity bit.

10. The ECC circuit according to claim 9, further comprising: A third multiplexer is configured to receive the pump position and provide the second half of the pump position at the first time and the first half of the pump position at the second time. as well as A third logic tree is configured to provide additional preliminary parity bits based on the first or second half of the pump position received from the third multiplexer, wherein the third parity bit is based on the additional preliminary parity bits.

11. The ECC circuit of claim 8, further comprising a latch configured to latch the first preliminary parity bit after the first time, wherein the logic gate is configured to generate the parity bit based on the second preliminary parity bit and the first preliminary parity bit stored in the latch.

12. The ECC circuit of claim 8, further comprising a second logic gate configured to generate a parity bit based on the parity bit and the read parity bit as part of a read operation.

13. The ECC circuit of claim 8, wherein the multiplexer is further configured to provide a third portion of the plurality of data bits as the pump position at a third time after the second time, and to provide a fourth portion of the plurality of data bits as the pump position at a fourth time after the third time, and The logic gate is configured to generate the parity bit based on the first preliminary parity bit, the second preliminary parity bit, the third preliminary parity bit based on the third portion of the plurality of data bits, and the fourth preliminary parity bit based on the fourth portion of the plurality of data bits.

14. The ECC circuit of claim 13, further comprising: A first latch is configured to store the first preliminary parity bit; A second latch is configured to store the second preliminary parity bit; as well as A third latch is configured to store the third preliminary parity bit.

15. A method for use in a semiconductor device, the method comprising: Divide multiple data bits into a first part and a second part; The first preliminary parity check bit is generated based on the first part using a logic tree at the first time. At a second time following the first time, a second preliminary parity bit is generated based on the second part using the same logic tree; and The first preliminary parity bit and the second preliminary parity bit are combined using corresponding gates that are separate from the logic tree to generate a parity bit.

16. The method of claim 15, further comprising: The plurality of data bits are divided into a first part, a second part, a third part, and a fourth part; A third preliminary parity bit is generated based on the third part at a third time following the second time. A fourth preliminary parity bit is generated based on the fourth portion at a fourth time following the third time; and The first, second, third, and fourth preliminary parity bits are combined to generate the parity bit.

17. The method of claim 15, further comprising: As part of the read operation, the plurality of data bits and the plurality of read parity bits are read from the memory array; The plurality of parity bits are combined with the plurality of data bits to generate a parity sub-bit; as well as Errors in the plurality of data bits are corrected based on the check bit.

18. The method of claim 15, further comprising latching the first preliminary parity bit after the first time.

19. The method of claim 15, further comprising: A third preliminary parity check bit is generated based on the first half of the first part; A fourth preliminary parity check bit is generated based on the second half of the first part; as well as The third preliminary parity bit and the fourth preliminary parity bit are combined to generate the second parity bit.

20. The method of claim 15, further comprising writing the plurality of data bits and the parity bit into the memory array as part of a write operation.

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