An aging test system for TSV reconstructed stacked memory

Abstract

The present invention discloses an aging test system for TSV reconstructed stacked memory, comprising a test fixture, a PCB board, and a drive circuit. The test fixture is fixed to the PCB board and is used to clamp the device under test, which is electrically connected to the PCB board. A heating device is provided on the top of the device under test. A temperature sensor is provided at the bottom of the device under test, which is electrically connected to the PCB board. The drive circuit is provided on the PCB board, and the circuit of the device under test is electrically connected to the drive circuit. A through hole is provided in the center of the PCB board at the bottom of the test fixture. A reinforcing plate is fixed to the bottom of the PCB board. A groove is provided in the center of the reinforcing plate. A spring is provided inside the groove, and a temperature sensor is provided on the top of the spring. This solves the problem of long-line signal transmission delay, increases the operating frequency, improves aging efficiency, and controls aging costs.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor integrated circuit aging test, and in particular to an aging test system for TSV reconstructed stacked memory. Background Art

[0002] With the rapid development of electronic technology, improvements in memory chip design capabilities, and advancements in manufacturing processes, memory chip speeds continue to increase. Three-dimensional assembly, exemplified by 3D packaging technology, has significantly increased memory capacity. To ensure the operational reliability of memory chips, aging screening is gaining increasing attention, and research on aging test methods is burgeoning. With recent shifts in the concept of dynamic aging, running functional tests at full speed in high-temperature aging environments has become a major technical challenge.

[0003] Traditional standard burn-in test equipment utilizes a driver board + burn-in board design. The driver board is placed at the back of the burn-in chamber and operates at room temperature, while the burn-in board is installed inside the chamber and withstands high temperatures. The driver board and burn-in board are electrically connected via a through-chamber connector. This traditional burn-in test system is designed for the burn-in of discrete and power circuits, resulting in low performance and inability to meet the dynamic burn-in requirements of high-speed memory. Driven by the growing demand for localization and military applications, dynamic burn-in test methods for high-speed memory are currently a hot topic of research.

[0004] Currently, due to the limited number of interface signals in traditional burn-in test equipment, a non-standard customized burn-in test method is often used. Specifically, both the driver board and the burn-in board are specially customized. The burn-in board is placed freely in a high-temperature drying oven, while the driver board is placed outside the oven, and the two boards are connected by a cable. This structure overcomes the limited number of interface signals in traditional standard burn-in test chambers, but due to the long transmission cables, it is still difficult to achieve full speed operation, and usually operates at a frequency of tens of MHz.

[0005] Existing traditional aging test systems are limited by the number of signals, connector selection, and wiring conditions of the through-cabin connection system. Signals can usually only operate within 20MHz, which seriously fails to meet the dynamic aging requirements of hundreds of megabytes of current high-speed interface memories represented by DDR3, DDR4, and NAND FLASH.

[0006] The use of non-standard customized aging systems is limited by long cable transmission lines. The main problem is large signal transmission delays that exceed the memory timing margin. Secondly, during long-line transmission, signal edge overshoot and reflections cause signal quality to deteriorate, making it difficult to operate at high frequencies. Finally, memory interfaces represented by DDR3 and DDR4 have many signals, requiring a large number of cable cores, making connection extremely inconvenient. Usually, only single-system one-to-one aging can be achieved.

[0007] In summary, traditional aging equipment has the disadvantages of low operating frequency and small number of signals, and the long cable transmission of non-standard customized aging systems leads to large signal delay, low operating frequency and low aging efficiency. Summary of the Invention

[0008] In order to solve the problems existing in the prior art, the present invention provides an aging test system for TSV reconstructed stacked memory to solve the problem of long-line signal transmission delay, increase the operating frequency, improve the aging efficiency, and control the aging cost.

[0009] To achieve the above object, the present invention provides the following technical solutions:

[0010] An aging test system for TSV reconstructed stacked memory, including a test fixture, a PCB board and a drive circuit;

[0011] The test fixture is fixed on the PCB board, and the test fixture is used to clamp the device under test. The device under test is electrically connected to the PCB board, and a heating device is provided on the top of the device under test;

[0012] A temperature sensor is provided at the bottom of the device under test, and the temperature sensor is electrically connected to the PCB board; the driving circuit is provided on the PCB board, and the circuit of the device under test is electrically connected to the driving circuit.

[0013] Preferably, a through hole is opened in the center of the PCB board at the bottom of the test fixture, a reinforcing plate is fixed to the bottom of the PCB board, a groove is provided in the center of the reinforcing plate, a spring is provided inside the groove, and a temperature sensor is provided on the top of the spring.

[0014] Preferably, the reinforcement plate is fixed to the PCB board by screws.

[0015] Preferably, the temperature sensor is electrically connected to the connector via an electric wire, and the connector is electrically connected to the PCB board.

[0016] Preferably, the driving circuit is FPGA.

[0017] Preferably, the driving circuit is arranged at the center of the PCB board, the number of the test fixtures is four, and the four test fixture arrays are arranged outside the driving circuit.

[0018] Preferably, the test fixture includes a cover plate, a rotating handle, a thread, a pressing block, a heating rod, an electric wire, a spring pin seat, and a spring pin;

[0019] The top of the cover plate is provided with a through hole, the through hole is provided with a thread, and the rotary handle passes through the through hole and is threadedly connected to the cover plate; the bottom of the rotary handle is connected to a pressing block, and a heating component is provided inside the pressing block;

[0020] A spring pin holder is fixed to the bottom of the cover plate, a spring pin is arranged inside the spring pin holder, the bottom of the spring pin is connected to the PCB board, and the device under test is electrically connected to the PCB board through the spring pin.

[0021] Furthermore, the heating component includes a heating rod and an electric wire. The heating rod is arranged inside the pressing block, and the heating rod is connected to the power supply through the electric wire.

[0022] Furthermore, a high-temperature organic sheet is provided at the bottom of the pressing block.

[0023] Preferably, the test fixture is electrically connected to the connector via a power supply cable, and the connector is connected to the PCB power supply circuit.

[0024] Compared with the prior art, the present invention has the following beneficial technical effects:

[0025] The present invention provides an aging test system for TSV reconstructed stacked memory. By arranging a driver and a circuit under test on the same PCB board, the memory under test can be operated at the highest operating speed, realizing the combination of testing and aging, and achieving true dynamic aging. The aging board has a compact structure and can achieve one-to-four aging in a single board size of about 200mm×200mm, occupying a small space and making aging more economical. The system can be operated independently of the aging box and adopts a solution of local heating of the circuit under test, with precise temperature control, low energy consumption, low equipment dependence, and other peripheral components and PCBs not being subjected to high-temperature environments. Fewer optional circuit requirements are required, the design is more universal, and the cost of the entire aging system is lower. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 This is a schematic structural diagram of an aging test system for TSV reconstructed stacked memory according to the present invention;

[0027] Figure 2 Schematic diagram of the memory structure processed based on TSV reconstruction stacking process;

[0028] Figure 3 This is a schematic diagram of the TSV stacked memory aging test fixture structure;

[0029] Figure 4 This is a schematic structural diagram of an aging test system for TSV reconstructed stacked memory according to the present invention;

[0030] In the accompanying drawings: 1 is a cover; 2 is a rotary handle; 3 is a thread; 4 is a pressure block; 5 is a heating rod; 6 is an electric wire; 7 is a high-temperature organic thin film material; 8 is a device under test; 9 is a spring pin holder; 10 is a spring pin; 11 is a test fixture; 12 is a PCB board; 13 is a reinforcement plate; 14 is a screw; 15 is a temperature sensor; 16 is a spring; 17 is a connector; 18 is an electric wire; 19 is a power supply cable; 20 is a drive circuit; 21 is a TSV silicon substrate; 22 is an interlayer solder ball; 23 is a memory bare core; 24 is a filling glue; 25 is an external PAD. DETAILED DESCRIPTION

[0031] The present invention will be further described in detail below with reference to specific embodiments, which are intended to explain the present invention rather than to limit it.

[0032] The test principle referred to in this invention includes two aspects: electrical principle and temperature control principle. Figure 1 As shown, the present invention adopts a one-to-four design in terms of electrical design, that is, one driver circuit drives four memory circuits under test. The driver circuit uses an FPGA with a large number of IOs, high interface performance, and programmable characteristics. The four memory circuits under test use independent interfaces to ensure full-speed function operation.

[0033] In this invention, four independent control logic blocks are integrated within the FPGA to independently control the power supply and drive the circuits under test at four test stations. Each test station is designed with a 64-bit control bus and a 72-bit data bus. The memory control circuit is integrated in an IP format. Test patterns are sent to the FPGA from the host computer via the communication port, and the FPGA's top-level control logic is responsible for loading test vectors.

[0034] Memory structures processed based on TSV reconstruction stacking process such as Figure 2 As shown, in this TSV stacked memory structure, the TSV silicon substrate 21 is 200 μm thick and primarily made of silicon; the interlayer solder balls 22 are approximately 50 μm high and primarily made of a lead-tin alloy; the memory die 23 embedded within the TSV substrate is primarily made of silicon; the filler 24 between the different silicon substrates is primarily made of epoxy; and the TSV stacked memory has an external PAD 25. As can be seen from this structure, the primary material of this stacked memory is silicon. Due to the high thermal conductivity of silicon itself, the height between silicon layers is very small (typically 50 μm), and the presence of epoxy filler and solder balls results in a very low overall thermal resistance and uniform temperature distribution. To address this thermal characteristic of this memory, the present invention proposes a method of top-surface heating and bottom-surface temperature measurement. The temperature at the center of the bottom surface of the memory is used as the overall operating temperature of the memory. By measuring this temperature point and using it as a temperature control parameter, the heating power of the top-surface heating element is controlled, thereby ensuring that the entire memory operates within a certain temperature range and achieving high temperature accuracy.

[0035] like Figure 3 As shown, the TSV stacked memory aging test fixture structure of the present invention includes a cover plate 1, a rotating handle 2, a thread 3, a pressing block 4, a heating rod 5, a wire 6, a high-temperature organic sheet 7, a device under test 8, a spring pin seat 9 and a spring pin 10.

[0036] A through hole is provided on the top of the cover plate 1, and a thread 3 is provided on the through hole. The rotating handle 2 passes through the through hole and is threadedly connected to the cover plate 1; the bottom of the rotating handle 2 is connected to a pressing block 4, and a heating component is provided inside the pressing block 4.

[0037] The bottom of the cover 1 is fixed to the spring pin holder 9 by a snap-fit ​​structure. A spring pin 10 is provided inside the spring pin holder 9. The bottom of the spring pin 10 is connected to the PCB board 12. The device under test 8 is electrically connected to the PCB board 12 through the spring pin 10.

[0038] The heating component includes a heating rod 5 and an electric wire 6 . The heating rod 5 is arranged inside the pressing block 4 , and the heating rod 5 is connected to a power supply through the electric wire 6 .

[0039] The vertical movement of the pressure block 4 is controlled by rotating the handle 2. The pressure block 4 is made of metal, typically copper, and has a heater rod 5 embedded within it. Electrical power is supplied to the heater rod 5 via a wire 6, generating heat. The LTCC substrate 5 utilizes multiple layers of copper as the metal wiring layer, sintered at low temperatures. A high-temperature organic sheet 7 is located at the bottom of the pressure block 4. This acts as a buffer to protect the device under test and stabilize the temperature. The device under test 8 is placed on a pogo pin holder 9, which is a square-shaped structure with a hollow center, exposing the center of the bottom surface of the device under test. The device under test 8 is electrically connected to the PCB 12 via pogo pins 10.

[0040] like Figure 4 As shown, an aging test system for TSV reconstructed stacked memory includes a test fixture 11, a PCB board 12 and a driving circuit 20.

[0041] The test fixture 11 is fixed on the PCB board 12. The test fixture 11 is used to clamp the device under test 8. The device under test 8 is electrically connected to the PCB board 12. A heating device is provided on the top of the device under test 8.

[0042] A temperature sensor 15 is provided at the bottom of the device under test 8 , and the temperature sensor 15 is electrically connected to the PCB board 12 ; a driving circuit 20 is provided on the PCB board 12 , and the circuit of the device under test 8 is electrically connected to the driving circuit 20 .

[0043] In this aging system, the test fixture 11 is fixed to the PCB using positioning pins and connected to the PCB power supply circuit via a connector 17 and a power supply cable 19. The PCB board 12 has a window at the center of the test fixture's abdomen. The reinforcement plate 13 is connected to the PCB board 12 via screws 14. The temperature sensor 15 is fixed inside the reinforcement plate 13 via a spring 16 and is electrically connected to the PCB board 12 via a wire 18 and a connector 17. The drive circuit 20 is an FPGA and is placed at the center of the PCB board 12.

[0044] Designed on PCB 12, the temperature measurement circuit, heating drive circuit, and temperature control MCU enable precise control of each workstation through a temperature control algorithm running in the MCU. Furthermore, the MCU receives commands from the host computer to set the temperature and transmits the current operating temperature in real time. This MCU-based temperature control method utilizes heating from a top test fixture and sampling from a bottom temperature sensor.

[0045] The test fixture structure has a heating rod embedded in the internal pressing block, a sampling organic board transition under the pressing block, a hollowed-out bottom center of the socket, and a test fixture structure with a temperature sensor embedded in the reinforcement board; the FPGA is centered on the aging board structure, with four test fixtures distributed around it, and the test fixture heating wires and sensor wires are connected to the PCB through connectors.

[0046] In the present invention, by arranging the driver and the circuit under test on the same PCB board, the memory under test can be operated at the highest operating speed, realizing the combination of testing and aging, and achieving true dynamic aging.

[0047] The aging board has a compact structure and can realize one-to-four aging in a single board size of about 200mm×200mm, which takes up little space and makes aging more economical.

[0048] It operates independently of the aging chamber and adopts a solution of local heating of the circuit under test. It has precise temperature control, low energy consumption, low equipment dependence, and other peripheral components and PCBs are not subjected to high temperature environment. There are fewer requirements for optional circuits, the design is more universal, and the cost of the entire aging system is lower.

Claims

1. An aging test system for TSV reconstructed stacked memory, characterized in that: It includes a test fixture (11), a PCB board (12) and a drive circuit (20); The test fixture (11) is fixed on the PCB board (12), and the test fixture (11) is used to clamp the device under test (8). The device under test (8) is electrically connected to the PCB board (12), and a heating device is provided on the top of the device under test (8); A through hole is provided at the center of the PCB board (12) at the bottom of the test fixture (11); a reinforcing plate (13) is fixed to the bottom of the PCB board (12); a groove is provided at the center of the reinforcing plate (13); a spring (16) is provided inside the groove; and a temperature sensor (15) is provided on the top of the spring (16); The test fixture (11) comprises a cover plate (1), a rotating handle (2), a thread (3), a pressing block (4), a heating rod (5), an electric wire (6), a spring pin seat (9), and a spring pin (10); The top of the cover plate (1) is provided with a through hole, the through hole is provided with a thread (3), and the rotary handle (2) passes through the through hole and is threadedly connected to the cover plate (1); the bottom of the rotary handle (2) is connected to a pressing block (4), and a heating component is provided inside the pressing block (4); A spring pin seat (9) is fixed to the bottom of the cover plate (1), a spring pin (10) is provided inside the spring pin seat (9), the bottom of the spring pin (10) is connected to the PCB board (12), and the device under test (8) is electrically connected to the PCB board (12) via the spring pin (10); A high-temperature organic sheet (7) is provided at the bottom of the pressing block (4); A temperature sensor (15) is provided at the bottom of the device under test (8), and the temperature sensor (15) is electrically connected to the PCB board (12); the drive circuit (20) is provided on the PCB board (12), and the circuit of the device under test (8) is electrically connected to the drive circuit (20).

2. The burn-in test system for TSV reconstructed stacked memory according to claim 1, characterized in that: The reinforcing plate (13) is fixed on the PCB board (12) by means of screws (14).

3. The burn-in test system for TSV reconstructed stacked memory according to claim 1, characterized in that: The temperature sensor (15) is electrically connected to the connector (17) via an electric wire (18), and the connector (17) is electrically connected to the PCB board (12).

4. The burn-in test system for TSV reconstructed stacked memory according to claim 1, characterized in that: The driving circuit (20) is an FPGA.

5. The burn-in test system for TSV reconstructed stacked memory according to claim 1, characterized in that: The driving circuit (20) is arranged at the center of the PCB board (12), the number of the test fixtures (11) is four, and the four test fixtures (11) are arranged in an array outside the driving circuit (20).

6. The burn-in test system for TSV reconstructed stacked memory according to claim 1, characterized in that: The heating component comprises a heating rod (5) and an electric wire (6). The heating rod (5) is arranged inside the pressing block (4), and the heating rod (5) is connected to a power supply via the electric wire (6).

7. The burn-in test system for TSV reconstructed stacked memory according to claim 1, characterized in that: The test fixture (11) is electrically connected to the connector (17) via a power supply cable (19), and the connector (17) is connected to a PCB power supply circuit.

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