A low power consumption clock amplifier circuit
By introducing a switching circuit and enable signal generator into the clock amplifier circuit, the clock amplifier is controlled to operate only on the rising and falling edge of the input signal. Combined with a high-pass filter, the problem of high power consumption of traditional clock amplifiers is solved and low power consumption is achieved and good noise performance.
Patent Information
- Application Number
- CN202210662215.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-06-13
- Publication Date
- 2024-12-31
- Estimated Expiration
- 2042-06-13
AI Technical Summary
Traditional reference clock amplifiers consume a lot of power and cannot be used in low-power fields, and solutions that damage noise performance when reducing power consumption are not economical and practical.
A low-power clock amplifier circuit is designed, using a switching circuit and an enable signal generator. The main clock amplifier is controlled to operate only on the rising and falling edge of the input signal through the enable signal, and the AC coupling of the signal is achieved in combination with a high-pass filter. The different intensities of PMOS and NMOS tubes generate signals with different duty cycles, reducing unnecessary power consumption.
While keeping the noise performance of the clock amplifier unchanged, the power consumption of the clock amplifier is greatly reduced, and is suitable for clock circuits, significantly reducing the power consumption of the circuit.
Smart Images
Figure CN114944834B_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the field of electronic circuits, and in particular to a low-power consumption clock amplifier circuit. Background Art
[0002] Traditional reference clock amplifiers are usually implemented using AC-coupled inverters. To achieve better noise performance, it is often necessary to increase the power consumption of the clock amplifier. The power consumption of reference clock amplifiers using traditional structures is usually relatively large and cannot be used in the field of low power consumption. In addition, the performance of reference clock amplifiers with traditional structures is very sensitive to the amplitude of the input signal. A small amplitude input clock signal will cause the power consumption of the clock amplifier to increase significantly. In recent years, there have also been some structures of low-power clock amplifiers, but these structures achieve low power consumption at the expense of the noise performance of the clock amplifier, so they are not an economical and practical solution. Summary of the invention
[0003] In view of the deficiencies in the prior art, the present invention realizes a low-power clock amplifier circuit, which reduces the power consumption of the clock amplifier while keeping the performance of the clock amplifier substantially unchanged.
[0004] The purpose of the present invention is achieved through the following technical solutions:
[0005] A low-power clock amplifier circuit, the clock amplifier circuit comprising a main clock amplifier, a switch circuit, and an enable signal generator;
[0006] The master clock amplifier comprises a reference clock input terminal inp, a reference clock input terminal outn, a positive power supply port vddp and a negative power supply port vddn;
[0007] The switch circuit includes a PMOS tube and an NMOS tube; the switch circuit enables and shuts down the main clock amplifier;
[0008] The enable signal generator includes an input terminal in, a positive phase output terminal swp and a negative phase output terminal swn; the enable signal generator is capable of generating an enable control signal that enables the main clock amplifier to work only during a certain part of the input signal;
[0009] The reference signal is simultaneously input to the input terminal inp of the enable signal generator and the input terminal in of the main clock amplifier; the inverting output terminal swn of the enable signal generator is connected to the gate terminal of the NMOS of the switch circuit, and the positive output terminal swp of the enable signal generator is connected to the gate terminal of the PMOS of the switch circuit;
[0010] in,
[0011] The source end of the NMOS tube of the switch circuit is connected to the inverting power port vddn of the main clock amplifier, and the source end of the PMOS tube of the switch circuit is connected to the positive power port vddp of the main clock amplifier;
[0012] Alternatively, the drain end of the NMOS tube of the switch circuit is connected to the inverting power port vddn of the main clock amplifier, and the drain end of the PMOS tube of the switch circuit is connected to the positive power port vddp of the main clock amplifier.
[0013] Furthermore, the enable signal generator includes two NMOS tubes and two PMOS tubes, which are connected in an inverter manner, wherein the strengths of the NMOS tubes and the PMOS tubes are different, and respectively generate a signal sw_n with a duty cycle greater than 50% and a signal sw_p with a duty cycle less than 50%.
[0014] Furthermore, the clock amplifier circuit also includes a high-pass filter, which can realize AC coupling of the signal. The reference signal is filtered by the high-pass filter and then input to the input terminal inp of the enable signal generator and the input terminal in of the main clock amplifier.
[0015] Furthermore, the clock amplifier circuit is implemented by a triode.
[0016] The beneficial effects of the present invention are as follows:
[0017] The low-power clock amplifier of the present invention can greatly reduce the power consumption of the clock amplifier circuit while keeping the noise performance of the reference clock amplifier basically unchanged. The present invention can be widely used in clock circuits and can greatly reduce the power consumption of the clock amplifier. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Figure 1 Schematic diagram of the clock amplifier circuit of the present invention; wherein, Figures (a) and (b) are two different connection modes of the switch circuit and the main clock amplifier; Figures (c) and (d) are schematic diagrams of Figures (a) and (b) with high-pass filters added.
[0019] Figure 2 This is the circuit diagram of the enable signal generator.
[0020] Figure 3 Figure 2 is the voltage and current waveform of a traditional clock amplifier.
[0021] Figure 4 It is a schematic diagram of the voltage and current waveform of the present invention. DETAILED DESCRIPTION
[0022] The present invention will be described in detail below based on the accompanying drawings and preferred embodiments, and the purpose and effects of the present invention will become more clear. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.
[0023] like Figure 1 As shown, the low-power clock amplifier circuit of the present invention includes a high-pass filter, an enable signal generator, a switching circuit and a main clock amplifier. As one embodiment, the clock amplifier circuit of the present invention can be implemented by a triode. The high-pass filter is capable of realizing AC coupling of the signal. The reference signal is filtered by the high-pass filter and input to the input terminal inp of the enable signal generator and the input terminal in of the main clock amplifier, thereby avoiding the influence of the common mode level of the previous stage circuit on the present invention. However, if the common mode level of the previous stage circuit is consistent with the common mode level of the present invention, the high-pass filter is not necessary. The common mode electrical frequency Vbias of the high-pass filter is generally half the power supply voltage, but it can also be another bias level.
[0024] The main amplifier can be switched by the PM circuit SW / NM SW The main amplifier is mainly composed of an amplifier based on an inverter structure (PM 1 / NM 1 ). The master clock amplifier includes a reference clock input terminal inp, a reference clock input terminal outn, a positive power supply port vddp and a negative power supply port vddn; the switch circuit includes a PMOS tube and an NMOS tube; the switch circuit enables and shuts down the master clock amplifier; the enable signal generator includes an input terminal in, a positive output terminal swp and a negative output terminal swn; the enable signal generator is an enable control signal that can generate an enable control signal that enables the master clock amplifier to work only during a certain part of the input signal; the reference signal is simultaneously input to the input terminal inp of the enable signal generator and the input terminal in of the master clock amplifier; the negative output terminal swn of the enable signal generator is connected to the gate terminal of the NMOS of the switch circuit, and the positive output terminal swp of the enable signal generator is connected to the gate terminal of the PMOS of the switch circuit. Among them, the source end of the NMOS tube of the switching circuit is connected to the inverting power port vddn of the main clock amplifier, and the source end of the PMOS tube of the switching circuit is connected to the positive power port vddp of the main clock amplifier; or, the drain end of the NMOS tube of the switching circuit is connected to the inverting power port vddn of the main clock amplifier, and the drain end of the PMOS tube of the switching circuit is connected to the positive power port vddp of the main clock amplifier.
[0025] Since the noise of the clock amplifier mainly contributes to the rising and falling edges of the output signal, the clock amplifier is enabled by generating an enable signal through an enable signal generator, so that the clock amplifier only works at the rising and falling edges of the input signal, thus avoiding the waste of power consumption of the clock amplifier.
[0026] Enable signal generator circuit as Figure 2 As shown, the enable signal generator includes two NMOS tubes and two PMOS tubes, which are connected in an inverter manner. The strengths of the NMOS tubes and the PMOS tubes are different, and they respectively generate a signal sw_n with a duty cycle greater than 50% and a signal sw_p with a duty cycle less than 50%. The main function of the enable signal generator is to generate an enable signal that enables the clock amplifier to work only on the rising and falling edges of the input signal. In the present invention, the PM in the enable signal generator can be adjusted. swp / NM swp and PM swn / NM swn The enable signal generator is only used to generate a signal to enable the main clock amplifier, so the noise of the enable signal amplifier has little effect on the noise performance of the clock amplifier. This can reduce the size of the enable signal generator to be much smaller than the size of the main clock amplifier, that is, use a tube type with a higher threshold voltage and a smaller W / L to achieve lower power consumption. Figure 2 PM swp / NM swp The intensity ratio is less than one, PM swn / NM swn The intensity ratio is greater than one, thereby generating a signal sw_n with a duty cycle greater than 50% and a signal sw_p with a duty cycle less than 50%. The specific value can be adjusted according to the amplitude of the input signal and the process, etc. to further adjust the pulse width of the enable signal generator.
[0027] The voltage and current waveforms of traditional clock amplifiers are as follows: Figure 3 As shown, the conventional clock amplifier still consumes power even if the output signal of the clock amplifier has reached the power supply voltage or a low level, which results in a large part of the power consumption of the conventional clock amplifier being wasted.
[0028] The voltage waveforms of each node of the clock amplifier of the present invention and the current waveform of the clock amplifier are as follows: Figure 4As shown in the figure, sw_eq represents an equivalent enable signal, and sw_eq only becomes high level at the rising and falling edges of the clock. Therefore, the clock amplifier only works at the rising and falling edges of the input signal, thus avoiding the waste of power consumption of the clock amplifier. totalcurrent represents the power consumption of the clock amplifier. It can be seen that the power consumption is used to the best effect. Current is consumed only when it is useful for improving circuit performance, and there is basically no current consumption at other times.
[0029] Those skilled in the art can understand that the above are only preferred examples of the invention and are not intended to limit the invention. Although the invention is described in detail with reference to the above examples, those skilled in the art can still modify the technical solutions recorded in the above examples or replace some of the technical features therein with equivalents. Any modification, equivalent replacement, etc. made within the spirit and principle of the invention shall be included in the protection scope of the invention.
Claims
1. A low power consumption clock amplifier circuit, characterized in that: The clock amplifier circuit includes a main clock amplifier, a switch circuit, and an enable signal generator; The master clock amplifier comprises a reference clock input terminal inp, a reference clock input terminal outn, a positive power supply port vddp and a negative power supply port vddn; The switch circuit includes a PMOS tube and an NMOS tube; the switch circuit enables and shuts down the main clock amplifier; The enable signal generator comprises an input terminal in, a positive phase output terminal swp and a negative phase output terminal swn; the enable signal generator is capable of generating an enable control signal that enables the main clock amplifier to work only during a certain part of the input signal; The reference signal is simultaneously input to the input terminal inp of the enable signal generator and the input terminal in of the main clock amplifier; the inverting output terminal swn of the enable signal generator is connected to the gate terminal of the NMOS of the switch circuit, and the positive output terminal swp of the enable signal generator is connected to the gate terminal of the PMOS of the switch circuit; Wherein, the source end of the NMOS tube of the switch circuit is connected to the inverting power port vddn of the main clock amplifier, and the source end of the PMOS tube of the switch circuit is connected to the positive power port vddp of the main clock amplifier; Alternatively, the drain end of the NMOS tube of the switch circuit is connected to the inverting power port vddn of the main clock amplifier, and the drain end of the PMOS tube of the switch circuit is connected to the positive power port vddp of the main clock amplifier.
2. The low power consumption clock amplifier circuit according to claim 1, characterized in that: The enable signal generator includes two NMOS tubes and two PMOS tubes, which are connected in an inverter manner. The NMOS tubes and the PMOS tubes have different strengths and respectively generate a signal sw_n with a duty cycle greater than 50% and a signal sw_p with a duty cycle less than 50%.
3. The low power consumption clock amplifier circuit according to claim 1, characterized in that: The clock amplifier circuit also includes a high-pass filter, which can realize AC coupling of the signal. The reference signal is filtered by the high-pass filter and then input to the input terminal inp of the enable signal generator and the input terminal in of the main clock amplifier.
4. The low power consumption clock amplifier circuit according to claim 1, characterized in that: The clock amplifier circuit is implemented by a triode.