Method for selecting a photolithography process and semiconductor processing system

Abstract

A semiconductor processing system includes a first photolithography system and a second photolithography system. The semiconductor processing system includes a layout database storing a plurality of layouts representing features to be formed in a wafer. The semiconductor processing system includes a layout analyzer that analyzes the layouts and selects the first photolithography system or the second photolithography system based on the dimensions of the features in the layouts.

Description

Technical Field

[0001] Embodiments of the present application relate to systems and methods for selecting a photolithography process and a semiconductor processing system. Background Art

[0002] There is a constant demand for increased computing power in electronic devices, including smartphones, tablets, desktop computers, laptops, and many other types of electronic devices. Integrated circuits provide the computing power for these electronic devices. One way to increase computing power in integrated circuits is to increase the number of transistors and other integrated circuit components that can be included in a given area of ​​a semiconductor substrate. One way to increase the density of transistors formed in a given area is to reduce the size of the transistor components and the size of the corresponding interconnect structures associated with the transistors.

[0003] The photolithography process is used to pattern the layers of a semiconductor wafer according to the features to be formed in the semiconductor wafer. The size of the features that can be formed at the later end is affected by the type of photolithography process used. Various types of photolithography systems can be used to perform the photolithography process. Summary of the Invention

[0004] In some embodiments, a method for selecting a lithography process includes storing layout data associated with a layout of a wafer and extracting feature data representing dimensions associated with features of the layout from the layout. The method includes comparing the feature data with a selection rule and selecting the layout between an EUV lithography process and a non-EUV lithography process based on the feature data and the selection rule.

[0005] In some embodiments, a method for selecting a lithography process includes storing a plurality of layouts in a layout database, each layout corresponding to a respective stage of semiconductor processing, and retrieving selection rule data including selection rules for selecting between a first lithography system and a second lithography system. The method includes extracting feature data associated with each layout, analyzing the feature data for each layout using the selection rule data, and selecting the first lithography system or the second lithography system for each layout based on the analysis of the feature data using the selection rule data.

[0006] In some embodiments, a semiconductor processing system includes a first lithography system and a second lithography system. The system includes a layout database and a layout analyzer, wherein the layout database includes a plurality of layouts, each layout representing a feature to be formed in a wafer, and the layout analyzer is configured to extract layout feature data from each layout, compare the feature data for each layout with a selection rule, and select the first lithography system or the second lithography system for each layout based on the feature data and the selection rule data. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When with Figure 1When read together, various aspects of the present disclosure can be best understood from the following detailed description. It is worth noting that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 is a block diagram of a semiconductor processing system according to some embodiments.

[0009] Figure 2A-2F is a cross-sectional view of a wafer at an intermediate stage of processing according to some embodiments.

[0010] Figure 3-Figure 6 is a top view of a layout associated with a wafer according to some embodiments.

[0011] Figure 7 is a cross-sectional view of a wafer according to some embodiments.

[0012] Figure 8 is a flow chart of a process for processing a wafer according to some embodiments.

[0013] Figure 9 is a flow chart of a process for processing a wafer according to some embodiments. DETAILED DESCRIPTION

[0014] In the following description, a number of thicknesses and materials are described for various layers and structures within the integrated circuit die. For various embodiments, specific dimensions and materials are given by way of example. Based on this disclosure, those skilled in the art will recognize that other dimensions and materials can be used in many cases without departing from the scope of this disclosure.

[0015] The following disclosure provides many different embodiments or examples for implementing different components of the described subject matter. Specific examples of components and arrangements are described below to simplify this description. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, forming a first component above or on a second component may include an embodiment in which the first and second components are formed to be in direct contact, and may also include an embodiment in which an additional component may be formed between the first and second components so that the first and second components may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not, in itself, represent a relationship between the various embodiments and / or configurations discussed.

[0016] Additionally, to facilitate description of one element or component relative to another element or component as illustrated in the figures, spatially relative terms such as "lower," "beneath," "beneath," "above," and "over" may be used herein. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0017] In the following description, certain specific details are set forth in order to provide a thorough understanding of the various embodiments of the present disclosure. However, those skilled in the art will appreciate that the present disclosure can be practiced without these specific details. In other cases, well-known structures associated with electronic components and manufacturing techniques have not been described in detail to avoid unnecessarily obscuring the description of the embodiments of the present disclosure.

[0018] Unless the context requires otherwise, throughout this specification and the claims that follow, the word "comprise" and variations such as "including" and "comprising" are to be interpreted in an open, inclusive sense, i.e., as "including but not limited to."

[0019] The use of ordinal numbers such as first, second, and third does not necessarily imply a sense of order in ranking, but may simply distinguish between multiple instances of an action or structure.

[0020] References throughout this specification to "some embodiments" or "one embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least some of the embodiments. Thus, appearances of the phrases "in some embodiments," "in one embodiment," or "in some embodiments" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0021] As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the content clearly dictates otherwise. It should also be noted that the term "or" is generally employed in its sense including "and / or" unless the content clearly dictates otherwise.

[0022] Embodiments of the present disclosure provide a semiconductor processing system that selects between different types of photolithography processes for each of a plurality of layouts for processing a semiconductor wafer. The semiconductor processing system includes a layout database and a layout analyzer. The layout database includes layout data associated with each photolithography mask to be used to process the semiconductor wafer. The layout analyzer analyzes the layout of features associated with each mask. The layout analyzer can analyze the distribution of critical dimensions (CDs), pitches, and other aspects associated with the layout. The layout analyzer processes the layout feature data according to selection rule data. The selection rule data determines which type of photolithography process should be used for a given layout. The layout analyzer selects a photolithography process for each layout for applying the layout to the semiconductor wafer.

[0023] Layout analysis and lithography process selection have various benefits. For example, when the layout analyzer detects very small pitch, CD, or other dimensional aspects of the layout, the layout analyzer selects the extreme ultraviolet (EUV) lithography process that can most reliably transfer the corresponding pattern to the semiconductor wafer. In the case where the layout does not include very small pitch, CD, or other dimensional aspects, the layout analyzer can select a lithography process other than EUV lithography. These other lithography processes may be well suited to transfer patterns with loose dimensional constraints. The result is that lithography resources are efficiently managed, layout features are properly and reliably transferred to the wafer, and wafer yield is improved.

[0024] Figure 1 FIG1 is a block diagram of a semiconductor processing system 100 according to some embodiments. The semiconductor processing system 100 may correspond to a system that processes a wafer 102. The semiconductor processing system 100 may ultimately cut the wafer 102 into individual integrated circuits. The semiconductor processing system 100 performs multiple semiconductor processes on the wafer 102 to form semiconductor layers, dielectric layers, conductive layers, and various other structures or components, thereby producing fully functional integrated circuits.

[0025] Semiconductor processing system 100 includes semiconductor processing equipment 104. Typically, semiconductor processing equipment 104 undergoes a number of processes during manufacturing. These processes may include thin film deposition, etching processes, dopant implantation processes, annealing processes, epitaxial growth processes, chemical mechanical planarization (CMP) processes, and other types of processes. Semiconductor processing equipment 104 includes tools and other equipment for performing semiconductor processing on wafers.

[0026] In some embodiments, the semiconductor processing equipment 104 includes a thin film deposition chamber. The thin film deposition chamber may include a chemical vapor deposition chamber, a sputtering chamber, a physical vapor deposition chamber, an atomic layer deposition chamber, a plasma enhanced vapor deposition chamber, an epitaxial growth chamber, or other types of thin film deposition chambers. Based on this disclosure, those skilled in the art will recognize that the semiconductor processing equipment 104 may include thin film deposition chambers other than those described above without departing from the scope of this disclosure.

[0027] In some embodiments, the semiconductor processing equipment 104 includes an etching chamber. The etching chamber is used to etch thin films deposited on the wafer 102. The etching chamber may include a chamber for wet etching, dry etching, plasma etching, or other types of etching processes. Etching chambers other than those described above may be used without departing from the scope of the present disclosure.

[0028] In some embodiments, semiconductor processing equipment 104 includes a dopant implantation chamber. The dopant implantation chamber may include an ion implantation chamber in which wafer 102 is bombarded with dopant ions. Dopant ions are implanted into wafer 102 according to selected parameters for the ion implantation process. The dopant implantation chamber may include dopant implantation types other than those described above without departing from the scope of the present disclosure.

[0029] The semiconductor processing equipment 104 may include equipment that assists in thin film deposition processes, etching processes, ion implantation processes, annealing processes, photolithography processes, and other types of processes. Some semiconductor processing equipment 104 may be located entirely within a semiconductor processing chamber. Some semiconductor processing equipment 104 may be located partially within the semiconductor processing chamber 102 and partially outside the semiconductor processing chamber. Some semiconductor processing equipment 104 may be located entirely outside the semiconductor processing chamber.

[0030] The semiconductor processing equipment 104 may include electrical components for generating electric fields, voltages, magnetic fields, electrical signals, or other types of electrical effects. Thus, the semiconductor processing equipment 104 may include electrodes, wires, radio frequency power supplies, transmitters, receivers, or other types of electrical devices that may be used in semiconductor processing.

[0031] The semiconductor processing equipment 104 may include equipment for managing gases or fluids within a semiconductor processing chamber. The processing equipment may include components for introducing gases or fluids into the semiconductor processing chamber, for removing gases or fluids from the semiconductor processing chamber, and for monitoring and controlling the flow, presence, or composition of gases within the processing chamber.

[0032] The semiconductor processing system 100 includes an EUV lithography system 106 and a 193i lithography system 108. Either of the lithography systems 106 and 108 can be used for various lithography patterning processes. The lithography patterning process generally includes depositing a photoresist on the surface of the wafer 102 and then exposing the photoresist to lithography light through a mask. The mask includes a pattern corresponding to the desired layout of features on a particular layer of the wafer 102 or a particular processing stage of the wafer 102. Although in many cases, either the EUV lithography system 106 or the 193i lithography system 108 can be used, in some cases, it may be more beneficial to use one over the other. This can be understood in part by a basic description of the EUV lithography system 106 and the 193i lithography system 108. Although Figure 1 An EUV lithography system 106 and a 193i lithography system 108 are shown, but the principles of the present disclosure can be extended to a first lithography system and a second lithography system different from the first lithography system.

[0033] The EUV lithography system 106 generates EUV light. As used herein, the terms "EUV light" and "EUV radiation" may be used interchangeably. In some embodiments, the EUV light has a wavelength between 10 nm and 15 nm. In one example, the EUV light has a center wavelength of 13.5 nm. In a lithography process, one of the factors that affects the size of features that can be formed in a wafer is the wavelength of the light used in the lithography process. Because EUV light has a very small wavelength, very small features can be defined on the wafer 102 using EUV light. Different EUV generation processes can provide EUV light of different wavelength ranges and different center wavelengths. Therefore, without departing from the scope of the present disclosure, the EUV light can have a different wavelength range and a different center wavelength than those described above.

[0034] The process used to generate EUV light can be very complex. In one example, the EUV lithography system 106 is a plasma pulse EUV generation system. The EUV lithography system 106 generates EUV light by passing tin droplets into an EUV generation chamber. Each droplet is illuminated by one or more precision laser pulses. The precision laser pulses generate plasma from each droplet. The plasmatized tin droplets emit EUV light with a central wavelength of 13.5 nm. The EUV light scatters and strikes a large collecting mirror. The large collecting mirror reflects the EUV light and focuses it onto an EUV scanner. The EUV scanner includes precision optics for reflecting, guiding, focusing, and conditioning the EUV light reflected from an EUV reticle or mask within the scanner. After reflecting from the EUV reticle or mask, the EUV light includes the pattern of the EUV reticle or mask. The EUV light is focused onto the wafer 102 to transfer the pattern of the reticle or mask to the photoresist layer on the wafer 102. In one example, the EUV lithography system 106 can produce a single exposure pitch as small as 28 nm.

[0035] The 193i lithography system 108 generates ultraviolet (UV) light with a central wavelength of 193 nm. UV light is light that passes through or reflects from a mask or reticle. Additional lenses and mirrors direct the light onto the wafer 102. The final lens is a layer of liquid placed over the wafer 102. The wavelength of the UV light is contracted within the liquid. This contraction of the UV light wavelength within the liquid allows for the formation of smaller pitches in the photoresist than would otherwise be possible without the aid of the liquid layer. In one example, the 193i lithography system has a minimum single-exposure resolution of 71 nm.

[0036] Semiconductor processing system 100 may use either EUV lithography system 106 or 193i lithography system 108 for each lithography process. Advantages and disadvantages of these different lithography processes will be described in more detail below and may become more relevant after describing various pattern layouts associated with processing of wafer 102.

[0037] Semiconductor processing system 100 includes a layout database 110. Layout database 110 includes multiple layouts 112. Each layout 112 represents a pattern of features to be formed in wafer 102 at a stage of processing. For example, a first layout may represent a region of a semiconductor substrate where an N-well will be formed. A second layout may represent a region of a semiconductor substrate where a P-well will be formed. A third layout 112 may represent a region where trenches will be etched to define semiconductor fins. Another layout may represent a region in a first interlayer dielectric layer where metal lines and conductive vias will be formed. Another layout may represent a region in a second interlayer dielectric layer where metal lines and conductive vias will be formed. A large number of layouts 112 may be used from the beginning to the end of processing wafer 102.

[0038] Typically, a lithography process can be associated with each layout 112. A mask or reticle can be generated for each layout 112. The mask or reticle carries the pattern of the layout 112 or a seed pattern that starts from it and realizes the layout after various semiconductor processes. The lithography process transfers the pattern of the mask or reticle to the photoresist on the wafer 102. An example of a layout is an analog graphic database system (GDS) layout, but other types or formats of layouts can also be used. The layout 112 can be generated using one or more specialized software programs for generating layouts for semiconductor processing, and a lithography mask can be generated based on the layout. As previously described, the semiconductor processing system 100 can select from the EUV lithography system 106 or the 193i lithography system 108 for each layout.

[0039] The semiconductor processing system 100 includes a layout analyzer 114. The layout analyzer 114 is configured to analyze each layout 112. The layout analyzer 114 is configured to select, for each layout 112, either the EUV lithography system 106 or the 193i lithography system 108 to perform a lithography process associated with the layout.

[0040] When layout analyzer 114 analyzes layout 112, layout analyzer 114 extracts layout feature data 116 associated with layout 112. Layout feature data 116 may include data related to the size, shape, and location of features in layout 112. Layout analyzer 114 determines whether a lithography process associated with layout 112 should be performed using EUV lithography system 106 or 193i lithography system 108 based on the layout feature data 116 extracted from layout 112 by layout analyzer 114.

[0041] In some embodiments, layout feature data 116 includes pitch data 118. Pitch data 118 includes data related to one or more pitches associated with layout 112. A pitch can correspond to the distance between similar portions of two adjacent features. For example, if layout 112 includes two adjacent metal lines, the pitch associated with the two metal lines can be the distance between an edge of the first metal line and the same edge of the second adjacent metal line.

[0042] Pitch data 118 may include pitches associated with a large number of adjacent features in layout 112. In some cases, pitch data 118 may include every pitch associated with layout 112. In other cases, pitch data 118 may include pitches associated with a sampling of features associated with layout 112. In some cases, pitch data 118 may include pitches associated with features in a selected area of ​​layout 112. In one example, layout analyzer 114 extracts pitch data 118 associated with a 5 μm×5 μm portion of layout 112, although other area values ​​may be used without departing from the scope of this disclosure.

[0043] Pitch data 118 includes a threshold pitch value. Pitch data 118 may indicate whether each pitch in layout 112 is less than the threshold pitch value. The threshold pitch value may correspond to a pitch value that is equal to or less than the minimum single exposure pitch value associated with 193i lithography system 108. Pitch data 118 may indicate the percentage of pitches in layout 112 or in a sampling area of ​​layout 112 that are less than or equal to the threshold pitch value. In the example where the minimum single exposure pitch value for 193i lithography system 108 is 71 nm, the threshold pitch value may be 71 nm. Alternatively, the threshold pitch value may be selected from a range of values ​​between 65 and 75 nm. Other threshold pitch values ​​may be used without departing from the scope of the present disclosure.

[0044] In some embodiments, layout feature data 116 includes CD data 120. CD data 120 includes data related to one or more CDs associated with layout 112. The CD associated with a feature may correspond to the smallest dimension associated with the feature. For example, if layout 112 includes a metal line with a length of 100 nm and a width of 20 nm, the CD associated with the metal line may be 20 nm, which is related to the width, because the width is the smallest lateral dimension of the metal line.

[0045] CD data 120 may include a pitch associated with a number of adjacent features in layout 112. In some cases, CD data 120 may include a CD for each feature associated with layout 112. In other cases, CD data 120 may include CD associated with a sampling of features associated with layout 112. In some cases, CD data 120 may include CD associated with features in a selected area of ​​layout 112. In one example, layout analyzer 114 extracts CD data 120 associated with a 5 μm×5 μm portion of layout 112, although other area values ​​may be used without departing from the scope of this disclosure.

[0046] In some embodiments, CD data 120 includes a threshold CD value. CD data 120 may indicate whether each CD in layout 112 is less than the threshold CD value. The threshold CD value may correspond to a CD value that is equal to or less than a minimum single-exposure CD value associated with 193i lithography system 108. CD data 120 may indicate a percentage of CDs in layout 112 or in a sampled region of layout 112 that are less than or equal to the threshold CD value.

[0047] The layout feature data 116 may also include information indicating whether there is a pitch variation between adjacent features or a CD variation between adjacent features. The layout feature data 116 may include ratios of adjacent pitches, ratios of adjacent CDs, and information indicating whether there are different CDs and different pitches associated with adjacent features.

[0048] Layout feature data 116 may also indicate the distance between corners of adjacent features. For example, in many cases, features associated with layout 112 include shapes other than rectangles, circles, oblongs, or ovals. The corners or closest points of two adjacent features may be very close together and may be much smaller than a threshold distance between them. Additionally, the corners of a single feature may be close together and may be much smaller than a threshold critical distance. Each of these factors can be used to determine whether a layout should be implemented using EUV lithography system 106 or 193i lithography system 108.

[0049] The layout feature data 116 may also include information indicating whether there is a pitch variation between adjacent features or a CD variation between adjacent features. The layout feature data 116 may include a ratio of adjacent pitches, a ratio of adjacent CDs, or information indicating whether there are different CDs and different pitches associated with adjacent features.

[0050] The layout analyzer 114 may include selection rule data 122. The selection rule data 122 may include rules or guidelines for determining whether an EUV lithography system 106 or a 193i lithography system 108 should be used to implement a particular layout 112. The layout analyzer 114 compares the layout feature data 116 with the selection rule data 122. The layout analyzer 114 determines which lithography system should be used to implement the layout based on the comparison of the selection rule data 122 with the layout feature data 116.

[0051] In some embodiments, selection rule data 122 may determine whether EUV lithography system 106 or 193i lithography system 108 should be implemented based on whether one or more pitches of layout 112 are less than a threshold pitch. In this case, if any pitch is less than the threshold pitch, layout analyzer 114 determines that EUV lithography system 106 should be used for the lithography process associated with the layout. Otherwise, 193i lithography system 108 may be used.

[0052] In some embodiments, the selection rule data 122 may determine whether the EUV lithography system 106 or the 193i lithography system 108 should be implemented based on whether the percentage of pitches less than the threshold pitch is less than the threshold percentage. For example, the threshold percentage may be between 45% and 55%. If the percentage of pitches less than the threshold pitch is less than the threshold percentage, the layout analyzer 114 may select the EUV lithography system 106 to perform the lithography process associated with the layout.

[0053] In some embodiments, the selection rule data 122 may include a rule regarding a threshold CD. If one or more CDs associated with the layout 112 are less than the threshold CD, the rule may indicate that the layout analyzer 114 should select the EUV lithography system 106 to perform the lithography process associated with the layout. In another example, if the percentage of CDs less than the threshold CD is less than a threshold percentage, the selection rule data 122 may indicate that the layout analyzer 114 should select the EUV lithography system 106 to perform the lithography process associated with the layout.

[0054] In some embodiments, the selection rule data 122 may include rules related to both pitch and CD. The selection rule data 122 may indicate that if one or more of the pitch and CD are less than their respective thresholds, then the layout analyzer 114 should select the EUV lithography system 106 to perform the lithography process associated with the layout. The selection rule data 122 may indicate that if a percentage of the pitch and a percentage of the CD are less than their respective thresholds, then the layout analyzer 114 should select the EUV lithography system 106 to perform the lithography process associated with the layout.

[0055] In some embodiments, the selection rule data 122 may include rules related to the distance between corners of adjacent features. If the distance between corners of adjacent features is less than a threshold distance, the selection rule data 122 may indicate that the layout analyzer 114 should select the EUV lithography system 106 to perform the lithography process associated with the layout. The selection rule data 122 may also include data related to whether the corners of a single feature can be closer than a threshold distance, or whether the percentage of corners that are closer than the threshold distance is less than a threshold percentage.

[0056] In some embodiments, the selection rule data 122 may include multiple rules related to pitch, CD, distance between corners, and other characteristics. The selection rule data 122 may indicate that the layout analyzer 114 should select the EUV lithography system 106 for the lithography process based on the satisfaction of all or part of the selection rule data 122.

[0057] In some embodiments, the layout analyzer 114 generates a layout score based on the layout feature data 116 and the selection rule data 122. The score can be based on the number of selection rule data satisfied (or violated) by the layout feature data 116. The selection of the EUV lithography system 106 or the 193i lithography system 108 can be based on the layout score. For example, the layout score associated with the layout can be compared to a threshold layout score, and the EUV lithography system 106 or the 193i lithography system 108 can be selected based on the comparison of the layout score to the threshold layout score.

[0058] The semiconductor processing system 100 may also include a layout adjustment system. The layout adjustment system can adjust the layout after the layout analyzer 114 determines that an EUV process should be used. The layout adjustment system can modify the design rules and layout to match the EUV process plan after determining that an EUV process should be used. In some cases, if additional process steps are used, additional layouts may be generated. In some cases, after determining that an EUV process should be used, some layouts may be modified, and others may be removed. In one example, due to different design rules associated with the EUV process, the EUV process may result in the ability to place conductive vias closer together in the layout. The layout defining the placement of these conductive vias may need to be adjusted. In addition, the layout of features above and below the conductive vias in the wafer may also need to be adjusted to account for the new arrangement of the conductive vias. Various types of layout adjustments can be performed based on different design rules associated with the EUV process. Therefore, the layout adjustment system can automatically adjust the layout to achieve compatibility after the selection of EUV due to changes in the arrangement of certain features.

[0059] Semiconductor processing system 100 may also include process adjustment system 126. If layout analyzer 114 determines that EUV lithography system 106 should be used for a particular layout 112, whereas 193i lithography system 108 was previously used for that layout 112, adjustments to the overall semiconductor process may be implemented. For example, exposure times may need to be adjusted, dielectric deposition and etching processes may be eliminated, or other aspects of the semiconductor process may be altered if EUV lithography replaces 193i lithography. More details on potential changes in the process are provided below.

[0060] Figure 2A-2F is a cross-sectional view of wafer 102 during a processing stage associated with an EUV lithography process, according to some embodiments. Figure 2A 1 , the wafer includes a target layer 130 above a substrate 131. The target layer 130 may include a semiconductor substrate, a dielectric layer, an interlayer dielectric layer above a semiconductor substrate, or other types of layers that may be part of the wafer 102 at a particular processing stage. The substrate 131 may include a semiconductor substrate, a Si layer, or other types of layers that may be part of the wafer 102 at a particular processing stage. Various types of materials may be used for the target layer 130 without departing from the scope of the present disclosure.

[0061] Target layer 130 is covered by a layer of photoresist 132. Photoresist 132 may include a material that undergoes a physical change when exposed to light. Depending on the type of material of photoresist 132, the physical change may weaken or strengthen the portion of photoresist 132 illuminated by the photolithographic light. Various types of photoresists may be used without departing from the scope of the present disclosure.

[0062] exist Figure 2B In the EUV lithography process, the wafer has been exposed to EUV light. Figure 1 As described, EUV light is generated in an EUV generation chamber and reflected from a photomask or mask including a pattern associated with a desired layout. After the EUV light is reflected from the photomask, the EUV light carries the pattern of the photomask. The EUV light then irradiates the photoresist 132. Depending on the pattern of the photomask, some portions of the photoresist 132 receive EUV light while other portions do not receive EUV light. In one example, the portion of the photoresist 132 that receives or is exposed to EUV light undergoes structural changes. After being exposed to EUV light, the photoresist is exposed to an etching process. The etching process may include a wet or dry etching process that selectively etches the exposed portions of the photoresist 132 relative to the unexposed portions of the photoresist 132. In Figure 2B In the example shown, the result is trenches 134 formed in photoresist layer 132. Trenches 134 correspond to a layout pattern associated with a mask or reticle used in a photolithography process.

[0063] exist Figure 2C In the embodiment of the present invention, an etching process is performed. The etching process may include wet etching or dry etching. The etching process is an anisotropic etching process that selectively etches downward. The etching process etches the portion of the target layer 130 exposed in the trench 134 in the photoresist 132. As a result, the target layer 130 is etched below the trench 134, thereby extending the trench 134 into the target layer 130. Various types of etching processes may be used without departing from the scope of the present disclosure.

[0064] exist Figure 2D , the photoresist 132 is removed. The photoresist 132 can be removed by exposing the photoresist 132 to an etchant that selectively etches the photoresist 132 relative to the target layer 130. As a result, the photoresist 132 is completely removed, thereby exposing the entire target layer 130. The trench 134 remains on the target layer 130.

[0065] exist Figure 2E , metal 136 is deposited on target layer 130. Metal 136 completely fills trench 134. Metal 136 also accumulates on the top surface of target layer 130. The metal may include tungsten, copper, titanium, aluminum, gold, or other suitable metal. Metal 136 may be deposited by physical vapor deposition (PVD), atomic layer deposition (ALD), or chemical vapor deposition (CVD). Metal 136 may have a thickness between 5 nm and 30 nm. In practice, the thickness of metal 136 is selected to ensure that trench 134 is completely filled with metal 136. Other materials, deposition processes, and thicknesses may be used for metal 136 without departing from the scope of the present disclosure.

[0066] exist Figure 2FIn the embodiment of the present invention, a planarization process is performed to remove metal 136 from the top surface of target layer 130. This process may include a CMP process to ensure that the top surface of target layer 130 is planar. As a result of the planarization process, individual metal lines 138 remain in trenches 134. The individual metal lines 138 are electrically and physically separated from each other.

[0067] The metal lines 138 have a pitch P. As used herein, pitch P may be defined as the distance between a portion of a feature and a corresponding portion of an adjacent feature. Figure 2F In the example shown, the pitch corresponds to the distance between the right edge of metal line 138 and the right edge of an adjacent metal line 138. Alternatively, the pitch can be defined as the center-to-center distance, the left-edge-to-left-edge distance, or other similar distance between two adjacent metal lines 138.

[0068] about Figure 2A-2F The EUV lithography process described is a single exposure lithography process. The photoresist 132 is exposed to EUV light only once. The pattern of the mask or reticle can be transferred to the photoresist 132 through a single exposure. Due to the nature of EUV lithography, as previously described, a single exposure process can be used to generate a pitch P of less than 71 nm. Figure 2A-2F In the example of FIG. 5 , the pitch may be between 20 nm and 71 nm, although other values ​​may be used without departing from the scope of the present disclosure.

[0069] It is also possible to form features with a pitch less than 71 nm using the 193i lithography system 108. However, these processes are more complex and use more steps than the EUV processes performed using the EUV lithography system 106. One example of a 193i lithography process that can be used to form features with a pitch less than 71 nm is to use a single exposure plus spacer technique. In the single exposure plus spacer technique, the photoresist 132 is deposited on the target layer 130, such as Figure 2A As shown. Then, a trench 134 is formed in the photoresist 132. However, due to the limitation of the 193i lithography process, the trench 134 in the 193i lithography process is initially smaller than that in the EUV lithography process. Figure 2B A thin spacer layer is then conformally deposited on top of the photoresist 132, on the sidewalls of the photoresist 132 in the trench 134, and on the exposed surface of the target layer 130 in the trench 134. The thickness of the spacer layer is selected to correspond to the desired width of the metal line (or other feature) to be formed in the target layer 130.

[0070] After depositing the spacer layer, an etching process is performed to remove the spacer layer from the photoresist 132 and the top surface of the target layer 130. As a result, the spacer layer remains only on the sidewalls of the trenches 134 in the photoresist 132. Mandrel material is then deposited on the exposed portions of the top surface of the target layer 130 between the remaining portions of the spacer layer. In practice, the mandrel material is conformally deposited and then recessed so that the mandrel material remains only between the remaining portions of the spacer layer. The remaining portions of the mandrel material correspond to corresponding mandrels on the target layer 130 located between the remaining portions of the spacer layer on the sidewalls of the photoresist 132.

[0071] After the mandrel is formed, the remaining portion of the spacer layer is completely removed. Because the thickness of the spacer layer corresponds to the desired thickness (or CD) of the metal line to be formed in the target layer 130, after the spacer layer is removed, a gap exists between the mandrel and the photoresist 132, and the width of the gap corresponds to the desired thickness of the metal line to be formed in the target layer 130. The target layer 130 is exposed in the gap. A trench can be etched in the target layer 130 through the gap between the mandrel and the photoresist 132.

[0072] After etching the trenches, the mandrels and photoresist 132 may be removed. Metal lines 138 may then be formed in the trenches, substantially as Figure 2E and Figure 2F As shown in FIG. Metal lines 138 formed using a single-exposure 193i lithography plus spacer technique can have the same pitch as a single-exposure EUV process. However, single-exposure 193i lithography plus spacer technique is significantly more complex and time-consuming than a single-exposure EUV process. Therefore, when layout 112 requires a pitch less than 71 nm or is to be formed with a pitch less than 71 nm, it may be beneficial to select EUV lithography system 108 to perform the lithography process.

[0073] Another process that can be used to form a pitch less than 71 nm using the 193i lithography system 108 is a multiple exposure lithography scheme. In the multiple exposure lithography scheme, the trenches 134 are formed in the target layer 130 by multiple lithography exposure steps. In the first exposure step, substantially as shown in FIG. Figure 2A-2D The first set of trenches is formed as shown, but with approximately twice the desired final pitch. The initial photoresist is then removed and a second layer of photoresist is deposited on the target layer 130. A second exposure process is performed with the mask shifted so that a second set of trenches is formed in the process midway between the first set of trenches, which is essentially Figures 2A-2D After forming the second set of grooves alternating with the first set of grooves, the final pattern of grooves has the desired pitch and may be approximately equal to Figure 2FHowever, this process requires about twice as many steps as a single-exposure EUV process. In addition, if the second set of trenches is not moved to the exact middle of the first set of trenches during the second exposure, the pitch between adjacent trenches will be unequal.

[0074] Therefore, if a layout requires features with a pitch smaller than that which can be formed using 193i lithography without using spacer technology or multiple exposures, then using EUV lithography may be beneficial. However, even if pitches smaller than 71 nm exist, there may be situations where 193i lithography is generally more desirable. These situations may include whether there are only a small number of such pitches, whether the pitch between adjacent features is consistent, or whether there may be other sensitive sensors. Therefore, as previously described, the layout analyzer 114 may implement various selection rules to determine whether EUV lithography should be used instead of 193i lithography for a particular layout.

[0075] Figure 3 Layout 112 is illustrated in accordance with some embodiments. Layout 112 corresponds to a top view of a desired pattern to be achieved in wafer 102 at a particular processing stage. Figure 3 In the example shown in FIG. 1 , layout 112 corresponds to a top view of a metal line 138 that will be formed in target layer 130 corresponding to an interlayer dielectric layer. Layout 112 is not an actual wafer, even though the features marked are represented using the same Figure 2A-2F Similar marks. On the contrary, as Figure 1 As depicted, layout 112 is a visual representation of a layout plan stored in layout database 110 .

[0076] Layout analyzer 114 analyzes layout 112 and identifies pitch data 118. Pitch data 118 indicates the presence of a plurality of different pitches. A first pitch P1 may be less than 71 nm, or some other threshold pitch value. A second pitch P2 may be greater than the threshold pitch value and, in any case, be significantly different from first pitch P1. Pitches P3-P5 may be the same as pitch P1.

[0077] The layout analyzer 114 analyzes and Figure 3 Layout characteristic data 116 associated with the layout 112 is obtained and compared to selection rule data 122. The selection rule data may indicate that if there are pitches less than 71 nm, if the pitches are not periodic, and if there are different pitches, then the EUV lithography system 106 should be used to perform the lithography process associated with the layout 112. Alternatively, the layout rules may determine that the 193i lithography system 108 may be used to perform the lithography process associated with the layout 112 even if some of the pitches are less than a threshold pitch value.

[0078] Figure 4 Layout 112 is illustrated in accordance with some embodiments. Layout 112 corresponds to a top view of a desired pattern to be achieved in wafer 102 at a particular processing stage. Figure 4 In the example of FIG. 1 , layout 112 corresponds to a top view of a metal line 138 that will be formed in target layer 130 corresponding to an interlayer dielectric layer. Layout 112 is not an actual wafer, even if the same Figure 2A-2F Like reference numerals mark features. Figure 1 As depicted, layout 112 is a visual representation of a layout plan stored in layout database 110 .

[0079] Layout analyzer 114 analyzes layout 112 and identifies CD data 120. CD data 120 indicates the presence of multiple different CDs. A first CD, CD1, may be greater than 30 nm, or some other threshold CD value. A second CD, CD2, may be less than the threshold CD value, and in any case, significantly less than CD1. CD3 may be equal to CD2. CD4 may be equal to CD1.

[0080] The layout analyzer 114 analyzes and Figure 4 Layout feature data 116 associated with the layout 112 is obtained and the layout feature data 116 is compared to selection rule data 122. The selection rule data may indicate whether there are CDs less than a threshold CD value, and if different CDs are present, then the EUV lithography system 106 should be used to perform the lithography process associated with the layout 112. Alternatively, the layout rule may determine that even if there are some CDs less than the threshold CD value, the 193i lithography system 108 may be used to perform the lithography process associated with the layout 112.

[0081] Figure 5 is a diagram of layout 112 associated with a particular processing stage of wafer 102 according to some embodiments. As an example, Figure 5 Layout 112 corresponds to the primary circuits under pad (CUP) associated with the formation of a gate-all-around nanostructure transistor. Layout 112 includes features 139. Features 139 may include conductive vias, semiconductor structures, metal lines, trench isolations, or other types of components formed in target layer 130. Figure 5 A pair of exterior angles 140 and 145 are shown. Exterior angle 140 corresponds to the adjacent angle of adjacent feature 139. Exterior angle 145 corresponds to the adjacent exterior angle of adjacent feature 139. Figure 5 Also shown are pairs of interior angles 141 and 143. Interior angle 141 corresponds to an adjacent interior angle of single feature 139. Interior angle 143 corresponds to the other adjacent interior angle of single feature 139.

[0082] Each pair of corners can be separated by a different distance. For example, outer corners 140 can be separated by a first distance D1. Inner corners 141 can be separated by a second distance D2. Inner corners 143 can be separated by a third distance D3. Outer corners 145 can be separated by a fourth distance D4. Layout analyzer 114 can analyze layout feature data 116 including distances D1-D4 and compare distances D1-D4 to selection rule data 122. Selection rule data 122 can include a threshold inner corner distance and a threshold outer corner distance. The threshold inner corner distance can be similar to a threshold CD. The threshold outer corner distance can be similar to a threshold pitch. Selection rule data 122 can indicate that if one or more of the inner corner distance or the outer corner distance is less than the threshold inner corner distance or the outer corner distance, then EUV lithography system 106 should be used for the corresponding lithography process. In some cases, a single-exposure EUV system can replace up to six 193i lithography exposure processes. Various selection rule data 122 related to inner corner distances and outer corner distances can be used without departing from the scope of this disclosure. Additionally, the outer and inner corner distance rules may be combined with the pitch and CD rules via the selection rule data 122 to determine which lithography system should be used.

[0083] Figure 6 is an illustration of layout 112 according to some embodiments. Layout 112 corresponds to a particular level of wafer 102 and a layout of metal lines 138. Layout analyzer 114 extracts layout feature data 116 and identifies distances D1-D3 between adjacent metal lines 138. Selection rule data 122 may indicate a threshold spacing distance between metal lines. For example, the threshold spacing distance may be between 15 and 25 nm, although other threshold spacing distances may be used without departing from the scope of the present disclosure. If distance D1-D3 is less than the threshold metal line spacing distance, selection rule data 122 may indicate that layout analyzer 114 should select EUV lithography system 106 to perform a lithography process associated with layout 112.

[0084] exist Figure 6 In the embodiment of the present invention, the separation distances D1-D3 are equal and can all be less than the threshold separation distance. However, in other cases, there may be various distances between adjacent metal lines. In addition, there may be various pitches and CDs associated with the metal lines. The selection rule data 122 can define multiple rules related to a threshold pitch, a threshold separation distance, a threshold CD, a threshold angular separation distance, a pitch difference, a CD difference, a ratio of different pitches, a ratio of different CDs, a ratio of different metal line separation distances, a ratio of different angular separation distances, or a combination of these factors.

[0085] Figure 7FIG1 is a cross-sectional view of wafer 102 according to some embodiments. Wafer 102 includes metal lines 138 formed in target layer 130 according to an EUV lithography process. Metal lines 138 appropriately reflect desired features according to layout 112. The metal lines define pitches P1-P5, CD1-CD6, and depths D1-D6. Due to the characteristics of the single-exposure EUV lithography process, pitches P1-P5 are equal, critical dimensions CD1-CD6 are equal, and depths D1-D6 are equal.

[0086] However, if a 193i lithography process is used in conjunction with spacer technology to form metal lines 138, pitches P1-P5 are likely not all equal. Specifically, pitches P1, P3, and P5 may be identical, but pitches P2 and P4 may differ from pitches P1, P3, and P5. If a 193i lithography process with multiple exposure and multiple etching techniques is used, pitches P1-P5, CD1-CD6, and depths D1-D6 may differ due to the characteristics of the multiple exposure technique. Therefore, layout analyzer 114, based on the selection of selection rule data 122, may determine to use EUV lithography system 106 to perform the lithography process associated with layout 112.

[0087] Figure 8 is a flow chart of a method 800 for processing a wafer according to some embodiments. The method 800 may use Figure 1-Figure 7 At 802, method 800 includes storing layout data associated with a layout of a wafer. An example of the layout data is Figure 1 The layout database 110. An example of a layout is Figure 1 An example of a wafer layout 112 is Figure 1 At 804, method 800 includes extracting feature data representing dimensions associated with features of the layout from the layout. An example of feature data is Figure 1 At 806, method 800 includes comparing the characteristic data to a selection rule. An example of a selection rule is Figure 1 The selection rule data 122. At 808, the method 800 includes selecting between an EUV lithography process and a non-EUV lithography process for layout based on the characterization data and the selection rule.

[0088] Figure 9 is a flow chart of a method 900 for processing a wafer according to some embodiments. The method 900 may use Figure 1-8 At 902, method 900 includes storing a plurality of layouts in a layout database, each layout corresponding to a respective stage of semiconductor processing. An example of a layout database is Figure 1 A layout database 110. An example of a layout is Figure 1 At 904, method 900 includes retrieving selection rule data, the selection rule data including selection rule data for selecting between the first lithography system and the second lithography system. An example of the selection rule data is Figure 1 An example of a first lithography system is Figure 1 An example of a second EUV lithography system is Figure 1 193i lithography system. At 906, method 900 includes extracting feature data associated with the layout for each layout. An example of feature data is Figure 1 At 908, the method 900 includes analyzing the feature data with the selection rule data for each layout. At 910, the method 900 includes selecting a first lithography system or a second lithography system for each layout based on the analyzing the feature data with the selection rule data.

[0089] Embodiments of the present disclosure provide a semiconductor processing system that selects from different types of photolithography processes for each of a plurality of layouts for processing a semiconductor wafer. The semiconductor processing system includes a layout database and a layout analyzer. The layout database includes layout data associated with each photolithography mask to be used to process the semiconductor wafer. The layout analyzer analyzes the layout of features associated with each mask. The layout analyzer can analyze the distribution of critical dimensions (CDs), pitches, and other aspects associated with the layout. The layout analyzer processes the layout feature data according to selection rule data. The selection rule data determines which type of photolithography process should be used for a given layout. The layout analyzer selects a photolithography process for each layout for transferring the layout to the semiconductor wafer.

[0090] Layout analysis and lithography process selection have various benefits. For example, when the layout analyzer detects very small pitch, CD or other dimensional aspects of the layout, the layout analyzer selects the extreme ultraviolet (EUV) lithography process that can most reliably impart the corresponding pattern to the semiconductor wafer. In the case where the layout does not include very small pitch, CD or other dimensional aspects, the layout analyzer can select a lithography process other than EUV lithography. These other lithography processes may be very suitable for delivering patterns with loose dimensional constraints. This allows lithography resources to be effectively managed, layout features to be correctly and reliably delivered to the wafer, and wafer yield to be improved.

[0091] In some embodiments, a method includes storing layout data associated with a layout of a wafer and extracting, from the layout, dimension feature data representing features associated with the layout. The method includes comparing the dimension feature data with a selection rule and selecting, based on the dimension feature data and the selection rule, between an EUV lithography process and a non-EUV lithography process for the layout.

[0092] In some embodiments, the feature data includes pitch data representing a dimension of a pitch associated with the features of the layout. In some embodiments, the selection rule data includes a threshold pitch value. In some embodiments, the selection rule indicates that the EUV lithography process should be used if a selected amount of the pitch is less than the threshold pitch value. In some embodiments, the feature data includes critical dimension data representing a critical dimension associated with the features of the layout. In some embodiments, the selection rule data includes a threshold critical dimension value. In some embodiments, the selection rule indicates that the EUV lithography process should be used based on whether a selected value of the critical dimension is less than the threshold critical dimension value. In some embodiments, the feature data includes angular distance data representing a distance between corners of one or more features of the layout. In some embodiments, the selection rule data includes a threshold angular spacing value. In some embodiments, the selection rule indicates that the EUV lithography process should be used based on whether a selected value of a selected spacing distance between the corners is less than the threshold angular spacing value. In some embodiments, the method further includes performing the selected lithography process on a wafer used for the layout.

[0093] In some embodiments, a method includes storing a plurality of layouts in a layout database, each layout corresponding to a respective stage of semiconductor processing, and retrieving selection rule data including a selection rule for selecting between a first lithography system and a second lithography system. The method includes extracting feature data associated with the layout for each layout, analyzing the feature data for each layout using the selection rule data, and selecting the first lithography system or the second lithography system for each layout based on the analysis of the feature data using the selection rule data.

[0094] In some embodiments, the method further comprises performing a selected lithography process on a wafer for each layout. In some embodiments, the first lithography system is an extreme ultraviolet lithography system. In some embodiments, the second lithography system is an 193i lithography system. In some embodiments, the method further comprises adjusting one or more layouts in response to selecting the first lithography system. In some embodiments, the method further comprises adjusting a wafer fabrication process associated with the one or more layouts in response to selecting the first lithography system.

[0095] In some embodiments, a semiconductor processing system includes a first lithography system and a second lithography system. The semiconductor processing system includes a layout database and a layout analyzer, wherein the layout database includes a plurality of layouts, each layout representing a feature to be formed in a wafer, and the layout analyzer is configured to extract layout feature data from each layout, compare the feature data of each layout with a selection rule, and select the first lithography system or the second lithography system for each layout based on the feature data and the selection rule data.

[0096] In some embodiments, the first lithography system is an EUV lithography system. In some embodiments, the semiconductor processing system further comprises a process adjustment system configured to adjust a process step associated with the layout based on selecting the first lithography system or the second lithography system for the layout.

[0097] The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use this disclosure as a basis for designing or modifying other processes and structures for performing the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art will also appreciate that such equivalent structures do not depart from the spirit and scope of the present invention, and that various modifications, substitutions, and variations may be made to this document without departing from the spirit and scope of the present invention.

Claims

1. A method for selecting a photolithography process, comprising: storing layout data associated with a layout for a wafer; extracting, from the layout, feature data representing dimensions associated with features of the layout; comparing the characteristic data with selection rules; and Based on the feature data and the selection rule, a selection is made between an EUV lithography process and a non-EUV lithography process for the layout, wherein the feature data includes pitch data representing a size of a pitch associated with the feature of the layout, and the selection rule data includes a threshold pitch value and a threshold percentage value, wherein the selection rule indicates that the EUV lithography process is used if the percentage by which the pitch is less than the threshold pitch value is less than the threshold percentage value.

2. The method for selecting a photolithography process according to claim 1 , further comprising: The layout is adjusted in response to selecting the EUV lithography process.

3. The method for selecting a photolithography process according to claim 1, wherein: The EUV lithography process uses EUV light having a wavelength between 10 nm and 15 nm.

4. The method for selecting a photolithography process according to claim 1, wherein: The selection rule indicates that if the selected amount of the pitch is less than the threshold pitch value, then the EUV lithography process should be used.

5. The method for selecting a photolithography process according to claim 1, wherein: The feature data includes critical dimension data representing a critical dimension associated with the feature of the layout.

6. The method for selecting a photolithography process according to claim 5, wherein: The selection rule data includes a threshold critical dimension value.

7. The method for selecting a photolithography process according to claim 6, wherein: The selection rule indicates that the EUV lithography process should be used based on whether the selected value of the CD is less than the threshold CD value.

8. The method for selecting a photolithography process according to claim 1, wherein: The feature data includes angular distance data representing distances between corners of one or more features of the layout.

9. The method for selecting a photolithography process according to claim 8, wherein: The selection rule data includes a threshold angular separation value.

10. The method according to claim 9, wherein: The selection rule indicates that the EUV lithography process should be used based on whether a selected value of a selected separation distance of the corners is less than the threshold angular separation value. 11 . The method for selecting a photolithography process according to claim 1 , further comprising performing the selected photolithography process on a wafer for the layout.

12. A method for selecting a photolithography process, comprising: storing a plurality of layouts in a layout database, each layout corresponding to a respective stage of semiconductor processing; retrieving selection rule data, the selection rule data comprising a selection rule for selecting between a first lithography system and a second lithography system, wherein the first lithography system is an EUV lithography system; extracting feature data related to the layout for each layout; analyzing the feature data for each layout using the selection rule data; and Based on an analysis of the feature data using the selection rule data, the first lithography system or the second lithography system is selected for each layout, wherein the feature data includes pitch data representing a size of a pitch associated with a feature of the layout, and the selection rule data includes a threshold pitch value and a threshold percentage value, wherein the selection rule indicates that the EUV lithography system should be used if the percentage by which the pitch is less than the threshold pitch value is less than the threshold percentage value. 13 . The method for selecting a lithography process according to claim 12 , further comprising performing the selected lithography process on a wafer for each layout.

14. The method for selecting a photolithography process according to claim 12, wherein: The feature data includes angular distance data representing distances between corners of one or more features of the layout.

15. The method for selecting a photolithography process according to claim 12, wherein: The second lithography system is a 193i lithography system. 16 . The method for selecting a lithography process according to claim 12 , further comprising adjusting one or more layouts in response to selecting the first lithography system. 17 . The method for selecting a lithography process according to claim 16 , further comprising adjusting a wafer fabrication process associated with the one or more layouts in response to selecting the first lithography system.

18. A semiconductor processing system comprising: a first lithography system, wherein the first lithography system is an EUV lithography system; a second lithography system; a layout database comprising a plurality of layouts, each layout representing a feature to be formed in the wafer; and A layout analyzer is configured to extract layout feature data from each layout, compare the feature data of each layout with a selection rule, and select the first lithography system or the second lithography system for each layout based on the feature data and the selection rule data, wherein the feature data includes pitch data representing a size of a pitch associated with the feature of the layout, the selection rule data includes a threshold pitch value and a threshold percentage value, and wherein the selection rule indicates that the EUV lithography system should be used if a percentage by which the pitch is less than the threshold pitch value is less than the threshold percentage value.

19. The semiconductor processing system of claim 18, wherein: The feature data includes angular distance data representing distances between corners of one or more features of the layout.

20. The semiconductor processing system of claim 18, further comprising a process adjustment system configured to adjust a process step associated with a layout based on selecting the first photolithography system or the second photolithography system for the layout.

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