An Address Allocation Method and System for a Chip Component Based on a Serial Connection Method

Abstract

The present invention discloses a method and system for address allocation of a chip component based on a series connection mode. The method includes: sending an address allocation instruction to the chip component, where the chip component includes a main control chip and a plurality of slave chips, and the main control chip is communicatively connected to the slave chips and adjacent slave chips in a series connection mode. The main control chip receives the address allocation instruction and sequentially allocates chip addresses to the slave chips. By using the embodiments of the present invention, it can perform chip address allocation in a series connection mode, realize automatic allocation of addresses of the entire chip component, and reduce the hardware complexity.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip control, and particularly relates to an address allocation method and system for a chip component based on a series connection method. Background Art

[0002] For a complex chip communication system, it usually consists of a control chip and numerous slave chips. In this system, the control chip is responsible for controlling each slave chip, that is, directly controlling each slave chip through a control chip, and each slave chip is independent of each other.

[0003] In the prior art, the master control chip distributes addresses to each slave chip, and each slave chip receives the address data and returns the allocated address to the control chip to verify the allocation result. Since the control chip distributes addresses to each slave chip, there are too many connections between the chips, increasing the chip pins and also increasing the complexity of the system design. Therefore, it has a certain impact on the reliability of the complex chip communication system, which is an urgent problem to be solved. Summary of the Invention

[0004] The purpose of the present invention is to provide an address allocation method and system for a chip component based on a series connection method to solve the deficiencies in the prior art. It can perform chip address allocation through a series connection method, realize automatic address allocation of the entire chip component, and reduce the hardware complexity.

[0005] An embodiment of the present application provides an address allocation method for a chip component based on a series connection method, and the method includes:

[0006] Sending an address allocation instruction to the chip component, where the chip component includes a master control chip and several slave chips, and the master control chip is communicatively connected to the slave chips and adjacent slave chips through a series connection method;

[0007] The master control chip receives the address allocation instruction and sequentially allocates chip addresses to the slave chips.

[0008] Optionally, before sending the address allocation instruction to the chip component, the method includes:

[0009] Storing the identity identification information of the chip component and the initial address information of the chip component on a pre-set address space;

[0010] Obtaining the address allocation instruction of the chip component and packing the address allocation instruction into an address configuration command frame according to the address space.

[0011] Optionally, the address allocation instruction includes: a read address operation instruction, a parsed address operation instruction, and a flag information instruction. Packing the address allocation instruction into an address configuration command frame according to the address space includes:

[0012] Converting the read address operation instruction and the parsed address operation instruction into a frame structure form and storing them in the address field of the address configuration command frame;

[0013] Converting the flag information instruction into a frame structure form and storing it in the control field of the address configuration command frame.

[0014] Optionally, sending the address allocation instruction to the chip component includes:

[0015] Sending the address configuration command frame to the chip component and operating on the chip component according to the address allocation instruction in the address configuration command frame.

[0016] Optionally, the master chip receives the address allocation instruction and sequentially allocates chip addresses to the slave chips, including:

[0017] The master chip receives the address allocation instruction and sets a sending port, and the address configuration command frame included in the address allocation instruction is sent to the first slave chip through the one sending port;

[0018] The first slave chip receives the address configuration command frame sent by the master chip at the downlink data receiving port and updates and sets the current address information of the first slave chip according to the received address configuration command frame;

[0019] The first slave chip that has set the current address information sends the address configuration command frame to the second slave chip. After receiving the address configuration command frame, the second slave chip sets the address information, and the operation is sequentially performed until the address allocation of all chips in the chip component is completed.

[0020] Optionally, the slave chip includes an address processing unit. The first slave chip that has set the current address information sends the address configuration command frame to the second slave chip, including:

[0021] The first slave chip receives the address configuration command frame sent by the master chip at the downlink data receiving port, updates the address configuration command frame through the address processing unit, and sends the updated address configuration command frame to the second slave chip from the downlink data sending port of the first slave chip, where updating the address configuration command frame includes updating the offset of the address information in the address configuration command frame.

[0022] Another embodiment of the present application provides an address allocation system for a chip component based on a series connection method. The system includes:

[0023] A sending module, configured to send an address allocation instruction to a chip component, where the chip component includes a main control chip and a plurality of slave chips, and the main control chip is communicatively connected to the slave chips and adjacent slave chips in series;

[0024] A receiving module, configured to receive the address allocation instruction by the main control chip and sequentially allocate chip addresses to the slave chips.

[0025] Optionally, the system further includes:

[0026] A storage module, configured to store the identity identification information of the chip component and the initial address information of the chip component on a preset address space;

[0027] An obtaining module, configured to obtain the address allocation instruction of the chip component and package the address allocation instruction into an address configuration command frame according to the address space.

[0028] Optionally, the obtaining module includes:

[0029] A first conversion unit, configured to convert the read address operation instruction and the parsed address operation instruction into a frame structure form and store them in the address domain of the address configuration command frame;

[0030] A second conversion unit, configured to convert the flag information instruction into a frame structure form and store it in the control domain of the address configuration command frame.

[0031] Optionally, the sending module includes:

[0032] A sending unit, configured to send the address configuration command frame to the chip component and operate on the chip component according to the address allocation instruction in the address configuration command frame.

[0033] Optionally, the receiving module includes:

[0034] A first receiving unit, configured to receive the address allocation instruction by the main control chip and set a sending port, and the address configuration command frame included in the address allocation instruction is sent to a first slave chip through the sending port;

[0035] A second receiving unit, configured to receive the address configuration command frame sent by the main control chip at a downlink data receiving port by the first slave chip and update and set the current address information of the first slave chip according to the received address configuration command frame.

[0036] A setting unit is configured to set a first slave chip that has completed the current address information to send an address configuration command frame to a second slave chip. After receiving the address configuration command frame, the second slave chip sets the address information, and the operation is performed in sequence until the address allocation of all chips in the chip component is completed.

[0037] Optionally, the setting unit includes:

[0038] An update subunit is configured to enable a first slave chip to receive an address configuration command frame sent by the master chip at a downlink data receiving port, update the address configuration command frame through the address processing unit, and send the updated address configuration command frame from the downlink data sending port of the first slave chip to a second slave chip. Herein, updating the address configuration command frame includes updating the offset of the address information in the address configuration command frame.

[0039] Another embodiment of the present application provides a storage medium in which a computer program is stored. Wherein, the computer program is configured to execute the method described in any one of the above when running.

[0040] Another embodiment of the present application provides an electronic device, including a memory and a processor. A computer program is stored in the memory, and the processor is configured to run the computer program to execute the method described in any one of the above.

[0041] Compared with the prior art, the present invention first sends an address allocation instruction to a chip component, where the chip component includes a master chip and several slave chips, and the master chip is communicatively connected to the slave chips and adjacent slave chips in series. The master chip receives the address allocation instruction and sequentially allocates chip addresses to the slave chips. It can perform chip address allocation in series, realize automatic address allocation of the entire chip component, and reduce the hardware complexity. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 It is a hardware structure block diagram of a computer terminal for an address allocation method of a chip component based on a series connection manner provided by an embodiment of the present invention;

[0043] Figure 2 It is a flowchart of an address allocation method of a chip component based on a series connection manner provided by an embodiment of the present invention;

[0044] Figure 3 It is an application schematic diagram of an address allocation of a chip component based on a series connection manner provided by an embodiment of the present invention;

[0045] Figure 4 It is a schematic diagram of the structure of an address allocation system of a chip component based on a series connection manner provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0046] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0047] The embodiments of the present invention first provide an address allocation method for a chip component based on a series connection method, which can be applied to electronic devices, such as computer terminals, specifically, ordinary computers, tablets, etc.

[0048] The following takes running on a computer terminal as an example to describe it in detail. Figure 1 It is a hardware structure block diagram of a computer terminal for an address allocation method of a chip component based on a series connection method provided by the embodiments of the present invention. As Figure 1 shown, the computer terminal may include one or more ( Figure 1 only one is shown in the figure) processors 102 (the processor 102 may include, but is not limited to, processing devices such as a microprocessor MCU or a field programmable gate array FPGA) and a memory 104 for storing data. Optionally, the above computer terminal may further include a transmission device 106 for communication functions and an input / output device 108. Those of ordinary skill in the art can understand that Figure 1 the structure shown is only schematic and does not limit the structure of the above computer terminal. For example, the computer terminal may further include more or fewer components than Figure 1 shown in the figure, or have a different configuration from Figure 1 shown in the figure.

[0049] The memory 104 can be used to store software programs and modules of application software, such as program instructions / modules corresponding to the address allocation method of the chip component based on the series connection method in the embodiments of the present application. The processor 102 executes various functional applications and data processing by running the software programs and modules stored in the memory 104, that is, the above method is implemented. The memory 104 may include a high-speed random access memory, and may further include a non-volatile memory, such as one or more magnetic storage devices, flash memories, or other non-volatile solid-state memories. In some instances, the memory 104 may further include a memory remotely disposed relative to the processor 102, and these remote memories may be connected to the computer terminal through a network. Examples of the above network include, but are not limited to, the Internet, an enterprise intranet, a local area network, a mobile communication network, and combinations thereof.

[0050] The transmission device 106 is used to receive or send data via a network. Specific examples of the above-mentioned network may include a wireless network provided by a communication provider of a computer terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a Radio Frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0051] A serial chip communication system usually consists of a main control chip and numerous slave chips to form a system. The number of slave chips only represents a plurality and does not serve to limit the number of arithmetic chips. In a serial chip communication system, serial interfaces are usually used for interconnection (such as the UART protocol). Because its connection circuit is simple and has high reliability, it is widely used for interconnection between boards or within boards. The serial interface communication method usually only supports the point-to-point method. If a one-to-many master-slave communication method is required, the serial interface data of each slave chip needs to be received and input from the upper-level chip first and then output to the next level. This method also requires a unique chip address to be assigned to each slave chip separately. The common method for setting the chip address is to connect a DIP switch or directly jump a resistor on the chip pins to set different addresses for each chip address. However, this method increases the chip pins and also increases the system design complexity, having a certain impact on reliability.

[0052] See Figure 2 , Figure 2 The flowchart of a method for address allocation of a chip component based on a serial connection provided by an embodiment of the present invention may include the following steps:

[0053] S201: Send an address allocation instruction to the chip component, where the chip component includes a main control chip and several slave chips, and the main control chip is communicatively connected to the slave chips and adjacent slave chips in a serial connection manner.

[0054] Specifically, the chip component includes a main control chip and several slave chips. See Figure 3 , Figure 3 The application schematic diagram of address allocation of a chip component based on a serial connection provided by an embodiment of the present invention. The figure includes a main control chip and multiple slave chips. The main control chip is connected to the first slave chip, and the first slave chip is sequentially connected to the next slave chip, thus forming a serial communication system. Among them, the main control chip includes at least one transmission port (TX in the figure), and each slave chip includes at least a downlink data transmission port (RX0 in the figure) and a downlink data reception port (RX1 in the figure).

[0055] Furthermore, asFigure 3 In the serial communication system shown, at least one transmission port (TX) of the master control chip is connected to the downlink data receiving port (RX1 in the figure) of the first slave chip, the downlink data transmission port (RX0 in the figure) of the first slave chip is connected to the downlink data receiving port (RX1 in the figure) of the second slave chip, and so on, until the Nth slave chip. The downlink data transmission port of the Nth slave chip can be left floating.

[0056] Before sending the address allocation instruction to the chip component, the method includes:

[0057] Step 1: Store the identity identification information of the chip component and the initial address information of the chip component in a pre-set address space.

[0058] Specifically, since there are multiple slave chips in the chip component, the identity identification of the slave chip can be used to indicate the slave chip that the master control chip will operate on. For example, an indication field can be set in the address space of the pre-set master control chip, and the identity identification of the slave chip is stored in this indication field; and since the master control chip will access not the entire slave chip but a section of the address space on the slave chip, the initial address information of the address space of the slave chip is used to indicate the address of the address space that the master control chip will access.

[0059] Step 2: Obtain the address allocation instruction of the chip component, and pack the address allocation instruction into an address configuration command frame according to the address space.

[0060] The address allocation instruction may include an indication of the address allocation operation attribute, including a read address operation instruction, a parse address operation instruction, and a flag information instruction. Among them, packing the address allocation instruction into an address configuration command frame according to the address space may include:

[0061] a. Convert the read address operation instruction and the parse address operation instruction into a frame structure form, and store them in the address field of the address configuration command frame.

[0062] b. Convert the flag information instruction into a frame structure form, and store it in the control field of the address configuration command frame.

[0063] In order for the chip component to receive the address assignment instruction and avoid errors caused by multiple transmissions after an accidental interruption, the address assignment instruction can be packaged into an address configuration command frame. Specifically, the address configuration command frame can be divided into two parts: a control domain command frame and an address domain command frame. The read address operation instruction and the parsed address operation instruction are converted into a frame structure form and stored in the address domain of the address configuration command frame; the flag information instruction is converted into a frame structure form and stored in the control domain of the address configuration command frame. The purpose of this is to distinguish and identify the content of the address configuration command frame, that is, in this way, it is judged whether the data frame is an address configuration command frame through the address configuration command flag.

[0064] Sending the address assignment instruction to the chip component includes:

[0065] Sending the address configuration command frame to the chip component and operating on the chip component according to the address assignment instruction in the address configuration command frame.

[0066] Exemplarily, by first identifying the data received and parsed by the address configuration command frame, it is judged whether this data frame is an address configuration command frame; if it is an address configuration command frame, the address information of the current chip is updated, and the address information in the address configuration command frame is written into the address information register of the current chip.

[0067] S202: The master chip receives the address assignment instruction and sequentially assigns chip addresses to the slave chips.

[0068] Specifically, the master chip receiving the address assignment instruction and sequentially assigning chip addresses to the slave chips may include:

[0069] The master chip receives the address assignment instruction and sets a sending port, and the address configuration command frame included in the address assignment instruction is sent to the first slave chip through the sending port. The first slave chip receives the address configuration command frame sent by the master chip at the downlink data receiving port and updates and sets the current address information of the first slave chip according to the received address configuration command frame. The first slave chip that has set the current address information sends the address configuration command frame to the second slave chip, and the second slave chip sets the address information after receiving the address configuration command frame, and operates sequentially until the address assignment of all chips in the chip component is completed.

[0070] It should be noted that the slave chip includes an address processing unit. The first slave chip that has set the current address information sending the address configuration command frame to the second slave chip may include:

[0071] The first slave chip receives the address configuration command frame sent by the master chip at the downlink data receiving port, updates the address configuration command frame through the address processing unit, and sends the updated address configuration command frame from the downlink data sending port of the first slave chip to the second slave chip. Among them, updating the address configuration command frame includes updating the offset of the address information in the address configuration command frame.

[0072] Specifically, the master chip can send the address configuration command frame to the slave chips in a broadcast manner. After the downlink data receiving port of the slave chip receives the information data frame, it receives and parses the data. The slave chip identifies the address configuration command frame. If so, it enters the address processing module; otherwise, it transfers to other processing modules. After completing the above steps, the data frame is sent from the downlink data sending port of the slave chip to the next slave chip, updating the address of the current slave chip, and at the same time updating the address information in the address configuration command frame, which can be completed by updating the offset of the address information in the address configuration command frame. Among them, the offset can be carried in the address configuration command frame itself or a fixed value, such as a fixed value of 1.

[0073] It can be seen that the present invention first sends an address allocation instruction to a chip component, where the chip component includes a master chip and several slave chips, and the master chip is communicatively connected to the slave chips and adjacent slave chips in series. The master chip receives the address allocation instruction and sequentially allocates chip addresses to the slave chips. It can perform chip address allocation in series, realize automatic address allocation of the entire chip component, and reduce the hardware complexity.

[0074] Another embodiment of the present application provides an address allocation system for a chip component based on a series connection method, which is applied to the address allocation method for a chip component based on a series connection method described in any one of the above, as Figure 4 shown in the structural schematic diagram of an address allocation system for a chip component based on a series connection method. The system includes:

[0075] A sending module 401, configured to send an address allocation instruction to a chip component, where the chip component includes a master chip and several slave chips, and the master chip is communicatively connected to the slave chips and adjacent slave chips in series;

[0076] A receiving module 402, configured to receive the address allocation instruction by the master chip and sequentially allocate chip addresses to the slave chips.

[0077] Specifically, the system further includes:

[0078] A storage module, configured to store the identity identification information of the chip component and the initial address information of the chip component in a pre-set address space;

[0079] An acquisition module, configured to acquire an address allocation instruction of the chip component, and pack the address allocation instruction into an address configuration command frame according to the address space.

[0080] Specifically, the acquisition module includes:

[0081] A first conversion unit, configured to convert the read address operation instruction and the parsed address operation instruction into a frame structure form, and store them in the address domain of the address configuration command frame;

[0082] A second conversion unit, configured to convert the flag information instruction into a frame structure form, and store it in the control domain of the address configuration command frame.

[0083] Specifically, the sending module includes:

[0084] A sending unit, configured to send the address configuration command frame to the chip component, and operate on the chip component according to the address allocation instruction in the address configuration command frame.

[0085] Specifically, the receiving module includes:

[0086] A first receiving unit, configured to receive the address allocation instruction by the master chip and set a sending port, and the address configuration command frame included in the address allocation instruction is sent to the first slave chip through the sending port;

[0087] A second receiving unit, configured to receive the address configuration command frame sent by the master chip at the downlink data receiving port of the first slave chip, and update and set the current address information of the first slave chip according to the received address configuration command frame;

[0088] A setting unit, configured to set the first slave chip that has completed the current address information to send an address configuration command frame to the second slave chip, and the second slave chip sets the address information after receiving the address configuration command frame, and operates in sequence until the address allocation of all chips in the chip component is completed.

[0089] Specifically, the setting unit includes:

[0090] An update subunit, configured to receive the address configuration command frame sent by the master chip at the downlink data receiving port of the first slave chip, update the address configuration command frame through the address processing unit, and send the updated address configuration command frame to the second slave chip from the downlink data sending port of the first slave chip, where updating the address configuration command frame includes updating the offset of the address information in the address configuration command frame.

[0091] Compared with the prior art, the present invention first sends an address assignment instruction to a chip component, where the chip component includes a main control chip and several slave chips, and the main control chip is communicatively connected to the slave chips and adjacent slave chips in series. The main control chip receives the address assignment instruction and sequentially assigns chip addresses to the slave chips. It can perform chip address assignment in series, realizing automatic address assignment for the entire chip component and reducing the hardware complexity.

[0092] An embodiment of the present invention also provides a storage medium, in which a computer program is stored. Wherein, the computer program is configured to execute the steps in any one of the above method embodiments when running.

[0093] Specifically, in this embodiment, the above storage medium can be configured to store a computer program for executing the following steps:

[0094] S201: Send an address assignment instruction to a chip component, where the chip component includes a main control chip and several slave chips, and the main control chip is communicatively connected to the slave chips and adjacent slave chips in series;

[0095] S202: The main control chip receives the address assignment instruction and sequentially assigns chip addresses to the slave chips.

[0096] Specifically, in this embodiment, the above storage medium can include but is not limited to: various media such as USB flash drives, read-only memories (ROM for short), random access memories (RAM for short), mobile hard disks, magnetic disks, or optical discs that can store computer programs.

[0097] Compared with the prior art, the present invention first sends an address assignment instruction to a chip component, where the chip component includes a main control chip and several slave chips, and the main control chip is communicatively connected to the slave chips and adjacent slave chips in series. The main control chip receives the address assignment instruction and sequentially assigns chip addresses to the slave chips. It can perform chip address assignment in series, realizing automatic address assignment for the entire chip component and reducing the hardware complexity.

[0098] An embodiment of the present invention also provides an electronic device, including a memory and a processor. A computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0099] Specifically, the above electronic device may further include a transmission device and an input / output device. Wherein, the transmission device is connected to the above processor, and the input / output device is connected to the above processor.

[0100] Specifically, in this embodiment, the above-mentioned processor may be configured to execute the following steps through a computer program:

[0101] S201: Send an address allocation instruction to the chip component, where the chip component includes a main control chip and a plurality of slave chips, and the main control chip is communicatively connected to the slave chips and adjacent slave chips in series;

[0102] S202: The main control chip receives the address allocation instruction and sequentially allocates chip addresses to the slave chips.

[0103] Compared with the prior art, the present invention first sends an address allocation instruction to the chip component, where the chip component includes a main control chip and a plurality of slave chips, and the main control chip is communicatively connected to the slave chips and adjacent slave chips in series. The main control chip receives the address allocation instruction and sequentially allocates chip addresses to the slave chips. It can perform chip address allocation in series, realizing automatic address allocation of the entire chip component and reducing the complexity of the hardware.

[0104] It should be noted that for the foregoing method embodiments, for the sake of simple description, they are all expressed as a series of action combinations. However, those skilled in the art should know that the present invention is not limited by the described action sequence, because according to the present invention, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to the present invention.

[0105] In the above embodiments, the descriptions of the various embodiments have their own emphases. For the parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0106] In several embodiments provided by the present invention, it should be understood that the disclosed device can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the above-mentioned unit division is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed mutual coupling or direct coupling or communication connection can be through some interfaces, and the indirect coupling or communication connection of the device or unit can be in an electrical or other form.

[0107] The units described above as separate components may or may not be physically separated. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed over multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0108] In addition, the functional units in various embodiments of the present invention may be integrated in a processing unit, or each unit may exist physically alone, or two or more units may be integrated in one unit. The above integrated units can be implemented in the form of hardware or in the form of software functional units.

[0109] If the above integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable memory. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions for causing a computer device (which can be a personal computer, a server or a network device, etc.) to execute all or part of the steps of the methods in various embodiments of the present invention. The aforementioned memory includes: various media such as USB flash drives, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), mobile hard disks, magnetic disks or optical discs that can store program codes.

[0110] The embodiments of the present invention have been introduced in detail above. Specific examples are used in this article to elaborate on the principles and implementation manners of the present invention. The descriptions of the above embodiments are only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. An address allocation method for a chip component based on a series connection method, characterized in that The method includes: Sending an address assignment instruction to a chip component, where the chip component includes a main control chip and several slave chips, and the main control chip is communicatively connected to the slave chips and adjacent slave chips in series; The main control chip receives the address assignment instruction and sequentially assigns chip addresses to the slave chips; The main control chip receives the address assignment instruction and sequentially assigns chip addresses to the slave chips, including: The main control chip receives the address assignment instruction and sets a sending port, and the address configuration command frame included in the address assignment instruction is sent to the first slave chip through the sending port; The first slave chip receives the address configuration command frame sent by the main control chip at the downlink data receiving port and updates and sets the current address information of the first slave chip according to the received address configuration command frame; The first slave chip that has set the current address information sends an address configuration command frame to the second slave chip, and the second slave chip sets the address information after receiving the address configuration command frame, and operates sequentially until the address assignment of all chips in the chip component is completed; The slave chip includes an address processing unit. The first slave chip that has set the current address information sends an address configuration command frame to the second slave chip, including: The first slave chip receives the address configuration command frame sent by the main control chip at the downlink data receiving port, updates the address configuration command frame through the address processing unit, and sends the updated address configuration command frame to the second slave chip from the downlink data sending port of the first slave chip, where updating the address configuration command frame includes updating the offset of the address information in the address configuration command frame.

2. The method according to claim 1, wherein Before sending the address assignment instruction to the chip component, the method includes: Storing the identity identification information of the chip component and the initial address information of the chip component on a pre-set address space; Obtaining the address assignment instruction of the chip component and packing the address assignment instruction into an address configuration command frame according to the address space.

3. The method according to claim 2, wherein The address assignment instruction includes: a read address operation instruction, a parse address operation instruction, and a flag information instruction. Packing the address assignment instruction into an address configuration command frame according to the address space includes: Converting the read address operation instruction and the parse address operation instruction into a frame structure form and storing them in the address field of the address configuration command frame; Converting the flag information instruction into a frame structure form and storing it in the control field of the address configuration command frame.

4. The method according to claim 3, wherein Sending the address assignment instruction to the chip component includes: Sending the address configuration command frame to the chip component and operating on the chip component according to the address assignment instruction in the address configuration command frame.

5. An address allocation system for a chip component based on a series connection method, which is used to execute the method described in any one of claims 1-4, characterized in that, The system includes: A sending module for sending an address assignment instruction to a chip component, where the chip component includes a main control chip and several slave chips, and the main control chip is communicatively connected to the slave chips and adjacent slave chips in series; A receiving module for the main control chip to receive the address assignment instruction and sequentially assign chip addresses to the slave chips.

6. The system according to claim 5, wherein The system further includes: A storage module, configured to store the identity identification information of the chip component and the initial address information of the chip component on a pre-set address space; An acquisition module, configured to acquire an address allocation instruction of the chip component, and pack the address allocation instruction into an address configuration command frame according to the address space.

7. A storage medium, characterized in that, A computer program is stored in the storage medium, wherein the computer program is configured to execute the method described in any one of claims 1 to 4 when running.

8. An electronic device, comprising a memory and a processor, characterized in that, A computer program is stored in the memory, and the processor is configured to run the computer program to execute the method described in any one of claims 1 to 4.

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