A shielded gate MOSFET device and its manufacturing method

Abstract

This application discloses a shielded-gate MOSFET device and its fabrication method, belonging to the field of semiconductor devices and manufacturing. In this method, a thick oxide layer at the bottom of the trench serves as a thick dielectric layer for the shield gate. The trench is deposited and etched back, leaving the gate polysilicon on the trench sidewalls. The thin layer of polysilicon in the center of the trench is removed to fill the contact hole dielectric layer. Compared to related technologies that first deposit the source and then the gate polysilicon, this device uses deep contact holes instead of the polysilicon in the traditional shield gate, streamlining the process.

Description

Technical Field

[0001] The present application relates to the field of semiconductor devices and manufacturing, and in particular to a shielded gate MOSFET device and a manufacturing method thereof. Background Art

[0002] With the growing demand for electronic consumer products, the demand for MOSFETs is increasing, such as in applications such as drivers, electronic communications equipment, and power devices. MOSFET devices control drain current through gate voltage and are widely used due to their low drive power, low drive current, high input impedance, fast switching speed, and good thermal stability.

[0003] In related technologies, the design and manufacturing methods of MOSFET devices have been continuously improved. As market competition becomes more intense, the requirements for cost control are becoming increasingly higher. How to reduce manufacturing costs without reducing device performance is also an important research direction at present.

[0004] One of the main directions for controlling manufacturing costs is related to the number of photolithography times. Polysilicon deposition is achieved using a photolithography plate, and in related technologies, if polysilicon is deposited multiple times, the number of times the photolithography plate is used needs to be increased. Summary of the Invention

[0005] The present application provides a shielded gate MOSFET device and a manufacturing method thereof, which can solve the cost problem caused by the large number of photolithography times in related technologies.

[0006] In one aspect, an embodiment of the present application provides a method for manufacturing a shielded gate MOSFET device, the method comprising:

[0007] Providing a substrate 1, and etching a first trench S1 on the substrate 1;

[0008] Filling the bottom of the first trench S1 with a shield gate thick dielectric layer 2;

[0009] A gate dielectric layer 3 is formed above the shield gate thick dielectric layer 2 and on the inner wall of the first trench S1;

[0010] Depositing gate polysilicon 4 close to the sidewall of the gate dielectric layer 3;

[0011] Performing an ion implantation process to form a well 5 on both sides of the gate dielectric layer 3 and forming a source 6 above the well 5;

[0012] Depositing a contact hole dielectric layer 7 above the source 6 and the shield gate thick dielectric layer 2;

[0013] Etching the contact hole dielectric layer 7 to form a contact hole 71 above the shield gate thick dielectric layer 2, the gate polysilicon 4 and the source electrode 6;

[0014] A backside metal 8 is formed on the backside of the substrate 1 and a frontside metal 9 is filled in the contact hole 71 .

[0015] In another aspect, a shielded gate MOSFET device is provided, the device comprising at least:

[0016] A substrate 1 having a first deep trench S1; a shield gate thick dielectric layer 2 filling the bottom of the first deep trench S1; a gate polysilicon 4 formed above the shield gate thick dielectric layer 2; and a gate dielectric layer 3 provided on the sidewalls of the gate polysilicon 4, which is in close contact with the inner wall of the first deep trench S1.

[0017] A gate polysilicon 4 is formed on the shielding gate thick dielectric layer 2; a gate dielectric layer 3 is provided on the sidewalls of the gate polysilicon 4; a well 5 is provided on both sides of the gate dielectric layer 3; a source 6 is provided above the well 5; and a contact hole dielectric layer 7 covers the top of the shielding gate thick dielectric layer 2 and the top of the source 6;

[0018] A back metal 8 is formed on the back side of the substrate 1 ; and a front metal 9 is filled in the contact hole 71 above the well 5 , the gate polysilicon 4 and the shield gate thick dielectric layer 2 .

[0019] In summary, the present invention provides a device manufacturing method for a shielded gate MOSFET, including: providing a substrate, etching a first trench on the substrate; filling a shielding gate thick dielectric layer at the bottom of the first trench; forming a gate dielectric layer above the shielding gate thick dielectric layer and on the inner wall of the first trench; depositing gate polysilicon close to the sidewalls of the gate dielectric layer; performing an ion implantation process to form a well on both sides of the gate dielectric layer, and forming a source above the well; depositing a contact hole dielectric layer above the source and the shielding gate thick dielectric layer; etching the contact hole dielectric layer to form a contact hole above the shielding gate thick dielectric layer, the gate polysilicon and the source; forming a back metal on the back side of the substrate and filling a front metal in the contact hole. In an embodiment of the present application, a thick oxide layer process at the bottom of the trench is used as a thick dielectric layer for the shielding gate, a thin layer of polysilicon material is used to deposit the trench and after back-etching, the gate polysilicon on the trench sidewalls is left, and the thin layer of polysilicon in the middle of the trench is removed to fill the contact hole dielectric layer; compared with the related art of first depositing the source and then depositing the gate polysilicon, this device uses deep contact holes to replace the polysilicon in the traditional shielding gate, which has the effect of streamlining the process flow. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0021] Figure 1 is a flow chart of a method for manufacturing a shielded gate MOSFET device provided by an embodiment of the invention;

[0022] Figure 2-Figure 7 It is a semiconductor structure diagram in each process step of preparing a shielded gate MOSFET device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0023] The following is a clear and complete description of the technical solutions in this application in conjunction with the accompanying drawings. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0024] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this application and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0025] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal connections between two components; they can refer to wireless connections or wired connections. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0026] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0027] Please refer to Figure 1, which shows a schematic flow chart of a method for manufacturing a shielded gate MOSFET device provided in an exemplary embodiment of the present application, the method comprising:

[0028] Step 101: providing a substrate and etching a first trench on the substrate.

[0029] Step 102: Filling a shield gate thick dielectric layer at the bottom of the first trench.

[0030] Step 103 : forming a gate dielectric layer above the shield gate thick dielectric layer and on the inner wall of the first trench.

[0031] Step 104 : depositing gate polysilicon close to the sidewall of the gate dielectric layer.

[0032] Step 105 : Perform an ion implantation process to form wells on both sides of the gate dielectric layer, and form a source electrode above the well.

[0033] Step 106 : depositing a contact hole dielectric layer on the source and shield gate thick dielectric layers.

[0034] Step 107 , etching the contact hole dielectric layer to form a contact hole above the shield gate thick dielectric layer, the gate polysilicon, and the source electrode.

[0035] Step 108 : forming a backside metal layer on the backside of the substrate and filling the contact holes with a frontside metal layer.

[0036] Specifically, refer to Figure 2-Figure 7 , Figure 2-Figure 7 It is a semiconductor structure diagram in each process step of manufacturing a shielded gate MOSFET device according to an embodiment of the present invention.

[0037] First, if Figure 2 As shown, a substrate 1 is provided, and a first trench S1 is formed by etching on the substrate 1. Specifically, the substrate 1 can be one of single crystal silicon, polycrystalline silicon, amorphous silicon, or gallium arsenide, silicon gallium compound, etc., or a structure having silicon on an insulating layer or an epitaxial layer on silicon, etc., and examples are not given here one by one.

[0038] Then, if Figure 3 As shown, a shielding gate thick dielectric layer 2 is filled at the bottom of the first trench S1 , and the depth of the shielding gate thick dielectric layer 2 is lower than the depth of the first trench S1 .

[0039] like Figure 4 As shown, a gate dielectric layer 3 is formed above the shielding gate thick dielectric layer 2 and on the inner wall of the first trench S1. Further, as shown in FIG. Figure 5As shown, gate polysilicon 4 is deposited near the sidewall of the gate dielectric layer 3, wherein the formation of the gate polysilicon 4 includes the following: polysilicon 11 is deposited inside the first trench S1 and on the top of the substrate 1, wherein a thin layer of polysilicon is formed on the flat area above the shielding gate thick dielectric layer 2 and on the top of the substrate 1, and a thick layer of polysilicon is formed near the sidewall of the gate dielectric layer 3; the thin layer of polysilicon is removed, leaving the gate polysilicon 4 near the sidewall of the gate dielectric layer 3, and the gate polysilicon 4 is located above the shielding gate thick dielectric layer 2.

[0040] The thickness of the shielding gate thick dielectric layer 2 and the thickness of the gate dielectric layer 3 are not limited.

[0041] Continue to refer Figure 5 , an ion implantation process is performed to form wells 5 on both sides of the gate dielectric layer 3, and a source electrode 6 is formed above the well 5. Specifically, the material of the source electrode 6 can be a combination of any one or more metals selected from Ti, Pt, Au, W, and Ni, which is not limited in this embodiment of the present application.

[0042] refer to Figure 6 A contact hole dielectric layer 7 is deposited above the source 6 and the shielding gate thick dielectric layer 2. After the contact hole dielectric layer 7 is deposited, the contact hole dielectric layer 7 is etched to form a contact hole 71 above the shielding gate thick dielectric layer 2, the gate polysilicon 4 and the source 6.

[0043] Finally, if Figure 7 As shown, a back metal 8 is formed on the back side of the substrate 1 , and a front metal 9 is filled in the contact hole 71 .

[0044] In summary, the present invention provides a device manufacturing method for a shielded gate MOSFET, including: providing a substrate, etching a first trench on the substrate; filling a shielding gate thick dielectric layer at the bottom of the first trench; forming a gate dielectric layer above the shielding gate thick dielectric layer and on the inner wall of the first trench; depositing gate polysilicon close to the sidewalls of the gate dielectric layer; performing an ion implantation process to form a well on both sides of the gate dielectric layer, and forming a source above the well; depositing a contact hole dielectric layer above the source and the shielding gate thick dielectric layer; etching the contact hole dielectric layer to form a contact hole above the shielding gate thick dielectric layer, the gate polysilicon and the source; forming a back metal on the back side of the substrate and filling a front metal in the contact hole. In an embodiment of the present application, a thick oxide layer process is used at the bottom of the trench as a thick dielectric layer for the shielding gate. After the channel is deposited and etched back, the gate polysilicon on the trench sidewalls is left, and the thin layer of polysilicon in the middle of the trench is removed to fill the contact hole dielectric layer. Compared with the related art of first depositing gate polysilicon and then depositing shielding gate polysilicon, this device uses deep contact holes to replace the polysilicon in the traditional shielding gate, which has the effect of streamlining the process flow.

[0045] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of this application.

Claims

1. A method for manufacturing a shielded gate MOSFET device, characterized in that: The preparation method comprises: Providing a substrate (1), and etching a first trench (S1) on the substrate (1); Filling the bottom of the first trench (S1) with a shielding gate thick dielectric layer (2); forming a gate dielectric layer (3) above the shielding gate thick dielectric layer (2) and on the inner wall of the first trench (S1); Depositing gate polysilicon (4) close to the sidewall of the gate dielectric layer (3); Performing an ion implantation process to form wells (5) on both sides of the gate dielectric layer (3), and forming a source (6) above the well (5); Depositing a contact hole dielectric layer (7) above the source electrode (6) and the shielding gate thick dielectric layer (2); Etching the contact hole dielectric layer (7) to form a contact hole (71) above the shielding gate thick dielectric layer (2), the gate polysilicon (4) and the source electrode (6); A back metal (8) is formed on the back side of the substrate (1) and a front metal (9) is filled in the contact hole (71).

2. The method according to claim 1, characterized in that Depositing gate polysilicon (4) close to the sidewall of the gate dielectric layer (3), comprising: Depositing polysilicon (11) inside the first trench (S1) and on the top of the substrate (1), wherein a thin layer of polysilicon is formed on the flat area above the shielding gate thick dielectric layer (2) and on the top of the substrate (1), and a thick layer of polysilicon is formed close to the sidewall of the gate dielectric layer (3); The thin layer of polysilicon is removed, leaving the gate polysilicon (4) close to the side wall of the gate dielectric layer (3).

3. A shielded gate MOSFET device, characterized in that: The device comprises at least: A substrate (1) provided with a first trench (S1); a shielding gate thick dielectric layer (2) filled in the bottom of the first trench (S1); a gate polysilicon (4) formed above the shielding gate thick dielectric layer (2); and a gate dielectric layer (3) provided on the sidewall of the gate polysilicon (4) and closely attached to the inner wall of the first trench (S1); A gate polysilicon (4) formed above the shielding gate thick dielectric layer (2); a gate dielectric layer (3) provided on the sidewalls of the gate polysilicon (4); wells (5) on both sides of the gate dielectric layer (3); a source (6) provided above the well (5); and a contact hole dielectric layer (7) covering the top of the shielding gate thick dielectric layer (2) and the top of the source (6); A back metal (8) formed on the back side of the substrate (1); and a front metal (9) filled in the contact hole (71) above the well (5), the gate polysilicon (4), and the shielding gate thick dielectric layer (2).

4. The shielded gate MOSFET device according to claim 3, wherein: The depth of the gate dielectric layer (3) is the same as the depth of the gate polysilicon (4).

5. The shielded gate MOSFET device according to claim 3, wherein: The shielding gate thick dielectric layer (2) is filled in the first trench (S1).

6. The shielded gate MOSFET device according to claim 3, wherein: The substrate (1) is a silicon substrate, and an epitaxial layer is provided on the silicon substrate.

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