Fast recovery diode chip manufacturing method

Abstract

This invention provides a method for manufacturing a fast recovery diode chip, relating to the field of semiconductor technology. The method includes: phosphorus doping the back sides of a first wafer and a second wafer, wherein both the first and second wafers are N-type silicon single-crystal wafers; silicon-silicon bonding the phosphorus-doped first and second wafers; diffusion to form an N+ region and a buffer layer with gradually varying concentration on the back side of the first wafer; forming a planar termination protection structure on the front side of the first wafer; grinding away the second wafer; and metallizing the back side of the first wafer. This method innovatively uses silicon-silicon bonding technology, successfully replacing epitaxial wafers with silicon single-crystal wafers. The performance of the resulting fast recovery product essentially reaches that of epitaxial planar diode products, while significantly reducing the production cost of the fast recovery product, making it suitable for economical mass production.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a fast recovery diode chip. Background Art

[0002] Fast Recovery Diode (FRD) is a semiconductor power device with good switching characteristics and short reverse recovery time. It is often used as a high-frequency rectifier diode, freewheeling diode, and damping diode in power electronic circuits, and has great development prospects and market demand. From the perspective of withstand voltage range, FRD is mainly used in induction cookers, power supplies, variable frequency home appliances, variable frequency welding machines, electric vehicles and other products. The development of technology and the improvement of consumption levels have brought the application of semiconductor power devices into a wider field, and people have higher and higher requirements for the characteristics of semiconductor power devices and the requirements for cost reduction.

[0003] At present, FRD is generally designed and developed with PIN structure. As the application side has higher and higher requirements for circuit stability and lower and lower power consumption, the requirements for dynamic parameters of FRD are also getting higher and higher, especially the requirements for forward conduction voltage drop and reverse recovery characteristics. At present, double buffer structure is generally used for the design and manufacture of fast recovery products.

[0004] However, the FRDs with better performance are all manufactured using epitaxial wafers. As the breakdown voltage requirements become higher and higher, the thickness of the epitaxial layer of the corresponding epitaxial wafers also becomes thicker and thicker. The production cost of epitaxial wafers is relatively high, and the thickness of their epitaxial layers directly affects the procurement cost of epitaxial wafers. The cost of FRDs manufactured using epitaxial wafers is relatively high, and cannot meet the current demand for cost reduction. Summary of the invention

[0005] The purpose of the present invention includes providing a method for manufacturing a fast recovery diode chip, the performance of the fast recovery product produced by the method substantially reaches the performance of a planar epitaxial diode product, and the production cost of the fast recovery product is greatly reduced.

[0006] The embodiments of the present invention can be implemented as follows:

[0007] The present invention provides a method for manufacturing a fast recovery diode chip, and the method for manufacturing a fast recovery diode chip comprises:

[0008] Doping the back sides of the first wafer and the second wafer with phosphorus, wherein both the first wafer and the second wafer are N-type silicon single wafers;

[0009] Performing silicon-silicon bonding on the phosphorus-doped first wafer and the second wafer;

[0010] Diffusion forms an N+ region and a buffer layer with a gradient concentration on the back side of the first wafer;

[0011] forming a planar terminal protection structure on the front side of the first wafer;

[0012] grinding away the second wafer;

[0013] The back side of the first wafer is metallized.

[0014] In an optional embodiment, the step of phosphorus doping the back sides of the first wafer and the second wafer comprises:

[0015] Grinding and polishing the first wafer and the second wafer;

[0016] Phosphorus pre-expansion is performed on the polished surfaces of the first wafer and the second wafer.

[0017] In an optional embodiment, the step of performing phosphorus pre-expansion on the polished surfaces of the first wafer and the second wafer comprises:

[0018] The first wafer and the second wafer are subjected to phosphorus pre-diffusion using a POCl3 liquid source diffusion method.

[0019] In an optional embodiment, the step of performing silicon-silicon bonding on the phosphorus-doped first wafer and the second wafer comprises:

[0020] bonding the polished surfaces of the first wafer and the second wafer to each other;

[0021] Pre-bonding the first wafer and the second wafer by stacking and expanding;

[0022] The pre-bonded first wafer and second wafer are re-bonded and phosphorus re-expanded.

[0023] In an optional embodiment, the step of pre-bonding the bonded first wafer and the second wafer by stacking and expanding includes:

[0024] The first wafer and the second wafer are stacked together with their smooth sides facing smooth sides and their rough sides facing rough sides, and placed on a silicon plate boat with inserted rods, and a pressing block is placed on the top layer. The silicon plate boat is pushed into a furnace tube at a first preset temperature and evacuated to a preset vacuum degree for a first preset time to complete the pre-bonding of the first wafer and the second wafer.

[0025] In an optional embodiment, the thickness of the pressed block is greater than or equal to 1 cm.

[0026] In an optional embodiment, the first preset temperature is: 300-600°C, the preset vacuum degree is: 1-10Pa, and the first preset time is: 6-12 hours.

[0027] In an optional embodiment, the step of rebonding and re-expanding the pre-bonded first wafer and the second wafer comprises:

[0028] The silicon plate boat is taken out and directly transferred to the furnace tube for rebonding and phosphorus re-expansion at a second preset temperature for a second preset time.

[0029] In an optional embodiment, the second preset temperature is 1200-1280° C., and the second preset time is 20-40 hours.

[0030] In an optional embodiment, the step of forming a planar terminal protection structure on the front side of the first wafer includes:

[0031] After oxidation of the front side of the first wafer, the exit ring and main junction window are photoetched and P-doping and oxidation push-junction are completed;

[0032] Photolithography to etch out the N+ window and complete N+ doping and oxidation junction;

[0033] Photolithography is used to etch out the P+ window, and P+ doping and oxidation junction are completed;

[0034] Perform PSG deposition and photoetch to form contact holes;

[0035] Introduce heavy metal pt and perform diffusion annealing;

[0036] metallizing the front side of the first wafer;

[0037] A silicon nitride passivation protection layer is formed on the front side of the metallized first wafer.

[0038] The beneficial effects of the fast recovery diode chip manufacturing method provided by the embodiment of the present invention include:

[0039] This method innovatively uses silicon-silicon bonding technology and successfully replaces epitaxial wafers with silicon single crystals. The performance of the fast recovery products produced basically reaches that of planar epitaxial diode products, and the production cost of fast recovery products is greatly reduced, making it suitable for economical mass production. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0041] Figure 1 A flowchart of a method for manufacturing a fast recovery diode chip provided by an embodiment of the present invention;

[0042] Figure 2 A schematic diagram of a structure in which a first wafer and a second wafer are bonded to each other;

[0043] Figure 3 A schematic diagram of a structure in which a first wafer and a second wafer are pre-bonded in a stacking manner;

[0044] Figure 4 A schematic diagram of forming a planar terminal protection structure on the front side of a first wafer;

[0045] Figure 5 It is a schematic diagram of the structure after the back side of the first chip is metallized.

[0046] Icons: 10 - first chip; 11 - first doped region; 20 - second chip; 21 - second doped region; 30 - plug-in rod; 40 - silicon plate boat; 50 - press block; 60 - passivation protective layer; 70 - first metal layer; 80 - silicon nitride passivation protective layer; 90 - second metal layer. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0048] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0049] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0050] In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear to indicate an orientation or position relationship, they are based on the orientation or position relationship shown in the accompanying drawings, or are the orientation or position relationship in which the product of the invention is usually placed when used. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0051] In addition, the terms “first”, “second”, etc., if used, are merely used to distinguish between the descriptions and should not be understood as indicating or implying relative importance.

[0052] It should be noted that, in the absence of conflict, the features in the embodiments of the present invention may be combined with each other.

[0053] Please refer to Figure 1 This embodiment provides a method for manufacturing a fast recovery diode chip, the method comprising the following steps:

[0054] S1: phosphorus-doping the optical surfaces of the first wafer 10 and the second wafer 20.

[0055] The first wafer 10 and the second wafer 20 are both N-type silicon single wafers.

[0056] The specific process of phosphorus doping is: firstly, the first wafer 10 and the second wafer 20 are ground and polished; then, phosphorus pre-diffusion is performed on the ground and polished surfaces of the first wafer 10 and the second wafer 20. Specifically, the first wafer 10 and the second wafer 20 are pre-diffused with phosphorus using a POCl3 liquid source diffusion method, so that phosphorus diffuses into the wafer surface, and the square resistance can be made to 0.1-1.0Ω. In this way, a first doped region 11 is formed on the first wafer 10 (see Figure 2 ), a second doping region 21 is formed on the second wafer 20 (see Figure 2 ).

[0057] S2: Perform silicon-silicon bonding on the phosphorus-doped first wafer 10 and the second wafer 20 .

[0058] First, see Figure 2 The polished surfaces of the first wafer 10 and the second wafer 20 after phosphorus pre-expansion are bonded to each other.

[0059] Then, the first wafer 10 and the second wafer 20 are pre-bonded by stacking.

[0060] For details, please refer to Figure 3 , the first wafer 10 and the second wafer 20 are stacked together with the smooth surface facing the smooth surface and the rough surface facing the rough surface, and placed on the silicon plate boat 40 with the plug 30 inserted, and the pressing block 50 is placed on the top layer, and the silicon plate boat 40 is pushed into the furnace tube at the first preset temperature and evacuated to the preset vacuum degree, and the vacuum is continued for the first preset time, so as to complete the low-temperature pre-bonding of the first wafer 10 and the second wafer 20, so that the first wafer 10 and the second wafer 20 are stably bonded. Among them, the thickness of the pressing block 50 is greater than or equal to 1 cm, the first preset temperature is: 300-600℃, the preset vacuum degree is: 1-10Pa, and the first preset time is: 6-12 hours.

[0061] Finally, the pre-bonded first wafer 10 and second wafer 20 are re-bonded and phosphorus re-expanded.

[0062] Specifically, after the low-temperature pre-bonding is completed, the silicon plate boat 40 is taken out and directly transferred to the high-temperature furnace tube, and re-bonding and phosphorus re-expansion are continued at a second preset temperature for a second preset time, so that the light surfaces of the first wafer 10 and the second wafer 20 are firmly bonded together. The second preset temperature is: 1200-1280°C, and the second preset time is: 20-40 hours.

[0063] S3: Diffusion is performed on the back side of the first wafer 10 to form an N+ region and a buffer layer with a gradient concentration.

[0064] Of course, in other embodiments, phosphorus diffusion may be performed twice to form N - NN + structure.

[0065] S4: forming a planar terminal protection structure on the front side of the first wafer 10. That is, a reliable planar terminal protection structure is formed on the front side of the first wafer 10 through a series of production processes in the semiconductor chip manufacturing process.

[0066] See also Figure 4 , S4 specifically includes the following steps:

[0067] 1) After oxidation of the front side of the first wafer 10, a photolithography exit ring and a main junction window are performed, and P-doping and oxidation push-junction are completed;

[0068] 2) Photolithography to etch out the N+ window and complete N+ doping and oxidation junction;

[0069] 3) Photolithography to etch out the P+ window, and complete P+ doping and oxidation junction pushing; perform PSG deposition, and photolithography to etch out the contact hole;

[0070] 4) introducing heavy metal pt, and performing diffusion annealing, and performing heavy metal doping in the contact hole, wherein the passivation protection layer 60 may be a silicon oxide-based passivation protection layer, such as silicon dioxide, or a PSG film passivation protection layer;

[0071] 5) Metallizing the front surface of the first wafer 10 to form a first metal layer 70;

[0072] 6) A silicon nitride passivation protection layer 80 is formed on the front surface of the metallized first wafer 10 . The silicon nitride passivation protection layer 80 may also be replaced by polyimide.

[0073] S5: Grinding away the second wafer 20.

[0074] S6: Please refer to Figure 5 , the back side of the first wafer 10 is metalized to form a second metal layer 90 .

[0075] In this way, the manufacturing process of the fast recovery diode chip is completed.

[0076] The fast recovery diode chip manufacturing method provided in this embodiment is not limited to the manufacturing of planar fast recovery diodes, but can also be used in mesa structure fast recovery products.

[0077] The beneficial effects of the fast recovery diode chip manufacturing method provided in this embodiment include:

[0078] This method innovatively uses silicon-silicon bonding technology and successfully replaces epitaxial wafers with silicon single crystals. The performance of the fast recovery products produced basically reaches that of planar epitaxial diode products, and the production cost of fast recovery products is greatly reduced, making them suitable for economical mass production.

[0079] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A method for manufacturing a fast recovery diode chip, characterized in that: The fast recovery diode chip manufacturing method comprises: The back surfaces of a first wafer (10) and a second wafer (20) are doped with phosphorus, wherein the first wafer (10) and the second wafer (20) are both N-type silicon single wafers; The phosphorus-doped first wafer (10) and the second wafer (20) are subjected to silicon-silicon bonding, comprising: bonding the polished surfaces of the first wafer (10) and the second wafer (20) to each other; stacking the first wafer (10) and the second wafer (20) with their smooth surfaces facing each other and their rough surfaces facing each other, and placing them on a silicon plate boat (40) with a plug (30) inserted therein, placing a pressing block (50) on the top layer, pushing the silicon plate boat (40) into a furnace tube at a first preset temperature, and then evacuating to a preset vacuum. degree, for a first preset time, to complete pre-bonding of the first wafer (10) and the second wafer (20), the first preset temperature being 300-600° C., the preset vacuum degree being 1-10 Pa, and the first preset time being 6-12 hours; taking out the silicon plate boat (40), directly transferring it to a furnace tube, and re-bonding and phosphorus re-expansion at a second preset temperature for a second preset time, the second preset temperature being 1200-1280° C., and the second preset time being 20-40 hours; Diffusion forms an N+ region and a buffer layer with a gradient concentration on the back side of the first wafer (10); forming a planar terminal protection structure on the front side of the first wafer (10); Grinding away the second wafer (20); The back side of the first wafer (10) is metallized.

2. The method for manufacturing a fast recovery diode chip according to claim 1, characterized in that: The step of performing phosphorus doping on the back sides of the first wafer (10) and the second wafer (20) comprises: Grinding and polishing the first wafer (10) and the second wafer (20); Phosphorus pre-expansion is performed on the polished surfaces of the first wafer (10) and the second wafer (20).

3. The method for manufacturing a fast recovery diode chip according to claim 2, characterized in that: The step of performing phosphorus pre-expansion on the polished surfaces of the first wafer (10) and the second wafer (20) comprises: The first wafer (10) and the second wafer (20) are subjected to phosphorus pre-diffusion together using a POCl3 liquid source diffusion method.

4. The method for manufacturing a fast recovery diode chip according to claim 1, characterized in that: The thickness of the pressing block (50) is greater than or equal to 1 cm.

5. The method for manufacturing a fast recovery diode chip according to claim 1, characterized in that: The step of forming a planar terminal protection structure on the front side of the first wafer (10) comprises: After oxidation of the front side of the first wafer (10), a photolithography exit ring and a main junction window are formed, and P-doping and oxidation push-junction are completed; Photolithography to etch out the N+ window and complete N+ doping and oxidation junction; Photolithography is used to etch out the P+ window, and the P+ doping and oxidation junction are completed; Perform PSG deposition and photoetch to form contact holes; Introduce heavy metal pt and perform diffusion annealing; Metallizing the front side of the first wafer (10); A silicon nitride passivation protection layer (80) is formed on the front side of the metallized first wafer (10).

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