Semiconductor structure defect monitoring method and device, computer device and storage medium
By acquiring images of semiconductor structures and calculating geometric parameters, the problem of the inability to monitor capacitor defects online in existing technologies has been solved. This enables accurate identification and quantity statistics of capacitor defect types, improving the guidance and economy of the production process.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-05-31
- Publication Date
- 2026-07-21
AI Technical Summary
Existing technologies cannot accurately monitor capacitor defects and their types online during semiconductor manufacturing, leading to DRAM integrated circuit failures. Furthermore, traditional methods such as PFA are time-consuming, highly destructive, and costly.
By acquiring images of the semiconductor structure, the geometric parameters of the capacitor pillars and capacitor support structure openings are determined, including incomplete etching, capacitor pillar tilt, and capacitor pillar misalignment. Images are acquired using an electron microscope in backscattered electron mode, and the geometric parameters are calculated to determine the defect type.
It enables accurate online monitoring of capacitor defects and their types during the manufacturing process, qualitatively distinguishing defect types, quantitatively collecting defect quantities, guiding production process improvements, and reducing costs.
Smart Images
Figure CN114975153B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, and in particular to a method, apparatus, computer device, and storage medium for monitoring semiconductor structural defects. Background Technology
[0002] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory. DRAM typically includes capacitors and transistors. Capacitors store data, while transistors control access to the data stored in the capacitors. Therefore, capacitors are an essential component in DRAM integrated circuit manufacturing.
[0003] With the development of semiconductor technology, the aspect ratio of capacitors has been continuously increasing, reaching over 40. This inevitably leads to various defects in capacitors during the manufacturing process, causing DRAM integrated circuits to fail.
[0004] Traditional methods for determining capacitor structural defects include Physical Failure Analysis (PFA), which involves slicing the DRAM wafer to directly observe the capacitor structure. However, PFA is time-consuming, destructive, wasteful of wafers, and costly. Another method is in-circuit measurement, but typical in-circuit measurement methods can only determine if there is a large capacitor via misalignment, resulting in inaccurate measurements. Therefore, it is currently impossible to accurately monitor capacitor defects and their types in-circuit during the manufacturing process. Summary of the Invention
[0005] Therefore, it is necessary to provide a semiconductor structure defect monitoring method, device, computer equipment, and storage medium to address the problem in existing technologies that cannot accurately monitor capacitor defects and their types online during the manufacturing process.
[0006] To achieve the above objectives, in one respect, the present invention provides a semiconductor structure defect monitoring method, comprising:
[0007] An image of a semiconductor structure is acquired, the semiconductor structure including a plurality of spaced capacitor pillars, a capacitor support structure connecting the plurality of capacitor pillars, and at least one opening in the capacitor support structure, the image of the semiconductor structure including a pattern exposed at the top of the semiconductor structure;
[0008] Determine the geometric parameters of the capacitor column and the opening of the capacitor support structure;
[0009] Based on the geometric parameters, it is determined whether the semiconductor structure has capacitance defects, including at least one of insufficient etching, tilted capacitor pillars, and misaligned capacitor pillars.
[0010] In one embodiment, the capacitance defect includes insufficient etching, and the geometric parameters of the capacitor support structure opening include the area of the capacitor support structure opening; determining whether the semiconductor structure has a capacitance defect based on the geometric parameters includes:
[0011] Determine the area of the region in the opening of the capacitor support structure where the gray value is less than the gray value threshold;
[0012] Determine the area ratio of the region to the opening area of the capacitor support structure, and compare the area ratio with a ratio threshold.
[0013] If the area ratio is less than the ratio threshold, the semiconductor structure is determined to have an insufficient etching defect.
[0014] In one embodiment, determining whether the semiconductor structure has a capacitance defect based on the geometric parameters further includes:
[0015] If the area ratio is greater than or equal to the ratio threshold, then the semiconductor structure is determined to be free from defects caused by insufficient etching.
[0016] In one embodiment, the grayscale threshold is associated with the grayscale value of the standard capacitor support structure opening in an image of the semiconductor structure.
[0017] In one embodiment, the grayscale threshold is obtained based on the grayscale values of the openings of the standard capacitor support structure in different regions.
[0018] In one embodiment, the capacitance defect includes a tilted capacitor post, and determining the geometric parameters of the capacitor post includes:
[0019] Based on the center point of the capacitor column, fit an elliptic curve;
[0020] Calculate the ellipticity of the elliptic curve.
[0021] In one embodiment, determining whether the semiconductor structure has a capacitance defect based on the geometric parameters includes:
[0022] Compare the ellipticity with the ellipticity threshold;
[0023] If the ellipticity is greater than the ellipticity threshold, then the semiconductor structure is determined to have a defect of tilted capacitor pillars.
[0024] In one embodiment, determining whether the semiconductor structure has a capacitance defect based on the geometric parameters further includes:
[0025] If the ellipticity is less than or equal to the ellipticity threshold, then the semiconductor structure is determined to be free of defects such as tilted capacitor pillars.
[0026] In one embodiment, the tilting of the capacitor post includes the capacitor post moving closer to the ground and the capacitor post moving away from the ground. Determining the geometric parameters of the capacitor post further includes:
[0027] Obtain the distance between the center points of the two capacitor pillars adjacent to the opening of the capacitor support structure;
[0028] Determining whether the semiconductor structure has capacitance defects based on the geometric parameters further includes:
[0029] Compare the distance with a distance threshold;
[0030] If the ellipticity is greater than the ellipticity threshold and the distance is greater than the distance threshold, then the semiconductor structure is determined to have a defect of capacitor column misalignment.
[0031] If the ellipticity is greater than the ellipticity threshold and the distance is less than or equal to the distance threshold, then the semiconductor structure is determined to have a defect of close proximity of capacitor pillars.
[0032] In one embodiment, the capacitance defect further includes capacitor column misalignment. Determining whether the semiconductor structure has a capacitance defect based on the geometric parameters further includes:
[0033] If the ellipticity is less than or equal to the ellipticity threshold, and the center distance is outside the distance range, then the semiconductor structure is determined to have a defect of misaligned capacitor pillars.
[0034] In one embodiment, determining whether the semiconductor structure has a capacitance defect based on the geometric parameters further includes:
[0035] If the ellipticity is less than or equal to the ellipticity threshold and the center distance is within the specified distance range, then the semiconductor structure is determined to be free from defects such as capacitor pillar misalignment.
[0036] In one embodiment, acquiring an image of the semiconductor structure includes:
[0037] Images of the semiconductor structure were acquired using an electron microscope in backscattered electron mode.
[0038] On the other hand, the present invention also provides a semiconductor structure defect monitoring device, comprising:
[0039] An acquisition module is used to acquire an image of a semiconductor structure, the semiconductor structure including a plurality of spaced capacitor pillars, a capacitor support structure connecting the plurality of capacitor pillars, and at least one opening in the capacitor support structure, the image of the semiconductor structure including a pattern exposed at the top of the semiconductor structure;
[0040] A geometric parameter determination module is used to determine the geometric parameters of the capacitor column and the opening of the capacitor support structure;
[0041] The defect determination module is used to determine whether there is a capacitor defect in the semiconductor structure based on the geometric parameters. The capacitor defect includes at least one of insufficient etching, tilted capacitor pillars, and misaligned capacitor pillars.
[0042] In one embodiment, the capacitor defect includes insufficient etching, and the geometric parameters of the capacitor support structure opening include the area of the capacitor support structure opening; the defect judgment module includes:
[0043] An area determination unit is used to determine the area of the region in the opening of the capacitor support structure where the gray value is less than the gray threshold.
[0044] A ratio determination and comparison unit is used to determine the area ratio of the area of the region to the area of the opening of the capacitor support structure, and compare the area ratio with a ratio threshold.
[0045] An insufficient etching determination unit is used to determine that the semiconductor structure has an insufficient etching defect when the area ratio is less than the ratio threshold.
[0046] In one embodiment, the capacitance defect includes a tilted capacitor column, and the geometric parameter determination module includes:
[0047] The curve fitting unit is used to fit an elliptical curve based on the center point of the capacitor column;
[0048] An ellipticity calculation unit is used to calculate the ellipticity of the elliptic curve.
[0049] In one embodiment, the defect determination module includes:
[0050] An ellipticity comparison unit is used to compare the ellipticity with an ellipticity threshold.
[0051] A capacitor column tilt determination unit is used to determine that the semiconductor structure has a capacitor column tilt defect when the ellipticity is greater than the ellipticity threshold.
[0052] In one embodiment, the tilting of the capacitor column includes the capacitor column moving closer and the capacitor column moving away, and the geometric parameter determination module further includes:
[0053] The distance acquisition unit is used to acquire the distance between the center points of two capacitor pillars adjacent to the opening of the capacitor support structure;
[0054] The defect detection module also includes:
[0055] A distance comparison unit is used to compare the distance with a distance threshold;
[0056] The capacitor column tilt determination unit is used to determine that the semiconductor structure has a defect of capacitor column deviation when the ellipticity is greater than the ellipticity threshold and the distance is greater than the distance threshold; and to determine that the semiconductor structure has a defect of capacitor column proximity when the ellipticity is greater than the ellipticity threshold and the distance is less than or equal to the distance threshold.
[0057] In one embodiment, the capacitor defect further includes capacitor post misalignment, and the defect determination module further includes:
[0058] A capacitor column misalignment determination unit is used to determine that the semiconductor structure has a capacitor column misalignment defect when the ellipticity is less than or equal to the ellipticity threshold and the center distance is outside the distance range.
[0059] In another aspect, the present invention also provides a computer device, including a memory and a processor, wherein the memory stores a computer program that can run on the processor, and the processor executes the program to implement the steps of the semiconductor structure defect monitoring method provided by the present invention.
[0060] In another aspect, the present invention also provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the semiconductor structure defect monitoring method provided by the present invention.
[0061] The semiconductor structural defect monitoring method, apparatus, computer device, and storage medium of the present invention have the following beneficial effects:
[0062] By acquiring an image of a semiconductor structure, including multiple spaced capacitor pillars, a capacitor support structure connecting multiple capacitance values, and at least one opening in the capacitor support structure, the image of the semiconductor structure, including the exposed top view, allows for the determination of the geometric parameters of the capacitor pillars and the opening in the capacitor support structure. Furthermore, based on these geometric parameters, the presence of capacitor defects in the semiconductor structure can be determined. Capacitor defects include at least one of incomplete etching, capacitor pillar tilting, and capacitor pillar misalignment. This allows for accurate online monitoring of capacitor defects and their types during the manufacturing process. This qualitative differentiation of defect types and quantitative collection of defect quantities is beneficial for identifying and resolving problems in the production process and is of great significance for guiding subsequent production. Attached Figure Description
[0063] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0064] Figure 1 This is a cross-sectional view of a semiconductor structure provided in one embodiment;
[0065] Figure 2 A top view of a semiconductor structure provided in one embodiment;
[0066] Figure 3 This is a schematic diagram of an under-etched semiconductor structure provided in one embodiment;
[0067] Figure 4 This is a schematic diagram of a semiconductor structure near a capacitor pillar provided in one embodiment;
[0068] Figure 5 This is a schematic diagram of a semiconductor structure with a deviated capacitor pillar provided in one embodiment;
[0069] Figure 6 This is a schematic diagram of a semiconductor structure with misaligned capacitor pillars provided in one embodiment;
[0070] Figure 7 A flowchart of a semiconductor structure defect monitoring method provided in one embodiment;
[0071] Figure 8 This is a schematic diagram of a semiconductor structure image provided in one embodiment;
[0072] Figure 9 A flowchart of a semiconductor structure defect monitoring method provided in one embodiment;
[0073] Figure 10 This is a schematic diagram of a partial image of a semiconductor structure provided in one embodiment;
[0074] Figure 11 This is a schematic diagram of a partial image of a semiconductor structure provided in one embodiment;
[0075] Figure 12 A flowchart of a semiconductor structure defect monitoring method provided in one embodiment;
[0076] Figure 13 A flowchart of a semiconductor structure defect monitoring method provided in one embodiment;
[0077] Figure 14 A flowchart of a semiconductor structure defect monitoring method provided in one embodiment;
[0078] Figure 15 This is a structural block diagram of a semiconductor structural defect monitoring device provided in one embodiment;
[0079] Figure 16 This is an internal structural diagram of a computer device provided in one embodiment.
[0080] Explanation of reference numerals in the attached figures:
[0081] 100 - Semiconductor structure; 10 - Capacitor pillar; 20 - Capacitor support structure; 30 - Opening of capacitor support structure; 40 - Substrate. Detailed Implementation
[0082] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0083] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0084] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
[0085] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.
[0086] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0087] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of the invention, thus allowing for variations in the illustrated shape due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the invention.
[0088] The semiconductor structure defect monitoring method provided in this application embodiment can be applied to, for example... Figure 1 and Figure 2 The application environment shown. Figure 1 This is a cross-sectional view of a semiconductor structure provided in one embodiment. Figure 2 This is a top view of a semiconductor structure provided in one embodiment. Figure 1 and Figure 2 As shown, the semiconductor structure 100 includes a plurality of spaced capacitor pillars 10, a capacitor support structure 20 connecting the plurality of capacitor pillars 10, and at least one capacitor support structure opening 30. The plurality of capacitor pillars 10 are disposed on the substrate 40, each capacitor support structure opening 30 is located between the plurality of capacitor pillars 10, and the plurality of capacitor pillars 10 are arranged around the corresponding capacitor support structure opening 30.
[0089] Ideally, there are no residues within the opening 30 of the capacitor support structure, the capacitor pillars 10 are vertically positioned on the substrate 40, and the distance between adjacent capacitor pillars 10 is within a set range. In practical applications, the aspect ratio of the capacitor pillars is as high as 40 or more, which may lead to the following three defects:
[0090] First, insufficient etching resulted in residue within the opening 30 of the capacitor support structure. For example... Figure 3 As shown, there are remnants in the capacitor support structure opening 30 at the circle that are significantly higher than the normal plane.
[0091] Second, a defect occurs where the capacitor pillars are tilted, causing the top and bottom centers of capacitor pillar 10 to not coincide. For example... Figure 4 As shown, the top of one capacitor post 10 is close to the top of another capacitor post 10 at the circled area. In this case, the center of the top and bottom of this capacitor post 10 does not coincide, and the distance between the centers of the two capacitor posts 10 is much smaller than the normal distance, resulting in a defect where the capacitor posts are too close together. Figure 5As shown, the top of one capacitor post 10 at the circled area is far from the top of the other capacitor post 10. At this point, the center of the top and bottom of this capacitor post 10 does not coincide, but the distance between the centers of the two capacitor posts 10 is much greater than the normal distance, indicating a capacitor post misalignment defect. Both capacitor post misalignment and capacitor post proximity defects fall under the category of capacitor post tilting defects.
[0092] Third, a defect occurs where the capacitor pillars are misaligned, resulting in a distance between the centers of two capacitor pillars 10 that is much smaller than normal, or a distance between the centers of two capacitor pillars 10 that is much larger than normal. In this case, the centers of the top and bottom of the capacitor pillars 10 coincide, meaning that the capacitor pillars 10 are vertically positioned on the substrate 40. Figure 6 As shown, the three capacitor pillars 10 at the circle are vertically arranged on the substrate 40. The distance between the centers of the two capacitor pillars 10 on the left is much smaller than the normal distance, while the distance between the centers of the two capacitor pillars 10 on the right is much larger than the normal distance.
[0093] The semiconductor structure can be, but is not limited to, DRAM integrated circuits. The presence of at least one of the three defects mentioned above in the capacitor pillars can lead to DRAM integrated circuit failure. Therefore, it is necessary to monitor capacitor defects and their types online during the manufacturing process to facilitate the resolution of problems in the production process.
[0094] Please see Figure 7 This invention provides a method for monitoring semiconductor structural defects, using this method to... Figures 1-6 Taking defect monitoring of a semiconductor structure as an example, the following steps are included:
[0095] Step S702: Obtain an image of the semiconductor structure.
[0096] The semiconductor structure includes multiple spaced capacitor pillars, a capacitor support structure connecting the multiple capacitor pillars, and at least one opening in the capacitor support structure. The image of the semiconductor structure includes a pattern showing the exposed top of the semiconductor structure.
[0097] Step S704: Determine the geometric parameters of the capacitor column and the opening of the capacitor support structure.
[0098] Step S706: Determine whether there are capacitance defects in the semiconductor structure based on the geometric parameters.
[0099] Among them, capacitor defects include at least one of insufficient etching, tilted capacitor pillars, and misaligned capacitor pillars.
[0100] The aforementioned semiconductor structure defect monitoring method acquires an image of the semiconductor structure, which includes multiple spaced capacitor pillars, a capacitor support structure connecting multiple capacitance values, and at least one opening in the capacitor support structure. The image includes the top view of the semiconductor structure. Based on the image, the geometric parameters of the capacitor pillars and the opening in the capacitor support structure can be determined. Furthermore, based on these geometric parameters, the presence of capacitor defects in the semiconductor structure can be determined. Capacitor defects include at least one of incomplete etching, capacitor pillar tilting, and capacitor pillar misalignment. This method allows for accurate online monitoring of capacitor defects and their types during the manufacturing process. This qualitative differentiation of defect types and quantitative collection of defect quantities is beneficial for identifying and resolving problems in the production process and is of great significance for guiding subsequent production.
[0101] In one embodiment, step S702 includes: acquiring an image of the semiconductor structure using an electron microscope in backscattered electron mode.
[0102] Specifically, a scanning electron microscope (SEM) is placed above a semiconductor structure to capture images of it. SEM is an observation method that falls between transmission electron microscopy and optical microscopy. It uses a narrow, focused beam of high-energy electrons to scan the sample. Through the interaction between the beam and the material, various physical information is excited, collected, amplified, and re-imaged to characterize the microscopic morphology of the material.
[0103] For example, the PRO Vision 2E electron beam measurement system, set to high-voltage mode, captures backscattered electron imaging (BSE) images of semiconductor structures within a field of view (FOV). Backscattered electrons are a subset of incident electrons reflected back by atomic nuclei in a solid sample; they include both elastic and inelastic backscattered electrons. Backscattered electrons have high energies, a significant portion of which are close to the incident electron energy E0, resulting in a large area of backscattered electrons within the sample and low imaging resolution.
[0104] Figure 8 This is a schematic diagram of a semiconductor structure image acquired by SEM in BSE mode according to one embodiment. Identification is performed based on the grayscale levels corresponding to each region of the semiconductor structure image, such as... Figure 8 As shown, the semiconductor structure image includes multiple capacitor pillars 10, capacitor support structures 20 connecting the multiple capacitor pillars 10, and multiple capacitor support structure openings 30. Each capacitor support structure opening 30 is located between the multiple capacitor pillars 10, and the multiple capacitor pillars 10 are arranged around the corresponding capacitor support structure opening 30.
[0105] In the above embodiments, an electron microscope is used to acquire images of the semiconductor structure in backscattered electron mode. Based on the acquired semiconductor images, the geometric parameters of the capacitor pillars and the openings of the capacitor support structure can be determined, thereby determining whether there are capacitor defects in the conductor structure and realizing online monitoring of capacitor manufacturing defects.
[0106] Please see Figure 9 In one embodiment, the capacitor defect includes insufficient etching, and the geometric parameters of the capacitor support structure opening include the area of the capacitor support structure opening. The method specifically includes the following steps:
[0107] Step S902: Obtain an image of the semiconductor structure.
[0108] The semiconductor structure includes multiple spaced capacitor pillars, a capacitor support structure connecting the multiple capacitor pillars, and at least one opening in the capacitor support structure. The image of the semiconductor structure includes a pattern showing the exposed top of the semiconductor structure.
[0109] Step S904: Determine the opening area of the capacitor support structure.
[0110] Specifically, step S904 includes: performing image recognition on the image of the semiconductor structure to determine the outlines of the capacitor pillars and the openings of the capacitor support structure; and determining the area of the openings of the capacitor support structure based on the distribution of the outlines of the capacitor pillars and the openings of the capacitor support structure in the image of the semiconductor structure.
[0111] For example, the opening area of the capacitor support structure is the total area of the opening of the capacitor support structure and the capacitor column adjacent to it.
[0112] Step S906: Determine the area of the region in the opening of the capacitor support structure where the gray value is less than the gray value threshold.
[0113] The grayscale threshold is a grayscale value between insufficient and sufficient etching. If the grayscale value of the capacitor support structure opening is greater than the grayscale threshold, it is considered insufficient etching; if the grayscale value is less than the grayscale threshold, it is considered sufficient etching. In practical applications, etching residues may be distributed in part or all of the area of the capacitor support structure opening. Determining the area of the capacitor support structure opening where the grayscale value is less than the grayscale threshold allows us to obtain the area of the capacitor support structure opening not covered by residues.
[0114] Specifically, step S906 includes: performing image recognition on the image of the semiconductor structure to determine the outline of the opening of the capacitor support structure; and determining the area of the region in the opening of the capacitor support structure with a gray value less than the gray value threshold based on the distribution position of the outline of the opening of the capacitor support structure in the semiconductor structure.
[0115] Step S908: Determine the area ratio of the region area to the opening area of the capacitor support structure, and compare the area ratio with the ratio threshold.
[0116] In step S910, if the area ratio is less than the ratio threshold, it is determined that the semiconductor structure has a defect of insufficient etching.
[0117] Figure 10 This is a schematic diagram of a partial image of a semiconductor structure provided in one embodiment. Figure 10 As shown, a partial image of the semiconductor structure includes a complete capacitor support structure opening 30 and multiple capacitor pillars 10 arranged around this opening 30. The area of the region within the opening 30 with a grayscale value less than the grayscale threshold is relatively small compared to the area of the opening 30 itself, indicating an insufficient etching defect in the semiconductor structure.
[0118] In step S912, if the area ratio is greater than or equal to the ratio threshold, it is determined that the semiconductor structure does not have a defect of insufficient etching.
[0119] Figure 11 This is a schematic diagram of a partial image of a semiconductor structure provided in another embodiment. Figure 11 As shown, a partial image of the semiconductor structure includes a complete capacitor support structure opening 30 and multiple capacitor pillars 10 arranged around this opening 30. The area of the region in the capacitor support structure opening 30 with a grayscale value lower than the grayscale threshold is larger than the area of the opening 30 itself, indicating that the semiconductor structure does not have defects due to insufficient etching.
[0120] In this embodiment, step S706 is achieved by executing steps S906, S908, S910 and S912.
[0121] In the above embodiments, the metrology-based inspection (MBI) method determines whether there is an etching defect in the semiconductor structure. It can use semiconductor images to identify etching defects in the semiconductor structure and judges the defects based on the area ratio of the area of the region with a gray value less than the gray value threshold in the opening of the capacitor support structure to the area of the opening of the capacitor support structure. The larger the area ratio, the smaller the possibility of etching defects. The defects with an area ratio less than the ratio threshold are judged as etching defects. It is not affected by factors such as shooting distance, which may cause the size of the opening of the capacitor support structure in the semiconductor structure image to be different. The accuracy of the structure judgment is high.
[0122] For example, the grayscale threshold is associated with the grayscale value of the standard capacitor support structure opening in the image of the semiconductor structure.
[0123] Among them, the standard capacitor support structure opening is a capacitor support structure opening without any residue in the semiconductor structure, such as... Figure 3 The capacitor support structure opening is located at the circle in the middle of the image. Specifically, an image of the semiconductor structure including the standard capacitor support structure opening can be captured, and the grayscale value of the standard capacitor support structure opening can be obtained from this semiconductor structure image. A grayscale threshold can then be determined, such as using a process control grayscale threshold corresponding to the grayscale value of the standard capacitor support structure opening obtained from this semiconductor structure image as the grayscale threshold.
[0124] In practical applications, semiconductor structure images contain a large number of capacitor support structure openings. Most of these openings have no residue. Therefore, the gray level distribution of the capacitor support structure openings in the semiconductor structure image can be statistically analyzed, and the gray level of most of the capacitor support structure openings can be determined as the gray level threshold.
[0125] For example, the grayscale threshold is obtained based on the grayscale value of the openings of the standard capacitor support structure in different regions.
[0126] The regions may include, but are not limited to, the central and edge regions of the semiconductor structure. Specifically, the average grayscale value of the openings of the standard capacitor support structure in different regions is first calculated, and then the grayscale threshold is determined based on the average value to take into account the differences in grayscale values between the openings of the standard capacitor support structure in different regions.
[0127] Please see Figure 12 In one embodiment, the capacitor defect includes a tilted capacitor post, the geometric parameters of which include the ellipticity of the capacitor post. The method specifically includes the following steps:
[0128] Step S1202: Obtain an image of the semiconductor structure.
[0129] The semiconductor structure includes multiple spaced capacitor pillars, a capacitor support structure connecting the multiple capacitor pillars, and at least one opening in the capacitor support structure. The image of the semiconductor structure includes a pattern showing the exposed top of the semiconductor structure.
[0130] Step S1204: Fit an elliptical curve based on the center point of the capacitor column.
[0131] Specifically, step S1204 includes: performing image recognition on the image of the semiconductor structure to determine the outline of the capacitor pillar and the center point of the capacitor pillar; and fitting the minimum elliptical curve that surrounds the outline of the capacitor pillar with the center point of the capacitor pillar as the center.
[0132] Step S1206: Calculate the ellipticity of the elliptic curve.
[0133] Step S1208: Compare the ellipticity with the ellipticity threshold.
[0134] Step S1210: If the ellipticity is greater than the ellipticity threshold, it is determined that the semiconductor structure has a defect of tilted capacitor pillars.
[0135] Step S1212: If the ellipticity is less than or equal to the ellipticity threshold, it is determined that the semiconductor structure does not have a defect of tilted capacitor pillars.
[0136] In this embodiment, step S704 is achieved by executing steps S1204 and S1206, and step S706 is achieved by executing steps S1208, S1210 and S1212.
[0137] In the above embodiments, the ellipticity of the capacitor pillars is calculated using images of the semiconductor structure, and the tilting defect of the capacitor pillars can be identified based on the ellipticity. While capacitor pillars are theoretically circular, in practice, considering process variations, they may be elliptical. Characterizing this ellipticity, if the capacitor pillar is tilted, a trailing effect will appear in the semiconductor structure image. If the ellipticity exceeds the process control specifications, it indicates that the centers of the top and bottom of the capacitor pillar do not coincide. In this case, it is determined that the semiconductor structure has a tilting defect, and the judgment result is more consistent with the actual situation.
[0138] For example, the tilting of the capacitor column includes the capacitor column moving closer and the capacitor column moving away. The geometric parameters of the capacitor column also include the distance between the center points of two capacitor columns adjacent to the opening of the capacitor support structure. Step S704 further includes: obtaining the distance between the center points of two capacitor columns adjacent to the opening of the capacitor support structure.
[0139] Specifically, obtaining the distance between the center points of the two capacitor pillars adjacent to the opening of the capacitor support structure includes: performing image recognition on an image of the semiconductor structure to determine the distribution position of the center points of the two capacitor pillars adjacent to the opening of the capacitor support structure in the image of the semiconductor structure; and determining the distance between the center points of the two capacitor pillars adjacent to the opening of the capacitor support structure based on the distribution position of the center points of the two capacitor pillars adjacent to the opening of the capacitor support structure in the image of the semiconductor structure.
[0140] Accordingly, step S1210 includes: if the distance between the center points of two capacitor pillars adjacent to the opening of the capacitor support structure is greater than a distance threshold, it is determined that the semiconductor structure has a defect of capacitor pillar deviation; if the distance between the center points of two capacitor pillars adjacent to the opening of the capacitor support structure is less than or equal to the distance threshold, it is determined that the semiconductor structure has a defect of capacitor pillar proximity.
[0141] In the above embodiment, based on the determination that the semiconductor structure has a defect of tilted capacitor pillars, the distance between the center points of two capacitor pillars adjacent to the opening of the capacitor support structure is obtained again using an image of the semiconductor structure. If this distance is greater than a distance threshold, the tilt of the capacitor pillars in the semiconductor structure is determined to be specifically a deviation of the capacitor pillars; if this distance is less than or equal to the distance threshold, the tilt of the capacitor pillars in the semiconductor structure is determined to be specifically a convergence of the capacitor pillars.
[0142] Please see Figure 13 In one embodiment, the capacitor defect includes capacitor post misalignment, wherein the geometric parameters of the capacitor post include the ellipticity of the capacitor post and the distance between the center points of two capacitor posts adjacent to the opening of the capacitor support structure. The method specifically includes the following steps:
[0143] Step 1302: Obtain an image of the semiconductor structure.
[0144] The semiconductor structure includes multiple spaced capacitor pillars, a capacitor support structure connecting the multiple capacitor pillars, and at least one opening in the capacitor support structure. The image of the semiconductor structure includes a pattern showing the exposed top of the semiconductor structure.
[0145] Step S1304: Fit an elliptical curve based on the center point of the capacitor column, and calculate the ellipticity of the elliptical curve.
[0146] Step S1306: Obtain the distance between the center points of the two capacitor pillars adjacent to the opening of the capacitor support structure.
[0147] Step S1308: If the ellipticity is less than or equal to the ellipticity threshold, and the distance between the center points of the two capacitor pillars adjacent to the opening of the capacitor support structure is outside the distance range, then it is determined that the semiconductor structure has a defect of capacitor pillar misalignment.
[0148] Step S1310: If the ellipticity is less than or equal to the ellipticity threshold, and the distance between the center points of the two capacitor pillars adjacent to the opening of the capacitor support structure is within the distance range, then it is determined that the semiconductor structure does not have a defect of capacitor pillar misalignment.
[0149] In this embodiment, step S704 is achieved by executing steps S1304 and S1306, and step S706 is achieved by executing steps S1308, S1310 and S1312.
[0150] In the above embodiments, if the ellipticity of the ellipse is within the process control specifications, it indicates that the centers of the top and bottom of the capacitor pillars coincide, and the semiconductor structure does not have a capacitor pillar tilt defect. Further, the distance between the center points of two capacitor pillars adjacent to the opening of the capacitor support structure is obtained. If the distance between the center points of the two capacitor pillars adjacent to the opening of the capacitor support structure is outside the specified range, it is determined that the semiconductor structure has a capacitor pillar misalignment defect; if the distance between the center points of the two capacitor pillars adjacent to the opening of the capacitor support structure is within the specified range, it is determined that the semiconductor structure does not have a capacitor pillar misalignment defect.
[0151] Please see Figure 14 In one embodiment, capacitor defects include insufficient etching, tilted capacitor pillars, and misaligned capacitor pillars. The method specifically includes the following steps:
[0152] Step 1402: Obtain an image of the semiconductor structure.
[0153] The semiconductor structure includes multiple spaced capacitor pillars, a capacitor support structure connecting the multiple capacitor pillars, and at least one opening in the capacitor support structure. The image of the semiconductor structure includes a pattern showing the exposed top of the semiconductor structure.
[0154] Step S1404: Determine the opening area of the capacitor support structure.
[0155] Step S1406: Determine the area of the region in the opening of the capacitor support structure where the gray value is less than the gray value threshold.
[0156] Step S1408: Determine the area ratio of the region area to the opening area of the capacitor support structure, and compare the area ratio with the ratio threshold.
[0157] In step S1410, if the area ratio is less than the ratio threshold, it is determined that the semiconductor structure has a defect of insufficient etching.
[0158] Step S1412: Fit an elliptical curve based on the center point of the capacitor column, and calculate the ellipticity of the elliptical curve.
[0159] Step S1414: Obtain the distance between the center points of the two capacitor pillars adjacent to the opening of the capacitor support structure.
[0160] Step S1416: If the ellipticity is greater than the ellipticity threshold and the distance between the center points of the two capacitor pillars adjacent to the opening of the capacitor support structure is greater than the distance threshold, then it is determined that the semiconductor structure has a defect of capacitor pillar deviation.
[0161] Step S1418: If the ellipticity is greater than the ellipticity threshold, and the distance between the center points of the two capacitor pillars adjacent to the opening of the capacitor support structure is less than or equal to the distance threshold, then it is determined that the semiconductor structure has a defect of capacitor pillars being too close together.
[0162] Step S1420: If the ellipticity is less than or equal to the ellipticity threshold, and the distance between the center points of the two capacitor pillars adjacent to the opening of the capacitor support structure is outside the distance range, then it is determined that there is a defect of capacitor pillar misalignment in the semiconductor structure.
[0163] Step S1422: If the area ratio is greater than or equal to the ratio threshold, and the ellipticity is less than or equal to the ellipticity threshold, and the distance between the center points of the two capacitor pillars adjacent to the opening of the capacitor support structure is within the distance range, then it is determined that there is no capacitor defect in the semiconductor structure.
[0164] Specifically, the judgment results are shown in Table 1 below:
[0165] Table 1: Results of Capacitor Defect Judgment
[0166] serial number Insufficient etching Ellipticity Distance from the center point of the capacitor Capacitor defects 1 No defects normal normal No defects 2 No defects normal bad Capacitor column misalignment 3 No defects bad Less than the threshold capacitor post near 4 No defects bad Greater than the threshold capacitor column deviation 5 bad normal normal Insufficient etching 6 bad normal bad Insufficient etching + misaligned capacitor posts 7 bad bad Less than the threshold Insufficient etching + capacitor pillars close together 8 bad bad Greater than the threshold Insufficient etching + capacitor post misalignment
[0167] In one embodiment, the method further includes uploading the determination result to a statistical process control system (SPC chart system).
[0168] Specifically, the measurement equipment is set to upload the judgment results for online monitoring.
[0169] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.
[0170] Based on the same inventive concept, this application also provides a semiconductor structure defect monitoring device for implementing the semiconductor structure defect monitoring method described above. The solution provided by this device is similar to the implementation described in the above method; therefore, the specific limitations in one or more embodiments of the semiconductor structure defect monitoring device provided below can be found in the limitations of the semiconductor structure defect monitoring method described above, and will not be repeated here.
[0171] In one embodiment, such as Figure 15As shown, a semiconductor structural defect monitoring device 1500 is provided, including: an acquisition module 1501, a geometric parameter determination module 1502, and a defect judgment module 1503, wherein:
[0172] The acquisition module 1501 is used to acquire an image of a semiconductor structure, the semiconductor structure including a plurality of spaced capacitor pillars, a capacitor support structure connecting the plurality of capacitor pillars, and at least one opening in the capacitor support structure, the image of the semiconductor structure including a pattern exposed on the top of the semiconductor structure.
[0173] The geometric parameter determination module 1502 is used to determine the geometric parameters of the capacitor column and the opening of the capacitor support structure.
[0174] The defect judgment module 1503 is used to determine whether there are capacitor defects in the semiconductor structure based on geometric parameters. The capacitor defects include at least one of insufficient etching, tilted capacitor pillars, and misaligned capacitor pillars.
[0175] In one embodiment, the capacitor defect includes insufficient etching, and the geometric parameters of the capacitor support structure opening include the area of the capacitor support structure opening. The defect judgment module 1503 includes an area determination unit, a ratio determination and comparison unit, and an insufficient etching judgment unit.
[0176] The area determination unit is used to determine the area of the region in the opening of the capacitor support structure where the gray value is less than the gray value threshold.
[0177] The ratio determination comparison unit is used to determine the area ratio of the region area to the opening area of the capacitor support structure, and compare the area ratio with the ratio threshold.
[0178] The insufficient etching determination unit is used to determine that there is an insufficient etching defect in the semiconductor structure when the area ratio is less than the proportional threshold.
[0179] For example, the insufficient etching determination unit is also used to determine that the semiconductor structure does not have an insufficient etching defect when the area ratio is greater than or equal to the ratio threshold.
[0180] For example, the grayscale threshold is associated with the grayscale value of the standard capacitor support structure opening in the image of the semiconductor structure.
[0181] For example, the grayscale threshold is obtained based on the grayscale value of the openings of the standard capacitor support structure in different regions.
[0182] In one embodiment, the capacitor defect includes a tilted capacitor column, and the geometric parameter determination module 1502 includes a curve fitting unit and an ellipticity calculation unit.
[0183] The curve fitting unit is used to fit an elliptical curve based on the center point of the capacitor column.
[0184] Ellipticity calculation unit, used to calculate the ellipticity of elliptic curves.
[0185] For example, the defect judgment module 1503 includes an ellipticity comparison unit and a capacitor column tilt judgment unit.
[0186] Ellipticity comparison unit is used to compare ellipticity with an ellipticity threshold.
[0187] The capacitor pillar tilt determination unit is used to determine that the semiconductor structure has a defect of capacitor pillar tilt when the ellipticity is greater than the ellipticity threshold.
[0188] For example, the capacitor pillar tilt determination unit is also used to determine that the semiconductor structure does not have a defect of capacitor pillar tilt when the ellipticity is less than or equal to the ellipticity threshold.
[0189] For example, the tilting of the capacitor column includes the capacitor column moving closer and the capacitor column moving away, and the geometric parameter determination module 1502 also includes a distance acquisition unit.
[0190] The distance acquisition unit is used to acquire the distance between the center points of two capacitor pillars adjacent to the opening of the capacitor support structure.
[0191] The defect detection module also includes a distance comparison unit.
[0192] The distance comparison unit is used to compare the distance with a distance threshold.
[0193] The capacitor pillar tilt determination unit is used to determine that the semiconductor structure has a defect of capacitor pillar deviation when the ellipticity is greater than the ellipticity threshold and the distance is greater than the distance threshold; and to determine that the semiconductor structure has a defect of capacitor pillar proximity when the ellipticity is greater than the ellipticity threshold and the distance is less than or equal to the distance threshold.
[0194] For example, the capacitor defect also includes capacitor post misalignment, and the defect judgment module 1503 also includes a capacitor post misalignment judgment unit.
[0195] The capacitor column misalignment determination unit is used to determine that there is a defect of capacitor column misalignment in the semiconductor structure when the ellipticity is less than or equal to the ellipticity threshold and the distance is outside the distance range.
[0196] For example, the capacitor pillar misalignment determination unit is also used to determine that the semiconductor structure does not have a defect of capacitor pillar misalignment when the ellipticity is less than or equal to the ellipticity threshold and the distance is within the distance range.
[0197] In one embodiment, the acquisition module 1501 is used to acquire images of semiconductor structures using an electron microscope in backscattered electron mode.
[0198] Each module in the aforementioned semiconductor structural defect monitoring device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can call and execute the corresponding operations of each module.
[0199] In one embodiment, a computer device is provided, the internal structure of which can be shown as follows: Figure 16 As shown, the computer device includes a processor, memory, communication interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, NFC (Near Field Communication), or other technologies. When executed by the processor, the computer program implements a semiconductor structural defect monitoring method. The display screen can be a liquid crystal display (LCD) or an e-ink display. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad mounted on the computer device casing, or an external keyboard, touchpad, or mouse.
[0200] Those skilled in the art will understand that Figure 16 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.
[0201] In one embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above-described method embodiments.
[0202] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps in the above method embodiments.
[0203] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.
[0204] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties.
[0205] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.
[0206] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0207] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A method for monitoring semiconductor structural defects, characterized in that, include: An image of a semiconductor structure is acquired, the semiconductor structure including a plurality of spaced capacitor pillars, a capacitor support structure connecting the plurality of capacitor pillars, and at least one opening in the capacitor support structure, the image of the semiconductor structure including a pattern exposed at the top of the semiconductor structure; Determine the geometric parameters of the capacitor column and the opening of the capacitor support structure; Based on the geometric parameters, it is determined whether the semiconductor structure has capacitance defects, including at least one of insufficient etching, tilted capacitor pillars, and misaligned capacitor pillars. The capacitor defect includes insufficient etching, and the geometric parameters of the capacitor support structure opening include the area of the capacitor support structure opening. Determining whether the semiconductor structure has capacitance defects based on the geometric parameters includes: Determine the area of the region in the opening of the capacitor support structure where the gray value is less than the gray value threshold; Determine the area ratio of the region to the opening area of the capacitor support structure, and compare the area ratio with a ratio threshold. If the area ratio is less than the ratio threshold, the semiconductor structure is determined to have an insufficient etching defect.
2. The method according to claim 1, characterized in that, Determining whether the semiconductor structure has capacitance defects based on the geometric parameters further includes: If the area ratio is greater than or equal to the ratio threshold, then the semiconductor structure is determined to be free from defects caused by insufficient etching.
3. The method according to claim 1, characterized in that, The grayscale threshold is associated with the grayscale value of the standard capacitor support structure opening in the image of the semiconductor structure.
4. The method according to claim 3, characterized in that, The grayscale threshold is obtained based on the grayscale value of the opening of the standard capacitor support structure in different regions.
5. The method according to claim 1, characterized in that, The capacitor defect includes a tilted capacitor column, and the geometric parameters of the capacitor column are determined as follows: Based on the center point of the capacitor column, fit an elliptic curve; Calculate the ellipticity of the elliptic curve.
6. The method according to claim 5, characterized in that, Determining whether the semiconductor structure has capacitance defects based on the geometric parameters includes: Compare the ellipticity with the ellipticity threshold; If the ellipticity is greater than the ellipticity threshold, then the semiconductor structure is determined to have a defect of tilted capacitor pillars.
7. The method according to claim 6, characterized in that, Determining whether the semiconductor structure has capacitance defects based on the geometric parameters further includes: If the ellipticity is less than or equal to the ellipticity threshold, then the semiconductor structure is determined to be free of defects such as tilted capacitor pillars.
8. The method according to claim 6, characterized in that, The tilting of the capacitor column includes both the capacitor column moving closer to the ground and the capacitor column moving away from the ground. Determining the geometric parameters of the capacitor column also includes: Obtain the distance between the center points of the two capacitor pillars adjacent to the opening of the capacitor support structure; Determining whether the semiconductor structure has capacitance defects based on the geometric parameters further includes: The distance between the center points of the two capacitor pillars adjacent to the opening of the capacitor support structure is compared with a distance threshold. If the ellipticity is greater than the ellipticity threshold, and the distance between the center points of the two capacitor pillars adjacent to the opening of the capacitor support structure is greater than the distance threshold, then the semiconductor structure is determined to have a defect of capacitor pillar deviation. If the ellipticity is greater than the ellipticity threshold, and the distance between the center points of the two capacitor pillars adjacent to the opening of the capacitor support structure is less than or equal to the distance threshold, then the semiconductor structure is determined to have a defect of capacitor pillars being too close together.
9. The method according to claim 8, characterized in that, The capacitance defect also includes capacitor column misalignment. Determining whether the semiconductor structure has a capacitance defect based on the geometric parameters further includes: If the ellipticity is less than or equal to the ellipticity threshold, and the distance between the center points of the two capacitor pillars adjacent to the opening of the capacitor support structure is outside the distance range, then the semiconductor structure is determined to have a defect of capacitor pillar misalignment.
10. The method according to claim 9, characterized in that, Determining whether the semiconductor structure has capacitance defects based on the geometric parameters further includes: If the ellipticity is less than or equal to the ellipticity threshold, and the distance between the center points of the two capacitor pillars adjacent to the opening of the capacitor support structure is within the distance range, then it is determined that the semiconductor structure does not have a defect of capacitor pillar misalignment.
11. The method according to any one of claims 1-10, characterized in that, Acquire images of semiconductor structures, including: Images of the semiconductor structure were acquired using an electron microscope in backscattered electron mode.
12. A semiconductor structural defect monitoring device, characterized in that, include: An acquisition module is used to acquire an image of a semiconductor structure, the semiconductor structure including a plurality of spaced capacitor pillars, a capacitor support structure connecting the plurality of capacitor pillars, and at least one opening in the capacitor support structure, the image of the semiconductor structure including a pattern exposed at the top of the semiconductor structure; A geometric parameter determination module is used to determine the geometric parameters of the capacitor column and the opening of the capacitor support structure; The defect determination module is used to determine whether there is a capacitor defect in the semiconductor structure based on the geometric parameters. The capacitor defect includes at least one of insufficient etching, tilted capacitor pillars, and misaligned capacitor pillars. The capacitor defect includes insufficient etching, and the geometric parameters of the capacitor support structure opening include the area of the capacitor support structure opening. The defect detection module includes: An area determination unit is used to determine the area of the region in the opening of the capacitor support structure where the gray value is less than the gray threshold. A ratio determination and comparison unit is used to determine the area ratio of the area of the region to the area of the opening of the capacitor support structure, and compare the area ratio with a ratio threshold. An insufficient etching determination unit is used to determine that the semiconductor structure has an insufficient etching defect when the area ratio is less than the ratio threshold.
13. The apparatus according to claim 12, characterized in that, The capacitor defect includes a tilted capacitor column, and the geometric parameter determination module includes: The curve fitting unit is used to fit an elliptical curve based on the center point of the capacitor column; An ellipticity calculation unit is used to calculate the ellipticity of the elliptic curve.
14. The apparatus according to claim 13, characterized in that, The defect detection module includes: An ellipticity comparison unit is used to compare the ellipticity with an ellipticity threshold. A capacitor column tilt determination unit is used to determine that the semiconductor structure has a capacitor column tilt defect when the ellipticity is greater than the ellipticity threshold.
15. The apparatus according to claim 14, characterized in that, The tilting of the capacitor column includes the capacitor column moving closer to the ground and the capacitor column moving away from the ground. The geometric parameter determination module further includes: The distance acquisition unit is used to acquire the distance between the center points of two capacitor pillars adjacent to the opening of the capacitor support structure; The defect detection module also includes: A distance comparison unit is used to compare the distance between the center points of the two capacitor pillars adjacent to the opening of the capacitor support structure with a distance threshold. The capacitor column tilt determination unit is used to determine that the semiconductor structure has a defect of capacitor column deviation when the ellipticity is greater than the ellipticity threshold and the distance between the center points of the two capacitor columns adjacent to the opening of the capacitor support structure is greater than the distance threshold; and to determine that the semiconductor structure has a defect of capacitor column proximity when the ellipticity is greater than the ellipticity threshold and the distance between the center points of the two capacitor columns adjacent to the opening of the capacitor support structure is less than or equal to the distance threshold.
16. The apparatus according to claim 15, characterized in that, The capacitor defect also includes misaligned capacitor posts, and the defect detection module further includes: A capacitor column misalignment determination unit is used to determine that the semiconductor structure has a capacitor column misalignment defect when the ellipticity is less than or equal to the ellipticity threshold and the distance between the center points of the two capacitor columns adjacent to the opening of the capacitor support structure is outside the distance range.
17. A computer device comprising a memory and a processor, wherein the memory stores a computer program executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the method according to any one of claims 1-11.
18. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1-11.