A three-dimensional integrated silicon-based inertial microsystem with embedded microchannels and a manufacturing method thereof

Abstract

The present application relates to a three-dimensional integrated silicon-based inertial microsystem with embedded microchannels and a manufacturing method thereof, including a first passive adapter board, a second passive adapter board, a third passive adapter board, and a fourth passive adapter board that are electrically connected in sequence. A first active chip is electrically connected to the surface of the second passive adapter board facing the third passive adapter board. A cavity for accommodating the first active chip is provided in the third passive adapter board. A second active chip is provided on the fourth passive connection board. A first heat dissipation system, a second heat dissipation system, a third heat dissipation system, and a fourth heat dissipation system are sequentially provided on the first passive adapter board, the second passive adapter board, the third passive adapter board, and the fourth passive adapter board. The first heat dissipation system includes two bottom grooves opened on the surface of the first passive adapter board and a cavity connecting the two bottom grooves. The second heat dissipation system, the third heat dissipation system, and the fourth heat dissipation system are interconnected and respectively communicate with the two bottom grooves to form heat dissipation microchannels, improving the heat dissipation effect.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a three-dimensional integrated silicon-based inertial microsystem with embedded microchannels and a manufacturing method thereof. Background Art

[0002] As inertial microsystems continue to develop in the direction of miniaturization and high performance, the number of devices integrated in inertial microsystems continues to increase, and the packaging density continues to increase. The increase in the amount of data processed has caused a sharp increase in the power consumption of processors, power supplies, and dedicated integrated circuits in inertial microsystems, and the increase in packaging density has made it difficult for chips to dissipate heat. Both of these factors will cause the temperature of the chip to rise sharply, causing reliability problems for MEMS inertial devices, processors, power supplies, dedicated integrated circuits, and other chips. In severe cases, it will lead to the failure of the inertial microsystem. Therefore, three-dimensional integrated silicon-based inertial microsystems face very severe reliability issues, and microfluidic heat dissipation is an effective solution to this problem. Microfluidics can not only help silicon-based inertial microsystems to dissipate heat effectively, but also adapt to the integrated manufacturing process of silicon-based inertial microsystems without the need to introduce new equipment. Summary of the invention

[0003] The object of the present invention is to provide a three-dimensional integrated silicon-based inertial microsystem with embedded microfluidic channels and a manufacturing method thereof, so as to solve the problem of heat dissipation difficulty of the existing three-dimensional integrated inertial microsystem.

[0004] In the first aspect, the present application provides a three-dimensional integrated silicon-based inertial microsystem with embedded microfluidic channels, which adopts the following technical solutions:

[0005] A three-dimensional integrated silicon-based inertial microsystem with embedded microfluidic channels comprises a first passive adapter board, a second passive adapter board, a third passive adapter board and a fourth passive adapter board which are electrically connected in sequence, a first active chip is electrically connected to the surface of the second passive adapter board facing the third passive adapter board, a cavity for accommodating the first active chip is provided on the surface of the third passive adapter board facing the second passive adapter board, a second active chip is provided on the side of the fourth passive connecting board away from the third passive connecting board, a first heat dissipation system is provided on the first passive adapter board, a second heat dissipation system is provided on the second passive adapter board, a third heat dissipation system is provided on the third passive adapter board, and a fourth heat dissipation system is provided on the fourth passive connecting board; the first heat dissipation system comprises two bottom grooves provided on the surface of the first passive adapter board facing the second passive adapter board, and a cavity connecting the two bottom grooves, the second heat dissipation system, the third heat dissipation system and the fourth heat dissipation system are connected, and are respectively connected with the two bottom grooves to form a heat dissipation microfluidic channel.

[0006] The formed heat dissipation microchannel is as follows: the heat dissipation fluid enters the first bottom groove through the fourth heat dissipation system, the third heat dissipation system and the second heat dissipation system, then flows out from the second bottom groove through the cavity, and finally flows out through the second heat dissipation system, the third heat dissipation system and the fourth heat dissipation system.

[0007] A first groove structure is formed on the surface of the first passive adapter board relative to the second passive adapter board. The first groove structure is a cavity connecting the two bottom grooves.

[0008] The second heat dissipation system includes a second groove structure. The second groove structure is formed on the surface of the second passive adapter board relative to the first passive adapter board. The second groove structure is aligned with the first groove structure, and the first groove structure and the second groove structure form a cavity connecting the two bottom grooves.

[0009] The first groove structure and the second groove structure include a plurality of strip-shaped grooves. The ends of adjacent two strip-shaped grooves are connected to form a serpentine flow channel.

[0010] The strip-shaped grooves are perpendicular to the connection line of the central positions of the two bottom grooves.

[0011] The serpentine flow channel covers the entire first active chip.

[0012] The second heat dissipation system further includes a second inlet and a second outlet formed on the second passive adapter board. The second inlet and the second outlet are aligned with the two bottom grooves. The third heat dissipation system includes a third inlet and a third outlet formed on the third passive adapter board. The fourth heat dissipation system includes a fourth inlet and a fourth outlet formed on the fourth passive adapter board. The fourth inlet, the third inlet and the second inlet are sequentially connected to the first bottom groove, and the fourth outlet, the third outlet and the second outlet are sequentially connected to the second bottom groove.

[0013] The size of the fourth inlet is larger than that of the third inlet, and the size of the fourth outlet is larger than that of the third outlet.

[0014] Two distribution grooves are formed on the surface of the second passive adapter board facing the first adapter board, which are respectively aligned with the bottom grooves. The cross-sectional size of the distribution grooves is larger than that of the second inlet and the second outlet.

[0015] An intermediate passive adapter layer can be selectively arranged between the second passive adapter board and the third passive adapter board. The intermediate passive adapter layer includes a passive adapter board support layer, a passive adapter isolation layer and an active chip layer which are sequentially arranged and electrically connected in the direction from the second passive adapter board to the third passive adapter board. The passive adapter board support layer has the same structure as the third passive adapter board. Through holes communicating with the second heat dissipation system and the third heat dissipation system are formed in the passive adapter board support layer and the passive adapter isolation layer.

[0016] The passive transfer partition is a passive transfer board partition; or the passive transfer partition includes a passive transfer first partition and a passive transfer second partition which are arranged in sequence from bottom to top and electrically connected, the passive transfer first partition is provided with a first through hole connected to the second heat dissipation system and the third heat dissipation system, the passive transfer second partition is provided with a second through hole connected to the first through hole and the third heat dissipation system, the surfaces facing each other of the passive transfer first partition and the passive transfer second partition are respectively provided with groove structures I and groove structures II facing each other, and the cavity formed between the groove structure I and the groove structure II connects the first through hole and the second through hole.

[0017] The first passive adapter is provided with a first interconnection system, the second passive adapter is provided with a second interconnection system, the third passive connection board is provided with a third interconnection system, the fourth passive connection board is provided with a fifth interconnection system, the fourth interconnection system is formed on the first active chip, and the sixth interconnection system is formed on the second active chip. The first passive adapter and the second passive adapter are electrically connected through the first interconnection system and the second interconnection system, the first active chip is electrically connected to the second passive adapter through the second interconnection system and the fourth interconnection system, the second passive adapter is electrically connected to the third passive adapter through the second interconnection system and the third interconnection system, the third passive adapter is electrically connected to the fourth passive adapter through the third interconnection system and the fifth interconnection system, and the fourth passive adapter is electrically connected to the second active chip through the fifth interconnection system and the sixth interconnection system.

[0018] The first interconnection system includes a first TSV structure, a first insulating layer, a first bonding pad, and a first bump structure arranged on a first passive transfer board. The first TSV structure is filled with a conductive material for signal interconnection. The first insulating layer is located on both sides of the first passive transfer board facing toward and away from the second passive insulating board. The first bonding pad is arranged on both sides of the first passive transfer board facing toward and away from the second passive insulating board. The first bump structure is welded to the first bonding pad and is located on the side of the first passive transfer board away from the second passive connection board.

[0019] The second interconnection system includes a second TSV structure, a second insulating layer, a second bonding pad, and a second redistribution layer arranged on the second passive adapter. The second TSV structure is filled with a conductive material for signal interconnection. The second insulating layer is located on both sides of the second passive adapter facing toward and away from the first passive adapter. The second passive adapter is provided with a second bonding pad on both sides facing toward and away from the first passive adapter. A second redistribution layer is provided on the side of the second passive adapter away from the first passive adapter.

[0020] The first bonding pad is electrically connected to the second bonding pad.

[0021] The third interconnection system includes a third TSV structure, a third insulating layer, and a third bonding pad arranged on the third passive transfer board. The third TSV structure is filled with metal or low-resistance silicon for signal interconnection. The third insulating layer is located on both sides of the third passive transfer board facing toward and away from the second passive transfer board. The third bonding pad is arranged on both sides of the third passive transfer board facing toward and away from the second passive transfer board.

[0022] The third bonding pad is electrically connected to the second bonding pad.

[0023] The fourth interconnection system includes a fourth bump structure and a fourth underfill material disposed on the first active chip. The fourth bump structure is located on a side of the first active chip facing the second passive adapter board, and the first active chip is electrically connected to the second redistribution layer. The fourth bump structure is filled with the fourth underfill material after being electrically connected.

[0024] The first active chip includes at least one active chip.

[0025] The first active chip is a high-power chip. Specifically, the first active chip includes at least one of a processor in a silicon-based inertial microsystem, a dedicated integrated circuit chip, and the like.

[0026] The fifth interconnection system includes a fifth TSV structure, a fifth insulating layer, a fifth bonding pad, and a fifth redistribution layer arranged on the fourth passive transfer board. The fifth TSV structure is filled with conductive material for signal interconnection. The fifth insulating layer is located on both sides of the fourth passive transfer board facing toward and away from the third insulating board. The fourth passive transfer board is provided with fifth bonding pads on both sides facing toward and away from the third insulating board. The fifth redistribution layer is located on the side of the fourth passive transfer board away from the third passive transfer board.

[0027] The fifth bonding pad is electrically connected to the third bonding pad.

[0028] The sixth interconnection system includes a sixth bump structure and a sixth underfill material disposed on the second active chip. The sixth bump structure is located on a side of the second active chip facing the fourth passive connection board. The sixth bump structure is electrically connected to the fifth redistribution layer. The bump structure of the second active chip is filled with the underfill material after being electrically connected.

[0029] The second active chip includes at least one active chip.

[0030] The second active chip is a low-power chip. Specifically, the second active chip includes at least one of a MEMS accelerometer sensitive structure and a MEMS gyroscope sensitive structure in a silicon-based inertial microsystem.

[0031] The conductive material filled in the first TSV structure, the second TSV structure, the third TSV structure, and the fifth TSV structure is at least one of copper, low-resistance silicon, tungsten, and silver.

[0032] The materials of the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer are silicon dioxide.

[0033] The materials of the fourth underfill material and the sixth underfill material are resin.

[0034] The materials of the first bonding pad, the second bonding pad, the third bonding pad, the fifth bonding pad, the second redistribution layer, and the fifth redistribution layer are at least one of copper and gold.

[0035] The optional bump materials of the first bump structure include at least one of SnAg and SnAgCu.

[0036] The optional bump materials of the fourth bump structure and the sixth bump structure include at least one of SnBi and SnPb.

[0037] In a second aspect, the present application provides a manufacturing method for a three-dimensional integrated silicon-based inertial microsystem with an embedded microchannel, adopting the following technical solutions:

[0038] A manufacturing method for a three-dimensional integrated silicon-based inertial microsystem with an embedded microchannel includes the following steps:

[0039] S1: Form a first interconnection system and a first heat dissipation system on a first passive adapter board, form a second interconnection system and a second heat dissipation system on a second passive adapter board, form a third interconnection system and a third heat dissipation system on a third passive adapter board, and form a fifth interconnection system and a fourth heat dissipation system on a fourth passive adapter board; form a fourth interconnection system on a first active chip and a sixth interconnection system on a second active chip;

[0040] S2: Electrically connect the first passive adapter board and the second passive adapter board through the first interconnection system and the second interconnection system, electrically connect the first active chip and the second passive adapter board through the second interconnection system and the fourth interconnection system, electrically connect the second passive adapter board and the third passive adapter board through the second interconnection system and the third interconnection system, electrically connect the third passive adapter board and the fourth passive adapter board through the third interconnection system and the fifth interconnection system, and electrically connect the fourth passive adapter board and the second active chip through the fifth interconnection system and the sixth interconnection system; at the same time, the first heat dissipation system, the second heat dissipation system, the third heat dissipation system, and the fourth heat dissipation system are connected through to form a heat dissipation microchannel.

[0041] In summary, the beneficial effects of the present invention compared with the prior art are:

[0042] (1) The three-dimensional integrated silicon-based inertial microsystem with embedded microchannels realizes that the passive adapter board under the active chip has both the functions of electrical signal conduction and heat dissipation. Its main microchannel process is carried out on the passive adapter board, which causes little damage to the active chip.

[0043] (2) The three-dimensional integrated silicon-based inertial microsystem with embedded microchannels dissipates the heat of the active chip to the outside of the microsystem through the heat dissipation fluid in the passive adapter board, with good heat dissipation effect and high thermal reliability of the system.

[0044] (3) The process of the microchannel heat dissipation system is adapted to the three-dimensional integration process of the silicon-based inertial microsystem, without the need to introduce new equipment and with low cost. Description of the Drawings

[0045] Figure 1 and Figure 9 are schematic cross-sectional views of the three-dimensional integrated silicon-based inertial microsystem with embedded microchannels according to an embodiment of the present invention;

[0046] Figure 2 is a schematic structural view of the first passive adapter board;

[0047] Figure 3 is a schematic structural view of the second passive adapter board;

[0048] Figure 4 is a schematic assembly structure view between the first passive adapter board and the second passive adapter board;

[0049] Figure 5 is a schematic structural view of the third passive adapter board;

[0050] Figure 6 is a schematic assembly structure view among the first passive adapter board, the second passive adapter board, and the first active chip;

[0051] Figure 7 is a schematic structural view of the fourth passive adapter board;

[0052] Figure 8 is a schematic assembly structure view between the fourth passive adapter board and the second active chip;

[0053] Figure 10 is a schematic top view of the three-dimensional integrated silicon-based inertial microsystem with embedded microchannels according to an embodiment of the present invention.

[0054] Figure 11 is a schematic top view of the first groove structure according to an embodiment of the present invention.

[0055] Description of the Reference Numerals:

[0056] 10. First passive adapter board; 11. First interconnection system; 111. First TSV structure; 112. First insulating layer; 113. First bonding pad; 114. First bump structure; 12. First heat dissipation system; 121. First groove structure; 122. First bottom groove ； 123. Second bottom groove ；

[0057] 20. Second passive adapter board; 21. Second interconnection system; 211. Second TSV structure; 212. Second insulating layer; 213. Second bonding pad; 214. Second redistribution layer; 22. Second heat dissipation system; 221. Second groove structure; 222. Second inlet; 223. Second outlet;

[0058] 30. Third passive adapter board; 31. Third interconnection system; 311. Third TSV structure; 312. Third insulating layer; 313. Third bonding pad; 32. Third heat dissipation system; 321. Third inlet; 322. Third outlet; 33. Cavity;

[0059] 40. First active chip; 41. Fourth interconnection system; 411. Fourth bump structure; 412. Fourth underfill material;

[0060] 50. Fourth passive adapter board; 51. Fifth interconnection system; 511. Fifth TSV structure; 512. Fifth insulating layer; 513. Fifth bonding pad; 514. Fifth redistribution layer; 52. Fourth heat dissipation system; 521. Fourth inlet; 522. Fourth outlet;

[0061] 60. Second active chip; 61. Sixth interconnection system; 611. Sixth bump structure; 612. Sixth underfill material. Detailed implementation manners

[0062] The following further describes the present application in detail with reference to the accompanying drawings and specific embodiments:

[0063] It should be noted that the accompanying drawings are all in very simplified forms and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0064] The core idea of the present invention is to provide a three-dimensional integrated silicon-based inertial microsystem with embedded microchannels and a manufacturing method thereof to solve the problem of difficult heat dissipation in existing three-dimensional integrated inertial microsystems.

[0065] To achieve the above idea, the embodiments of the present application disclose a three-dimensional integrated silicon-based inertial microsystem with embedded microchannels and a manufacturing method thereof.

[0066] As Figure 1 and Figure 9As shown in the figure, a three-dimensional integrated silicon-based inertial microsystem with embedded microchannels includes a first passive adapter board 10, a second passive adapter board 20, a third passive adapter board 30, a fourth passive adapter board 50, which are electrically connected in sequence, and an optional intermediate passive adapter layer located between the bottom passive adapter layer and the top passive adapter layer. Microchannels for the flow of heat dissipation fluid are formed between the first passive adapter board 10, the second passive adapter board 20, the intermediate passive adapter layer, the third passive adapter board 30, and the fourth passive adapter board 50, improving the heat dissipation effect of the microsystem.

[0067] As Figures 2 - 8 shown in the figure, on the surface of the second passive adapter board 20 facing the third passive adapter board 30, a first active chip 40 is electrically connected. On the surface of the third passive adapter board 30 facing the second passive adapter board 20, a cavity 33 for accommodating the first active chip 40 is provided. On the side of the fourth passive connection board facing away from the third passive connection board, a second active chip 60 is provided.

[0068] The first passive adapter board 10 is provided with a first heat dissipation system 12, and the second passive adapter board 20 is provided with a second heat dissipation system 22; the third passive adapter board 30 is provided with a third heat dissipation system 32, and the fourth passive adapter board 50 is provided with a fourth heat dissipation system 52.

[0069] As Figure 2 shown in the figure, the first heat dissipation system 12 includes two non-connected first bottom grooves 122 and second bottom grooves 123 formed on the surface of the first passive adapter board 10 facing the second passive adapter board 20. Between the first bottom groove 122 and the second bottom groove 123, a first groove structure 121 for connecting the first bottom groove 122 and the second bottom groove 123 is provided. The first groove structure 121 is formed on the surface of the first passive adapter board 10 facing the second passive adapter board 20. The first groove structure 121 includes a plurality of strip grooves, and the ends of adjacent two strip grooves are connected to form a serpentine flow channel.

[0070] As Figure 3 and Figure 4 shown in the figure, the second heat dissipation system 22 includes a second inlet 222, a second outlet 223 formed on the second passive adapter board 20, and a second groove structure 221 formed on the surface of the second passive adapter board 20 facing the first passive adapter board 10. The second groove structure 221 is in one-to-one correspondence with the first groove structure 121, and the first groove structure 121 and the second groove structure 221 form a cavity connecting the two bottom grooves 122 and 123. The second inlet (222) faces the first bottom groove (122), and the second outlet (223) faces the second bottom groove (123).

[0071] As Figures 5 - 8As shown, the third heat dissipation system 32 includes a third inlet 321 and a third outlet 322 formed in the third passive adapter board 30; the fourth heat dissipation system 52 includes a fourth inlet 521 and a fourth outlet 522 formed in the fourth passive adapter board 50; the fourth inlet 521, the third inlet 321, and the second inlet 222 are sequentially connected to the first bottom groove 122, and the fourth outlet 522, the third outlet 322, and the second outlet 223 are sequentially connected to the second bottom groove 123. This enables the first heat dissipation system 12, the second heat dissipation system 22, the third heat dissipation system 32, and the fourth heat dissipation system 52 to be connected through, forming a heat dissipation microchannel: the heat dissipation fluid enters the first bottom groove 122 through the fourth inlet 521, the third inlet 321, and the second inlet 222, then flows out of the second bottom groove 123 through the cavity, and finally flows out through the second outlet 223, the third outlet 322, and the fourth outlet 522.

[0072] As Figure 1 shown, the size of the fourth inlet 521 is larger than that of the third inlet 321, and the size of the fourth outlet 522 is larger than that of the third outlet 322. This enables the smooth injection and outflow of the coolant. On the surface of the second passive adapter board 20 facing the first adapter board, two distribution grooves are formed that are respectively and directly opposite to the first bottom groove 122 and the second bottom groove 123, and the cross-sectional size of the distribution grooves is larger than that of the second inlet 222 and the second outlet 223. The distribution grooves have the same size as the first bottom groove 122 and the second bottom groove 123, jointly forming a channel that facilitates the distribution of the heat dissipation fluid.

[0073] The intermediate passive adapter layer includes a passive adapter board support layer, a passive adapter isolation layer, and an active chip layer that are sequentially arranged from bottom to top and electrically connected. The passive adapter board support layer has the same structure as the third passive adapter board 30. The passive adapter board support layer and the passive adapter isolation layer are provided with through holes that communicate with the second heat dissipation system 22 and the third heat dissipation system 32. Specifically, the passive adapter isolation layer can be a passive adapter board partition; the passive adapter isolation layer can also include a passive adapter first partition and a passive adapter second partition that are sequentially arranged from bottom to top and electrically connected. The passive adapter first partition is provided with a first through hole that communicates with the second heat dissipation system 22 and the third heat dissipation system 32, and the passive adapter second partition is provided with a second through hole that communicates with the first through hole and the third heat dissipation system 32. On the surfaces of the passive adapter first partition and the passive adapter second partition that face each other, groove structures Ⅰ and groove structures Ⅱ are respectively and directly opposite, and the cavity formed between the groove structures Ⅰ and groove structures Ⅱ communicates the first through hole and the second through hole. Specifically, in this embodiment, the intermediate passive adapter layer is not provided.

[0074] As Figure 1As shown, the first passive transfer board 10 is provided with a first interconnection system 11, the second passive transfer board 20 is provided with a second interconnection system 21, the third passive connection board is provided with a third interconnection system, the fourth passive connection board is provided with a fifth interconnection system, the fourth interconnection system 41 is formed on the first active chip 40, and the sixth interconnection system 61 is formed on the second active chip 60. The first passive transfer board 10 and the second passive transfer board 20 are electrically connected through the first interconnection system 11 and the second interconnection system 21, the first active chip 40 is electrically connected to the second passive transfer board 20 through the second interconnection system 21 and the fourth interconnection system, the second passive transfer board 20 is electrically connected to the third passive transfer board 30 through the second interconnection system and the third interconnection system, the third passive transfer board 30 is electrically connected to the fourth passive transfer board 50 through the third interconnection system and the fifth interconnection system, and the fourth passive transfer board 50 is electrically connected to the second active chip 60 through the fifth interconnection system and the sixth interconnection system.

[0075] like Figure 2 As shown, the first interconnection system includes a first TSV structure 111, a first insulating layer 112, a first bonding pad 113, and a first bump structure 114 disposed on the first passive transfer board 10. The first insulating layer 112 is located on both sides of the first passive transfer board 10 facing toward and away from the second passive insulating board. The first bonding pad 113 is disposed on both sides of the first passive transfer board 10 facing toward and away from the second passive insulating board. The first bump structure 114 is welded to the first bonding pad 113 and is located on the side of the first passive transfer board 10 away from the second passive connection board.

[0076] like Figure 3 and Figure 4 As shown, the second interconnection system includes a second TSV structure 211, a second insulating layer 212, a second bonding pad 213, and a second redistribution layer 214 disposed on the second passive transfer board 20. The second insulating layer 212 is located on both sides of the second passive transfer board 20 facing toward and away from the first passive transfer board 10. The second bonding pad 213 is disposed on both sides of the second passive transfer board 20 facing toward and away from the first passive transfer board 10. The second redistribution layer 214 is disposed on the side of the second passive transfer board 20 away from the first passive transfer board 10. The first bonding pad 113 is electrically connected to the second bonding pad 213.

[0077] like Figure 5 As shown, the third interconnection system 31 includes a third TSV structure 311, a third insulating layer 312, and a third bonding pad 313 disposed on the third passive transfer board 30. The third insulating layer 312 is located on both sides of the third passive transfer board 30 facing toward and away from the second passive transfer board 20. The third bonding pad 313 is disposed on both sides of the third passive transfer board 30 facing toward and away from the second passive transfer board 20. The third bonding pad 313 is electrically connected to the second bonding pad 213.

[0078] like Figure 6 As shown, the fourth interconnection system 41 includes a fourth bump structure 411 and a fourth underfill material 412 disposed on the first active chip 40. The fourth bump structure 411 is located on the side of the first active chip 40 facing the second passive transfer board 20, and the first active chip 40 is electrically connected to the second redistribution layer 214. The fourth underfill material 412 is filled between the fourth bump structure 411 and the second redistribution layer 214.

[0079] like Figure 7 As shown, the fifth interconnection system 51 includes a fifth TSV structure 511, a fifth insulating layer 512, a fifth bonding pad 513, and a fifth redistribution layer 514 disposed on the fourth passive transfer board 50. The fifth insulating layer 512 is located on both sides of the fourth passive transfer board 50 facing toward and away from the third insulating board. The fifth bonding pad 513 is disposed on both sides of the fourth passive transfer board 50 facing toward and away from the third insulating board. The fifth redistribution layer 514 is located on the side of the fourth passive transfer board 50 away from the third passive transfer board 30. The fifth bonding pad 513 is electrically connected to the third bonding pad 313.

[0080] like Figure 8 As shown, the sixth interconnection system 61 includes a sixth bump structure 611 and a sixth underfill material 612 disposed on the second active chip 60. The sixth bump structure 611 is located on the side of the second active chip 60 facing the fourth passive connection board. The sixth bump structure 611 is electrically connected to the fifth redistribution layer 514. The sixth underfill material 612 is filled between the sixth bump structure 611 and the fifth redistribution layer 514.

[0081] The first passive adapter board 10, the second passive adapter board 20, the third passive adapter board 30, and the fourth passive adapter board 50 are arranged in a direction in which the first TSV structure 111, the second TSV structure 211, the third TSV structure 311, and the fifth TSV structure 511 correspond to each other one by one, and the first TSV structure 111, the second TSV structure 211, the third TSV structure 311, and the fifth TSV structure 511 are filled with conductive materials to achieve electrical connection.

[0082] It is electrically connected to the sixth signal interconnection system through the first interconnection system 11, the second interconnection system 21, the third interconnection system 31, the fourth interconnection system 41, the fifth interconnection system 51. The first heat dissipation system 12, the second heat dissipation system 22, and the third heat dissipation system 32 are connected through the fourth microchannel heat dissipation system to form a microchannel, realizing that the passive interposer under the active chip has both the functions of electrical signal conduction and heat dissipation at the same time. The main process flow of this microchannel heat dissipation system is carried out on the passive interposer, with little damage to the active chip; this microchannel heat dissipation system process is adapted to the three-dimensional integration process of silicon-based inertial microsystems, without introducing new equipment and with low cost; this microchannel heat dissipation system dissipates the heat of the active chip to the outside of the microsystem through the heat dissipation fluid in the passive interposer, and has good heat dissipation effect.

[0083] This embodiment also discloses a manufacturing method of a three-dimensional integrated silicon-based inertial microsystem with an embedded microchannel, including the following steps:

[0084] S1: Form the first interconnection system 11 and the first heat dissipation system 12 on the first passive interposer 10, form the second interconnection system 21 and the second heat dissipation system 22 on the second passive interposer 20, form the third interconnection system 31 and the third heat dissipation system 32 on the third passive interposer 30, and form the fifth interconnection system 51 and the fourth heat dissipation system 52 on the fourth passive interposer 50; form the fourth interconnection system 41 on the first active chip 40 and form the sixth interconnection system 61 on the second active chip 60;

[0085] S2: Electrically connect the first passive interposer 10 and the second passive interposer 20 through the first interconnection system 11 and the second interconnection system 21, electrically connect the first active chip 40 and the second passive interposer 20 through the second interconnection system 21 and the fourth interconnection system, electrically connect the second passive interposer 20 and the third passive interposer 30 through the second interconnection system and the third interconnection system, electrically connect the third passive interposer 30 and the fourth passive interposer 50 through the third interconnection system and the fifth interconnection system, and electrically connect the fourth passive interposer 50 and the second active chip 60 through the fifth interconnection system and the sixth interconnection system; at the same time, the first heat dissipation system 12, the second heat dissipation system 22, the third heat dissipation system 32 and the fourth heat dissipation system 52 are connected through to form a heat dissipation microchannel.

[0086] Specifically, making the first interconnection system 11 electrically connected to the second interconnection system 12 includes: as Figure 2 shown, prepare the first TSV structure 111 on the first passive interposer 10 and fill it with a conductive material. After covering the two sides of the first passive interposer 10 with the first insulating layer 112, prepare the first bonding pad 113 on the first side of the first passive interposer 10, and open a number of connected first groove structures 121. Prepare the first bonding pad 113 on the second side of the first passive interposer, and process the first bump structure 114 on the first bonding pad; asFigure 3 As shown, a second TSV structure 211 is fabricated on the second passive interposer 20 and filled with a conductive material. After covering both sides of the second passive interposer 20 with a second insulating layer 212, a second bonding pad 213 is fabricated on the first side of the second passive interposer 20, and a number of connected second groove structures 221 are formed. A second bonding pad 213 and a second redistribution layer 214 are fabricated on the second side of the second passive interposer 20, and a second inlet 222 and a second outlet 223 are fabricated; as Figure 4 As shown, the first side of the first passive interposer 10 is bonded to the first side of the second passive interposer 20 in a face-to-face manner, such that the first bonding pad 113 of the first passive interposer 10 is electrically connected to the second bonding pad 213 of the second passive interposer 20, and the groove structure 121 of the first passive interposer 10 and the groove structure 221 of the second passive interposer 20 enclose to form a passage for the heat dissipation fluid; the second inlet 222 and the second outlet 223 serve as the inlet and outlet of the passage for the heat dissipation fluid, respectively.

[0087] Specifically, electrically connecting the third interconnecting system 31 and the fourth interconnecting system 41 to the second interconnecting system 21 includes: as Figure 5 As shown, a third TSV structure 311 is fabricated on the third passive interposer 30 and filled with a conductive material. After covering both sides of the third passive interposer 30 with a third insulating layer 312, third bonding pads 313 are fabricated on the first side and the second side of the third passive interposer 30, and a third inlet 321 and a third outlet 322 are fabricated. A cavity 33 is formed by laser cavity opening on the third passive interposer 30; as Figure 6 As shown, the first side of the third passive interposer 30 is bonded to the first side of the second passive interposer 20 in a face-to-face manner, such that the third bonding pad 313 is electrically connected to the second bonding pad 213, the inlet 321 of the heat dissipation fluid passage of the third passive interposer 30 is connected to the inlet 222 of the heat dissipation fluid passage of the second passive interposer 20, and the third outlet 322 is connected to the second outlet 223. A fourth bump structure 411 is fabricated on the first side of the first active chip 40. The first active chip 40 includes at least one active chip. In this embodiment, the number of the active chips is 1. The first active chip can be a high-power chip such as a processor or an application-specific integrated circuit chip. In this embodiment, the active chip is an application-specific integrated circuit chip. The first active chip 40 is placed in the cavity 33, such that the fourth bump structure 411 is electrically connected to the second redistribution layer 214, and then a fourth underfill material 412 is filled.

[0088] Electrically connecting the fifth interconnecting system 51 to the third interconnecting system 31 includes: as Figure 7As shown, a fifth TSV structure 511 is fabricated on the fourth passive interposer 50 and filled with a conductive material. After covering both sides of the fourth passive interposer 50 with a fifth insulating layer 512, a fifth bonding pad 512 is fabricated on the first side of the fourth passive interposer 50, a fifth bonding pad 513 and a fifth redistribution layer 514 are fabricated on the second side of the fourth passive interposer 50, and vias 521 and 522 are fabricated; as Figure 8 shown, the first side of the fourth passive interposer 50 is bonded face-to-face with the second side of the third passive interposer 30, such that the fifth bonding pad 513 is electrically connected to the third bonding pad 313, the fourth inlet 521 is connected to the third inlet 321 of the third passive interposer 30, and the fourth outlet 522 is connected to the third outlet 322.

[0089] As Figure 9 shown, electrically connecting the sixth interconnect system to the fifth interconnect system includes: fabricating a sixth bump structure 611 on the first side of the second active chip 60, the first active chip 60 including at least one active chip. In this embodiment, the number of active chips is 1. The first active chip may be a low-power chip such as a MEMS accelerometer or a MEMS gyroscope. In this embodiment, the active chip uses a MEMS accelerometer chip. The second active chip 60 is placed on the fourth passive interposer 50 such that the sixth bump structure 611 is electrically connected to the fifth redistribution layer 514, and then a sixth underfill material 612 is filled.

[0090] The above embodiments have described in detail different configurations of the three-dimensional integrated silicon-based inertial microsystem with an embedded microchannel. Of course, the present invention includes but is not limited to the configurations listed in the above embodiments. Any content obtained by transformation based on the configurations provided in the above embodiments belongs to the scope protected by the present invention. Those skilled in the art can draw inferences from the content of the above embodiments.

Claims

1. A three-dimensional integrated silicon-based inertial microsystem with embedded microchannels, characterized in that: It comprises a first passive adapter board (10), a second passive adapter board (20), a third passive adapter board (30), and a fourth passive adapter board (50) which are electrically connected in sequence. The surface of the second passive adapter board (20) facing the third passive adapter board (30) is electrically connected to a first active chip (40); the surface of the third passive adapter board (30) facing the second passive adapter board (20) is provided with a cavity (33) for accommodating the first active chip (40); and the side of the fourth passive connection board facing away from the third passive connection board is provided with a second active chip (60). The first passive adapter board (10) is provided with a first heat dissipation system (12), the second passive adapter board (20) is provided with a second heat dissipation system (22), the third passive adapter board (30) is provided with a third heat dissipation system (32), and the fourth passive adapter board (50) is provided with a fourth heat dissipation system (52); The first heat dissipation system (12) comprises a first bottom groove (122) and a second bottom groove (123) which are arranged on the surface of the first passive adapter plate (10) facing the second passive adapter plate (20); a cavity which communicates with the first bottom groove (122) and the second bottom groove (123) is arranged between the first bottom groove (122) and the second bottom groove (123); the second heat dissipation system (22), the third heat dissipation system (32) and the fourth heat dissipation system (52) are connected, and are respectively connected with the first bottom groove (122) and the second bottom groove (123) to form a heat dissipation microchannel.

2. The three-dimensional integrated silicon-based inertial microsystem with embedded microchannels according to claim 1, characterized in that: A first groove structure (121) is provided on the surface of the first passive adapter plate (10) facing the second passive adapter plate (20), and the first groove structure is a cavity connecting the two bottom grooves (122, 123).

3. The three-dimensional integrated silicon-based inertial microsystem with embedded microchannels according to claim 2, characterized in that: The second heat dissipation system (22) comprises a second groove structure (221), the second groove structure (221) being arranged on a surface of the second passive adapter plate (20) opposite to the first passive adapter plate (10), the second groove structure (221) being opposite to the first groove structure (121), and the first groove structure (121) and the second groove structure (221) forming a cavity connecting the first bottom groove (122) and the second bottom groove (123).

4. The three-dimensional integrated silicon-based inertial microsystem with embedded microchannels according to any one of claim 3, characterized in that: The first groove structure (121) and the second groove structure (221) comprise a plurality of strip grooves, and the ends of two adjacent strip grooves are connected to form a flow channel.

5. The three-dimensional integrated silicon-based inertial microsystem with embedded microchannels according to claim 1, characterized in that: The second heat dissipation system (22) further comprises a second inlet (222) and a second outlet (223) which are arranged on the second passive adapter plate (20), wherein the second inlet (222) is opposite to the first bottom groove (122), and the second outlet (223) is opposite to the second bottom groove (123); The third heat dissipation system (32) comprises a third inlet (321) and a third outlet (322) which are opened on the third passive adapter plate (30); The fourth heat dissipation system (52) comprises a fourth inlet (521) and a fourth outlet (522) which are opened on the fourth passive adapter plate (50); The fourth inlet (521), the third inlet (321), and the second inlet (222) are sequentially connected to the first bottom groove (122), and the fourth outlet (522), the third outlet (322), and the second outlet (223) are sequentially connected to the second bottom groove (123).

6. The three-dimensional integrated silicon-based inertial microsystem with embedded microchannels according to claim 5, characterized in that: The size of the fourth inlet (521) is larger than that of the third inlet (321), and the size of the fourth outlet (522) is larger than that of the third outlet (322).

7. The three-dimensional integrated silicon-based inertial microsystem with embedded microchannels according to claim 1, characterized in that: On the surface of the second passive adapter board (20) facing the first adapter board, two distribution grooves opposite to the first bottom groove (122) and the second bottom groove (123) are provided, and the cross-sectional size of the distribution grooves is larger than that of the second inlet (222) and the second outlet (223).

8. The three-dimensional integrated silicon-based inertial microsystem with embedded microchannels according to claim 1, characterized in that: An intermediate passive adapter layer can be selectively arranged between the second passive adapter board (20) and the third passive adapter board (30). The intermediate passive adapter layer includes a passive adapter board support layer, a passive adapter isolation layer, and an active chip layer that are sequentially arranged from bottom to top and electrically connected. The passive adapter board support layer has the same structure as the third passive adapter board (30). Through holes communicating with the second heat dissipation system (22) and the third heat dissipation system (32) are provided on the passive adapter board support layer and the passive adapter isolation layer.

9. The three-dimensional integrated silicon-based inertial microsystem with embedded microchannels according to claim 8, characterized in that: The passive adapter isolation layer is a passive adapter board partition; Or the passive adapter isolation layer includes a passive adapter first partition and a passive adapter second partition that are sequentially arranged from bottom to top and electrically connected. The passive adapter first partition is provided with a first through hole communicating with the second heat dissipation system (22) and the third heat dissipation system (32), and the passive adapter second partition is provided with a second through hole communicating with the first through hole and the third heat dissipation system (32). Opposite surfaces of the passive adapter first partition and the passive adapter second partition are respectively provided with a pair of opposite groove structures Ⅰ and groove structures Ⅱ, and a cavity formed between the groove structures Ⅰ and groove structures Ⅱ communicates the first through hole and the second through hole.

10. A manufacturing method of a three-dimensional integrated silicon-based inertial microsystem with embedded microchannels, characterized in that: It includes the following steps: S1: Form a first interconnection system (11) and a first heat dissipation system (12) on the first passive adapter board (10), a second interconnection system (21) and a second heat dissipation system (22) on the second passive adapter board (20), a third interconnection system (31) and a third heat dissipation system (32) on the third passive adapter board (30), and a fifth interconnection system (51) and a fourth heat dissipation system (52) on the fourth passive adapter board (50); form a fourth interconnection system (41) on the first active chip (40) and a sixth interconnection system (61) on the second active chip (60); S2: Electrically connect the first passive adapter board (10) and the second passive adapter board (20) through the first interconnection system (11) and the second interconnection system (21), electrically connect the first active chip (40) and the second passive adapter board (20) through the second interconnection system (21) and the fourth interconnection system (41), electrically connect the second passive adapter board (20) and the third passive adapter board (30) through the second interconnection system (21) and the third interconnection system (31), electrically connect the third passive adapter board (30) and the fourth passive adapter board (50) through the third interconnection system (31) and the fifth interconnection system (51), and electrically connect the fourth passive adapter board (50) and the second active chip (60) through the fifth interconnection system (51) and the sixth interconnection system (61); meanwhile, the first heat dissipation system (12), the second heat dissipation system (22), the third heat dissipation system (32) and the fourth heat dissipation system (52) are connected to form a heat dissipation microchannel.

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