Polysilicon resistor with continuous u-shaped polysilicon resistor element and related methods

Abstract

The present disclosure relates to a polysilicon resistor with continuous U-shaped polysilicon resistor elements and related methods. A resistor includes at least one polysilicon resistor element located in a semiconductor substrate, each polysilicon resistor element having a continuous U-shape with a continuous lateral bottom. The resistor can include an insulator located within a valley of the continuous U-shape of each polysilicon resistor element. Multiple polysilicon resistor elements can be sequentially interconnected to form a serpentine polysilicon resistor. The resistor can also include a dopant-containing high resistivity (HR) polysilicon layer located thereunder to provide electrical isolation from and better thermal conduction to an underlying semiconductor substrate, for example. The resistor can be used in an SOI substrate. Related methods are also disclosed.

Description

Technical Field

[0001] This disclosure relates to integrated circuits (ICs), and more specifically, to polysilicon resistors having one or more continuous U-shaped polysilicon resistor elements, each U-shaped polysilicon resistor element having a continuous lateral bottom. Background Technology

[0002] Resistors used in ICs are typically formed in an interlayer dielectric (ILD) layer above the transistors. The ILD layer provides scaled interconnects for the IC. Resistors are often formed over oxide or shallow trench isolation (STI) in a substrate where transistors are formed, which reduces heat dissipation from the resistor to the substrate. Furthermore, the horizontal extension of the resistors within each layer occupies valuable area and potentially hinders access to other functional components below, requiring complex electrical connections to those components or the addition of more components not covered by the resistors. Trench resistors have been used to minimize the area used by the resistors, but the methods employed are complex because they require specialized materials for forming the trenches, filling the trenches, and connecting the bottom of the trenches. Summary of the Invention

[0003] One aspect of this disclosure relates to a resistor comprising: at least one polysilicon resistor element located in a semiconductor substrate, each polysilicon resistor element having a continuous U-shape having a continuous lateral bottom; and an insulator located within the valley of the continuous U-shape of each polysilicon resistor element.

[0004] Another aspect of this disclosure includes a resistor comprising: a plurality of interconnected polysilicon resistor elements in a semiconductor-on-insulator (SOI) substrate, each polysilicon resistor element having a continuous U-shape having a continuous lateral bottom, the plurality of polysilicon resistor elements forming a serpentine polysilicon resistor, wherein the SOI substrate includes a buried insulator layer above a base semiconductor substrate; a trench isolation insulator located in the valleys of the continuous U-shape of each polysilicon resistor element; and a doped high resistivity (HR) polycrystalline layer in the base semiconductor substrate below the buried insulator layer and below each polysilicon resistor element, wherein the dopant in the doped HR polycrystalline layer comprises an inert gas element, wherein each polysilicon resistor element extends through the buried insulator layer and into the doped HR polycrystalline layer.

[0005] One aspect of this disclosure relates to a method for forming a serpentine polysilicon resistor, the method comprising: forming a plurality of trenches in a semiconductor-on-insulator (SOI) substrate, the SOI substrate including an active semiconductor layer above a buried insulator layer, the buried insulator layer being located above a base semiconductor substrate, each trench extending into the base semiconductor substrate; filling each trench with a polysilicon member; forming an insulator in each polysilicon member to form a plurality of polysilicon resistor elements in a respective trench, each polysilicon resistor element having a continuous U-shape having a continuous lateral bottom and having the insulator in a valley of each U-shape; forming a doped high resistivity (HR) polysilicon layer in the base semiconductor substrate below the buried insulator layer and below each polysilicon resistor element, wherein the dopants in the doped HR polysilicon layer include inert gas elements; and sequentially interconnecting the ends of the plurality of polysilicon resistor elements to form the serpentine polysilicon resistor.

[0006] The above and other features of this disclosure will become apparent from the following more detailed description of embodiments thereof. Attached Figure Description

[0007] Embodiments of this disclosure will be described in detail with reference to the following accompanying drawings, wherein the same reference numerals denote the same elements, and wherein:

[0008] Figure 1 A cross-sectional view of a resistor according to an embodiment of the present disclosure is shown.

[0009] Figure 2 A top view of a resistor according to an embodiment of the present disclosure is shown.

[0010] Figure 3 Another cross-sectional view of a resistor according to an embodiment of the present disclosure is shown.

[0011] Figure 4 A cross-sectional view of a resistor according to another embodiment of the present disclosure is shown.

[0012] Figure 5 A top view of a resistor according to another embodiment of this disclosure is shown.

[0013] Figure 6 Another cross-sectional view of a resistor according to other embodiments of the present disclosure is shown.

[0014] Figure 7 A cross-sectional view of a resistor according to another embodiment of the present disclosure is shown.

[0015] Figure 8 A top view of a resistor according to another embodiment of the present disclosure is shown.

[0016] Figure 9 Another cross-sectional view of a resistor according to another embodiment of the present disclosure is shown.

[0017] Figure 10 A cross-sectional view of a resistor according to another embodiment of the present disclosure is shown.

[0018] Figure 11 A top view of a resistor according to another embodiment of this disclosure is shown.

[0019] Figure 12 A cross-sectional view of a resistor according to another embodiment of the present disclosure is shown.

[0020] Figure 13 A cross-sectional view of a resistor according to another embodiment of the present disclosure is shown.

[0021] Figure 14 A cross-sectional view of a resistor according to yet another embodiment of the present disclosure is shown.

[0022] Figure 15 A cross-sectional view of a resistor according to yet another embodiment of the present disclosure is shown.

[0023] Figure 16 A cross-sectional view of a resistor according to yet another embodiment of the present disclosure is shown.

[0024] Figure 17 A cross-sectional view of a preliminary structure of a method for forming a resistor according to an embodiment of the present disclosure is shown.

[0025] Figure 18 A cross-sectional view of a method for forming a resistor according to an embodiment of the present disclosure is shown, illustrating the formation of a polycrystalline silicon component.

[0026] Figure 19 A cross-sectional view of a method for forming a resistor according to an embodiment of the present disclosure is shown, illustrating the formation of a polycrystalline silicon resistor element.

[0027] Figure 20 A top view of a method for forming a resistor according to an embodiment of the present disclosure is shown after the formation of a polysilicon resistor element.

[0028] Figure 21 A cross-sectional view of the doping step of a method for forming a resistor according to an alternative embodiment of the present disclosure is shown.

[0029] Figure 22 A cross-sectional view is shown of several steps of a method for forming a resistor according to an alternative embodiment of the present disclosure.

[0030] Figure 23 A cross-sectional view of forming an insulating liner is shown in a method for forming a resistor according to other embodiments of the present disclosure.

[0031] Figure 24 Cross-sectional views are shown of several steps in a method for forming a resistor according to other embodiments of the present disclosure.

[0032] It should be noted that the accompanying drawings of this disclosure are not necessarily drawn to scale. The drawings are intended only to depict typical aspects of this disclosure and should not be considered as limiting the scope of this disclosure. In the drawings, similar reference numerals indicate similar elements between the figures. Detailed Implementation

[0033] In the following description, reference is made to the accompanying drawings, which form a part of this invention, and specific exemplary embodiments in which the present teachings may be practiced are illustrated by way of example. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present teachings, and it should be understood that other embodiments may be used and modifications may be made without departing from the scope of the present teachings. Therefore, the following description is merely illustrative.

[0034] It will be understood that when an element, such as a layer, region, or substrate, is described as being "on" or "above" another element, it can be directly on the other element, or there may be intermediate elements. In contrast, when an element is described as being "directly on" or "directly above" another element, there are no intermediate elements. It should also be understood that when an element is described as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intermediate elements.

[0035] References to "one embodiment" or "embodiment" and other variations thereof in the specification mean that a particular feature, structure, characteristic, etc., described in connection with that embodiment is included in at least one embodiment of the present disclosure. Therefore, the phrases "in one embodiment" or "in an embodiment," and any other variations appearing throughout the specification, do not necessarily refer to the same embodiment. It should be understood that the use of " / ", "and / or", and "at least one" in cases such as "A / B", "A and / or B", and "at least one of A and B" is intended to include selecting only the first listed option (A), or only the second listed option (B), or both options (A and B). As other examples, in the cases of “A, B, and / or C” and “at least one of A, B, and C”, these phrases are intended to encompass selecting only the first listed option (A), or only the second listed option (B), or only the third listed option (C), or only the first and second listed options (A and B), or only the first and third listed options (A and C), or only the second and third listed options (B and C), or all three options (A, B, and C). As will be apparent to those skilled in the art, this can be extended to many of the listed items.

[0036] Embodiments of this disclosure provide a resistor comprising at least one polysilicon resistor element located in a semiconductor substrate, each polysilicon resistor element having a continuous U-shape having a continuous lateral bottom. The resistor may include an insulator, such as a trench isolation insulator, located within the valleys of the U-shape of each polysilicon resistor element. Multiple resistor elements may be sequentially interconnected to form a serpentine polysilicon resistor. The resistivity of the resistor may be customized based on the number of resistor elements, the dopant in the polysilicon, and the depth of the resistor elements in the semiconductor substrate. The resistor may include an insulator, such as a trench isolation insulator, contacting the outer walls of the continuous U-shape of the resistor element to provide additional electrical isolation. In another embodiment, the resistor may include a doped high resistivity (HR) polysilicon layer located beneath it to provide electrical isolation from the semiconductor substrate and better thermal conductivity to the semiconductor substrate. The doped HR polysilicon region may also contact the outer walls of the continuous U-shape of the resistor element to provide, for example, additional electrical isolation from the semiconductor substrate and better thermal conductivity to the semiconductor substrate. If necessary, an insulating liner can be placed around the resistor element to provide additional electrical isolation. This resistor can be used on an SOI substrate, and its formation can be integrated with bipolar fabrication, eliminating the need to create trenches specifically for the resistor element. Compared to conventional resistors, this resistor offers an ultra-compact programmable resistor with improved heat dissipation. The majority of the resistor is vertical, which reduces its horizontal surface area and provides most of the resistance in the vertical portion of the continuous U-shaped polysilicon resistor element.

[0037] Figure 1-3 A view of a resistor 100 according to an embodiment of the present disclosure is shown. Figure 1 A cross-sectional view of resistor 100 is shown (see [reference]). Figure 1 (View line 1-1 in the image). Figure 2 A top view of resistor 100 is shown. Figure 3 Another cross-sectional view of resistor 100 according to an embodiment of the present disclosure is shown (see [link]). Figure 2 (See view line 3-3 in the figure). As shown, any resistor described herein can be formed adjacent to a complementary metal-oxide-semiconductor (CMOS) region 102 (as shown) that includes a CMOS device such as a field-effect transistor (FET). In some implementations, the formation of the resistor described herein can be integrated with the formation of a bipolar or CMOS device (not shown); however, this is not the case in all cases.

[0038] The resistor 100 described herein is formed in a semiconductor substrate 104, meaning the resistor element is not on or above the substrate. In one embodiment, the semiconductor substrate 104 may include a semiconductor-on-insulator (SOI) substrate 106, which includes an active semiconductor layer 108 (“SOI layer 108”), an insulating layer 110, and a base semiconductor substrate 112. The SOI layer 108 and the base semiconductor layer 112 may include, but are not limited to, silicon, germanium, silicon-germanium, silicon carbide, and materials substantially composed of one or more having the chemical formula Al. X1 Ga X2 In X3 As Y1 P Y2 N Y3 Sb Y4 Materials composed of group III-V compound semiconductors with defined compositions, where X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative proportions, each greater than or equal to zero, and X1 + X2 + X3 + Y1 + Y2 + Y3 + Y4 = 1 (where 1 is the total relative molar amount). Other suitable substrates include those with the composition Zn. A1 Cd A2 Se B1 Te B2 The semiconductor is a group II-VI compound semiconductor, wherein A1, A2, B1, and B2 are relative proportions, each being greater than or equal to zero and A1 + A2 + B1 + B2 = 1 (where 1 is the total molar amount). The insulating layer 110 (also referred to herein as "buried insulating layer 110") may comprise any suitable dielectric, such as, but not limited to, silicon dioxide, i.e., forming a buried oxide (BOX) layer. Strain may occur on a portion or throughout the semiconductor substrate. The precise thicknesses of the insulating layer 110 and the SOI layer 108 can vary widely depending on the intended application. Although shown in SOI substrate 104, embodiments of this disclosure can be formed in other substrates, such as bulk semiconductor substrates.

[0039] Resistor 100 also includes at least one polysilicon resistor element 120 located in semiconductor substrate 104. For example... Figure 1As shown, each polysilicon resistor element 120 has a continuous U-shape 122 with a continuous lateral bottom 124. That is, the continuous U-shape 122 is monolithic and is a single, uninterrupted material. The continuous lateral bottom 124 extends laterally, i.e., extends laterally on the page. The polysilicon of the polysilicon resistor element 120 can be undoped or in-situ doped with, for example, boron (B). Doping is the process of introducing impurities (dopants) into a semiconductor substrate or an element formed on a semiconductor substrate, typically performed using a mask (or an element previously formed in the appropriate location) to dope only certain areas of the substrate. Typically, in doping, the dopant, dose, and energy levels can be specified and / or the final doping level can be specified. This can be achieved by the number of atoms per square centimeter (atoms / cm²). 2 The dosage is specified by the energy level (in keV, or kiloelectron volts), thus obtaining the number of atoms per cubic centimeter (atoms / cm³). 3 The doping level (concentration in the substrate) is used to indicate the number of atoms. The number of atoms is typically specified in exponential notation, where a number like "3E15" represents 3 multiplied by 10 to the power of 15, or "3" followed by 15 zeros (3,000,000,000,000,000). Here, the polysilicon resistor element 120 can operate at 15 keV with, for example, 5E15 atoms / cm². 3 The dosage is in-situ doping with, for example, boron (B). Other dopants, dosages, and energy levels may also be used. Each polysilicon resistor element 120 (hereinafter referred to as "resistor element 120") extends through the buried insulating layer 110. Therefore, the outer sidewall 156 of resistor element 120 can be in direct contact with the buried insulating layer 110. Resistor element 120 is located within a trench 126 in semiconductor substrate 104. Resistor element 120 may also extend partially into the underlying semiconductor substrate 112. The depth or vertical extent of resistor element 120 can be user-defined, thereby allowing its resistivity value to be customized by controlling the length of resistor 100. In one embodiment, for example, as shown in the figure... Figure 1 As shown, the depth of resistor element 120 is greater than its width, thus ensuring that most of the resistivity provided is created by its vertical extent or depth. In a non-limiting example, at least 60% of the total resistivity of resistor 100 may be provided by the vertical extent of resistor element 120.

[0040] Resistor 100 also includes an insulator 130 located within valleys 132 of the continuous U-shape 122 of resistor element 120. In one embodiment, insulator 130 may include a trench isolation insulator, i.e., an insulator formed together with other trench isolations 134 for other structures, such as FETs within CMOS region 102. However, if desired, insulator 130 may be formed separately from trench isolations 134. Trench isolations (TI) 134 typically comprise trenches etched into semiconductor substrate 104 and filled with an insulating material to isolate a region of the substrate from an adjacent region of the substrate. During this process, insulator 130 may be formed by etching trenches in polysilicon components within trench 126 and filling the trenches with an insulating material to form the continuous U-shape 122 of resistor element 120. One or more transistors of a given polarity (e.g., FETs in CMOS region 102) may be disposed within the region isolated by TI 134. Insulator 130 and each TI 134 can be formed from any material now known or later developed to provide electrical insulation, such as: silicon nitride (Si3N4), silicon oxide (SiO2), fluorinated SiO2 (FSG), hydrogenated carbon silicon oxide (SiCOH), porous SiCOH, borosilicate glass (BPSG), silsesquioxane, carbon (C) doped oxides (i.e., organosilicones) including atoms of silicon (Si), carbon (C), oxygen (O) and / or hydrogen (H), thermosetting polyarylene ethers, spin-coated silicon-carbon polymer materials, near-frictionless carbon (NFC), or layers thereof. Insulator 130 and TI 134 can be formed by depositing selected insulating materials, for example by atomic layer deposition (ALD) and subsequent planarization. It should be recognized that the insulator 130 does not need to be formed together with the trench isolation; it can be formed separately to create the continuous U-shaped resistor element 120, for example, through appropriate trench openings within the polysilicon component in the trench 126 and deposition of insulating material (e.g., through atomic layer deposition (ALD) and planarization). Figure 2 and 3 As shown in the best embodiment, the insulator 130 extends through the continuous U-shape 122, such that the polysilicon in the resistor element 120 does not completely surround the insulator.

[0041] Resistor 100 may include a single resistive element 120, such as Figure 1 As shown. Alternatively, as Figure 2-3 As shown, resistor 100 may include a plurality of polysilicon resistor elements 120 sequentially coupled together to form a serpentine polysilicon resistor 136. Figure 2-3 As shown, the ends 138 (i.e., the continuous U-shaped ends) of a plurality of resistor elements 120 are sequentially coupled together via at least one conductive connector 140. Each conductive connector 140 connects one end 138 of the resistor element 120 (in... Figure 2-3(Indicated by dashed lines) Coupled to the other end 138 of the adjacent resistor element 120. The conductive connector 140 does not need to perfectly match the shape of the end 138 of the resistor element 120; therefore, in Figure 2 In this configuration, the end 138 appears at certain locations but not others. In any case, any number of U-shaped resistor elements 120 can be coupled together in this way to form a serpentine resistor 136 with any desired length and therefore any desired resistivity value. Figure 2 In the image, the serpentine resistor 136 moves up and down and in and out of the page in a sinusoidal curve. Figure 2 and 3 In the configuration, five (5) resistor elements 120 are sequentially coupled together; however, any number can be used. It should be noted that resistor elements 120 in... Figure 2 The components are shown in dashed lines because insulator 130 and conductive connector 140 cover them. Figure 3 In the diagram, the top of resistor element 120 is shown in dashed lines because of view line 3-3 ( Figure 2 It passes through insulator 130. Throughout the disclosure, conductive connector 140 is shown as residing in interconnect layer 168 (dashed box), for example, a dielectric layer. Other connectors, such as contacts, may also be used, as will be understood in the art.

[0042] Resistor 100 may further include a doped high resistivity (HR) polycrystalline layer 150 located beneath each resistor element 120 in the semiconductor substrate 104. The dopant of the HR polycrystalline layer 150 may include an inert gas element, such as argon (Ar), xenon (Xe), helium (He), krypton (Kr), and / or neon (Ne). In a non-limiting example, the dopant may include Ar. As shown, resistor 100 may also include an insulating layer 110 located above the doped HR polycrystalline layer 150. Figure 1 and 3 As shown, each resistor element 120 extends through the buried insulating layer 110 and into the base semiconductor substrate 112, and more specifically, into the doped HR polycrystalline layer 150. The HR polycrystalline layer 150 provides additional electrical isolation to contain any current leakage, for example, to the base semiconductor substrate 112. Compared to other insulators, the HR polycrystalline layer 150 also provides better thermal conductivity from the resistor 100 to, for example, the base semiconductor substrate 112. Although shown below the CMOS region 102, the HR polycrystalline layer 150 can be formed at any location, or omitted from any location, during ion implantation to create layer 150, for example, using a suitable mask.

[0043] In some embodiments, such as Figure 1 and 2As best shown, each insulator 130 may be a trench isolation insulator and is formed with a trench isolation 134 such that the insulator 154 also contacts the outer wall 156 of the continuous U-shape 122 of each resistor element 120. The insulator 154 helps prevent current leakage, for example, to the semiconductor substrate 104. Figure 2 As shown, in this embodiment, insulators 130 and 154 surround the continuous U-shaped resistor element 120 on all sidewalls of the vertical portion of the continuous U-shaped resistor element 120.

[0044] The conductive connector 140 can take many forms. In some embodiments, such as Figure 1-3 As shown, the conductive connector 140 may each include a polysilicon connector 160. Here, each polysilicon connector 160 can be connected to the polysilicon conductor layer 162 of the adjacent CMOS region 102. Figure 1 Located in the same layer. The polysilicon conductor layer 162 may include any polysilicon FET gate spanning the source / drain regions of the CMOS device. The use of the polysilicon connector 160 may require additional masking steps to remove the gate dielectric layer 167 formed for the device in the CMOS region 102. Figure 1 , 4 7, 10, 12). Each polysilicon connector 160 may have a nitride spacer 159 adjacent to it (only in... Figure 1 (marked in the middle).

[0045] Resistor 100 may also include a silicide layer 163 located above at least one of the polysilicon connectors 160. Figure 2-3 In the serpentine resistor 136, the terminal conductive connector 162 is the only polysilicon connector 160 on which a silicide layer 163 is included. The silicide layer 163 may not cover all ends 138 of the resistor element 120; therefore, in Figure 2 In the top view, some ends 138 of the resistor element 120 can be seen.

[0046] Figure 4-6 A view of a resistor 100 according to an alternative embodiment of the present disclosure is shown. More specifically, Figure 4 A cross-sectional view is shown. Figure 5 View line 4-4 in the middle, similar to Figure 1 ; Figure 5 A top view is shown, similar to Figure 2 ; Figure 6 An alternative embodiment of the conductive connector 140 is shown along... Figure 5 The cross-sectional view is shown in view line 6-6. Here, the conductive connector 140 comprises polysilicon, such as... Figure 1-3As shown, all polysilicon connectors 160 are covered by a silicide layer 163. Here, the silicide layer 163 covers all ends 138 of the resistor element 120. Figure 4 Silicides can be formed using any techniques known now or developed later, with or without masks, such as performing in-situ pre-cleaning, depositing metals (e.g., titanium, nickel, cobalt, etc.), annealing to react the metals with the polycrystalline silicon, and removing unreacted metals.

[0047] Figure 7-9 A view of a resistor 100 according to another embodiment of this disclosure is shown. More specifically, Figure 7 A cross-sectional view is shown. Figure 8 View line 7-7 in the image, similar to Figure 1 and 4 ; Figure 8 A top view is shown, similar to Figure 2 and 5 ; Figure 9 An alternative embodiment of the conductive connector 140 is shown along... Figure 8 The cross-sectional view is shown by line 9-9 in the diagram. In these embodiments, multiple resistor elements 120 are sequentially coupled together via at least one metal connector 166 in an interconnect layer 168 (dashed box) above the semiconductor substrate 104. That is, the conductive connector 140 includes conventional metal connectors 166, for example, a silicide layer with contact vias having metal wires is included in the interlayer dielectric of the interconnect layer 168. Therefore, metal connectors 166 are advantageous because they can be formed during conventional MOL and / or BEOL processes. Furthermore, as Figure 1-6 As shown, the use of the polysilicon connector 160 requires an additional masking step to remove the gate dielectric layer 167 formed for the devices in the CMOS region 102. Figure 1 , 4 (7, 10, 12). The use of metal connector 166 avoids this additional step. Regardless of the form of conductive connector 140, any form of vertical direct contact can be used as needed.

[0048] refer to Figure 10-13 In other embodiments, the doped high resistivity (HR) polycrystalline region 170 surrounds the outer wall 156 of the continuous U-shape 122 of each resistor element 120 instead of surrounding the insulator 154 along the outer wall 156 of the resistor element 120. Figure 1 In addition, in this paper, the doped HR polycrystalline layer 150 is formed only below the resistor element 120, that is, it is not below the CMOS region 102. Figure 10 It is a cross-sectional view. Figure 11 View line 10-10 in the middle; Figure 11 A top view of these embodiments is shown. (e.g.) Figure 11 As shown, the insulator 130 is located in the valley 132 of the continuous U-shape 122 and between adjacent resistor elements 120. Figure 10 and 11 The polysilicon conductor 160 is shown, with silicide only present on the outermost conductive connector 162. However, it should be noted that... Figure 10 and 11 Embodiments may use any form of conductive connector 140 as described herein. Figure 12 It shows Figure 10 A cross-sectional view of an embodiment, which has as follows Figure 1-6 The silicided polycrystalline silicon conductor 160 shown (having a silicide layer 163) Figure 13 It shows Figure 10 A cross-sectional view of an embodiment, which has as follows Figure 7-9 The metal connector 166 shown is connected to the insulator 154. Figure 1-6 In contrast, the doped HR polysilicon region 170 may be advantageous because it has a higher thermal conductivity than the insulator 154, and thus can provide improved heat dissipation from the resistor 100 to, for example, the semiconductor substrate 104.

[0049] refer to Figure 14-17 Another embodiment of resistors 100 and 136 is shown. Figure 14 A cross-sectional view is shown. Here, resistor 100 is essentially similar to... Figure 10-13 In this embodiment, each polysilicon resistor element 120 is located within a trench 126 in the semiconductor substrate 104, and an insulating liner 174 lines the trenches. The insulating liner 174 may comprise any material listed herein for the insulator 130, such as an oxide. An insulating liner 174 may be provided where, for example, electrical noise from the resistor 100 into the semiconductor substrate 104 is a problem. The insulating liner 174 can reduce current leakage and improve noise isolation. Therefore, the insulating liner 174 can reduce the additional thermal conductivity from the doped HR polysilicon region 170 compared to the insulation (similar to...) Figure 1 A trade-off is made between additional leakage / noise prevention for the insulator 154 of the outer wall 156 of the continuous U-shaped 122 that contacts each resistor element 120. It should be noted that the formation of the insulating liner 174 may require the use of additional masks to prevent the liner from forming in unwanted places. Figure 14 A polycrystalline silicon conductor 160 is shown, wherein only the conductive connector 162 at the very end has silicide. However, it should be noted that... Figure 14 Embodiments may use any form of conductive connector 140 as described herein. Figure 15 It shows Figure 14 An embodiment having, as Figure 1-6And the silicided polycrystalline silicon conductor 162 shown in Figure 12, Figure 16 It shows Figure 14 An embodiment having, as Figure 7-9 The metal connector 166 shown.

[0050] refer to Figure 17-24 The method of forming resistor 100, and in particular serpentine polysilicon resistor 136, will be described. Figure 17 A cross-sectional view of a preliminary structure 200 including a semiconductor substrate 104 is shown. In the example shown, the semiconductor substrate 104 includes an SOI substrate 106, which includes an active semiconductor layer 108 located above a buried insulating layer 110, which is located above a base semiconductor substrate 112. The semiconductor substrate 104 may include a designated CMOS region 102, and a region for a resistor 100 (to the right of the illustrated CMOS region 102). Figure 17 It is also shown that a plurality of trenches 126 are formed in the semiconductor substrate 104. The trenches 126 are in Figure 17 The inner and outer parts of the page are separated, for example, see Figure 2 and 20 The location of the resistor element 120. The trench 126 can be formed using any mask 202 now known or developed later, for example by deposition and patterning of the mask, as well as etching. Any number of trenches 126 can create any number of resistor elements 120. Figures 19-20 ). Figure 20 Four (4) resistor elements 120 are shown, but one, two, three, or more than four can be used. Mask 202 may, for example, include a pad nitride film. Trench 126 can be formed as part of a bipolar CMOS structure formed in other portions of the semiconductor substrate 204, such as trenches for a bipolar transistor structure, thus eliminating the need to form trench 100 specifically for the resistors. Mask 202 can be removed using any technique now known or developed later, such as an ashing process.

[0051] Figure 18 A cross-sectional view is shown of polysilicon components 204 formed in each trench 126. Figure 19 The structure after trench isolation is formed is shown. Figure 20 This shows the result after removing mask 202. Figure 19 A top view of the structure. Figure 18The diagram shows each trench 126 filled with a polysilicon component 204. The polysilicon component 104 can be formed using any suitable deposition technique (e.g., ALD) and planarization (e.g., chemical mechanical polishing (CMP)). The polysilicon component 104 can be undoped or in-situ doped with, for example, boron (B). Here, the polysilicon component 104 can be formed at 15 keV with, for example, 5E15 atoms / cm². 3 The dosage is, for example, boron (B) doping. Other dopants, dosages, and energy levels can also be used.

[0052] Figure 19 and 20 It is shown that an insulator 130 is formed in each polysilicon component 204, thereby forming a plurality of polysilicon resistor elements 120. Each polysilicon resistor element 120 has a continuous U-shape 122 in a corresponding trench, the continuous U-shape having a continuous lateral bottom 124, and an insulator 130 in the valley 132 of each continuous U-shape 122. Here, the insulator 130 can be formed by using a mask 206 ( Figure 19 The dashed lines in the diagram represent trenches (i.e., valleys 132) etched into each polysilicon component 204 to form the mask 206. The mask 206 can be part of a trench isolation mask (i.e., for trench isolation 134) or a separate mask. Figure 3 and 20 As shown, insulator 130 extends through polysilicon member 204 (in Figure 3 The polysilicon component 204 is branched to form a continuous U-shaped resistor element 120 (shown as resistor element 120 in the figure).

[0053] Figures 19-20 It shows Figure 1-6 The insulator 130 is shown here as being formed with trench isolation 134. That is, each insulator 130 is a trench-isolated insulator and is formed with trench isolation 134 such that its insulator 154 also contacts the outer sidewall 156 of the continuous U-shape 122 of each resistor element 120. In other words, forming an insulator 130 in each polysilicon component 204 also includes forming an insulator 154 to contact the outer sidewall 156 of the continuous U-shape 122 of each polysilicon resistor element 120. As described above, the insulator 154 helps prevent current leakage to, for example, the semiconductor substrate 104. It should be noted that the same process can occur in the CMOS region 102.

[0054] Figure 19Also shown is a doped HR polycrystalline layer 150 formed beneath a buried insulating layer 110 in a base semiconductor substrate 112 and beneath each polycrystalline silicon resistor element 120. The dopant of the HR polycrystalline layer 150 may include an inert gas element, such as argon (Ar), xenon (Xe), helium (He), krypton (Kr), and / or neon (Ne). In a non-limiting example, the dopant may include Ar. Layer 150 may be formed by ion implantation, for example, of an inert gas element. Although shown beneath each resistor element 120, it should be understood that masking can be used to selectively form the doped HR layer 150 only beneath desired resistor elements 120.

[0055] After the above steps, as Figure 20 As shown, any technique now known or developed in the future (such as ashing process) can be used to remove mask 206.

[0056] return Figure 2 , 3 5, 6, 8, and 9, the method may further include sequentially interconnecting the ends 138 of a plurality of polysilicon resistor elements 120 to form a serpentine polysilicon resistor 136. The ends 138 may be interconnected by forming any of the conductive connectors 140 described herein. For example, Figure 1-6 Siliconized polycrystalline silicon conductors, or Figure 7-9 The metal connector 166 is shown. The polysilicon connector 160 can be formed by depositing polysilicon and then patterning the polysilicon to form the connector, which may be related to forming a polysilicon conductor 161 in an adjacent CMOS region 102. Figure 1 This is done simultaneously. Any necessary siliconization, BEOL, and / or MOL processes can then be performed to create interconnects with other layers. For example, in Figure 2 In this example, the terminal conductive connector 162 is the only polysilicon connector 160 that includes a silicide layer 163. In another example, such as... Figure 5 and 6 As shown, a silicide layer 163 may be included above all polysilicon connectors 160. In another embodiment, as... Figure 7-9 As shown, a metal connector 166 can be used. The metal connector 166 can be formed using any known process, the details of which are well known to those skilled in the art.

[0057] refer to Figure 21 It shows the relationship with Figure 17 A cross-sectional view of a preliminary structure 200 that is basically similar. Figure 21 It shows the formation as Figure 10-13The doped HR polysilicon region 170 is shown. Here, to create the doped HR polysilicon region 170, ion implantation is performed in the trench 126, i.e., before forming the polysilicon member 204 therein. As described above, the implanted dopant may include an inert gas element, such as argon (Ar), xenon (Xe), helium (He), krypton (Kr), and / or neon (Ne). In a non-limiting example, the dopant may include Ar. Any suitable dose and energy level can be used. Ion implantation forms a doped HR polycrystalline layer 150 located below the trench 126 and reaching the semiconductor substrate 104, and forms the doped HR polycrystalline region 170 located in the active semiconductor layer 108 adjacent to the sidewalls of the trench 126. Figure 22 As shown in the cross-sectional view, when the trench 126 is filled with the polysilicon component 204 as previously described, the outer wall 156 of the continuous U-shape 122 of each polysilicon resistor element 120 contacts the doped HR polysilicon region 170. Figure 22 It is also shown that an insulator 130 is formed in each polysilicon component 204 (as described above herein) thereby forming a continuous U-shape 122 for each polysilicon resistor element 120.

[0058] Figure 23 and 24 It shows the relationship with... Figure 21 and 22 The process described is the same as the process described, but also includes forming an insulating liner 174 in each trench 126 before forming a polysilicon component 204 in each trench. Figure 23 The formation of an insulating liner 174 following ion implantation of a doped HR polycrystalline layer 150 and a doped HR polycrystalline silicon region 170 is shown. The insulating liner 174 can be formed using any suitable deposition technique, such as ALD. It should be noted that an additional mask (not shown) may be required to prevent the insulating liner 174 from forming in unwanted locations, such as over the CMOS region 102. As described herein, Figure 23 and 24 In the embodiments, the resistor element 120 can be interconnected with the conductive connector 140—see, for example... Figure 14-16 .

[0059] Embodiments of this disclosure provide a resistor 100 comprising a compact and programmable serpentine trench resistor 136. The resistivity of resistor 100 can be customized, for example, by the number of resistor elements 120 used, the depth of each resistor element 120, and the dopant in the resistor elements 120. In a non-limiting example, at least 60% of the total resistivity of resistor 100 can be provided by the vertical extent of resistor elements 120. Since most of the resistivity is provided in the vertical portion of the continuous U-shaped resistor elements 120, resistor 100 has a small footprint and can operate without much effort, for example, accessing structures located beneath semiconductor substrate 104. The polysilicon of resistor 100 can be formed as part of BI-CMOS polysilicon and CMOS multiconductor polysilicon, thus eliminating the need to explicitly form trenches for the resistor, saving time and cost. It can be based on insulator 154 ( Figure 1-9 The thickness and type of ) and / or the presence of doped HR polysilicon regions 170 (e.g., Figure 10-13 Thermal conductivity and electrical isolation can be customized by adjusting the thickness, dopant type, and dopant concentration of the insulating liner. Insulating liner 174 ( Figure 14-16 ) for using doped HR polysilicon region 170 (e.g. Figure 10-13 The embodiments provide additional electrical and noise isolation and thermal conductivity customization. Furthermore, current leakage and thermal conductivity from resistor 100 to, for example, semiconductor substrate 104 can be controlled based on the thickness, dopant type, and dopant concentration of the doped HR polycrystalline layer 150.

[0060] The methods described above are used in the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as bare dies, or in packages. In the latter case, the chips are mounted in single-chip packages (e.g., plastic carriers with leads attached to a motherboard or other higher-level carriers) or multi-chip packages (e.g., ceramic carriers with surface interconnects and / or buried interconnects). In any case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0061] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It will be further understood that, when used in this specification, the terms “comprising” and / or “including” specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. “Optional” or “optionally” indicates that an event or condition subsequently described may or may not occur, and the description includes cases where the event occurs and cases where the event does not occur.

[0062] The approximate language used throughout the specification and claims can be used to modify any quantitative expression that allows for variation without causing a change in its associated essential function. Therefore, values ​​modified by one or more terms such as “about,” “approximate,” and “substantially” are not limited to the specified exact values. In at least some cases, approximate language may correspond to the precision of the instrument used to measure the value. In this document and throughout the specification and claims, range limitations can be combined and / or interchanged, such ranges being identified and including all subranges contained therein, unless the context or language indicates otherwise. The term “approximate” applied to a specific value within a range applies to both values ​​and, unless otherwise dependent on the precision of the instrument used to measure the value, may indicate + / - 10% of said value.

[0063] All the means or steps plus functional elements in the following claims are intended to include any structure, material, action, and equivalent that performs the function in combination with other claimed elements of the specific claim. The present disclosure has been described for purposes of illustration and description, but such description is not intended to be exhaustive or to limit the disclosure to the forms disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the disclosure. The embodiments were chosen and described in order to best explain the principles and practical application of the disclosure and to enable others skilled in the art to understand the various embodiments of the disclosure with various modifications suitable for the particular intended use.

Claims

1. A resistor, comprising: At least one polysilicon resistor element located in a semiconductor substrate, each polysilicon resistor element having a continuous U-shape having a continuous lateral bottom; Insulator located within the continuous U-shaped valley of each polysilicon resistor element; A doped high resistivity HR polycrystalline layer located beneath each polycrystalline silicon resistor element in the semiconductor substrate; as well as An insulating layer is located above the doped high resistivity HR polycrystalline layer, wherein each polycrystalline silicon resistor element extends through the insulating layer and into the doped high resistivity HR polycrystalline layer.

2. The resistor according to claim 1, wherein, The dopants in the doped high resistivity HR polycrystalline layer include inert gas elements.

3. The resistor according to claim 2, further comprising: The doped high resistivity HR polycrystalline region surrounding the outer wall of the continuous U-shape of each polycrystalline silicon resistor element.

4. The resistor according to claim 3, wherein, Each polysilicon resistor element is located within a trench in the semiconductor substrate, the trench having an insulating liner therein.

5. The resistor according to claim 1, wherein, Each insulator is also isolated by a trench that contacts the outer wall of the continuous U-shape of each polysilicon resistor element.

6. The resistor according to claim 1, further comprising: Multiple polysilicon resistor elements are sequentially coupled together to form a serpentine polysilicon resistor.

7. The resistor according to claim 6, wherein, The ends of the plurality of polysilicon resistor elements are sequentially coupled together via at least one polysilicon connector, wherein each polysilicon connector is located in the same layer as the polysilicon conductor layer of the adjacent CMOS region; as well as The silicide layer is located above at least one of the at least one polysilicon connector.

8. The resistor according to claim 6, wherein, The plurality of polysilicon resistor elements are sequentially coupled together through at least one metal connector in an interconnect layer above the semiconductor substrate.

9. The resistor according to claim 1, wherein, Each element has a depth greater than its width.

10. A resistor comprising: A plurality of interconnected polysilicon resistor elements are located in a semiconductor-on-insulator (SOI) substrate, each polysilicon resistor element having a continuous U-shape having a continuous lateral bottom, the plurality of polysilicon resistor elements forming a serpentine polysilicon resistor, wherein the SOI substrate includes a buried insulator layer located above a base semiconductor substrate. The trench isolation insulator is located within the continuous U-shaped valley of each polysilicon resistor element; as well as Located beneath the buried insulator layer and below each polycrystalline silicon resistor element in the base semiconductor substrate, the dopants in the doped high resistivity HR polycrystalline layer include inert gas elements. Each polycrystalline silicon resistor element extends through the buried insulating layer and into the doped high resistivity HR polycrystalline layer.

11. The resistor of claim 10, further comprising: The doped high resistivity HR polycrystalline region surrounding the outer wall of the continuous U-shape of each polycrystalline silicon resistor element.

12. The resistor according to claim 11, wherein, Each polysilicon resistor element is located within a trench in the SOI substrate, the trench having an insulating liner therein.

13. The resistor according to claim 10, wherein, The trench isolation insulator also contacts the outer wall of the continuous U-shape of each polysilicon resistor element.

14. The resistor according to claim 10, wherein, The ends of the plurality of polysilicon resistor elements are sequentially coupled together via at least one polysilicon connector, wherein each polysilicon connector is located in the same layer as the polysilicon conductor layer of the adjacent CMOS region; as well as The silicide layer is located above at least one of the at least one polysilicon connector.

15. The resistor according to claim 10, wherein, The plurality of polysilicon resistor elements are sequentially coupled together through at least one metal connector in an interconnect layer above the base semiconductor substrate.

16. A method for forming a serpentine polysilicon resistor, the method comprising: Multiple trenches are formed in a semiconductor-on-insulator (SOI) substrate, the SOI substrate including an active semiconductor layer located above a buried insulating layer located above a base semiconductor substrate, and each trench extending into the base semiconductor substrate; Fill each trench with polycrystalline silicon components; An insulator is formed in each polysilicon component, thereby forming a plurality of polysilicon resistor elements in a corresponding trench, each polysilicon resistor element having a continuous U-shape having a continuous lateral bottom, and the insulator being located in the valley of each U-shape; A doped high resistivity (HR) polycrystalline layer is formed in the base semiconductor substrate below the buried insulator layer and below each polycrystalline silicon resistor element, wherein the dopants in the doped high resistivity (HR) polycrystalline layer include inert gas elements. as well as The ends of the plurality of polysilicon resistor elements are sequentially interconnected to form the serpentine polysilicon resistor. Each polycrystalline silicon resistor element extends through the buried insulating layer and into the doped high resistivity HR polycrystalline layer.

17. The method according to claim 16, wherein, Forming the doped high resistivity HR polycrystalline layer includes forming a doped high resistivity HR polycrystalline region surrounding the outer wall of the continuous U-shape of each polycrystalline silicon resistor element.

18. The method according to claim 16, wherein, Forming the insulator in each polysilicon component further includes forming the insulator to contact the outer wall of the continuous U-shape of each polysilicon resistor element.

19. The method of claim 16, further comprising: An insulating liner is formed in each trench before the polycrystalline silicon component is formed in each trench.

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