A current anti-backflow timing synchronization control circuit for isolated DC-DC

Abstract

A kind of anti-current back-priming timing synchronization control circuit for isolated DC-DC, including drive signal detection circuit K1, self-locking circuit K2, drive control circuit K3.Drive signal detection circuit K1 in each cycle the level state of the collector of triode Q1 is monitored, the state of the primary side drive signal that primary side PWM control chip outputs is detected, realizes the control of C1 level.Self-locking circuit K2 carries out monitoring to C1 level state, the switch of self-locking circuit is passed through, realizes the control of C2 level state.Drive control circuit K3 carries out monitoring to C2 level state, the switch of secondary side drive chip is passed through, realizes the control of secondary side drive signal, to reach the purpose of the simultaneous output control of primary side drive signal and secondary side drive signal.

Description

TECHNICAL FIELD

[0001] The application relates to a current anti-backflow timing synchronous control circuit for an isolated DC-DC, and belongs to the electrical field. BACKGROUND

[0002] The DC-DC converter based on the synchronous rectification control mode greatly improves the energy conversion efficiency, but also brings the current backflow phenomenon, which is particularly prominent in the application scene of large-capacitance load. This condition seriously affects the efficiency, service life, safety and reliability of the spacecraft secondary power system. Due to the limitation of the selection range of components in the field of aerospace secondary power and the high requirement of the reliability of components in the extremely complex application environment in space, the commonly used current anti-backflow PWM control chip cannot be applied to the field of aerospace secondary power. SUMMARY

[0003] The application solves the technical problem that the commonly used current anti-backflow PWM control chip cannot be applied to the field of aerospace secondary power in the prior art.

[0004] The application solves the above technical problem through the following technical scheme:

[0005] The application relates to a current anti-backflow timing synchronous control circuit for an isolated DC-DC, and belongs to the electrical field.

[0006] The driving control circuit K3 comprises a primary PWM control chip and a secondary driving chip. The driving signal detection circuit K1 controls the level signal state of the output end of the driving signal detection circuit K1 according to the state of the primary driving signal output by the primary PWM control chip in each period. The self-locking circuit K2 controls the level state of the output end of the self-locking circuit K2 through the switching control of the self-locking circuit K2 itself according to the level state of the output end of the driving signal detection circuit K1. The driving control circuit K3 controls the output of the secondary driving signal through the switching control of the secondary driving chip according to the level state of the output end of the self-locking circuit K2, so as to realize the simultaneous output control of the primary driving signal and the secondary driving signal.

[0007] The driving signal detection circuit K1 comprises a triode Q1, resistors R1, R2, R3 and R4. The resistors R1 and R2 are connected in parallel, and one end of the parallel connection is connected to the PWM1 and PWM2 ends of the primary PWM control chip, and the other end is connected to the base of the triode Q1. One end of the resistor R4 is connected to the CLOCK pin of the primary PWM control chip, and the other end is connected to the collector of the triode Q1. One end of the resistor R3 is connected to the emitter of the triode Q1, and the other end is connected to the base of the triode Q1.

[0008] Self-locking circuit K2 includes resistance R5, resistance R6, resistance R7, resistance R8, resistance R9, resistance R 10 , resistance R 11 , triode Q2, triode Q3, diode D1, resistance R5, resistance R6 and the emitter-collector of triode Q2 are connected in series, one end of which is connected to +5V power supply and the other end is connected to ground, resistance R7, resistance R8 and the emitter-collector of triode Q3 are connected in series, one end of which is connected to +5V power supply and the other end is connected to ground, resistance R9, resistance R 10 , resistance R 11 are connected in series, one end of which is connected to +5V power supply and the other end is connected to ground, the base of triode Q2 is connected to the connection point of resistance R7 and resistance R8, the base of triode Q3 is connected to the connection point of resistance R5 and resistance R6, the anode of diode D1 is connected to the connection point of resistance R9 and resistance R 10 , the cathode is connected to the base of triode Q2, and the collector of triode Q1 is connected to the base of triode Q3.

[0009] In the driving signal detection circuit K1, the connection point C1 of R4 and the collector of Q1 is used as an output end, when the primary side driving signal disappears, the level state of C1 is high, when the primary side driving signal is normal, the level state of C1 is low.

[0010] In the self-locking circuit K2, C1 is connected to the connection point of R5, R6 and Q3, which is used as the input end of the self-locking circuit, and the connection point C2 of resistance R 10 , resistance R 11 is used as the output end, when C1 is in high level state, the primary side driving signal disappears, the level of C2 is clamped to low level state until the primary side driving signal is generated, when C1 is in low level state, the primary side driving signal is normal, the level of C2 is clamped to high level state.

[0011] In the driving control circuit K3, C2 is connected to the control pin of the secondary side driving chip, the switching of the secondary side driving signal is controlled according to the level state of C2 through the control pin, when the level state of C2 is high, the primary side driving signal is normal, the secondary side driving chip normally sends out the secondary side driving signal, when the level state of C2 is low, the primary side driving signal disappears, the secondary side driving chip suspends sending out the secondary side driving signal, so as to realize the simultaneous output control of the primary side driving signal and the secondary side driving signal.

[0012] The primary side PWM control chip adopts UC1825ALQMLV chip, the secondary side driving chip adopts UC1715W-SP chip, and the control pin is the ENBL pin of the UC1715W-SP chip.

[0013] Compared with the prior art, the present application has the following advantages:

[0014] (1) The application provides a current anti-backflow timing synchronization control circuit for an isolated DC-DC, wherein a PWM control chip is used, in normal operation, the phase of a CLOCK signal is ahead of that of a primary side PWM signal in each cycle, and in the process of starting up, the CLOCK signal is generated earlier than the primary side PWM signal, and in the process of shutting down, the CLOCK signal disappears later than the primary side PWM signal; the primary side driving signal is detected cycle by cycle, and then the switching of the secondary side driving signal is controlled, so that the primary and secondary side driving signals are switched on and off simultaneously, thereby inhibiting the backflow of the capacitor array energy to the secondary side MOS tube in the process of switching on and off;

[0015] (2) The application is simulated and verified at the circuit level by Saber, and the timing synchronization control circuit does not affect the normal operation of the main power circuit. The timing synchronization control circuit detects the primary side PWM control signal cycle by cycle, and once the PWM control signal disappears, the secondary side MOS tube is immediately turned off, so that the primary and secondary side driving signals are switched on and off simultaneously.

[0016] (3) The application takes a half-bridge-full-wave rectifier converter based on discrete components as an example to verify the timing synchronization control circuit. In the case of a large capacitor array at the load end, the output voltage and output current of the main power circuit are tested in the process of switching on and off. In the case of a residual voltage on the capacitor array, the output voltage remains monotonic. In the case of a capacitor array at the output end, the output current slowly decreases to zero under light load, and no current reverse flow phenomenon occurs. It is shown that the timing synchronization control circuit can effectively inhibit the backflow of the load current to the secondary side MOS tube in the synchronous rectification mode. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 A timing synchronization control circuit structure diagram is provided for the application;

[0018] Figure 2 A timing diagram of PWM1 signal, PWM2 signal, CLOCK signal and control signal C in the process of starting up is provided for the application;

[0019] Figure 3 A timing diagram of PWM1 signal, PWM2 signal, CLOCK signal and control signal C in the process of shutting down is provided for the application;

[0020] Figure 4 A simulation waveform schematic diagram of PWM1 signal, PWM2 signal, CLOCK signal and control signal C in the process of starting up is provided for the application;

[0021] Figure 5 A simulation waveform schematic diagram of PWM1 signal, PWM2 signal, CLOCK signal and control signal C in the process of shutting down is provided for the application;

[0022] Figure 6 A schematic diagram of the measured waveforms of the PWM1 signal, PWM2 signal, CLOCK signal, and control signal C during the power-on process provided for the invention;

[0023] Figure 7 A schematic diagram of the measured waveforms of the PWM1 signal, PWM2 signal, CLOCK signal, and control signal C during the shutdown process provided for the invention;

[0024] Figure 8 The PWM3 signal, PWM4 signal, and output voltage V provided for the invention during the power-on process when the load-side capacitor array has residual voltage are... o Measured waveform diagram;

[0025] Figure 9 The invention provides a PWM4 signal and a MOSFET V during the shutdown process when the output terminal has a capacitor array. ds Output current I o Measured waveform diagram; Detailed Implementation

[0026] A timing synchronization control circuit for preventing current backflow in isolated DC-DC converters solves the problem of current backflow under synchronous rectification mode control. Utilizing the characteristics of a PWM control chip during normal operation, where the CLOCK signal leads the primary-side PWM signal in each cycle, and the CLOCK signal is generated before the primary-side PWM signal during power-on and disappears after the primary-side PWM signal during power-off, the circuit controls the secondary-side drive signal by detecting the presence of a primary-side drive signal cycle by cycle. This achieves the effect of simultaneous power-on and power-off of both the primary and secondary sides, thereby suppressing current backflow from the load side to the secondary-side MOSFET and improving the stability and reliability of the aerospace secondary power supply. The specific circuit structure is as follows:

[0027] It includes a drive signal detection circuit K1, a self-locking circuit K2, and a drive control circuit K3, wherein:

[0028] The drive control circuit K3 includes a primary-side PWM control chip and a secondary-side drive chip. The drive signal detection circuit K1 controls the level signal state of its output terminal based on the primary-side drive signal state output by the primary-side PWM control chip in each cycle. The self-locking circuit K2 controls the level state of its output terminal based on the level state of the output terminal of the drive signal detection circuit K1 through its own switching control. The drive control circuit K3 controls the output of the secondary-side drive signal based on the level state of the output of the self-locking circuit K2 through the switching control of the secondary-side drive chip, thus achieving simultaneous output control of the primary-side drive signal and the secondary-side drive signal.

[0029] The drive signal detection circuit K1 includes a transistor Q1, resistors R1, R2, R3, and R4. Resistors R1 and R2 are connected in parallel, with one end connected to the PWM1 and PWM2 terminals of the primary-side PWM control chip and the other end connected to the base of transistor Q1. One end of resistor R4 is connected to the CLOCK pin of the primary-side PWM control chip and the other end is connected to the collector of transistor Q1. One end of resistor R3 is connected to the emitter of transistor Q1 and the other end is connected to the base of transistor Q1.

[0030] The self-locking circuit K2 includes resistors R5, R6, R7, R8, R9, and R... 10 Resistance R 11 Transistors Q2 and Q3, diode D1, resistors R5 and R6 are connected in series with the emitter and collector of transistor Q2, with one end connected to a +5V power supply and the other end grounded. Resistors R7 and R8 are connected in series with the emitter and collector of transistor Q3, with one end connected to a +5V power supply and the other end grounded. Resistors R9 and R... 10 Resistance R 11 The transistors are connected in series, with one end connected to a +5V power supply and the other end grounded. The base of transistor Q2 is connected to the junction of resistors R7 and R8, and the base of transistor Q3 is connected to the junction of resistors R5 and R6. The anode of diode D1 is connected to resistors R9 and R1. 10 The cathode of transistor Q2 is connected to the base of transistor Q2, and the collector of transistor Q1 is connected to the base of transistor Q3.

[0031] In the drive signal detection circuit K1, the collector connection point C1 of R4 and Q1 is used as the output terminal. When the primary drive signal disappears, the level of C1 is high, and when the primary drive signal is normal, the level of C1 is low.

[0032] In the self-locking circuit K2, C1 is connected to the junction of R5, R6, and Q3, serving as the input terminal of the self-locking circuit. Resistor R... 10 Resistance R 11 The connection point C2 is used as the output terminal. When C1 is in a high-level state, the primary-side drive signal disappears, and the level of C2 is clamped to a low-level state until the primary-side drive signal is generated. When C1 is in a low-level state, the primary-side drive signal is normal, and the level of C2 is clamped to a high-level state.

[0033] In the drive control circuit K3, C2 is connected to the control pin of the secondary drive chip. The control pin controls the switching of the secondary drive signal according to the level state of C2. When the level state of C2 is high, the primary drive signal is normal and the secondary drive chip normally sends out the secondary drive signal. When the level state of C2 is low, the primary drive signal disappears and the secondary drive chip stops sending out the secondary drive signal, so as to realize the simultaneous output control of the primary drive signal and the secondary drive signal.

[0034] The primary-side PWM control chip uses the UC1825ALQMLV chip, the secondary-side driver chip uses the UC1715W-SP chip, and the control pin is the ENBL pin of the UC1715W-SP chip.

[0035] The self-locking circuit K2 is powered by 5V. When the drive control circuit K3 is activated, the self-locking circuit K2 clamps the voltage at C2 to a low level until the primary drive signal is output normally. When the drive control circuit K3 stops, the self-locking circuit K2 clamps the voltage at C2 to a low level.

[0036] Specifically, due to the limited range of components available for use in the aerospace secondary power supply field and the high reliability requirements of components in the extremely complex application environment of space, commonly used anti-current backflow PWM control chips cannot be applied to the aerospace secondary power supply field. The circuit structure proposed in this invention utilizes the working characteristics of the PWM control chip, where the CLOCK signal phase leads the primary-side PWM signal in each cycle during normal operation, and the CLOCK signal is generated before the primary-side PWM signal during power-on and disappears after the primary-side PWM signal during power-off. By detecting whether there is a primary-side drive signal output cycle by cycle, the switching of the secondary-side drive signal is controlled, realizing the logic control function of simultaneous on and off of the primary and secondary-side drives, thereby suppressing the backflow of energy from the load-side capacitor array to the secondary-side MOSFET during power-on and power-off.

[0037] The following is a further explanation based on specific embodiments:

[0038] In the current embodiment, the circuit is as follows: Figure 1 As shown, the first part consists of R1, R2, R3, R4, and Q1, as follows: Figure 1 As shown in K1; the second part consists of R5, R6, R7, R8, R9, R 10 R 11 It consists of Q2, Q3 and D1, such as Figure 1 As shown in K2; the third part consists of a primary-side PWM control chip and a secondary-side driver chip, as shown in... Figure 1 As shown in K3;

[0039] When the PWM control chip is working normally, its CLOCK signal leads the primary PWM signal in each cycle. During power-on, the CLOCK signal is generated before the primary PWM signal, and during power-off, the CLOCK signal disappears after the primary PWM signal. Therefore, when the PWM control chip is working normally, transistor Q1 always clamps the voltage at point C1 to zero, preventing the latching circuit in K2 from starting, and the voltage at point C2 remains high. During power-on, because the CLOCK signal is generated before the primary PWM signal, it opens the latching circuit in K2 before the PWM signal is generated. At this time, the voltage at point C2 is clamped to a low level until the primary PWM signal is generated. The timing relationship is as follows: Figure 2 As shown. During the shutdown process, since the CLOCK signal disappears later than the primary-side PWM signal, once the primary-side PWM signal stops emitting waves, the CLOCK signal will open the self-locking circuit in K2. At this time, the voltage at point C2 is clamped to a low level. The timing relationship is as follows. Figure 3 As shown.

[0040] As the above analysis shows, during the entire operation cycle of the PWM control chip, when the primary-side PWM signal is generated normally, the voltage at point C2 in K2 is at a high level; if the primary-side PWM signal cannot be generated, the voltage at point C2 in K2 is at a low level. Therefore, the secondary-side driver chip in K3 can determine whether the primary-side PWM signal is generated normally based on the voltage level of C2, thereby controlling the turn-on and turn-off of the secondary-side MOSFET to achieve the effect of simultaneous on / off operation of the primary and secondary sides.

[0041] The circuit was simulated and verified using Saber software. The main power topology employs a half-bridge full-wave rectifier circuit, with a UC1825 chip for primary-side control and a UC1715 chip for secondary-side control. The self-locking circuit is supplied with 5V. Figure 4 As shown, during the power-on process, the CLOCK signal is generated before the primary-side PWM signal. Due to the self-locking circuit, the C2 voltage is clamped to a low level until the primary-side PWM signal is emitted normally. Figure 5 As shown, during the shutdown process, the CLOCK signal disappears later than the primary side PWM signal. Due to the action of the self-locking circuit, the C2 voltage is clamped to a low level.

[0042] The synchronous timing control circuit was physically verified. The main power topology uses a half-bridge full-wave rectifier circuit, the primary-side control chip is a UC1825 chip, the secondary-side control chip is a UC1715 chip, and the self-locking circuit is supplied with 5V. Figure 6 , Figure 7 As shown, PWM1 corresponds to Figure 1 The drive signal for MOSFET M1, CLOCK corresponds to Figure 1The CLOCK signal in the code, C corresponds to Figure 1 The voltage at point C2 in the middle, corresponding to PWM4. Figure 1 During power-on, the CLOCK signal for the MOSFET M4 is generated before the primary-side PWM signal. Due to the self-locking circuit, the voltage C2 is clamped low until the primary-side PWM signal is emitted normally. During power-off, the CLOCK signal disappears after the primary-side PWM signal. Again, due to the self-locking circuit, the voltage C2 is clamped low.

[0043] In addition, with a large capacitor array at the load end, power-on and power-off tests were performed on the output voltage and output current of the main power circuit. With residual voltage in the capacitor array upon power-on, the output voltage waveform is as follows: Figure 8 As shown in the figure, the output voltage maintains a monotonically increasing trend. When the output is powered off under light load with a capacitor array at the output, the output current waveform is as follows. Figure 9 As shown in the figure, the output current slowly decreases to zero, and no reverse current flow occurs.

[0044] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

[0045] The contents not described in detail in this specification are common knowledge to those skilled in the art.

Claims

1. A timing synchronization control circuit for preventing reverse current flow in an isolated DC-DC converter, characterized in that: It includes a drive signal detection circuit K1, a self-locking circuit K2, and a drive control circuit K3, wherein: The drive control circuit K3 includes a primary-side PWM control chip and a secondary-side drive chip. The drive signal detection circuit K1 controls the level signal state of the output terminal of the drive signal detection circuit K1 according to the primary-side drive signal state output by the primary-side PWM control chip in each cycle. The self-locking circuit K2 controls the level state of the output terminal of the self-locking circuit K2 through its own switching control according to the level state of the output terminal of the drive signal detection circuit K1. The drive control circuit K3 controls the output of the secondary-side drive signal according to the level state of the output terminal of the self-locking circuit K2 through the switching control of the secondary-side drive chip, thus completing the simultaneous output control of the primary-side drive signal and the secondary-side drive signal. The drive signal detection circuit K1 includes transistor Q1, resistors R1, R2, R3, and R4. Resistors R1 and R2 are connected in parallel, with one end connected to the PWM1 and PWM2 terminals of the primary-side PWM control chip and the other end connected to the base of transistor Q1. One end of resistor R4 is connected to the CLOCK pin of the primary-side PWM control chip and the other end is connected to the collector of transistor Q1. One end of resistor R3 is connected to the emitter of transistor Q1 and the other end is connected to the base of transistor Q1. The self-locking circuit K2 includes resistors R5, R6, R7, R8, R9, and R... 10 Resistance R 11 Transistors Q2 and Q3, diode D1, resistors R5 and R6 are connected in series with the emitter and collector of transistor Q2, with one end connected to a +5V power supply and the other end grounded. Resistors R7 and R8 are connected in series with the emitter and collector of transistor Q3, with one end connected to a +5V power supply and the other end grounded. Resistors R9 and R... 10 Resistance R 11 The transistors are connected in series, with one end connected to a +5V power supply and the other end grounded. The base of transistor Q2 is connected to the junction of resistors R7 and R8, and the base of transistor Q3 is connected to the junction of resistors R5 and R6. The anode of diode D1 is connected to resistors R9 and R1. 10 The cathode of transistor Q2 is connected to the base of transistor Q2, and the collector of transistor Q1 is connected to the base of transistor Q3. In the drive signal detection circuit K1, the collector connection point C1 of R4 and Q1 is used as the output terminal. When the primary drive signal disappears, the level of C1 is high, and when the primary drive signal is normal, the level of C1 is low. In the self-locking circuit K2, C1 is connected to the junction of R5, R6, and Q3, serving as the input terminal of the self-locking circuit. Resistor R... 10 Resistance R 11 The connection point C2 is used as the output terminal. When C1 is in a high-level state, the primary-side drive signal disappears, and the level of C2 is clamped to a low-level state until the primary-side drive signal is generated. When C1 is in a low-level state, the primary-side drive signal is normal, and the level of C2 is clamped to a high-level state. In the drive control circuit K3, C2 is connected to the control pin of the secondary drive chip. The control pin controls the switching of the secondary drive signal according to the level state of C2. When the level state of C2 is high, the primary drive signal is normal and the secondary drive chip normally sends out the secondary drive signal. When the level state of C2 is low, the primary drive signal disappears and the secondary drive chip stops sending out the secondary drive signal, so as to realize the simultaneous output control of the primary drive signal and the secondary drive signal.

2. The anti-reverse current timing synchronization control circuit for isolated DC-DC converters according to claim 1, characterized in that: The primary-side PWM control chip uses the UC1825ALQMLV chip, and the secondary-side driver chip uses the UC1715W-SP chip. The control pin is the ENBL pin of the UC1715W-SP chip.

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