Dual-frequency high-efficiency power amplifier and chip

Abstract

The application discloses a kind of dual-frequency high-efficiency power amplifiers and chip, wherein amplifier includes: input stage circuit, first amplification circuit, second amplification circuit and output stage circuit, the circuit structure of first amplification circuit and second amplification circuit is identical, and relatively symmetrical;First amplification circuit includes sequentially connected first dual-frequency matching circuit, first amplification transistor, second dual-frequency matching circuit, second amplification transistor and third dual-frequency matching circuit;The input end of first dual-frequency matching circuit is connected with the output end of input stage circuit, and the output end of third dual-frequency matching circuit is connected with the input end of output stage circuit.The application adopts two-way two-stage symmetrical structure, first-stage amplification circuit is gain stage, can provide sufficient gain for circuit, second-stage amplification circuit is power stage, can provide high enough output power for circuit;And last-stage two-way power synthesis structure realizes 3W output power.The application can be widely applied in wireless communication technology field.

Description

Technical Field

[0001] This invention relates to the field of wireless communication technology, and in particular to a dual-band high-efficiency power amplifier and chip. Background Technology

[0002] In modern and future wireless communication systems, the main difference between 5G communication technology and previous generations of mobile communication technologies lies in the allocation of spectrum resources. 5G networks will be deployed in both the Sub-6GHz high-frequency band and the millimeter-wave band, giving 5G communication a wider spectrum of resources. This, in turn, increases the requirements for circuits and subsystems with broadband or multi-band capabilities. Millimeter-wave (mm wave) spectrum is attracting significant interest in applications such as 5G and future satellite communications, which extend far beyond traditional military and scientific uses in terms of investment and potential commercial value. On the one hand, mm wave offers significant advantages in spectrum availability, providing substantial capacity for electronic information systems; on the other hand, the extremely high operating frequency presents significant challenges for system and circuit design. Power amplifiers (PAs) are among the most critical circuit components, requiring performance indicators that meet output power while satisfying other requirements such as efficiency, linearity, and power consumption. In the millimeter-wave band, power loss, component sensitivity, and the physical limitations of transistor technology make power amplifier design more challenging than at lower frequencies.

[0003] Base stations in 5G systems require high integration and compact power amplifiers with high output power. Gallium nitride (GaN) HEMT technology offers high efficiency, high breakdown voltage, and high power density, and significantly improves broadband performance due to higher switching frequencies and smaller peripherals, resulting in smaller input and output capacitances and less parasitics. Therefore, GaN monolithic microwave integrated circuits (MMICs) are an excellent choice.

[0004] To enable a smooth transition and upgrade of wireless communication systems, meet the requirements of high-capacity, fast, accurate, and distortion-free data transmission, and maintain compatibility with existing equipment in second- to fourth-generation communication systems, current requirements necessitate that the radio frequency front-end (RF front-end) can operate on multiple frequencies or in a wideband manner. This makes it particularly important to implement wideband or dual-band power amplifiers (PAs) that cover multiple frequency bands while maintaining high efficiency. Summary of the Invention

[0005] In order to at least partially solve one of the technical problems existing in the prior art, the present invention aims to provide a dual-frequency high-efficiency power amplifier and chip.

[0006] The technical solution adopted in this invention is:

[0007] A dual-frequency high-efficiency power amplifier includes an input stage circuit, a first amplification circuit, a second amplification circuit, and an output stage circuit. The first amplification circuit and the second amplification circuit have the same circuit structure and are symmetrical.

[0008] The first amplifier circuit includes a first dual-frequency matching circuit, a first amplifying transistor, a second dual-frequency matching circuit, a second amplifying transistor, and a third dual-frequency matching circuit connected in sequence.

[0009] The input terminal of the first dual-frequency matching circuit is connected to the output terminal of the input stage circuit, and the output terminal of the third dual-frequency matching circuit is connected to the input terminal of the output stage circuit.

[0010] Furthermore, the input stage circuit includes a microstrip line M0; a first end of the microstrip line M0 is connected to the radio frequency signal input terminal, and a second end of the microstrip line M0 is connected to the input terminal of the first dual-frequency matching circuit.

[0011] Furthermore, the first dual-frequency matching circuit includes a microstrip line M1, a capacitor C1, and a microstrip line M5 connected in series.

[0012] The first end of the microstrip line M1 is connected to the output end of the input stage circuit, the second end of the microstrip line M1 is connected to the first end of the microstrip line M5 through capacitor C1, and the second end of the microstrip line M5 is connected to the gate of the first amplifying transistor Q1.

[0013] Furthermore, the dual-frequency high-efficiency power amplifier also includes a capacitor C0 and a microstrip line M2;

[0014] The first end of the capacitor C0 is connected to the output end of the input stage circuit, and the second end of the capacitor C0 is grounded; the first end of the microstrip line M2 is connected to the connection point between the microstrip line M1 and the capacitor C1, and the second end of the microstrip line M2 is grounded.

[0015] Furthermore, the second dual-frequency matching circuit includes a microstrip line M6, a capacitor C4, and a microstrip line M9 connected in series.

[0016] The drain of the first amplifying transistor Q1 is connected to the first end of the microstrip line M6, the second end of the microstrip line M6 is connected to the first end of the microstrip line M9 through the capacitor C4, and the second end of the microstrip line M9 is connected to the gate of the second amplifying transistor Q2.

[0017] Furthermore, the third dual-frequency matching circuit includes microstrip lines M10, M12, and M14 connected in series.

[0018] The first end of the microstrip line M10 is connected to the drain of the second amplifying transistor Q2, the second end of the microstrip line M10 is connected to the first end of the microstrip line M14 through the microstrip line M12, and the second end of the microstrip line M14 is connected to the input terminal of the output stage circuit.

[0019] Furthermore, the output stage circuit includes a microstrip line M15 and a capacitor C9 connected in series;

[0020] The first end of the microstrip line M15 is connected to the output of the third dual-frequency matching circuit, and the second end of the microstrip line M15 is connected to the radio frequency signal output through the capacitor C9.

[0021] Furthermore, a first isolation circuit and a second isolation circuit are provided between the first amplifier circuit and the second amplifier circuit;

[0022] The first isolation circuit includes a microstrip line M41, a resistor R0, and a microstrip line M42 connected in series. The first end of the microstrip line M41 is connected to the first dual-frequency matching circuit, the second end of the microstrip line M41 is connected to the first end of the resistor R0, the second end of the resistor R0 is connected to the microstrip line M42, and the microstrip lines M41 and M42 are symmetrically arranged on both sides of the resistor R0.

[0023] The second isolation circuit includes a microstrip line M111, a resistor R3, and a microstrip line M112 connected in series. The first end of the microstrip line M111 is connected to the third dual-frequency matching circuit, the second end of the microstrip line M111 is connected to the first end of the resistor R3, and the second end of the resistor R3 is connected to the microstrip line M112. The microstrip lines M111 and M112 are symmetrically arranged on both sides of the resistor R3.

[0024] Furthermore, the first amplifier circuit also includes a first gate bias circuit, a first drain bias circuit, a second gate bias circuit, and a second drain bias circuit.

[0025] The first gate bias circuit includes a microstrip line M3 and a resistor R1; the first end of the microstrip line M3 is connected to the DC input VG1, the second end of the microstrip line M3 is connected to the first end of the resistor R1, and the second end of the resistor R1 is connected to the first dual-frequency matching circuit.

[0026] The first drain bias circuit includes a microstrip line M7, a capacitor C2, and a capacitor C3; the first end of the microstrip line M7 is connected to the second dual-frequency matching circuit, and the second end of the microstrip line M7 is connected to the DC input VD1; one end of the capacitor C2 is connected to the DC input VD1, and the other end is grounded; one end of the capacitor C3 is connected to the DC input VD1, and the other end is grounded.

[0027] The second gate bias circuit includes a microstrip line M8 and a resistor R2; the first end of the microstrip line M8 is connected to the DC input VG2, the second end of the microstrip line M8 is connected to the first end of the resistor R2, and the second end of the resistor R2 is connected to the second dual-frequency matching circuit.

[0028] The second drain bias circuit includes a microstrip line M13, a capacitor C6, and a capacitor C7; the first end of the microstrip line M13 is connected to the third dual-frequency matching circuit, and the second end of the microstrip line M13 is connected to the DC input VD2; one end of the capacitor C6 is connected to the DC input VD2, and the other end is grounded; one end of the capacitor C7 is connected to the DC input VD2, and the other end is grounded.

[0029] Another technical solution adopted in this invention is:

[0030] A communication chip includes a dual-frequency high-efficiency power amplifier as described above.

[0031] The beneficial effects of this invention are: this invention adopts a two-way, two-stage symmetrical structure, the first-stage amplifier circuit is a gain stage, which can provide sufficient gain for the circuit, the second-stage amplifier circuit is a power stage, which can provide sufficiently high output power for the circuit; and the final stage two-way power combining structure achieves an output power of 3W. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following description is provided with accompanying drawings of the relevant technical solutions in the embodiments of the present invention or the prior art. It should be understood that the accompanying drawings described below are only for the purpose of clearly illustrating some embodiments of the technical solutions of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a schematic diagram of the structure of a dual-frequency high-efficiency power amplifier according to an embodiment of the present invention;

[0034] Figure 2 This is a schematic diagram of the overall circuit of a dual-frequency high-efficiency power amplifier according to an embodiment of the present invention;

[0035] Figure 3 This is a schematic diagram of the dual-frequency input matching circuit in an embodiment of the present invention;

[0036] Figure 4 This is a schematic diagram of the S-parameter simulation results of the dual-frequency input matching circuit in an embodiment of the present invention;

[0037] Figure 5 This is a schematic diagram of the inter-frequency matching circuit in an embodiment of the present invention;

[0038] Figure 6 This is a schematic diagram of the S-parameter simulation results of the inter-frequency matching circuit in an embodiment of the present invention;

[0039] Figure 7 This is a schematic diagram of the dual-frequency output matching circuit in an embodiment of the present invention;

[0040] Figure 8 This is a schematic diagram of the S-parameter simulation results of the dual-frequency output matching circuit in an embodiment of the present invention;

[0041] Figure 9 This is a schematic diagram of the small-signal simulation results in an embodiment of the present invention;

[0042] Figure 10 This is a schematic diagram of the circuit stability simulation results in an embodiment of the present invention;

[0043] Figure 11 This is a schematic diagram of the simulation results of the output power (Pout) changing with the input power (Pin) at 28GHz and 39GHz in an embodiment of the present invention;

[0044] Figure 12 This is a schematic diagram of the simulation results of the power-added efficiency (PAE) as a function of output power (Pout) at 28 GHz and 39 GHz in an embodiment of the present invention.

[0045] Figure 13 This is a schematic diagram of the simulation results of the large signal gain (Gain) as a function of output power (Pout) at 28GHz and 39GHz in an embodiment of the present invention. Detailed Implementation

[0046] The embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. The step numbers in the following embodiments are set only for ease of explanation, and there is no limitation on the order between the steps. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0047] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0048] In the description of this invention, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0049] In the description of this invention, unless otherwise explicitly defined, terms such as "set up," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0050] like Figure 1 and Figure 2 As shown, this embodiment provides a dual-band high-efficiency power amplifier. Optionally, the amplifier is a dual-band high-efficiency power amplifier based on 0.15um GaN HEMT technology, operating at 28GHz and 39GHz. The dual-band high-efficiency power amplifier includes: an input stage circuit, a first amplification circuit, a second amplification circuit, and an output stage circuit.

[0051] In this embodiment, a signal path is formed by two circuits: a first amplifier circuit and a second amplifier circuit. Both the first amplifier circuit and the second amplifier circuit employ two-stage amplification. After the first amplifier circuit and the second amplifier circuit are connected in parallel, the left end is connected to the output terminal of the input stage circuit, and the right end is connected to the input terminal of the output stage circuit. The input terminal of the input stage circuit is connected to the radio frequency signal input terminal, and the output terminal of the output stage circuit is the radio frequency signal output terminal.

[0052] The first amplifier circuit adopts a two-stage amplification structure, including: a first dual-frequency matching circuit, a first gate bias circuit, a first isolation circuit, a first amplifying transistor, a first drain bias circuit, a second dual-frequency matching circuit, a second gate bias circuit, a second amplifying transistor, a second drain bias circuit, a second isolation circuit, and a third dual-frequency matching circuit; wherein, the first dual-frequency matching circuit is connected to the output terminal of the input stage circuit at the left-hand junction point, the drain of the first amplifying transistor is connected to the input terminal of the second dual-frequency matching circuit, the output terminal of the second dual-frequency matching circuit is connected to the gate of the second amplifying transistor, and the third dual-frequency matching circuit is connected to the input terminal of the output stage circuit at the right-hand junction point.

[0053] The signal path structure, layout, component parameter settings, and function implementation of the second amplifier circuit are the same as those of the first amplifier circuit. The first and second amplifier circuits are symmetrical about the upper and lower paths of the RF signal input and output terminals. The phase and amplitude of the upper and lower signals reduce the loss of power combining of the upper and lower signals at the output terminal.

[0054] The output terminals of the first and second dual-frequency matching circuits are respectively provided with a first gate bias circuit and a second gate bias circuit, and the input terminals of the second and third dual-frequency matching circuits are respectively provided with a first drain bias circuit and a second drain bias circuit; wherein, the upper ends of the first and second gate bias circuits are respectively connected to the DC input terminals VG1 and VG2, and the upper ends of the first and second drain bias circuits are respectively connected to the DC input terminals VD1 and VD2; the sources of the first and second amplifying transistors are both grounded.

[0055] The input stage circuit includes a microstrip line M0; wherein the left end of the microstrip line M0 is connected to the RF signal input terminal, and the right end is connected to the input terminal of the first dual-frequency matching circuit; the input stage circuit is used to match the input impedance of the RF signal input port to 50 ohms.

[0056] The first dual-frequency matching circuit, i.e., the dual-frequency input matching circuit, is as follows: Figure 3 As shown, the circuit includes a microstrip line M1, a capacitor C1, and a microstrip line M5 connected in series. A capacitor C0 is located between microstrip line M1 and microstrip line M0, and a microstrip line M2 is located between microstrip line M1 and capacitor C1. The left end of capacitor C0 is connected to the output of the input stage circuit, and the right end is grounded. One end of microstrip line M2 is connected between microstrip line M1 and capacitor C1, and the other end is grounded. The output of microstrip line M5 is connected to the gate of the first amplifying transistor Q1. From left to right, the grounded capacitor C0 and the series-connected microstrip line M1 provide a resonant point at 28 GHz, and the grounded microstrip line M2 and the series-connected capacitor C1 provide a resonant point at 39 GHz. The series-connected microstrip line M5 on the right provides tuning for the dual-frequency input matching circuit, and the series capacitor C1 also acts as a DC blocking capacitor, effectively preventing the influence between the upper and lower DC inputs VG1 and blocking DC signals from flowing into the RF input terminal. The schematic diagram of the S-parameter simulation results of the dual-frequency input matching circuit of this invention is shown below. Figure 4 As shown.

[0057] The first gate bias circuit includes a microstrip line M3 and a resistor R1; wherein, the upper end of the microstrip line M3 is connected to the DC input VG1, and the lower end of the resistor R1 is connected between the capacitor C1 and the microstrip line M5; the first gate bias circuit serves to allow DC to pass through the gate and prevent radio frequency signals from flowing into the power supply port; wherein, since the radio frequency input signals are all blocked by the resistor R1, the length of the microstrip line M3 is adjustable to meet the layout requirements.

[0058] The first isolation circuit is connected between the first dual-frequency matching circuit of the first amplifier circuit and the second amplifier circuit, and includes two microstrip lines M4 connected in series and a resistor R0. One end of the microstrip line M4 is connected between the capacitor C1 and the microstrip line M5. The isolation resistor R0 is 152 ohms. The first isolation circuit reduces the energy reflection loss at the output of the dual-frequency input matching circuit.

[0059] The second dual-frequency matching circuit, i.e., the inter-frequency matching circuit, is as follows: Figure 5 As shown, the circuit includes a microstrip line M6, a capacitor C4, and a microstrip line M9 connected in series. A microstrip line M7 is connected between microstrip line M6 and capacitor C4, and a capacitor C5 is connected between capacitor C4 and microstrip line M9. One end of capacitor C5 is connected between capacitor C4 and microstrip line M9, and the other end is grounded. The input terminal of microstrip line M6 is connected to the drain of the first amplifying transistor Q1, and the output terminal of microstrip line M9 is connected to the gate of the second amplifying transistor Q2. From right to left, the series microstrip line M9 and the grounded capacitor C5 provide a resonant point at 28 GHz, and the series capacitor C4 and the grounded microstrip line M7 provide a resonant point at 39 GHz. The series microstrip line M6 on the left provides tuning for the inter-stage matching circuit, and the series capacitor C4 also acts as an inter-stage DC capacitor, effectively preventing interference between the first-stage drain DC input VD1 and the second-stage gate DC input VG2. A schematic diagram of the S-parameter simulation results of the inter-stage matching circuit of this invention is shown below. Figure 6 As shown.

[0060] The first drain bias circuit includes a microstrip line M7, capacitor C2, and capacitor C3. The right ends of capacitors C2 and C3 are connected to the DC input VD1, and the lower end of microstrip line M7 is connected between microstrip line M6 and capacitor C4. The first drain bias circuit supplies power to the drain of the first amplifying transistor Q1 and prevents the radio frequency signal from entering the DC input VD1. Capacitors C2 and C3 are both 1.77pF to suppress the radio frequency signal from entering the DC input. Microstrip line M7 participates in the impedance matching of the inter-frequency matching circuit.

[0061] The second gate bias circuit includes a microstrip line M8 and a resistor R2; wherein, the upper end of the microstrip line M8 is connected to the DC input VG2, and the lower end of the resistor R2 is connected between the capacitor C4 and the microstrip line M9; the second gate bias circuit has the same structure as the first gate bias circuit, but the parameters are different, and the required simulation requirements are met by adjustment and optimization.

[0062] The third dual-frequency matching circuit, i.e., the dual-frequency output matching circuit, is as follows: Figure 7As shown, the circuit includes microstrip lines M10, M12, and M14 connected in series. A microstrip line M13 is connected between M12 and M14. A capacitor C8 is connected between M14 and the output stage circuit. The input terminal of microstrip line M12 is connected to the drain of the second amplifying transistor Q2. The right end of capacitor C8 is connected to the input terminal of the output stage circuit, and the left end is grounded. From right to left, the grounded capacitor C8, together with the series-connected microstrip lines M14 and M12, provides a resonant point at 39 GHz. The grounded microstrip line M13 and the series-connected microstrip line M12 provide a resonant point at 28 GHz. The series-connected microstrip line M10 at the left end provides tuning for the dual-frequency output matching circuit. The dual-frequency output matching network performs power combining of the two signals at the end and optimizes the output return loss, enabling the invention to achieve maximum output power. A schematic diagram of the S-parameter simulation results of the dual-frequency output matching circuit of this invention is shown below. Figure 8 As shown.

[0063] The second drain bias circuit includes microstrip line M13, capacitor C6, and capacitor C7. The right ends of capacitors C6 and C7 are connected to the DC input VD2, and the lower end of microstrip line M13 is connected between microstrip lines M12 and M14. The second drain bias circuit has the same structure as the first drain bias circuit, but different parameters, which are adjusted and optimized to meet the required design requirements. The second drain bias circuit supplies power to the drain of the second amplifying transistor Q2 and prevents the radio frequency signal from entering the DC input VD2. Capacitors C6 and C7 are both 1.77pF to suppress the radio frequency signal from entering the DC input. Microstrip line M13 participates in the impedance matching of the dual-frequency output matching circuit.

[0064] The second isolation circuit is connected between the first amplifier circuit and the third dual-frequency matching circuit of the second amplifier circuit. It includes two microstrip lines M11 connected in series and a resistor R3. One end of the microstrip line M11 is connected between microstrip lines M10 and M12. The second isolation circuit has the same structure as the first isolation circuit, but different parameters. The isolation resistor R3 is 152 ohms, which reduces the energy reflection loss at the input of the dual-frequency output matching circuit.

[0065] The output stage circuit includes a microstrip line M15 and a capacitor C9 connected in series. The left end of the microstrip line M15 is connected to the output terminal of the third dual-frequency matching circuit, and the right end of the capacitor C9 is connected to the RF signal output terminal, which acts as a DC blocking capacitor and effectively prevents the drain DC input VD2 from flowing into the RF output terminal.

[0066] The gate width of the first amplifying transistor Q1 is 4*50um, and the gate width of the second amplifying transistor Q2 is 4*100um. In order to obtain an output power of 4W, various matching losses were considered in the design and sufficient loss margin was reserved. As the total gate width of the transistor increases, the output power capability of the transistor increases, but at the same time the gain of the transistor decreases. Finally, the performance was weighed and the two transistors of the above size were selected as a compromise. The static operating points of the transistors are set as follows: both the upper and lower paths are Class AB, the first gate DC voltage is VG1 = -1.7V, the second gate DC voltage is VG2 = -1.5V, and the drain DC voltages VD1 and VD2 are both 28V.

[0067] according to Figure 9 , Figure 10 The schematic diagrams of small-signal simulation and circuit stability simulation results show that at 28 GHz, the small-signal gain S21 is greater than 26 dB; at 39 GHz, the small-signal gain S21 is greater than 15 dB; the input return loss S11 at both frequencies is below -11 dB; the output return loss S22 at both frequencies is below -17 dB; and StabFact is greater than 1, indicating that the overall matching degree and stability of the circuit have achieved excellent results.

[0068] according to Figure 11 The simulation results shown are illustrated at 28 GHz and 39 GHz, where the output power (Pout) varies with the input power (Pin). It can be seen that as the input power increases, the saturated output power at both operating frequencies reaches 35 dBm, or 3 W.

[0069] according to Figure 12 The simulation results of power-added efficiency (PAE) at 28 GHz and 39 GHz as a function of output power are shown in the figure. It can be seen that as the output power increases, the peak PAE at 28 GHz reaches 38% and the peak PAE at 39 GHz reaches 29%.

[0070] according to Figure 13 The simulation results of the large-signal gain at 28 GHz and 39 GHz as a function of input power are shown in the diagram. It can be seen that as the output power increases, the large-signal gain at both operating frequencies slowly decreases from a linear gain.

[0071] This power amplifier achieves a size of 1.6mm*1.2mm, which is smaller than existing GaN process power amplifiers.

[0072] In summary, the dual-frequency high-efficiency power amplifier of this embodiment has the following advantages and beneficial effects compared with the prior art:

[0073] (1) The present invention adopts a two-way two-stage symmetrical structure, wherein the first stage amplifier circuit is a gain stage that can provide sufficient gain for the circuit, and the second stage amplifier circuit is a power stage that can provide sufficiently high output power for the circuit; and the final stage two-way power combining structure achieves an output power of 3W.

[0074] (2) The present invention balances the overall circuit stability and gain. Since the losses caused by the parasitic parameters of each passive and active device are sufficient to make the circuit stable, the present invention reduces the traditional RC parallel stabilization circuit, thereby improving the gain.

[0075] (3) The overall circuit of this invention uses microstrip lines and capacitors to design dual-frequency input, inter-stage, and output matching circuits. Adjustment and optimization are simple and feasible. In addition, since the grounding inductor can be equivalent to a short-circuited microstrip line and the grounding capacitor can be equivalent to an open-circuited microstrip line in the millimeter-wave band, the loss caused by the components themselves is greatly reduced by using microstrip lines to replace unnecessary lumped components.

[0076] (4) The drain bias circuit and the dual-frequency matching circuit used in this invention reuse the same microstrip line, which not only provides DC signal input, but also participates in the impedance matching of the circuit. Taking all the above factors into account, this invention can meet various performance parameters while reducing the circuit size.

[0077] This embodiment also provides a communication chip, which includes, as shown in the example below. Figure 1 The dual-frequency high-efficiency power amplifier shown is shown.

[0078] The communication chip in this embodiment corresponds to the dual-frequency high-efficiency power amplifier described above, and therefore possesses the corresponding functions and beneficial effects of the amplifier embodiment.

[0079] In the foregoing description of this specification, references to terms such as "one embodiment," "another embodiment," or "some embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of the present invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0080] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

[0081] The above is a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. A dual-frequency high-efficiency power amplifier, characterized in that, The operating frequencies are 28GHz and 39GHz, and it includes an input stage circuit, a first amplifier circuit, a second amplifier circuit, and an output stage circuit. The first amplifier circuit and the second amplifier circuit have the same circuit structure and are symmetrical. The dual-frequency high-efficiency power amplifier also includes capacitor C0, microstrip line M2, microstrip line M7, microstrip line M13, and capacitor C8. The first amplifier circuit includes a first dual-frequency matching circuit, a first amplifying transistor, a second dual-frequency matching circuit, a second amplifying transistor, and a third dual-frequency matching circuit connected in sequence. The input terminal of the first dual-frequency matching circuit is connected to the output terminal of the input stage circuit, and the output terminal of the third dual-frequency matching circuit is connected to the input terminal of the output stage circuit. The first dual-frequency matching circuit includes a microstrip line M1, a capacitor C1, and a microstrip line M5. The first end of microstrip line M1 is connected to the output of the input stage circuit, and the second end of microstrip line M1 is connected to the first end of microstrip line M5 via capacitor C1. The second end of microstrip line M5 is connected to the gate of the first amplifying transistor Q1. One end of capacitor C0 is connected to the first end of microstrip line M1, and the second end of capacitor C0 is grounded. The first end of microstrip line M2 is connected to the junction between microstrip line M1 and capacitor C1, and the second end of microstrip line M2 is grounded. Capacitor C0 and microstrip line M1 provide a resonant point at 28 GHz, microstrip line M2 and capacitor C1 provide a resonant point at 39 GHz, and microstrip line M5 provides tuning for the first dual-frequency matching circuit; at the same time, capacitor C1 also serves as DC blocking. The second dual-frequency matching circuit includes a microstrip line M6, a capacitor C4, a capacitor C5, and a microstrip line M9. The drain of the first amplifying transistor Q1 is connected to the first end of the microstrip line M6. The second end of the microstrip line M6 is connected to the first end of the microstrip line M9 through the capacitor C4. The second end of the microstrip line M9 is connected to the gate of the second amplifying transistor Q2. One end of the microstrip line M7 is connected to the second end of the microstrip line M6, and the other end is connected to the bias voltage VD1. One end of the capacitor C5 is connected to the first end of the microstrip line M9, and the other end is grounded. Microstrip line M9 and capacitor C5 provide a resonant point at 28 GHz, capacitor C4 and microstrip line M7 provide a resonant point at 39 GHz, and microstrip line M6 provides tuning for the second dual-frequency matching circuit; at the same time, capacitor C4 also serves as DC blocking. The third dual-frequency matching circuit includes microstrip line M10, microstrip line M12, and microstrip line M14; the first end of microstrip line M10 is connected to the drain of the second amplifying transistor Q2, the second end of microstrip line M10 is connected to the first end of microstrip line M14 through microstrip line M12, and the second end of microstrip line M14 is connected to the input terminal of the output stage circuit; one end of microstrip line M13 is connected to the first end of microstrip line M14, and the other end is connected to the bias voltage VD2; the first end of capacitor C8 is connected to the second end of microstrip line M14, and the second end of capacitor C8 is grounded; Capacitor C8 provides a resonant point at 39 GHz with microstrip lines M14 and M12, microstrip lines M13 and M12 provide a resonant point at 28 GHz, and microstrip line M10 provides tuning for the third dual-frequency matching circuit.

2. The dual-frequency high-efficiency power amplifier according to claim 1, characterized in that, A first isolation circuit and a second isolation circuit are also provided between the first amplifier circuit and the second amplifier circuit; The first isolation circuit includes a microstrip line M41, a resistor R0, and a microstrip line M42 connected in series. The first end of microstrip line M41 is connected to the first end of microstrip line M5 in the first amplifier circuit. The second end of microstrip line M41 is connected to the first end of resistor R0. The second end of resistor R0 is connected to the first end of microstrip line M42. The second end of microstrip line M42 is connected to the first end of microstrip line M5 in the second amplifier circuit. Microstrip lines M41 and M42 are symmetrically arranged on both sides of resistor R0. The second isolation circuit includes a microstrip line M111, a resistor R3, and a microstrip line M112 connected in series. The first end of the microstrip line M111 is connected to the second end of the microstrip line M10 in the first amplifier circuit. The second end of the microstrip line M111 is connected to the first end of the resistor R3. The second end of the resistor R3 is connected to the first end of the microstrip line M112. The second end of the microstrip line M112 is connected to the second end of the microstrip line M10 in the second amplifier circuit. The microstrip lines M111 and M112 are symmetrically arranged on both sides of the resistor R3.

3. A communication chip, characterized in that, Includes the dual-frequency high-efficiency power amplifier as described in claim 1 or 2.

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