Charge pump circuit for phase-locked loop

Abstract

This invention provides a charge pump circuit for a phase-locked loop (PLL), relating to the field of integrated circuit radio frequency circuit technology. The device includes: a bias circuit; and a main charge pump core circuit for generating low mismatch current, comprising a charging branch, a switching branch, and a discharging branch, the switching branch being connected to both the charging and discharging branches; wherein the bias circuit generates the bias voltages required for the charging and discharging branches respectively; the charging branch includes a first operational amplifier and has a first node and a second node, the charging branch being used to clamp the first node and the second node to equalize their potentials; the discharging branch includes a second operational amplifier and has a third node and a fourth node, the discharging branch being used to clamp the third node and the fourth node to equalize their potentials. This invention increases the voltage output range of the charge pump while ensuring a low mismatch current.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit radio frequency circuit technology, and in particular to a charge pump circuit for a phase-locked loop. Background Technology

[0002] With the advent of the 5G and IoT era, and the continuous increase in data transmission rates in modern communication systems, low-jitter, low-spurious clock signals are becoming increasingly important. During modulation / demodulation in wireless communication systems, excessive spurious clock signals can cause crosstalk to adjacent channels, leading to a decrease in the signal-to-noise ratio and deteriorating communication quality.

[0003] In current wireless communication systems, the clock signal is typically provided by a phase-locked loop (PLL). Charge-pump PLLs, with their high performance and low power consumption, have become a classic PLL implementation method. For example... Figure 1 As shown, the existing charge pump phase-locked loop includes modules such as a frequency and phase discriminator 101, a charge pump 102, a low-pass filter 103, a voltage-controlled oscillator 104, and a frequency divider 105. Among them, the charge pump 102 is a core module in the charge pump phase-locked loop. Its main function is to convert the error signal generated by the preceding frequency and phase discriminator 101 into charge and inject it into the low-pass filter 103, thereby controlling the voltage-controlled oscillator 104 to generate a signal of the correct frequency.

[0004] The charge pump operates in four states: charging, discharging, dead-zone protection, and high-impedance. When the phase-locked loop (PLL) is locked, the charge pump is in both the dead-zone and high-impedance states. In the dead-zone state, the charge pump needs to have a small mismatch current to prevent it from losing lock and causing output stray noise. In the high-impedance state, the charging branch and the discharging branch need to exhibit high-impedance characteristics at the Vcont port.

[0005] Therefore, the performance of the charge pump has a significant impact on the overall performance of the phase-locked loop, mainly including: (1) the mismatch between the upper and lower currents of the charge pump is the main source of stray noise in the phase-locked loop; (2) the magnitude of the charge pump current affects the noise of the phase-locked loop; (3) the output voltage range of the charge pump determines the input voltage range of the voltage-controlled oscillator.

[0006] Therefore, how to achieve a charge pump with low mismatch, low noise, and wide output range is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0007] In view of the above problems, the present invention provides a charge pump circuit for a phase-locked loop, which increases the voltage output range of the charge pump while ensuring a small mismatch current.

[0008] The present invention provides a charge pump circuit for a phase-locked loop, comprising: a bias circuit 301; a main charge pump core circuit 302 for generating low mismatch current, including a charging branch 303, a switching branch 304, and a discharging branch 305, wherein the switching branch 304 is connected to the charging branch 303 and the discharging branch 305 respectively; wherein, the bias circuit 301 is used to generate the bias voltage required by the charging branch 303 and the discharging branch 305 respectively; the charging branch 303 includes a first operational amplifier OP1 and is provided with a first node N1 and a second node N2, and the charging branch 303 is used to clamp the first node N1 and the second node N2 with the first operational amplifier OP1; the discharging branch 305 includes a second operational amplifier OP2 and is provided with a third node N3 and a fourth node N4, and the discharging branch 305 is used to clamp the third node N3 and the fourth node N4 with the second operational amplifier OP2.

[0009] Furthermore, the current at the first node N1 is equal to the current at the third node N3.

[0010] Further, the bias circuit 301 includes a current source I1, a first resistor R1, a second resistor R2, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a fifth PMOS transistor MP5, and a sixth PMOS transistor MP6. The current source I1, the first resistor R1, the fifth NMOS transistor MN5, and the seventh NMOS transistor MN7 are connected in series between the power supply terminal VDD and the ground terminal GND. The gate of the fifth NMOS transistor MN5 is connected to the junction of the current source I1 and the first resistor R1. The gate of the seventh NMOS transistor MN7 is connected to the junction of the first resistor R1 and the fifth NMOS transistor MP6. At the connection point of transistor MN5; the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, the second resistor R2, the sixth NMOS transistor MN6 and the eighth NMOS transistor MN8 are connected in series between the power supply terminal VDD and the ground terminal GND. The gate of the fifth PMOS transistor MP5 is connected to the connection point of the second resistor R2 and the sixth PMOS transistor MP6. The gate of the sixth PMOS transistor MP6 is connected to the connection point of the second resistor R2 and the sixth NMOS transistor MN6. The gate of the sixth NMOS transistor MN6 is connected to the gate of the fifth NMOS transistor MN5. The gate of the eighth NMOS transistor MN8 is connected to the gate of the seventh NMOS transistor MN7.

[0011] Furthermore, the sixth NMOS transistor MN6 has the same size as the fifth NMOS transistor MN5, and the eighth NMOS transistor MN8 has the same size as the seventh NMOS transistor MN7.

[0012] Furthermore, the charging branch 303 also includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, and a fourth PMOS transistor MP4, wherein: the first PMOS transistor MP1 is connected in series between the power supply terminal VDD and the positive input terminal of the first operational amplifier OP1; the second PMOS transistor MP2 is connected in series between the power supply terminal VDD and the negative input terminal of the first operational amplifier OP1; the gates of the first PMOS transistor MP1 and the second PMOS transistor MP2 are connected together to the gate of the fifth PMOS transistor MP5 of the bias circuit 301; the third PMOS transistor MP3 is connected in series between the positive input terminal of the first operational amplifier OP1 and the discharge branch 305; the gate of the third PMOS transistor MP3 is connected to the gate of the sixth PMOS transistor MP6 of the bias circuit 301; the fourth PMOS transistor MP4 is connected in series between the negative input terminal of the first operational amplifier OP1 and the switching branch 304; the gate of the fourth PMOS transistor MP4 is connected to the output terminal of the first operational amplifier OP1; the first node N1 and the second node N2 are respectively disposed at the positive input terminal and the negative input terminal of the first operational amplifier OP1.

[0013] Furthermore, the size of the first PMOS transistor MP1 is twice the size of the fifth PMOS transistor MP5 in the bias circuit 301, and the size of the third PMOS transistor MP3 is twice the size of the sixth PMOS transistor MP6 in the bias circuit 301; the size of the second PMOS transistor MP2 is ten times the size of the first PMOS transistor MP1, and the size of the fourth PMOS transistor MP4 is ten times the size of the third PMOS transistor MP3.

[0014] Furthermore, the discharge branch 305 also includes a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, and a fourth NMOS transistor MN4, wherein: the first NMOS transistor MN1 is connected in series between the third PMOS transistor MP3 of the charging branch 303 and the positive input terminal of the second operational amplifier OP2; the second NMOS transistor MN2 is connected in series between the switching branch 304 and the inverting input terminal of the second operational amplifier OP2; the third NMOS transistor MN3 is connected in series between the positive input terminal of the second operational amplifier OP2 and the ground terminal GND; the fourth NMOS transistor MN4 is connected in series between the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, and the fourth NMOS transistor MN4. Four NMOS transistors MN4 are connected in series between the inverting input terminal of the second operational amplifier OP2 and the ground terminal GND; the gates of the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are connected together to the gate of the seventh NMOS transistor MN7 of the bias circuit 301; the gate of the first NMOS transistor MN1 is connected to the gate of the fifth NMOS transistor MN5 of the bias circuit 301; and the gate of the second NMOS transistor MN2 is connected to the output terminal of the second operational amplifier OP2; the third node N3 and the fourth node N4 are respectively located at the positive input terminal and the inverting input terminal of the second operational amplifier OP2.

[0015] Furthermore, the size of the first NMOS transistor MN1 is twice the size of the fifth NMOS transistor MN5, and the size of the third NMOS transistor MN3 is twice the size of the seventh NMOS transistor MN7; the size of the second NMOS transistor MN2 is 10 times the size of the first NMOS transistor MN1, and the size of the fourth NMOS transistor MN4 is 10 times the size of the third NMOS transistor MN3.

[0016] Furthermore, the switching branch 304 includes a first transmission gate TG1, a second transmission gate TG2, a third transmission gate TG3, a fourth transmission gate TG4, and a third operational amplifier OP3, wherein: the first transmission gate TG1 and the third transmission gate TG3 are connected in series between the charging branch 303 and the discharging branch 305; the second transmission gate TG2 and the fourth transmission gate TG4 are connected in series between the charging branch 303 and the discharging branch 305; the positive input terminal of the third operational amplifier OP3 is connected to the connection point of the second transmission gate TG2 and the fourth transmission gate TG4; the inverting input terminal of the third operational amplifier OP3 is connected to the output terminal and connected to the connection point of the first transmission gate TG1 and the third transmission gate TG3.

[0017] Furthermore, the positive control terminal of the first transmission gate TG1 and the negative control terminal of the second transmission gate TG2 are driven by the UP signal generated by the frequency and phase detector, and the negative control terminal of the first transmission gate TG1 and the positive control terminal of the second transmission gate TG2 are driven by the UP signal generated by the frequency and phase detector. The third transmission gate TG3 and the fourth transmission gate TG4 are driven by the DW signal generated by the frequency and phase detector; the positive control terminal of the third transmission gate TG3 and the positive control terminal of the fourth transmission gate TG4 are driven by the DW signal generated by the frequency and phase detector. The signal drives the circuit; the output node Vcont of the charge pump circuit is located between the second transmission gate TG2 and the fourth transmission gate TG4.

[0018] Compared with the prior art, the charge pump circuit for phase-locked loops provided by the present invention has at least the following beneficial effects:

[0019] (1) This invention proposes a new charge pump circuit. While ensuring low current mismatch, it increases the output voltage range of the charge pump by increasing the impedance of the charging branch and the discharging branch, which can greatly improve the output spurious of the charge pump and increase the output frequency of the charge pump phase-locked loop under the same conditions.

[0020] (2) This invention utilizes the high gain and low input offset voltage characteristics of the operational amplifier to ensure accurate current replication while greatly increasing the output impedance of the circuit, thereby reducing current mismatch and increasing the voltage output range of the charge pump, and thus improving the frequency output range and spurious performance of the phase-locked loop under the same conditions. Attached Figure Description

[0021] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0022] Figure 1 A schematic diagram of the structure of a prior art charge pump phase-locked loop is shown.

[0023] Figure 2 A schematic diagram of a charge pump circuit for a phase-locked loop according to an embodiment of the present invention is shown.

[0024] [Explanation of Labels in the Attached Image]

[0025] Existing technology:

[0026] 101-Frequency and phase detector; 102-Charge pump circuit; 103-Low-pass filter; 104-Voltage-controlled oscillator; 105-Frequency divider;

[0027] Embodiments of the present invention:

[0028] 301 - Bias circuit; 302 - Main charge pump core circuit; 303 - Charging branch; 304 - Switching branch; 305 - Discharging branch;

[0029] I1 - Current source; R1 - First resistor; R2 - Second resistor; MP1 - First PMOS transistor; MP2 - Second PMOS transistor; MP3 - Third PMOS transistor; MP4 - Fourth PMOS transistor; MP5 - Fifth PMOS transistor; MP6 - Sixth PMOS transistor;

[0030] MN1 - First NMOS transistor; MN2 - Second NMOS transistor; MN3 - Third NMOS transistor; MN4 - Fourth NMOS transistor; MN5 - Fifth NMOS transistor; MN6 - Sixth NMOS transistor; MN7 - Seventh NMOS transistor; MN8 - Eighth NMOS transistor;

[0031] OP1 - First operational amplifier; OP2 - Second operational amplifier; OP3 - Third operational amplifier;

[0032] TG1 - First transmission gate; TG2 - Second transmission gate; TG3 - Third transmission gate; TG4 - Fourth transmission gate;

[0033] N1 - First node; N2 - Second node; N3 - Third node; N4 - Fourth node;

[0034] VDD - Power supply terminal; GND - Ground terminal; Vcont - Output node. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to specific embodiments and the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0036] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0037] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0038] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0039] Figure 1 A schematic diagram of the structure of a prior art charge pump phase-locked loop is shown.

[0040] like Figure 1 As shown, the existing charge pump phase-locked loop includes modules such as a frequency and phase detector 101, a charge pump 102, a low-pass filter 103, a voltage-controlled oscillator 104, and a frequency divider 105. The frequency and phase detector 101 compares the reference clock with the signal from the voltage-controlled oscillator 104 after frequency division by the frequency divider 105, outputting UP and DW signals to control the charge pump 102. The charge pump 102, through a switching circuit, converts the error signal output by the frequency and phase detector 101 into a current signal, injecting it into the low-pass filter 103 to generate a voltage signal controlling the voltage-controlled oscillator 104. This voltage signal, through loop feedback, forms the clock signal of the required frequency. The main objective of this invention is to optimize the specific circuit structure of the charge pump 102.

[0041] In view of this, embodiments of the present invention provide a charge pump circuit for a phase-locked loop, characterized by low mismatch and a high output voltage range.

[0042] Figure 2 A schematic diagram of a charge pump circuit according to an embodiment of the present invention is shown.

[0043] like Figure 2 As shown, this embodiment of the invention provides a charge pump circuit for a phase-locked loop, including a bias circuit 301 and a main charge pump core circuit 302. The main charge pump core circuit 302 is used to generate a low mismatch current and includes a charging branch 303, a switching branch 304, and a discharging branch 305. The switching branch 304 is connected to both the charging branch 303 and the discharging branch 305. The bias circuit 301 is used to generate the bias voltages required for the charging branch 303 and the discharging branch 305, respectively.

[0044] The charging branch 303 includes a first operational amplifier OP1 and is provided with a first node N1 and a second node N2. The charging branch 303 is used to clamp the first operational amplifier OP1 so that the potentials of the first node N1 and the second node N2 are equal.

[0045] The discharge branch 305 includes a second operational amplifier OP2 and is provided with a third node N3 and a fourth node N4. The discharge branch 305 is used to clamp the third node N3 and the fourth node N4 by using the second operational amplifier OP2 to make the potentials of the second node N3 and the fourth node N4 equal.

[0046] Therefore, the charging branch 303 uses the first operational amplifier OP1 for clamping, controlling the current of the second node N2 to accurately replicate the current of the first node N1. Furthermore, the configuration of the first operational amplifier OP1, through current negative feedback technology, significantly improves the impedance of the charging branch 303. Similarly, the discharging branch 305 uses the second operational amplifier OP2 for clamping, controlling the current of the fourth node N4 to accurately replicate the current of the third node N3. Furthermore, the configuration of the second operational amplifier OP2, through current negative feedback technology, significantly improves the impedance of the discharging branch 305.

[0047] Furthermore, the current at the first node N1 is equal to the current at the third node N3. Therefore, the configuration of the first operational amplifier OP1 and the second operational amplifier OP2 ensures that the current in the charging branch is equal to the current in the discharging branch, increases the impedance of the charging and discharging branches, reduces the influence of the output node Vcont voltage on the current in the charging and discharging branches, and thus increases the voltage output range of the charge pump.

[0048] In this embodiment of the invention, a first operational amplifier OP1 is added to the charging branch 303 to clamp the potentials of the first node N1 and the second node N2. Similarly, a second operational amplifier OP2 is added to the discharging branch 305 to clamp the potentials of the third node N3 and the fourth node N4, thus suppressing the mismatch between the charging and discharging currents. While ensuring low mismatch current, current negative feedback technology is used to increase the output impedance of the charging branch 303 and the discharging branch 305, reducing the impact of the output node Vcont voltage on the charging and discharging currents. This improves the output voltage range of the charge pump while maintaining low mismatch.

[0049] like Figure 2 As shown, specifically, the bias circuit 301 includes a current source I1, a first resistor R1, a second resistor R2, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a fifth PMOS transistor MP5, and a sixth PMOS transistor MP6.

[0050] In this configuration, the current source I1, the first resistor R1, the fifth NMOS transistor MN5, and the seventh NMOS transistor MN7 are connected in series between the power supply terminal VDD and the ground terminal GND. The gate of the fifth NMOS transistor MN5 is connected to the connection point of the current source I1 and the first resistor R1, and the gate of the seventh NMOS transistor MN7 is connected to the connection point of the first resistor R1 and the fifth NMOS transistor MN5.

[0051] The fifth PMOS transistor MP5, the sixth PMOS transistor MP6, the second resistor R2, the sixth NMOS transistor MN6, and the eighth NMOS transistor MN8 are connected in series between the power supply terminal VDD and the ground terminal GND. The gate of the fifth PMOS transistor MP5 is connected to the connection point of the second resistor R2 and the sixth PMOS transistor MP6. The gate of the sixth PMOS transistor MP6 is connected to the connection point of the second resistor R2 and the sixth NMOS transistor MN6. The gate of the sixth NMOS transistor MN6 is connected to the gate of the fifth NMOS transistor MN5. The gate of the eighth NMOS transistor MN8 is connected to the gate of the seventh NMOS transistor MN7.

[0052] Furthermore, the sixth NMOS transistor MN6 has the same size as the fifth NMOS transistor MN5, and the eighth NMOS transistor MN8 has the same size as the seventh NMOS transistor MN7.

[0053] Therefore, in the bias circuit 301, the first resistor R1, the fifth NMOS transistor MN5, and the seventh NMOS transistor MN7 constitute a self-biased low-voltage cascode circuit, converting the current from the current source I1 into the bias voltage required for the discharge branch. This ensures accurate current replication without consuming excess current, while simultaneously increasing the voltage swing. Similarly, the second resistor R2, the fifth PMOS transistor MP5, and the sixth PMOS transistor MP6 also constitute a self-biased low-voltage cascode circuit, ensuring accurate current replication without consuming excess current, while simultaneously increasing the voltage swing. Furthermore, NMOS transistors MN6 and MN8 are used to accurately replicate the current from the current source, ensuring that the current in the self-biased low-voltage cascode circuit formed by R2, MP5, and MP6 is equal to that in the self-biased low-voltage cascode circuit formed by R1, MN5, and MN7.

[0054] Continue as Figure 2 As shown, specifically, the charging branch 303 also includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, and a fourth PMOS transistor MP4.

[0055] The first PMOS transistor MP1 is connected in series between the power supply terminal VDD and the positive input terminal of the first operational amplifier OP1, and the second PMOS transistor MP2 is connected in series between the power supply terminal VDD and the inverted input terminal of the first operational amplifier OP1. The gates of the first PMOS transistor MP1 and the second PMOS transistor MP2 are connected together to the gate of the fifth PMOS transistor MP5 of the bias circuit 301.

[0056] The third PMOS transistor MP3 is connected in series between the positive input terminal of the first operational amplifier OP1 and the discharge branch 305. The gate of the third PMOS transistor MP3 is connected to the gate of the sixth PMOS transistor MP6 in the bias circuit 301. The fourth PMOS transistor MP4 is connected in series between the inverting input terminal of the first operational amplifier OP1 and the switching branch 304. The gate of the fourth PMOS transistor MP4 is connected to the output terminal of the first operational amplifier OP1.

[0057] The first node N1 and the second node N2 are respectively set at the positive input terminal and the inverting input terminal of the first operational amplifier OP1.

[0058] Therefore, in the charging branch 303, the biases of the first PMOS transistor MP1, the second PMOS transistor MP2, and the third PMOS transistor MP3 are all generated by the bias circuit 301, while the bias of the fourth PMOS transistor MP4 is generated by the output of the first operational amplifier OP1. MP1 and MP3 are used to initially amplify the current, while MP2, MP4, and OP1 are used to generate a high-precision, high-impedance current source.

[0059] Furthermore, the size of the first PMOS transistor MP1 is twice the size of the fifth PMOS transistor MP5 in the bias circuit 301, and the size of the third PMOS transistor MP3 is twice the size of the sixth PMOS transistor MP6 in the bias circuit 301. The size of the second PMOS transistor MP2 is ten times the size of the first PMOS transistor MP1, and the size of the fourth PMOS transistor MP4 is ten times the size of the third PMOS transistor MP3.

[0060] Continue as Figure 2 As shown, specifically, the discharge branch 305 also includes a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, and a fourth NMOS transistor MN4.

[0061] Specifically, the first NMOS transistor MN1 is connected in series between the third PMOS transistor MP3 in the charging branch 303 and the positive input terminal of the second operational amplifier OP2; the second NMOS transistor MN2 is connected in series between the switching branch 304 and the inverting input terminal of the second operational amplifier OP2; the third NMOS transistor MN3 is connected in series between the positive input terminal of the second operational amplifier OP2 and the ground terminal GND; and the fourth NMOS transistor MN4 is connected in series between the inverting input terminal of the second operational amplifier OP2 and the ground terminal GND.

[0062] The gates of the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are connected to the gate of the seventh NMOS transistor MN7 in the bias circuit 301. The gate of the first NMOS transistor MN1 is connected to the gate of the fifth NMOS transistor MN5 in the bias circuit 301. The gate of the second NMOS transistor MN2 is connected to the output terminal of the second operational amplifier OP2.

[0063] The third node N3 and the fourth node N4 are respectively set at the positive input terminal and the inverting input terminal of the second operational amplifier OP2.

[0064] Therefore, in the discharge branch 305, the biases of the first NMOS transistor MN1, the third NMOS transistor MN3, and the fourth NMOS transistor MN4 are all generated by the bias circuit 301, while the bias of the second NMOS transistor MN2 is generated by the output of the second operational amplifier OP2. MN1 and MN3 are used to initially amplify the current, while MN2, MN4, and OP2 are used to generate a high-precision, high-impedance current source.

[0065] Furthermore, the size of the first NMOS transistor MN1 is twice the size of the fifth NMOS transistor MN5, and the size of the third NMOS transistor MN3 is twice the size of the seventh NMOS transistor MN7. The size of the second NMOS transistor MN2 is ten times the size of the first NMOS transistor MN1, and the size of the fourth NMOS transistor MN4 is ten times the size of the third NMOS transistor MN3. Therefore, by setting the width-to-length ratio of MN2 and MN4 to be several times that of MN5 and MN7 in the discharge branch 305, a current several times that of the current source I1 can be obtained.

[0066] Continue as Figure 2 As shown, specifically, the switching branch 304 includes a first transmission gate TG1, a second transmission gate TG2, a third transmission gate TG3, a fourth transmission gate TG4, and a third operational amplifier OP3. The first transmission gate TG1 and the third transmission gate TG3 are connected in series between the charging branch 303 and the discharging branch 305; the second transmission gate TG2 and the fourth transmission gate TG4 are connected in series between the charging branch 303 and the discharging branch 305.

[0067] The positive input terminal of the third operational amplifier OP3 is connected to the connection point of the second transmission gate TG2 and the fourth transmission gate TG4; the inverting input terminal of the third operational amplifier OP3 is connected to the output terminal and to the connection point of the first transmission gate TG1 and the third transmission gate TG3.

[0068] Furthermore, the positive control terminal of the first transmission gate TG1 and the negative control terminal of the second transmission gate TG2 are driven by the UP signal generated by the frequency and phase detector, while the negative control terminal of the first transmission gate TG1 and the positive control terminal of the second transmission gate TG2 are generated by the frequency and phase detector in the preceding stage. Driven by signals. The UP signal and The signals are a pair of opposite signals; when the UP signal is high, When the signal is low, the charge pump circuit charges the low-pass filter through charging branch 303; when the UP signal is high, When the signal is low, the charging branch 303 presents a high impedance state to the output port to prevent current leakage from causing the phase-locked loop to lose lock.

[0069] The positive control terminal of the third transmission gate TG3 and the negative control terminal of the fourth transmission gate TG4 are driven by the DW signal generated by the frequency and phase detector. Driven by signals. DW signal and The signals are a pair of opposite signals; when the DW signal is high, When the signal is low, the low-pass filter discharges through the discharge branch 305 of the charge pump circuit; when the DW signal is high, When the signal is low, the discharge branch 305 presents a high impedance state to the output port to prevent current leakage from causing the charge pump to lose lock.

[0070] In this embodiment, the output node Vcont of the charge pump circuit is located between the second transmission gate TG2 and the fourth transmission gate TG4, and is also connected to the positive input terminal of the third operational amplifier OP3. The inverting input terminal and the output terminal of the third operational amplifier OP3 are connected to form a unity-gain amplifier, clamping Vcont and Vcont' to reduce charge sharing effect and output spurious emissions.

[0071] Based on the above disclosure, the basic working principle of the charge pump circuit for a phase-locked loop in this embodiment of the invention is as follows:

[0072] A self-biased low-voltage cascode circuit is formed by the first resistor R1, the fifth NMOS transistor MN5, and the seventh NMOS transistor MN7 to accurately replicate the current generated by the current source I1, thus biasing the discharge branch 305. A similar self-biased low-voltage cascode circuit is then formed by the second resistor R2, the fifth PMOS transistor MP5, and the sixth PMOS transistor MP6 to generate the bias for the charging branch 303. Since the current in the bias circuit 301 also generates noise, the current in the bias circuit 301 is biased in a low-current mode. Furthermore, the dimensions of the second NMOS transistor MN2 and the fourth NMOS transistor MN4 in the discharge branch 305 are several times larger than those of the fifth NMOS transistor MN5 and the seventh NMOS transistor MN7 in the bias circuit 301. Similarly, the dimensions of the second PMOS transistor MP2 and the fourth PMOS transistor MP4 in the charging branch 303 are several times larger than those of the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 in the bias circuit 301. This allows for a current several times greater than that of the current source I1, ensuring the charge pump current reaches the required value.

[0073] However, during this process, due to the channel length modulation effect of the transistor, the transistor still cannot accurately replicate the current of the bias circuit, resulting in a mismatch between the charging branch and the discharging branch, causing spurious signals in the output signal of the phase-locked loop.

[0074] This invention, through the addition of operational amplifiers OP1 and OP2 to the charging and discharging branches respectively, clamps the drains of transistors MP1 and MP2, and the drains of MN3 and MN4, ensuring their voltages are equal. This eliminates the channel length modulation effect of the transistors and achieves precise current replication. Furthermore, unlike traditional solutions, this invention, by adding operational amplifiers and utilizing current negative feedback, significantly increases the output impedance of the charging and discharging branches, reducing the impact of the output port voltage on the charging and discharging currents. This allows the circuit to maintain low mismatch while achieving a high output voltage range.

[0075] The switching circuit 304 replaces the traditional switch with a transmission gate, keeping the circuit in a constant conducting state. Furthermore, the third operational amplifier OP3 can reduce the charge sharing effect and further improve the linearity and stray performance of the charge pump.

[0076] It should also be noted that Cadence simulations show that under a working voltage of 1V and an output voltage of 0.2-0.8V, the current deviation between the charging and discharging branches is less than 0.1%. This demonstrates that the embodiments of the present invention have a simple structure, are easy to integrate, and are suitable for use in high-performance charge pump phase-locked loops.

[0077] In summary, this invention provides a charge pump circuit for a phase-locked loop, including a bias circuit 301 and a main charge pump core circuit 302. This invention generates a bias voltage for low-voltage cascode MN1 and MN3 through a first resistor R1, a fifth NMOS transistor MN5, and a seventh NMOS transistor MN7; and generates another bias voltage for low-voltage cascode MP1 and MP3 through a second resistor R2, a fifth PMOS transistor MP5, and a sixth PMOS transistor MP6. This accurately replicates the current of current source I1 while increasing the output range of the charge pump.

[0078] In the description of this invention, it should be understood that the terms "upper," "lower," "front," "rear," "left," and "right," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Throughout the drawings, the same elements are represented by the same or similar reference numerals. Conventional structures or constructions will be omitted where they may cause confusion in understanding the invention. Furthermore, the shape, size, and positional relationship of the components in the drawings do not reflect their actual size, scale, or actual positional relationship.

[0079] Similarly, to simplify the invention and aid in understanding one or more of the various disclosed aspects, in the above description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together into a single embodiment, figure, or description thereof. The use of terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicates that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0080] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified. Furthermore, the word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. Unless otherwise stated, the expressions "about," "approximately," "substantially," and "around" indicate less than 10%, preferably less than 5%.

[0081] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A charge pump circuit for a phase-locked loop, characterized in that, include: The bias circuit (301) includes: a current source (I1), a first resistor (R1), a second resistor (R2), a fifth NMOS transistor (MN5), a sixth NMOS transistor (MN6), a seventh NMOS transistor (MN7), an eighth NMOS transistor (MN8), a fifth PMOS transistor (MP5), and a sixth PMOS transistor (MP6). The current source (I1), the first resistor (R1), the fifth NMOS transistor (MN5), and the seventh NMOS transistor (MN7) are connected in series between the power supply terminal (VDD) and the ground terminal (GND). The main charge pump core circuit (302) is used to generate low mismatch current, including a charging branch (303), a switching branch (304) and a discharging branch (305), wherein the switching branch (304) is connected to the charging branch (303) and the discharging branch (305) respectively. The bias circuit (301) is used to generate the bias voltages required for the charging branch (303) and the discharging branch (305), respectively. The charging branch (303) includes a first operational amplifier (OP1) and is provided with a first node (N1) and a second node (N2). The charging branch (303) is used to clamp the first operational amplifier (OP1) so that the potentials of the first node (N1) and the second node (N2) are equal. The discharge branch (305) includes a second operational amplifier (OP2) and is provided with a third node (N3) and a fourth node (N4). The discharge branch (305) is used to clamp the third node (N3) and the fourth node (N4) by means of the second operational amplifier (OP2) to make their potentials equal. The charging branch (303) further includes a first PMOS transistor (MP1), a second PMOS transistor (MP2), a third PMOS transistor (MP3), and a fourth PMOS transistor (MP4), wherein: The first PMOS transistor (MP1) is connected in series between the power supply terminal (VDD) and the positive input terminal of the first operational amplifier (OP1), and the second PMOS transistor (MP2) is connected in series between the power supply terminal (VDD) and the negative input terminal of the first operational amplifier (OP1). The gates of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are connected together to the gate of the fifth PMOS transistor (MP5) of the bias circuit (301). The third PMOS transistor (MP3) is connected in series between the positive input terminal of the first operational amplifier (OP1) and the discharge branch (305), and the gate of the third PMOS transistor (MP3) is connected to the gate of the sixth PMOS transistor (MP6) of the bias circuit (301). The fourth PMOS transistor (MP4) is connected in series between the inverting input terminal of the first operational amplifier (OP1) and the switching branch (304), and the gate of the fourth PMOS transistor (MP4) is connected to the output terminal of the first operational amplifier (OP1). The first node (N1) and the second node (N2) are respectively located at the positive input terminal and the inverting input terminal of the first operational amplifier (OP1).

2. The charge pump circuit for a phase-locked loop according to claim 1, characterized in that, The current of the first node (N1) is equal to the current of the third node (N3).

3. The charge pump circuit for a phase-locked loop according to claim 1, characterized in that, The gate of the fifth NMOS transistor (MN5) is connected to the connection point of the current source (I1) and the first resistor (R1), and the gate of the seventh NMOS transistor (MN7) is connected to the connection point of the first resistor (R1) and the fifth NMOS transistor (MN5). The fifth PMOS transistor (MP5), the sixth PMOS transistor (MP6), the second resistor (R2), the sixth NMOS transistor (MN6), and the eighth NMOS transistor (MN8) are connected in series between the power supply terminal (VDD) and the ground terminal (GND). The gate of the fifth PMOS transistor (MP5) is connected to the connection point of the second resistor (R2) and the sixth PMOS transistor (MP6). The gate of the sixth PMOS transistor (MP6) is connected to the connection point of the second resistor (R2) and the sixth NMOS transistor (MN6). The gate of the sixth NMOS transistor (MN6) is connected to the gate of the fifth NMOS transistor (MN5). The gate of the eighth NMOS transistor (MN8) is connected to the gate of the seventh NMOS transistor (MN7).

4. The charge pump circuit for a phase-locked loop according to claim 3, characterized in that, The sixth NMOS transistor (MN6) has the same size as the fifth NMOS transistor (MN5), and the eighth NMOS transistor (MN8) has the same size as the seventh NMOS transistor (MN7).

5. The charge pump circuit for a phase-locked loop according to claim 1, characterized in that, The size of the first PMOS transistor (MP1) is twice the size of the fifth PMOS transistor (MP5) of the bias circuit (301), and the size of the third PMOS transistor (MP3) is twice the size of the sixth PMOS transistor (MP6) of the bias circuit (301). The size of the second PMOS transistor (MP2) is 10 times that of the first PMOS transistor (MP1), and the size of the fourth PMOS transistor (MP4) is 10 times that of the third PMOS transistor (MP3).

6. The charge pump circuit for a phase-locked loop according to claim 1, characterized in that, The discharge branch (305) further includes a first NMOS transistor (MN1), a second NMOS transistor (MN2), a third NMOS transistor (MN3), and a fourth NMOS transistor (MN4), wherein: The first NMOS transistor (MN1) is connected in series between the third PMOS transistor (MP3) of the charging branch (303) and the positive input terminal of the second operational amplifier (OP2), and the second NMOS transistor (MN2) is connected in series between the switching branch (304) and the inverting input terminal of the second operational amplifier (OP2); The third NMOS transistor (MN3) is connected in series between the positive input terminal of the second operational amplifier (OP2) and the ground terminal (GND), and the fourth NMOS transistor (MN4) is connected in series between the inverting input terminal of the second operational amplifier (OP2) and the ground terminal (GND). The gates of the third NMOS transistor (MN3) and the fourth NMOS transistor (MN4) are connected to the gate of the seventh NMOS transistor (MN7) of the bias circuit (301), the gate of the first NMOS transistor (MN1) is connected to the gate of the fifth NMOS transistor (MN5) of the bias circuit (301), and the gate of the second NMOS transistor (MN2) is connected to the output terminal of the second operational amplifier (OP2). The third node (N3) and the fourth node (N4) are respectively located at the positive input terminal and the inverting input terminal of the second operational amplifier (OP2).

7. The charge pump circuit for a phase-locked loop according to claim 6, characterized in that, The size of the first NMOS transistor (MN1) is twice the size of the fifth NMOS transistor (MN5), and the size of the third NMOS transistor (MN3) is twice the size of the seventh NMOS transistor (MN7). The size of the second NMOS transistor (MN2) is 10 times that of the first NMOS transistor (MN1), and the size of the fourth NMOS transistor (MN4) is 10 times that of the third NMOS transistor (MN3).

8. The charge pump circuit for a phase-locked loop according to claim 1, characterized in that, The switching branch (304) includes a first transmission gate (TG1), a second transmission gate (TG2), a third transmission gate (TG3), a fourth transmission gate (TG4), and a third operational amplifier (OP3), wherein: The first transmission gate (TG1) and the third transmission gate (TG3) are connected in series between the charging branch (303) and the discharging branch (305); the second transmission gate (TG2) and the fourth transmission gate (TG4) are connected in series between the charging branch (303) and the discharging branch (305). The positive input terminal of the third operational amplifier (OP3) is connected to the connection point of the second transmission gate (TG2) and the fourth transmission gate (TG4); the inverting input terminal of the third operational amplifier (OP3) is connected to the output terminal and connected to the connection point of the first transmission gate (TG1) and the third transmission gate (TG3).

9. The charge pump circuit for a phase-locked loop according to claim 8, characterized in that, The positive control terminal of the first transmission gate (TG1) and the negative control terminal of the second transmission gate (TG2) are driven by the UP signal generated by the frequency and phase detector, and the negative control terminal of the first transmission gate (TG1) and the positive control terminal of the second transmission gate (TG2) are driven by the signal generated by the frequency and phase detector. The positive control terminal of the third transmission gate (TG3) and the negative control terminal of the fourth transmission gate (TG4) are driven by the DW signal generated by the frequency and phase detector, and the negative control terminal of the third transmission gate (TG3) and the positive control terminal of the fourth transmission gate (TG4) are driven by the signal generated by the frequency and phase detector. The output node (Vcont) of the charge pump circuit is located between the second transmission gate (TG2) and the fourth transmission gate (TG4).

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