Analog-to-digital converter, chip and analog-to-digital conversion control method

Abstract

Embodiments of the present application provide an analog-to-digital converter, a chip and an analog-to-digital conversion control method. The analog-to-digital converter comprises multiple-stage analog-to-digital conversion circuits, and an inter-stage amplifier is arranged between any two adjacent stages of the analog-to-digital conversion circuits. The inter-stage amplifier comprises at least two amplifiers, and the at least two amplifiers are configured to amplify signals. In the analog-to-digital converter provided by the embodiments of the present application, the inter-stage amplifier is arranged to comprise at least two amplifiers, and the power consumption of the two amplifiers can be reduced. Therefore, compared with a single inter-stage amplifier, the power consumption of the analog-to-digital converter can be reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic circuits, and particularly relates to an analog-to-digital converter, a chip and an analog-to-digital conversion control method. BACKGROUND

[0002] Pipeline successive approximation register (SAR) analog-to-digital converter (Pipeline-SAR ADC) is a kind of analog-to-digital converter in which the full parallel (Flash) structure in pipeline analog-to-digital converter (Pipeline ADC) is replaced by successive approximation register (SAR) structure, and the front-end sample-and-hold function of traditional Pipeline ADC is realized by using the sample-and-hold network of the first-stage SAR ADC. Although the speed of the Pipeline-SAR ADC is reduced, the power consumption and area are greatly reduced. The main factor limiting the power consumption of the Pipeline-SAR ADC is the inter-stage amplifier. The open-loop amplification of the inter-stage amplifier is determined by the total resolution N-bit of the Pipeline-SAR ADC, and at least needs 20log(2^ N+1 )dB. The open-loop bandwidth of the inter-stage amplifier is determined by the speed of the Pipeline-SAR ADC, the resolution of the second-stage SAR ADC and the output load, and at least needs (1+2^ M )ln(2^ L+1 ) / (2*π*T RA )Hz (wherein M is the bit number of the first-stage analog-to-digital converter, L is the bit number of the second-stage analog-to-digital converter, T RA is the amplification time of the inter-stage amplifier). The load of the inter-stage amplifier is 2^ L Cu (wherein Cu represents the unit capacitance size).

[0003] In order to make the Pipeline-SAR ADC realize such high open-loop amplification and open-loop bandwidth, the power consumption of the inter-stage amplifier will be very high, so the power consumption of the traditional Pipeline-SAR ADC is still much higher than that of the SAR ADC. SUMMARY

[0004] The embodiments of the present application provide an analog-to-digital converter, a chip and an analog-to-digital conversion control method, which can reduce the power consumption of the analog-to-digital converter.

[0005] The embodiments of the present application provide an analog-to-digital converter, which comprises a plurality of stages of analog-to-digital conversion circuits, and an inter-stage amplifier is arranged between any two adjacent stages of analog-to-digital conversion circuits, the inter-stage amplifier comprises at least two amplifiers, and the at least two amplifiers are configured to amplify signals.

[0006] In some embodiments, the multi-stage analog-to-digital conversion circuit includes a first-stage analog-to-digital conversion circuit and a second-stage analog-to-digital conversion circuit, the inter-stage amplifier is arranged between the first-stage analog-to-digital conversion circuit and the second-stage analog-to-digital conversion circuit, and the inter-stage amplifier includes a first-stage amplifier and a second-stage amplifier, wherein:

[0007] The first-stage analog-to-digital conversion circuit is configured to sample an input signal and perform analog-to-digital conversion on the input signal to obtain a first digital signal and a residual voltage signal.

[0008] The first-stage amplifier is connected to the first-stage analog-to-digital conversion circuit and is configured to amplify the residual voltage signal to obtain and output a first amplified signal.

[0009] The second-stage amplifier is connected to the first-stage amplifier and is configured to sample and amplify the first amplified signal to obtain and output a second amplified signal.

[0010] The second-stage analog-to-digital conversion circuit is connected to the second-stage amplifier and is configured to sample and perform analog-to-digital conversion on the second amplified signal and output a second digital signal.

[0011] The analog-to-digital converter is configured to obtain an analog-to-digital conversion result of the input signal according to the first digital signal and the second digital signal.

[0012] In some embodiments, the first-stage amplifier is a passive amplifier.

[0013] In some embodiments, the first-stage amplifier is an active amplifier.

[0014] In some embodiments, the input signal is a single-ended signal, and the first-stage amplifier includes a first amplifier, a first capacitor, and a first switch.

[0015] A first input terminal of the first amplifier is connected to the first-stage analog-to-digital conversion circuit, a second input terminal of the first amplifier is connected to a common-mode node, and an output terminal of the first amplifier is connected to the second-stage amplifier.

[0016] A first terminal of the first capacitor is connected to the first input terminal of the first amplifier, and a second terminal of the first capacitor is connected to the output terminal of the first amplifier.

[0017] A first terminal of the first switch is connected to the first input terminal of the first amplifier, and a second terminal of the first switch is connected to the output terminal of the first amplifier.

[0018] The output terminal of the first amplifier is configured to output the first amplified signal.

[0019] In some embodiments, the first-stage amplifier further comprises a second switch, and the first input terminal of the first-stage amplifier is connected with the first-stage analog-to-digital conversion circuit through the second switch.

[0020] In some embodiments, the input signal is a differential signal, the first-stage analog-to-digital conversion circuit comprises a first output terminal and a second output terminal, the second-stage amplifier comprises a first input terminal and a second input terminal, and the first-stage amplifier comprises a first amplifier, a first capacitor, a second capacitor, a first switch and a third switch.

[0021] The first input terminal of the first amplifier is connected with the first output terminal of the first-stage analog-to-digital conversion circuit, the second input terminal of the first amplifier is connected with the second output terminal of the first-stage analog-to-digital conversion circuit, the first power terminal of the first amplifier is connected with the first input terminal of the second-stage amplifier, and the second power terminal of the first amplifier is connected with the second input terminal of the second-stage amplifier.

[0022] The first end of the first capacitor is connected with the first input terminal of the first amplifier, and the second end of the first capacitor is connected with the first power terminal of the first amplifier.

[0023] The first end of the first switch is connected with the first input terminal of the first amplifier, and the second end of the first switch is connected with the first power terminal of the first amplifier.

[0024] The first end of the second capacitor is connected with the second input terminal of the first amplifier, and the second end of the second capacitor is connected with the second power terminal of the first amplifier.

[0025] The first end of the third switch is connected with the second input terminal of the first amplifier, and the second end of the third switch is connected with the second power terminal of the first amplifier.

[0026] The first power terminal and the second power terminal of the first amplifier are used to output the first amplified signal.

[0027] In some embodiments, the first-stage amplifier further comprises a second switch and a fourth switch, the first input terminal of the first-stage amplifier is connected with the first output terminal of the first-stage analog-to-digital conversion circuit through the second switch, and the second input terminal of the first-stage amplifier is connected with the second output terminal of the first-stage analog-to-digital conversion circuit through the fourth switch.

[0028] In some embodiments, the second-stage amplifier is a passive amplifier.

[0029] In some embodiments, the input signal is a single-ended signal, and the second-stage amplifier comprises a third capacitor, a fourth capacitor, a sixth switch and a seventh switch.

[0030] a first end of the third capacitor is connected with the first-stage amplifier and grounded through the sixth switch; a second end of the third capacitor is connected with a first end of the fourth capacitor, and the second end of the third capacitor and the first end of the fourth capacitor are connected to a common-mode node through the seventh switch; and a second end of the fourth capacitor is connected with the second-stage analog-to-digital conversion circuit.

[0031] The second end of the fourth capacitor and the second end of the sixth capacitor are configured to output the second amplified signal.

[0032] In some embodiments, the second-stage amplifier further includes a fifth switch, and the first end of the third capacitor is connected with the first-stage amplifier through the fifth switch.

[0033] In some embodiments, the input signal is a differential signal, the first-stage amplifier includes a third output end and a fourth output end, the second-stage analog-to-digital conversion circuit includes a third input end and a fourth input end, and the second-stage amplifier includes a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a sixth switch, a seventh switch, a ninth switch, and a tenth switch.

[0034] a first end of the third capacitor is connected with the third output end of the first-stage amplifier and grounded through the sixth switch; a second end of the third capacitor is connected with a first end of the fourth capacitor, and the second end of the third capacitor and the first end of the fourth capacitor are connected to a common-mode node through the seventh switch; and a second end of the fourth capacitor is connected with the third input end of the second-stage analog-to-digital conversion circuit.

[0035] a first end of the fifth capacitor is connected with the fourth output end of the first-stage amplifier and grounded through the ninth switch; a second end of the fifth capacitor is connected with a first end of the sixth capacitor, and the second end of the fifth capacitor and the first end of the sixth capacitor are connected to a common-mode node through the tenth switch; and a second end of the sixth capacitor is connected with the fourth input end of the second-stage analog-to-digital conversion circuit.

[0036] The second end of the fourth capacitor and the second end of the sixth capacitor are configured to output the second amplified signal.

[0037] In some embodiments, the second-stage amplifier further includes a fifth switch and an eighth switch, the first end of the third capacitor is connected with the third output end of the first-stage amplifier through the fifth switch, and the first end of the fifth capacitor is connected with the fourth output end of the first-stage amplifier through the eighth switch.

[0038] In some embodiments, the second-stage amplifier is an active amplifier.

[0039] In some embodiments, the input signal is a single-ended signal, and the second-stage amplifier comprises a third capacitor, a fourth capacitor, a second amplifier, a sixth switch, and an eleventh switch;

[0040] A first end of the third capacitor is connected to the first-stage amplifier and grounded through the sixth switch; a second end of the third capacitor is connected to a first end of the fourth capacitor, and a second end of the fourth capacitor is connected to the second-stage analog-to-digital conversion circuit;

[0041] A first input end of the second amplifier is connected between the second end of the third capacitor and the first end of the fourth capacitor, a second input end of the second amplifier is connected to a common-mode node, and an output end of the second amplifier is connected to the second end of the fourth capacitor;

[0042] A first end of the eleventh switch is connected between the second end of the third capacitor and the first end of the fourth capacitor, and a second end of the eleventh switch is connected to the second end of the fourth capacitor;

[0043] The output end of the second amplifier is configured to output a second amplified signal.

[0044] In some embodiments, the second-stage amplifier further comprises a fifth switch, and the first end of the third capacitor is connected to the first-stage amplifier through the fifth switch.

[0045] In some embodiments, the input signal is a differential signal, the first-stage amplifier comprises a third output end and a fourth output end, the second-stage analog-to-digital conversion circuit comprises a third input end and a fourth input end, and the second-stage amplifier comprises a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a second amplifier, a sixth switch, a ninth switch, an eleventh switch, and a twelfth switch;

[0046] A first end of the third capacitor is connected to the third output end of the first-stage amplifier and grounded through the sixth switch; a second end of the third capacitor is connected to a first end of the fourth capacitor, and a second end of the fourth capacitor is connected to the third input end of the second-stage analog-to-digital conversion circuit; a first end of the eleventh switch is connected between the second end of the third capacitor and the first end of the fourth capacitor, and a second end of the eleventh switch is connected to the second end of the fourth capacitor;

[0047] A first end of the fifth capacitor is connected to a fourth output end of the first-stage amplifier and grounded through the ninth switch; a second end of the fifth capacitor is connected to a first end of the sixth capacitor, and a second end of the sixth capacitor is connected to a fourth input end of the second-stage analog-to-digital conversion circuit; a first end of the twelfth switch is connected between the second end of the fifth capacitor and the first end of the sixth capacitor, and a second end of the twelfth switch is connected to the second end of the sixth capacitor.

[0048] A first input end of the second amplifier is connected between a second end of the third capacitor and a first end of the fourth capacitor, a second input end of the second amplifier is connected between a second end of the fifth capacitor and a first end of the sixth capacitor, a first power supply end of the second amplifier is connected to the second end of the fourth capacitor, and a second power supply end of the second amplifier is connected to the second end of the sixth capacitor.

[0049] The first power supply end and the second power supply end of the second amplifier are configured to output a second amplified signal.

[0050] In some embodiments, the second-stage amplifier further includes a fifth switch and an eighth switch, and a first end of the third capacitor is connected to a third output end of the first-stage amplifier through the fifth switch, and a first end of the fifth capacitor is connected to a fourth output end of the first-stage amplifier through the eighth switch.

[0051] In some embodiments, the first-stage analog-to-digital conversion circuit includes:

[0052] a first capacitor array configured to sample an input signal and output a residual voltage signal, and the first-stage amplifier is connected to the first capacitor array;

[0053] a first comparator connected to the first capacitor array and configured to compare the residual voltage signal and output a first comparison result; and

[0054] a first logic control circuit connected to the first capacitor array and the first comparator and configured to perform logic control on the first capacitor array based on the first comparison result and output a first digital signal.

[0055] In some embodiments, the second-stage analog-to-digital conversion circuit includes:

[0056] a second capacitor array connected to the second-stage amplifier and configured to sample the second amplified signal;

[0057] a second comparator connected to the second capacitor array and configured to compare the second amplified signal and output a second comparison result; and

[0058] The second logic control circuit is connected with the second capacitor array and the second comparator, and is configured to perform logic control on the second capacitor array based on the second comparison result and output a second digital signal.

[0059] In some embodiments, the analog-to-digital converter further comprises:

[0060] The output circuit is connected with the first-stage analog-to-digital conversion circuit and the second-stage analog-to-digital conversion circuit, and is configured to obtain an analog-to-digital conversion result of the input signal according to the first digital signal and the second digital signal.

[0061] Embodiments of the present application also provide a chip comprising the analog-to-digital converter described in any of the above.

[0062] Embodiments of the present application also provide an analog-to-digital conversion control method, comprising:

[0063] An inter-stage amplifier is arranged between at least two adjacent-stage analog-to-digital conversion circuits of the analog-to-digital converter, and the inter-stage amplifier comprises at least two amplifiers configured to perform signal amplification.

[0064] In some embodiments, the two adjacent-stage analog-to-digital conversion circuits comprise a first-stage analog-to-digital conversion circuit and a second-stage analog-to-digital conversion circuit, and the at least two amplifiers comprise a first-stage amplifier and a second-stage amplifier, and the analog-to-digital conversion control method further comprises:

[0065] controlling the first-stage analog-to-digital conversion circuit to sample an input signal, performing analog-to-digital conversion on the input signal to obtain a first digital signal and a residual voltage signal, and holding the residual voltage signal;

[0066] controlling the first-stage amplifier to amplify the residual voltage signal to obtain a first amplified signal;

[0067] controlling the second-stage amplifier to sequentially sample and amplify the first amplified signal to obtain a second amplified signal;

[0068] controlling the second-stage analog-to-digital conversion circuit to sequentially sample and perform analog-to-digital conversion on the second amplified signal to obtain a second digital signal; and

[0069] obtaining an analog-to-digital conversion result of the input signal according to the first digital signal and the second digital signal.

[0070] In some embodiments, the second-stage amplifier is an active amplifier, and when the second-stage analog-to-digital conversion circuit is controlled to sequentially sample and perform analog-to-digital conversion on the second amplified signal, the first-stage analog-to-digital conversion circuit is synchronously controlled to perform next sampling and analog-to-digital conversion on the input signal.

[0071] In some embodiments, the second stage amplifier is a passive amplifier, and the second stage analog-digital conversion circuit is controlled to sample the second amplified signal synchronously when the first stage analog-digital conversion circuit is controlled to hold the residual voltage signal.

[0072] The first stage analog-digital conversion circuit is controlled to sample and analog-digital convert the input signal synchronously when the second stage analog-digital conversion circuit is controlled to analog-digital convert the second amplified signal.

[0073] In some embodiments, the first stage amplifier is controlled to amplify the residual voltage signal synchronously when the first stage analog-digital conversion circuit is controlled to hold the residual voltage signal.

[0074] In some embodiments, the second stage amplifier is controlled to sample the first amplified signal synchronously when the first stage amplifier is controlled to amplify the residual voltage signal.

[0075] In the analog-digital converter provided by the embodiments of the present application, the inter-stage amplifier is set to include at least two amplifiers, and the power consumption of both amplifiers can be reduced, so that the power consumption of the analog-digital converter can be reduced compared with a single inter-stage amplifier. BRIEF DESCRIPTION OF DRAWINGS

[0076] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some of the embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0077] Figure 1 The first circuit architecture diagram of the analog-digital converter provided by the embodiments of the present application.

[0078] Figure 2 The second circuit architecture diagram of the analog-digital converter provided by the embodiments of the present application.

[0079] Figure 3 The third circuit architecture diagram of the analog-digital converter provided by the embodiments of the present application.

[0080] Figure 4 The fourth circuit architecture diagram of the analog-digital converter provided by the embodiments of the present application.

[0081] Figure 5 The fifth circuit architecture diagram of the analog-digital converter provided by the embodiments of the present application.

[0082] Figure 6This is a sixth circuit architecture diagram of the analog-to-digital converter provided in an embodiment of the present application.

[0083] Figure 7 This is a seventh circuit architecture diagram of the analog-to-digital converter provided in an embodiment of the present application.

[0084] Figure 8 This is a diagram of the eighth circuit architecture of the analog-to-digital converter provided in an embodiment of the present application.

[0085] Figure 9 This is a ninth circuit architecture diagram of the analog-to-digital converter provided in an embodiment of the present application.

[0086] Figure 10 This is a first specific circuit structure diagram of the analog-to-digital converter provided in an embodiment of the present application.

[0087] Figure 11 for Figure 10 The operating timing diagram of the analog-to-digital converter is shown.

[0088] Figure 12 This is a second specific circuit structure diagram of the analog-to-digital converter provided in an embodiment of the present application.

[0089] Figure 13 This is a third specific circuit structure diagram of the analog-to-digital converter provided in an embodiment of the present application.

[0090] Figure 14 for Figure 13 The operating timing diagram of the analog-to-digital converter is shown.

[0091] Figure 15 A flow chart of the analog-to-digital conversion control method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0092] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0093] An embodiment of the present application provides an analog-to-digital converter (ADC) that can convert an input signal, such as an analog signal, into a digital signal and output the digital signal. In practical applications, the ADC can be a pipeline ADC, such as a pipeline successive approximation ADC (Pipeline-SAR ADC).

[0094] The analog-to-digital converter provided in the embodiments of the present application comprises a multi-stage analog-to-digital conversion circuit, for example, a two-stage, three-stage, four-stage or multi-stage analog-to-digital conversion circuit. An inter-stage amplifier is arranged between any two adjacent stages of the analog-to-digital conversion circuit, and the inter-stage amplifier comprises at least two amplifiers, for example, two, three, four or even more amplifiers. The at least two amplifiers are configured to amplify a signal.

[0095] For example, in some embodiments, the multi-stage analog-to-digital conversion circuit comprises a first-stage analog-to-digital conversion circuit and a second-stage analog-to-digital conversion circuit, and an inter-stage amplifier is arranged between the first-stage analog-to-digital conversion circuit and the second-stage analog-to-digital conversion circuit, and the inter-stage amplifier comprises a first-stage amplifier and a second-stage amplifier. For example, the first-stage analog-to-digital conversion circuit comprises a first-stage amplifier and a first-stage quantizer, and the second-stage analog-to-digital conversion circuit comprises a second-stage quantizer and a second-stage amplifier. Figure 1 , Figure 1 A first circuit architecture diagram of an analog-to-digital converter 100 provided in the embodiments of the present application is shown in FIG. 1. The analog-to-digital converter 100 comprises a first-stage analog-to-digital conversion circuit 10, a first-stage amplifier 20, a second-stage amplifier 30 and a second-stage analog-to-digital conversion circuit 40. The first-stage analog-to-digital conversion circuit 10 can have a bit number of M bits (Mbit), and the second-stage analog-to-digital conversion circuit 40 can have a bit number of L bits (Lbit). M and L are both positive integers.

[0096] The first-stage analog-to-digital conversion circuit 10 is configured to sample an input signal and perform analog-to-digital conversion on the input signal to obtain a first digital signal and a residual voltage signal. For example, an external signal source can input an input signal to the first-stage analog-to-digital conversion circuit 10, and the first-stage analog-to-digital conversion circuit 10 can sample the input signal and perform analog-to-digital conversion on the input signal to obtain a corresponding digital signal and a residual voltage signal. The digital signal is a first digital signal, and the first digital signal can be an Mbit digital signal. The residual voltage signal is a quantization residual error voltage signal after analog-to-digital conversion. The first-stage analog-to-digital conversion circuit 10 can simultaneously output the residual voltage signal and the first digital signal. In actual applications, the input signal can be a single-ended signal or a differential signal based on the requirements of different scenarios.

[0097] The first-stage amplifier 20 is connected to the first-stage analog-to-digital conversion circuit 10. The first-stage amplifier 20 is configured to amplify the residual voltage signal to obtain and output a first amplified signal.

[0098] The second-stage amplifier 30 is connected to the first-stage amplifier 20. The second-stage amplifier 30 is configured to sample and amplify the first amplified signal to obtain and output a second amplified signal. For example, the second-stage amplifier 30 can first sample the first amplified signal, then amplify the sampled signal to obtain the second amplified signal, and output the second amplified signal.

[0099] The second-stage analog-to-digital conversion circuit 40 is connected with the second-stage amplifier 30. The second-stage analog-to-digital conversion circuit 40 is configured to sample and analog-to-digital convert the second amplified signal, and output a second digital signal. For example, the second-stage analog-to-digital conversion circuit 40 can first sample the second amplified signal, and then analog-to-digital convert the sampled signal to obtain a corresponding digital signal, i.e., the second digital signal. The second digital signal can be an L-bit digital signal.

[0100] Therefore, the analog-to-digital converter 100 provided by the embodiments of the present application can amplify the input signal through the first-stage amplifier 20 and the second-stage amplifier 30, and analog-to-digital convert the input signal through the first-stage analog-to-digital conversion circuit 10 and the second-stage analog-to-digital conversion circuit 40 to obtain a corresponding digital signal.

[0101] Subsequently, the analog-to-digital converter 100 can obtain an analog-to-digital conversion result of the input signal according to the first digital signal and the second digital signal. For example, the first digital signal and the second digital signal can be combined to obtain a complete digital signal, and the complete digital signal can be output. The complete digital signal can be an M+L-bit digital signal. For example, the analog-to-digital converter 100 can input the first digital signal and the second digital signal into an external processor, and combine the first digital signal and the second digital signal through the external processor. In some embodiments, when the first digital signal and the second digital signal are combined, the first digital signal can be filled into high bits of the complete digital signal, and the second digital signal can be filled into low bits of the complete digital signal, to obtain a final complete digital signal.

[0102] The analog-to-digital converter 100 provided by the embodiments of the present application sets the inter-stage amplifier to include at least two amplifiers, and the power consumption of the two amplifiers can be reduced. Therefore, compared with a single inter-stage amplifier, the power consumption of the analog-to-digital converter 100 can be reduced.

[0103] In some embodiments, the first-stage amplifier 20 is an active amplifier.

[0104] In some embodiments, when the first-stage amplifier 20 is an active amplifier, the reference Figure 2 , Figure 2 FIG. 2 is a second circuit architecture diagram of the analog-to-digital converter 100 provided by the embodiments of the present application. The analog-to-digital converter 100 of the circuit architecture can be used to analog-to-digital convert an input signal when the input signal is a single-ended signal.

[0105] The first-stage amplifier 20 includes a first amplifier AMP1, a first capacitor CFP1, and a first switch SP1.

[0106] The first input terminal of the first amplifier AMP1 is connected with the first-stage analog-digital conversion circuit 10, the second input terminal of the first amplifier AMP1 is connected to a common-mode node VCM which can provide a common-mode voltage, and the output terminal of the first amplifier AMP1 is connected with the second-stage amplifier 30. The first terminal of the first capacitor CFP1 is connected with the first input terminal of the first amplifier AMP1, and the second terminal of the first capacitor CFP1 is connected with the output terminal of the first amplifier AMP1. The first terminal of the first switch SP1 is connected with the first input terminal of the first amplifier AMP1, and the second terminal of the first switch SP1 is connected with the output terminal of the first amplifier AMP1. The output terminal of the first amplifier AMP1 is configured to output a first amplified signal. In this embodiment, the first input terminal of the first amplifier AMP1 can be a negative input terminal, and the second input terminal can be a positive input terminal; or the first input terminal of the first amplifier AMP1 can be a positive input terminal, and the second input terminal can be a negative input terminal, in which case the lower-stage circuit needs to invert the signal.

[0107] In this embodiment, the residual voltage signal output by the first-stage analog-digital conversion circuit 10 can be input to the first amplifier AMP1 and the first capacitor CFP1, and the first amplifier AMP1 and the first capacitor CFP1 are configured to jointly amplify the residual voltage signal and output a first amplified signal through the output terminal of the first amplifier AMP1. When amplifying, the first switch SP1 is turned on. In this embodiment, the parameters of the first amplifier AMP1 and the capacitance value of the first capacitor CFP1 can be set according to actual needs.

[0108] It can be understood that in actual application, the first-stage amplifier 20 can further include a second switch SHP1, as shown in FIG. 2. The first input terminal of the first amplifier AMP1 is connected with the first-stage analog-digital conversion circuit 10 through the second switch SHP1. When the first capacitor CFP1 samples the residual voltage signal, the second switch SHP1 is turned on. When the first amplifier AMP1 and the first capacitor CFP1 jointly amplify the residual voltage signal, the second switch SHP1 can be controlled to be turned off. Figure 2

[0109] It should be noted that when the first-stage analog-digital conversion circuit 10 samples and performs analog-digital conversion on the input signal, the first capacitor CFP1 can sample the residual voltage signal synchronously, in which case the second switch SHP1 is turned on and the first switch SP1 is turned off. Therefore, the process of sampling the residual voltage signal by the first-stage amplifier 20 does not need to be performed separately, thereby saving the processing time of the first-stage amplifier 20 and further saving the time for analog-digital conversion by the analog-digital converter 100, and improving the analog-digital conversion efficiency.

[0110] In some embodiments, when the first-stage amplifier 20 is an active amplifier, reference can be made to FIG. 3. Figure 3 Figure 3 ​​A third circuit architecture of an analog-to-digital converter 100 is provided in the embodiments of the present application. The analog-to-digital converter 100 of the circuit architecture can be used to perform analog-to-digital conversion on an input signal when the input signal is a differential signal. The first-stage analog-to-digital conversion circuit 10 includes a first output terminal P1 and a second output terminal P2. The second-stage amplifier 30 includes a first input terminal P3 and a second input terminal P4.

[0111] The first-stage amplifier 20 includes a first capacitor CFP1, a second capacitor CFN1, a first amplifier AMP1, a first switch SP1, and a third switch SN1.

[0112] The first input terminal of the first amplifier AMP1 is connected to the first output terminal P1 of the first-stage analog-to-digital conversion circuit 10, the second input terminal of the first amplifier AMP1 is connected to the second output terminal P2 of the first-stage analog-to-digital conversion circuit 10, the first power supply terminal of the first amplifier AMP1 is connected to the first input terminal P3 of the second-stage amplifier 30, and the second power supply terminal of the first amplifier AMP1 is connected to the second input terminal P4 of the second-stage amplifier 30. The first power supply terminal and the second power supply terminal of the first amplifier AMP1 are used to output a first amplified signal. For example, the first input terminal of the first amplifier AMP1 can be a positive input terminal, the second input terminal can be a negative input terminal, the first power supply terminal can be a negative power supply terminal, and the second power supply terminal can be a positive power supply terminal.

[0113] The first end of the first capacitor CFP1 is connected to the first input terminal of the first amplifier AMP1, and the second end of the first capacitor CFP1 is connected to the first power supply terminal of the first amplifier AMP1. The first end of the first switch SP1 is connected to the first input terminal of the first amplifier AMP1, and the second end of the first switch SP1 is connected to the first power supply terminal of the first amplifier AMP1. The first end of the second capacitor CFN1 is connected to the second input terminal of the first amplifier AMP1, and the second end of the second capacitor CFN1 is connected to the second power supply terminal of the first amplifier AMP1. The first end of the third switch SN1 is connected to the second input terminal of the first amplifier AMP1, and the second end of the third switch SN1 is connected to the second power supply terminal of the first amplifier AMP1.

[0114] The residual voltage signal output by the first-stage analog-to-digital conversion circuit 10 can be input to the first capacitor CFP1, the second capacitor CFN1, and the first amplifier AMP1. The first capacitor CFP1, the second capacitor CFN1, and the first amplifier AMP1 are configured to collectively amplify the residual voltage signal and output a first amplified signal through the first power supply terminal and the second power supply terminal of the first amplifier AMP1. When amplifying, the first switch SP1 and the third switch SN1 are turned on. The capacitance values of the first capacitor CFP1 and the second capacitor CFN1 and the parameters of the first amplifier AMP1 can be set according to actual needs.

[0115] It can be understood that, in actual application, the first-stage amplifier 20 can further include a second switch SHP1 and a fourth switch SHN1. The first input terminal of the first amplifier AMP1 is connected with the first output terminal P1 of the first-stage analog-digital conversion circuit 10 through the second switch SHP1, and the second input terminal of the first amplifier AMP1 is connected with the second output terminal P2 of the first-stage analog-digital conversion circuit 10 through the fourth switch SHN1. When the first capacitor CFP1 and the second capacitor CFN1 sample the residual voltage signal, the second switch SHP1 and the fourth switch SHN1 are turned on. When the first capacitor CFP1, the second capacitor CFN1 and the first amplifier AMP1 collectively amplify the residual voltage signal, the second switch SHP1 and the fourth switch SHN1 can be controlled to be turned off.

[0116] It should be noted that, when the first-stage analog-digital conversion circuit 10 samples and converts the input signal, the first capacitor CFP1 and the second capacitor CFN1 can synchronously sample the residual voltage signal, at this time, the second switch SHP1 and the fourth switch SHN1 are turned on, and the first switch SP1 and the third switch SN1 are turned off. Therefore, the process of sampling the residual voltage signal by the first-stage amplifier 20 does not need to be performed separately, thereby saving the processing time of the first-stage amplifier 20, and further saving the time of analog-digital conversion of the analog-digital converter 100, and improving the analog-digital conversion efficiency.

[0117] In some embodiments, the first-stage amplifier 20 can also be a passive amplifier. When the first-stage amplifier 20 is a passive amplifier, the first amplifier AMP1 can be saved, and therefore the area of the first-stage amplifier 20 can be reduced, thereby reducing the overall area of the analog-digital converter 100.

[0118] In some embodiments, the second-stage amplifier 30 is a passive amplifier.

[0119] In some embodiments, when the second-stage amplifier 30 is a passive amplifier, the reference Figure 4 , Figure 4 FIG. 4 is a fourth circuit architecture diagram of an analog-digital converter 100 provided by an embodiment of the present application. The analog-digital converter 100 of the circuit architecture can be used to convert an input signal into a digital signal when the input signal is a single-ended signal.

[0120] The second-stage amplifier 30 includes a third capacitor CFP2, a fourth capacitor CFP2, a sixth switch SHP5 and a seventh switch SWCM1.

[0121] The first end of the third capacitor CSP2 is connected with the first-stage amplifier 20 and grounded through the sixth switch SHP5. The second end of the third capacitor CSP2 is connected with the first end of the fourth capacitor CFP2, and the second end of the third capacitor CSP2 and the first end of the fourth capacitor CFP2 are connected to a common-mode node VCM through the seventh switch SWCM1, and the common-mode node VCM can provide a common-mode voltage. The second end of the fourth capacitor CFP2 is connected with the second-stage analog-to-digital conversion circuit 40. The second end of the fourth capacitor CFP2 is used to output a second amplified signal. The capacitance values of the third capacitor CSP2 and the fourth capacitor CFP2 can be set according to actual needs.

[0122] The first-stage amplifier 20 can sample the first amplified signal through the third capacitor CSP2 after outputting the first amplified signal. When sampling the first amplified signal, the sixth switch SHP5 is turned off and the seventh switch SWCM1 is turned on. After sampling the first amplified signal, the third capacitor CSP2 and the fourth capacitor CFP2 can amplify the first amplified signal. When amplifying the first amplified signal, the sixth switch SHP5 is turned on and the seventh switch SWCM1 is turned off.

[0123] It can be understood that in actual application, the second-stage amplifier 30 can further include a fifth switch SHP4. The first end of the third capacitor CSP2 is connected with the first-stage amplifier 20 through the fifth switch SHP4. When the third capacitor CSP2 samples the first amplified signal, the fifth switch SHP4 is turned on. When the third capacitor CSP2 and the fourth capacitor CFP2 amplify the first amplified signal, the fifth switch SHP4 can be controlled to be turned off to avoid affecting the first-stage amplifier 20 during the amplification process of the second-stage amplifier 30.

[0124] In some embodiments, when the second-stage amplifier 30 is a passive amplifier, the first-stage amplifier 20 can further include a fifth switch SHP4. Figure 5 , Figure 5 FIG. 5 shows a fifth circuit architecture of an analog-to-digital converter 100 provided by an embodiment of the present application. The analog-to-digital converter 100 of the circuit architecture can be used to convert an input signal into a digital signal when the input signal is a differential signal. The first-stage amplifier 20 includes a third output terminal P5 and a fourth output terminal P6. The second-stage analog-to-digital conversion circuit 40 includes a third input terminal P7 and a fourth input terminal P8.

[0125] The second-stage amplifier 30 includes a third capacitor CSP2, a fourth capacitor CFP2, a fifth capacitor CSN2, a sixth capacitor CFN2, a sixth switch SHP5, a seventh switch SWCM1, a ninth switch SHN5, and a tenth switch SWCM2. The capacitance values of the third capacitor CSP2, the fourth capacitor CFP2, the fifth capacitor CSN2, and the sixth capacitor CFN2 can be set according to actual needs.

[0126] The first end of the third capacitor CSP2 is connected with the third output end P5 of the first stage amplifier 20 and grounded through the sixth switch SHP5. The second end of the third capacitor CSP2 is connected with the first end of the fourth capacitor CFP2, and the second end of the third capacitor CSP2 and the first end of the fourth capacitor CFP2 are connected to the common mode node VCM through the seventh switch SWCM1. The common mode node VCM can provide a common mode voltage. The second end of the fourth capacitor CFP2 is connected with the third input end P7 of the second stage analog-digital conversion circuit 40.

[0127] The first end of the fifth capacitor CSN2 is connected with the fourth output end P6 of the first stage amplifier 20 and grounded through the ninth switch SHN5. The second end of the fifth capacitor CSN2 is connected with the first end of the sixth capacitor CFN2, and the second end of the fifth capacitor CSN2 and the first end of the sixth capacitor CFN2 are connected to the common mode node VCM through the tenth switch SWCM2. The second end of the sixth capacitor CFN2 is connected with the fourth input end P8 of the second stage analog-digital conversion circuit 40.

[0128] The second end of the fourth capacitor CFP2 and the second end of the sixth capacitor CFN2 are used to output the second amplified signal.

[0129] After the first stage amplifier 20 outputs the first amplified signal, the first amplified signal can be sampled through the third capacitor CSP2 and the fifth capacitor CSN2. When sampling, the sixth switch SHP5 and the ninth switch SHN5 are turned off, and the seventh switch SWCM1 and the tenth switch SWCM2 are turned on. After sampling the first amplified signal, the first amplified signal can be amplified through the third capacitor CSP2, the fourth capacitor CFP2, the fifth capacitor CSN2 and the sixth capacitor CFN2. When amplifying, the sixth switch SHP5 and the ninth switch SHN5 are turned on, and the seventh switch SWCM1 and the tenth switch SWCM2 are turned off.

[0130] It can be understood that in actual application, the second stage amplifier 30 can further include the fifth switch SHP4 and the sixth switch SHP5. The first end of the third capacitor CSP2 is connected with the third output end P5 of the first stage amplifier 20 through the fifth switch SHP4. The first end of the fifth capacitor CSN2 is connected with the fourth output end P6 of the first stage amplifier 20 through the eighth switch SHN4. When the third capacitor CSP2 and the fifth capacitor CSN2 sample the first amplified signal, the fifth switch SHP4 and the eighth switch SHN4 are turned on. When amplifying the first amplified signal, the fifth switch SHP4 and the eighth switch SHN4 can be controlled to be turned off, so as to avoid affecting the first stage amplifier 20 during the amplification process of the second stage amplifier 30.

[0131] In some embodiments, the second stage amplifier 30 is an active amplifier.

[0132] In some embodiments, when the second-stage amplifier 30 is an active amplifier, the reference Figure 6 , Figure 6 A sixth circuit architecture of the analog-to-digital converter 100 is provided in the embodiments of the present application. The analog-to-digital converter 100 of the circuit architecture can be used to perform analog-to-digital conversion on an input signal when the input signal is a single-ended signal.

[0133] The second-stage amplifier 30 includes a third capacitor CSP2, a fourth capacitor CFP2, a second amplifier AMP2, a sixth switch SHP5, and an eleventh switch SP2. The capacitance values of the third capacitor CSP2 and the fourth capacitor CFP2 and the parameters of the second amplifier AMP2 can be set according to actual needs.

[0134] The first end of the third capacitor CSP2 is connected to the first-stage amplifier 20 and grounded through the sixth switch SHP5. The second end of the third capacitor CSP2 is connected to the first end of the fourth capacitor CFP2, and the second end of the fourth capacitor CFP2 is connected to the second-stage analog-to-digital conversion circuit 40. The first input end of the second amplifier AMP2 is connected between the second end of the third capacitor CSP2 and the first end of the fourth capacitor CFP2, the second input end of the second amplifier AMP2 is connected to a common-mode node VCM that can provide a common-mode voltage, and the output end of the second amplifier AMP2 is connected to the second end of the fourth capacitor CFP2. The first end of the eleventh switch SP2 is connected between the second end of the third capacitor CSP2 and the first end of the fourth capacitor CFP2, and the second end of the eleventh switch SP2 is connected to the second end of the fourth capacitor CFP2.

[0135] The output end of the second amplifier AMP2 is configured to output a second amplified signal.

[0136] After the first-stage amplifier 20 outputs the first amplified signal, the first amplified signal can be sampled by the third capacitor CSP2. When sampling, the sixth switch SHP5 is turned off, and the eleventh switch SP2 is turned on. After sampling the first amplified signal, the first amplified signal can be amplified by the third capacitor CSP2, the fourth capacitor CFP2, and the second amplifier AMP2. When amplifying, the sixth switch SHP5 is turned on, and the eleventh switch SP2 is turned off.

[0137] It can be understood that, in actual applications, the second-stage amplifier 30 can further include a fifth switch SHP4. The first end of the third capacitor CSP2 is connected to the first-stage amplifier 20 through the fifth switch SHP4. When sampling the first amplified signal, the fifth switch SHP4 is turned on. When amplifying the first amplified signal, the fifth switch SHP4 can be controlled to be turned off to avoid affecting the first-stage amplifier 20 during the amplification process of the second-stage amplifier 30.

[0138] In some embodiments, when the second-stage amplifier 30 is an active amplifier, the reference Figure 7 , Figure 7 A seventh circuit architecture of the analog-to-digital converter 100 according to an embodiment of the present application is provided. The analog-to-digital converter 100 of the circuit architecture can be used to convert an input signal into a digital signal when the input signal is a differential signal. The first-stage amplifier 20 includes a third output terminal P5 and a fourth output terminal P6. The second-stage analog-to-digital conversion circuit 40 includes a third input terminal P7 and a fourth input terminal P8.

[0139] The second-stage amplifier 30 includes a third capacitor CSP2, a fourth capacitor CFP2, a fifth capacitor CSN2, a sixth capacitor CFN2, a second amplifier AMP2, a sixth switch SHP5, an eleventh switch SP2, a ninth switch SHN5, and a twelfth switch SN2. The capacitance values of the third capacitor CSP2, the fourth capacitor CFP2, the fifth capacitor CSN2, and the sixth capacitor CFN2 and the parameters of the second amplifier AMP2 can be set according to actual needs.

[0140] The first terminal of the third capacitor CSP2 is connected to the third output terminal P5 of the first-stage amplifier 20 and grounded through the sixth switch SHP5. The second terminal of the third capacitor CSP2 is connected to the first terminal of the fourth capacitor CFP2, and the second terminal of the fourth capacitor CFP2 is connected to the third input terminal P7 of the second-stage analog-to-digital conversion circuit 40. The first terminal of the eleventh switch SP2 is connected between the second terminal of the third capacitor CSP2 and the first terminal of the fourth capacitor CFP2, and the second terminal of the eleventh switch SP2 is connected to the second terminal of the fourth capacitor CFP2.

[0141] The first terminal of the fifth capacitor CSN2 is connected to the fourth output terminal P6 of the first-stage amplifier 20 and grounded through the ninth switch SHN5. The second terminal of the fifth capacitor CSN2 is connected to the first terminal of the sixth capacitor CFN2, and the second terminal of the sixth capacitor CFN2 is connected to the fourth input terminal P8 of the second-stage analog-to-digital conversion circuit 40. The first terminal of the twelfth switch SN2 is connected between the second terminal of the fifth capacitor CSN2 and the first terminal of the sixth capacitor CFN2, and the second terminal of the twelfth switch SN2 is connected to the second terminal of the sixth capacitor CFN2.

[0142] The first input end of the second amplifier AMP2 is connected between the second end of the third capacitor CSP2 and the first end of the fourth capacitor CFP2, the second input end of the second amplifier AMP2 is connected between the second end of the fifth capacitor CSN2 and the first end of the sixth capacitor CFN2, the first power supply end of the second amplifier AMP2 is connected with the third input end P7 of the second-stage analog-digital conversion circuit 40, and the second power supply end of the second amplifier AMP2 is connected with the fourth input end P8 of the second-stage analog-digital conversion circuit 40. The first power supply end and the second power supply end of the second amplifier AMP2 are used to output a second amplified signal. For example, the first input end of the second amplifier AMP2 can be a positive input end, the second input end can be a negative input end, the first power supply end can be a negative power supply end, and the second power supply end can be a positive power supply end.

[0143] After the first-stage amplifier 20 outputs the first amplified signal, the first amplified signal can be sampled through the third capacitor CSP2 and the fifth capacitor CSN2. When sampling, the sixth switch SHP5 and the ninth switch SHN5 are turned off, and the eleventh switch SP2 and the twelfth switch SN2 are turned on. After sampling the first amplified signal, the first amplified signal can be amplified through the third capacitor CSP2, the fourth capacitor CFP2, the fifth capacitor CSN2, the sixth capacitor CFN2 and the second amplifier AMP2. When amplifying, the sixth switch SHP5 and the ninth switch SHN5 are turned on, and the eleventh switch SP2 and the twelfth switch SN2 are turned off.

[0144] It can be understood that in actual application, the second-stage amplifier 30 can further include the fifth switch SHP4 and the eighth switch SHN4. The first end of the third capacitor CSP2 is connected with the third output end P5 of the first-stage amplifier 20 through the fifth switch SHP4. The first end of the fifth capacitor CSN2 is connected with the fourth output end P6 of the first-stage amplifier 20 through the eighth switch SHN4. When sampling the first amplified signal, the fifth switch SHP4 and the eighth switch SHN4 are turned on. When amplifying the first amplified signal, the fifth switch SHP4 and the eighth switch SHN4 can be controlled to be turned off, so as to avoid affecting the first-stage amplifier 20 during the amplifying process of the second-stage amplifier 30.

[0145] As can be known from the description of the above embodiment, when the second-stage amplifier 30 is a passive amplifier, compared with the case that the second-stage amplifier 30 is an active amplifier, the second amplifier AMP2 can be saved, so that the area of the second-stage amplifier 30 can be reduced, thereby reducing the overall area of the analog-digital converter 100.

[0146] In some embodiments, with reference to Figure 8 , Figure 8 An eighth circuit architecture diagram of the analog-digital converter 100 provided by the embodiments of the present application is shown.

[0147] The analog-to-digital converter 100 further comprises an output circuit 50. The output circuit 50 is connected with the first-stage analog-to-digital conversion circuit 10 and the second-stage analog-to-digital conversion circuit 40. The output circuit 50 is configured to obtain the analog-to-digital conversion result of the input signal according to the first digital signal output by the first-stage analog-to-digital conversion circuit 10 and the second digital signal output by the second-stage analog-to-digital conversion circuit 40. For example, the first digital signal output by the first-stage analog-to-digital conversion circuit 10 and the second digital signal output by the second-stage analog-to-digital conversion circuit 40 are combined to obtain a complete digital signal, and the complete digital signal is output.

[0148] For example, the output circuit 50 can fill the first digital signal to the high bit of the complete digital signal and fill the second digital signal to the low bit of the complete digital signal to obtain the final complete digital signal.

[0149] It can be understood that, in some other embodiments, the analog-to-digital converter 100 can not comprise the output circuit 50, and the combination of the first digital signal and the second digital signal can be performed by an external processor.

[0150] In some embodiments, the reference Figure 9 , Figure 9 A ninth circuit architecture diagram of the analog-to-digital converter 100 according to an embodiment of the present application is provided.

[0151] Figure 9 The analog-to-digital converter 100 shown in Figure 1 The difference between the analog-to-digital converter 100 shown in and the analog-to-digital converter 100 shown in is that the analog-to-digital converter 100 further comprises a sampling circuit 60, the sampling circuit 60 is connected with the first-stage amplifier 20 and is configured to sample the first amplified signal; the second-stage amplifier 30 is connected with the sampling circuit 60 and is configured to amplify the signal output by the sampling circuit 60 and output the second amplified signal. In this embodiment, the sampling circuit 60 can be understood as the sampling circuit in the second-stage amplifier 30 in the above-mentioned embodiments, and the second-stage amplifier 30 in this embodiment can be understood as the circuit in the second-stage amplifier 30 in the above-mentioned embodiments except the sampling circuit. That is, in the above-mentioned embodiments, the sampling circuit is integrated in the second-stage amplifier 30 as a part of the second-stage amplifier 30; while in this embodiment, the sampling circuit is independent of the second-stage amplifier 30, that is, the sampling circuit 60.

[0152] The specific circuit structure of the sampling circuit 60 in this embodiment can refer to the structure of the sampling circuit in the second-stage amplifier 30 in the above-mentioned embodiments, for example, the third capacitor CSP2 in Figure 6 the third capacitor CSP2 and the fifth capacitor CSN2 in Figure 7 Therefore, the specific structure of the sampling circuit 60 will not be described here.

[0153] In the analog-to-digital converter 100 described in the above various embodiments, the first-stage analog-to-digital conversion circuit 10 has M bits, and the second-stage analog-to-digital conversion circuit 40 has L bits. Thus, the final digital signal has N bits, where N = M + L.

[0154] The analog-to-digital converter 100 provided by the embodiments of the present application has at least two amplifiers in the inter-stage amplifier. Thus, compared with a single inter-stage amplifier, the amplification time of each amplifier is shortened. In the case of the inter-stage amplifier including the first-stage amplifier 20 and the second-stage amplifier 30, when the amplification time of the first-stage amplifier 20 is half of that of a single inter-stage amplifier, the bandwidth requirement of the first-stage amplifier 20 is twice that of a single inter-stage amplifier according to the accuracy requirement of the front and rear stages. Since the bandwidth is inversely proportional to the load, the load of the first-stage amplifier 20 is greatly reduced, and thus the current required by the first-stage amplifier 20 is greatly reduced, thereby greatly reducing the power consumption of the first-stage amplifier 20. When the amplification time of the second-stage amplifier 30 is half of that of a single inter-stage amplifier, the bandwidth requirement of the second-stage amplifier 30 is reduced compared with a single inter-stage amplifier according to the accuracy requirement of the front and rear stages. Since the load of the second-stage amplifier 30 is the same as that of a single inter-stage amplifier, but the bandwidth requirement is reduced, when the bandwidth requirement of the second-stage amplifier 30 is achieved, the transconductance of the second-stage amplifier 30 is reduced, and thus the current required by the second-stage amplifier 30 is reduced, thereby reducing the power consumption of the second-stage amplifier 30. Thus, the power consumption of the entire analog-to-digital converter 100 is reduced.

[0155] The above embodiments describe the circuit architecture of the analog-to-digital converter 100, and the specific circuit structure of the analog-to-digital converter 100 is described below.

[0156] In some embodiments, the analog-to-digital converter 100 provided by the embodiments of the present application is as shown in FIG. 1. Figure 10 , Figure 10 The first specific circuit structure of the analog-to-digital converter 100 provided by the embodiments of the present application is shown in FIG. 1. Figure 10 The analog-to-digital converter 100 shown in FIG. 1 is a circuit architecture diagram when the first-stage amplifier 20 is an active amplifier, the second-stage amplifier 30 is a passive amplifier, and the input signal is a differential signal.

[0157] The first-stage analog-digital conversion circuit 10 comprises a first capacitor array 11, a first comparator 12 and a first logic control circuit 13. The first capacitor array 11 is configured to sample an input signal and output a residual voltage signal, and the first-stage amplifier 20 is connected to the first capacitor array 11. The first comparator 12 is connected to the first capacitor array 11 and is configured to compare the residual voltage signal and output a first comparison result. The first logic control circuit 13 is connected to the first capacitor array 11 and the first comparator 12 and is configured to perform logic control on the first capacitor array 11 based on the first comparison result and output a first digital signal.

[0158] The first capacitor array 11 comprises two groups of parallel capacitors, and each group of capacitors comprises CP(00), CP(0), …, CP(M-3), CP(M-2), CP(M-1) and the like. The input end of one group of capacitors is connected to reference voltages V REFN , V REFP and an input signal V IN+ through a plurality of switches, and the output end of the group of capacitors is commonly connected to a node VP, which is connected to the positive input end of the first comparator 12 and the first-stage amplifier 20. In addition, the node VP can also be connected to a common-mode node VCM through a switch SWCM1. The input end of the other group of capacitors is connected to reference voltages V REFN , V REFP and an input signal V IN- through a plurality of switches, and the output end of the group of capacitors is commonly connected to a node VN, which is connected to the negative input end of the first comparator 12 and the first-stage amplifier 20. In addition, the node VN can also be connected to the common-mode node VCM through a switch SWCM2.

[0159] The first comparator 12 compares the input signal sampled by the first capacitor array 11 and outputs a first comparison result to the first logic control circuit 13.

[0160] The first logic control circuit 13 performs logic control on the first capacitor array 11 based on the first comparison result and outputs a first digital signal Data[N:N-M-1].

[0161] The second-stage analog-digital conversion circuit 40 comprises a second capacitor array 41, a second comparator 42 and a second logic control circuit 43. The second capacitor array 41 is connected to the second-stage amplifier 30 and is configured to sample a second amplified signal output by the second-stage amplifier 30. The second comparator 42 is connected to the second capacitor array 41 and is configured to compare the second amplified signal and output a second comparison result. The second logic control circuit 43 is connected to the second capacitor array 41 and the second comparator 42 and is configured to perform logic control on the second capacitor array 41 based on the second comparison result and output a second digital signal.

[0162] The second capacitor array 41 includes two groups of capacitors connected in parallel, each group of capacitors includes multiple capacitors such as CP(00), CP(0), ... CP(L-3), CP(L-2), CP(L-1). The input end of one group of capacitors is connected to the reference voltage V through multiple switches. REFN 、V REFP The output terminals of this group of capacitors are commonly connected to the node VP, which is connected to the positive input terminal of the second comparator 42 and the fifth capacitor CSN2 through the sixth capacitor CFN2 of the second stage amplifier 30. In addition, the node VP can also be connected to the common mode node VCM through the sixth capacitor CFN2 and the switch SWCM1. The input terminals of another group of capacitors are connected to the reference voltage V through multiple switches. REFN 、V REFP The output terminals of the capacitor group are commonly connected to a node VN, which is connected to the negative input terminal of the second comparator 42 and the third capacitor CSP2 via the fourth capacitor CFP2 of the second-stage amplifier 30. Furthermore, the node VN can also be connected to the common-mode node VCM via the fourth capacitor CFP2 and the switch SWCM2.

[0163] The second comparator 42 performs a comparison operation on the second amplified signal outputted by the second-stage amplifier 30 , and outputs a second comparison result obtained by the comparison to the second logic control circuit 43 .

[0164] The second logic control circuit 43 performs logic control on the second capacitor array 41 based on the second comparison result, and outputs a second digital signal Data[L:1].

[0165] Also refer to Figure 11 , Figure 11 for Figure 10 The following is an operation timing diagram of the analog-to-digital converter 100. In the diagram, "SH1" indicates the sampling timing of the first-stage analog-to-digital conversion circuit 10, "SAR1 conversion" indicates the conversion timing of the first-stage analog-to-digital conversion circuit 10, and "hold" indicates the residual voltage holding timing of the first-stage analog-to-digital conversion circuit 10; "SH2" indicates the sampling timing of the second-stage analog-to-digital conversion circuit 40, and "SAR2 conversion" indicates the conversion timing of the second-stage analog-to-digital conversion circuit 40; "RA1" indicates the amplification timing of the first-stage amplifier 20, and "off" of the first-stage amplifier 20 indicates that the first-stage amplifier 20 is turned off; "SH4" indicates the sampling timing of the second-stage amplifier 30, and "RA2" indicates the amplification timing of the second-stage amplifier 30, and "off" of the second-stage amplifier 30 indicates that the second-stage amplifier 30 is turned off.

[0166] When the analog-to-digital converter 100 is running, the first-stage analog-to-digital conversion circuit 10 first performs sampling, then performs conversion after the sampling is completed, and then performs residual voltage holding after the conversion is completed. During the residual voltage holding stage of the first-stage analog-to-digital conversion circuit 10, the first-stage amplifier 20 synchronously performs amplification, and then is closed after the amplification is completed. During the amplification stage of the first-stage amplifier 20, the second-stage amplifier 30 synchronously performs sampling, and then performs amplification after the sampling is completed. During the sampling stage of the second-stage amplifier 30, the second-stage analog-to-digital conversion circuit 40 synchronously performs sampling, and then performs conversion after the sampling is completed. Thus, one analog-to-digital conversion process of the analog-to-digital converter 100 is completed. It can be understood that, when the second-stage amplifier 30 performs amplification, the second-stage analog-to-digital conversion circuit 40 can simultaneously perform analog-to-digital conversion.

[0167] It should be noted that, in the embodiment of the present application, when the second-stage analog-to-digital conversion circuit 40 performs conversion, the first-stage analog-to-digital conversion circuit 10 can synchronously perform sampling and conversion of the next time, and the conversion of the next time of the first-stage analog-to-digital conversion circuit 10 and the conversion of the present time of the second-stage analog-to-digital conversion circuit 40 are completed at the same time. Thus, the complete period of one analog-to-digital conversion process of the analog-to-digital converter 100 is the sum of the sampling time, the conversion time of the first-stage analog-to-digital conversion circuit 10, and the amplification time of the first-stage amplifier 20, the sampling time and the conversion time of the second-stage analog-to-digital conversion circuit 40 can be saved, and the amplification time of the first-stage amplifier 20 is smaller than the amplification time of the traditional inter-stage amplifier, thus the time required by the complete period of the analog-to-digital converter 100 can be reduced, and the processing efficiency of the analog-to-digital converter 100 is improved.

[0168] In some embodiments, the analog-to-digital converter 100 provided by the embodiment of the present application is as follows. Figure 12 , Figure 12 A second specific circuit structure diagram of the analog-to-digital converter 100 provided by the embodiment of the present application is shown in FIG. 4. Figure 12 The analog-to-digital converter 100 shown in FIG. 4 is a circuit architecture diagram when the first-stage amplifier 20 is an active amplifier, the second-stage amplifier 30 is an active amplifier, and the input signal is a single-ended signal.

[0169] The first-stage analog-to-digital conversion circuit 10 is different from the above-mentioned embodiment in that the first capacitor array 11 only includes a group of capacitors CP(00), CP(0), …, CP(M-3), CP(M-2), CP(M-1), and the negative input end of the first comparator 12 is connected to the reference voltage V REFN The same as the first-stage analog-to-digital conversion circuit 10 in the above-mentioned embodiment can be referred to the description in the above-mentioned embodiment, which will not be described here.

[0170] The second-stage analog-to-digital conversion circuit 40 differs from the above-mentioned embodiment in that the second capacitor array 41 includes only one set of capacitors CP(00), CP(0), ... CP(L-3), CP(L-2), CP(L-1), and the negative input terminal of the second comparator 42 is connected to the reference voltage V via the capacitor CSN. REFN The similarities between the second-stage analog-to-digital conversion circuit 40 and the above embodiment can be referred to the description of the above embodiment, which will not be repeated here.

[0171] In some embodiments, reference Figure 13 , Figure 13 This is a third specific circuit structure diagram of the analog-to-digital converter 100 provided in an embodiment of the present application. Figure 13 The analog-to-digital converter 100 shown is a specific circuit structure diagram when the first-stage amplifier 20 is an active amplifier, the second-stage amplifier 30 is an active amplifier, and the input signal is a differential signal.

[0172] Among them, the first-stage analog-to-digital conversion circuit 10 and the second-stage analog-to-digital conversion circuit 40 are the same as those in the above embodiment, and reference may be made to the description of the above embodiment, which will not be repeated here.

[0173] Also refer to Figure 14 , Figure 14 for Figure 13 FIG2 is a timing diagram of the operation of the analog-to-digital converter 100. The “off” of the second-stage analog-to-digital conversion circuit 40 indicates that the second-stage analog-to-digital conversion circuit 40 is off. The meanings of the remaining symbols in the timing diagram are the same as those in the above embodiment, and reference may be made to the description of the above embodiment, which will not be repeated here.

[0174] In the embodiment of the present application, when the analog-to-digital converter 100 is operating, the first-stage analog-to-digital conversion circuit 10 first performs sampling, performs conversion after sampling is completed, and performs residual voltage maintenance after conversion is completed. During the residual voltage maintenance phase of the first-stage analog-to-digital conversion circuit 10, the first-stage amplifier 20 synchronously performs amplification and is turned off after amplification is completed. During the amplification phase of the first-stage amplifier 20, the second-stage amplifier 30 synchronously performs sampling, performs amplification after sampling is completed, and is turned off after amplification is completed. During the amplification phase of the second-stage amplifier 30, the second-stage analog-to-digital conversion circuit 40 synchronously performs sampling, and performs conversion after sampling is completed. At this point, one analog-to-digital conversion process of the analog-to-digital converter 100 is completed.

[0175] It should be noted that, in the embodiments of the present application, when the second-stage analog-digital conversion circuit 40 is sampling and converting, the first-stage analog-digital conversion circuit 10 can synchronously sample and convert next time, and the next conversion of the first-stage analog-digital conversion circuit 10 and the current conversion of the second-stage analog-digital conversion circuit 40 are completed at the same time. Therefore, the complete period of one analog-digital conversion process of the analog-digital converter 100 is the sum of the sampling time, the conversion time of the first-stage analog-digital conversion circuit 10 and the amplification time of the first-stage amplifier 20, the sampling time and the conversion time of the second-stage analog-digital conversion circuit 40 can be saved, and the amplification time of the first-stage amplifier 20 is smaller than the amplification time of the traditional inter-stage amplifier, so the time required by the complete period of the analog-digital converter 100 can be reduced, thereby improving the processing efficiency of the analog-digital converter 100.

[0176] As can be known from the description of the above embodiments, the analog-digital converter 100 of the embodiments of the present application can achieve the following technical effects:

[0177] In the first aspect, the inter-stage amplifier is configured to include at least two amplifiers, and the power consumption of the two amplifiers can be reduced, so the power consumption of the analog-digital converter 100 can be reduced compared with a single inter-stage amplifier.

[0178] In the second aspect, the complete period of one analog-digital conversion process of the analog-digital converter 100 can save the sampling time and the conversion time of the second-stage analog-digital conversion circuit 40, or can save the sampling time and the conversion time of the second-stage analog-digital conversion circuit 40 and the amplification time of the first-stage amplifier 20 is smaller than the amplification time of the traditional inter-stage amplifier, so the time required by the complete period of the analog-digital converter 100 can be reduced, thereby improving the processing efficiency of the analog-digital converter 100.

[0179] In the third aspect, when one or both of the first-stage amplifier 20 and the second-stage amplifier 30 is a passive amplifier, the first amplifier AMP1 and / or the second amplifier AMP2 can be saved, so the area of the first-stage amplifier 20 and / or the second-stage amplifier 30 can be reduced, thereby reducing the overall area of the analog-digital converter 100.

[0180] The embodiments of the present application also provide a chip comprising the analog-digital converter 100 described in any of the above embodiments.

[0181] The embodiments of the present application also provide an analog-digital conversion control method, comprising: configuring an inter-stage amplifier between at least two adjacent stages of analog-digital conversion circuits of an analog-digital converter, the inter-stage amplifier including at least two amplifiers configured to amplify signals. The analog-digital conversion control method can be applied to the analog-digital converter 100 described in the above embodiments to control the analog-digital converter 100.

[0182] In some embodiments, the two adjacent analog-to-digital conversion circuits include a first analog-to-digital conversion circuit and a second analog-to-digital conversion circuit, and the at least two amplifiers include a first amplifier and a second amplifier. With reference to Figure 15 , Figure 15 A flowchart of an analog-to-digital conversion control method provided by an embodiment of the present application is shown. The analog-to-digital conversion control method includes the following steps:

[0183] 210, controlling the first analog-to-digital conversion circuit to sample the input signal, to perform analog-to-digital conversion on the input signal to obtain a first digital signal and a residual voltage signal, and to hold the residual voltage signal;

[0184] 220, controlling the first amplifier to amplify the residual voltage signal to obtain a first amplified signal;

[0185] 230, controlling the second amplifier to sequentially sample and amplify the first amplified signal to obtain a second amplified signal;

[0186] 240, controlling the second analog-to-digital conversion circuit to sequentially sample and perform analog-to-digital conversion on the second amplified signal to obtain a second digital signal;

[0187] 250, obtaining an analog-to-digital conversion result of the input signal according to the first digital signal and the second digital signal.

[0188] The specific implementation of each step can refer to the description of each embodiment of the analog-to-digital converter 100 above, and will not be repeated here.

[0189] In some embodiments, when the second amplifier 30 is an active amplifier, the second analog-to-digital conversion circuit 40 is controlled to sequentially sample and perform analog-to-digital conversion on the second amplified signal, and the first analog-to-digital conversion circuit 10 is simultaneously controlled to perform the next sampling and analog-to-digital conversion on the input signal.

[0190] In some embodiments, when the second amplifier is a passive amplifier, the first analog-to-digital conversion circuit 10 is controlled to hold the residual voltage signal, and the second analog-to-digital conversion circuit 40 is simultaneously controlled to sample the second amplified signal; the second analog-to-digital conversion circuit 40 is controlled to perform analog-to-digital conversion on the second amplified signal, and the first analog-to-digital conversion circuit 10 is simultaneously controlled to perform the next sampling and analog-to-digital conversion on the input signal.

[0191] In some embodiments, when the first analog-to-digital conversion circuit 10 is controlled to hold the residual voltage signal, the first amplifier 20 is simultaneously controlled to amplify the residual voltage signal.

[0192] In some embodiments, when the first amplifier 20 is controlled to amplify the residual voltage signal, the second amplifier 30 is simultaneously controlled to sample the first amplified signal.

[0193] The specific implementation of each step can refer to the description of each embodiment of the analog-to-digital converter 100, which will not be repeated here.

[0194] In the description of the present application, it should be understood that terms such as "first", "second" and the like are only used to distinguish similar objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated.

[0195] The analog-to-digital converter, chip and analog-to-digital conversion control method provided by the embodiments of the present application are described in detail. The principles and implementation manners of the present application are described by applying specific examples, and the above description of the embodiments is only used to help understand the present application. Meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation manner and application range will be changed, and the above description of the present application should not be understood as a limitation.

Claims

1. An analog-to-digital converter, characterized by The multi-stage analog-to-digital conversion circuit comprises two adjacent stages of analog-to-digital conversion circuits, and an inter-stage amplifier is arranged between any two adjacent stages of analog-to-digital conversion circuits, the inter-stage amplifier comprises at least two amplifiers connected in cascade, the at least two amplifiers comprise a first-stage amplifier and a second-stage amplifier, the first-stage amplifier and the second-stage amplifier are both configured to amplify a signal, the bandwidth of the first-stage amplifier is greater than the bandwidth of the second-stage amplifier, and at least one of the first-stage amplifier and the second-stage amplifier is a passive amplifier.

2. The analog-to-digital converter of claim 1, wherein, The multi-stage analog-to-digital conversion circuit comprises a first-stage analog-to-digital conversion circuit and a second-stage analog-to-digital conversion circuit, and the inter-stage amplifier is arranged between the first-stage analog-to-digital conversion circuit and the second-stage analog-to-digital conversion circuit, wherein: The first-stage analog-to-digital conversion circuit is configured to sample an input signal and perform analog-to-digital conversion on the input signal to obtain a first digital signal and a residual voltage signal; The first-stage amplifier is connected to the first-stage analog-to-digital conversion circuit and is configured to amplify the residual voltage signal to obtain and output a first amplified signal; The second-stage amplifier is connected to the first-stage amplifier and is configured to sample and amplify the first amplified signal to obtain and output a second amplified signal; The second-stage analog-to-digital conversion circuit is connected to the second-stage amplifier and is configured to sample and perform analog-to-digital conversion on the second amplified signal and output a second digital signal; The analog-to-digital converter is configured to obtain an analog-to-digital conversion result of the input signal according to the first digital signal and the second digital signal.

3. The analog-to-digital converter of claim 2, wherein, The first-stage amplifier is a passive amplifier.

4. The analog-to-digital converter of claim 2, wherein, The first-stage amplifier is an active amplifier.

5. The analog-to-digital converter of claim 4, wherein, The input signal is a single-ended signal, and the first-stage amplifier comprises a first amplifier, a first capacitor and a first switch; The first input end of the first amplifier is connected to the first-stage analog-to-digital conversion circuit, the second input end of the first amplifier is connected to a common-mode node, and the output end of the first amplifier is connected to the second-stage amplifier; The first end of the first capacitor is connected to the first input end of the first amplifier, and the second end of the first capacitor is connected to the output end of the first amplifier; The first end of the first switch is connected to the first input end of the first amplifier, and the second end of the first switch is connected to the output end of the first amplifier; The output end of the first amplifier is configured to output the first amplified signal.

6. The analog-to-digital converter of claim 5, wherein, The first-stage amplifier further comprises a second switch, and the first input end of the first amplifier is connected to the first-stage analog-to-digital conversion circuit through the second switch.

7. The analog-to-digital converter of claim 4, wherein, The input signal is a differential signal, the first-stage analog-to-digital conversion circuit comprises a first output end and a second output end, the second-stage amplifier comprises a first input end and a second input end, and the first-stage amplifier comprises a first amplifier, a first capacitor, a second capacitor, a first switch and a third switch; The first input end of the first amplifier is connected with the first output end of the first-stage analog-digital conversion circuit, the second input end of the first amplifier is connected with the second output end of the first-stage analog-digital conversion circuit, the first power supply end of the first amplifier is connected with the first input end of the second-stage amplifier, and the second power supply end of the first amplifier is connected with the second input end of the second-stage amplifier; The first end of the first capacitor is connected with the first input end of the first amplifier, and the second end of the first capacitor is connected with the first power supply end of the first amplifier; The first end of the first switch is connected with the first input end of the first amplifier, and the second end of the first switch is connected with the first power supply end of the first amplifier; The first end of the second capacitor is connected with the second input end of the first amplifier, and the second end of the second capacitor is connected with the second power supply end of the first amplifier; The first end of the third switch is connected with the second input end of the first amplifier, and the second end of the third switch is connected with the second power supply end of the first amplifier; The first power supply end and the second power supply end of the first amplifier are used for outputting the first amplified signal.

8. The analog-to-digital converter of claim 7, wherein, The first-stage amplifier further comprises a second switch and a fourth switch, the first input end of the first amplifier is connected with the first output end of the first-stage analog-digital conversion circuit through the second switch, and the second input end of the first amplifier is connected with the second output end of the first-stage analog-digital conversion circuit through the fourth switch.

9. The analog-to-digital converter of claim 2, wherein, The second-stage amplifier is a passive amplifier.

10. The analog-to-digital converter of claim 9, wherein, The input signal is a single-ended signal, and the second-stage amplifier comprises a third capacitor, a fourth capacitor, a sixth switch and a seventh switch; The first end of the third capacitor is connected with the first-stage amplifier and grounded through the sixth switch, the second end of the third capacitor is connected with the first end of the fourth capacitor, and the second end of the third capacitor and the first end of the fourth capacitor are connected to a common-mode node through the seventh switch, and the second end of the fourth capacitor is connected with the second-stage analog-digital conversion circuit; The second end of the fourth capacitor is used for outputting the second amplified signal.

11. The analog-to-digital converter of claim 10, wherein, The first end of the third capacitor is connected with the first-stage amplifier through the fifth switch.

12. The analog-to-digital converter of claim 9, wherein, The input signal is a differential signal, the first-stage amplifier comprises a third output end and a fourth output end, the second-stage analog-digital conversion circuit comprises a third input end and a fourth input end, and the second-stage amplifier comprises a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a sixth switch, a seventh switch, a ninth switch and a tenth switch; The first end of the third capacitor is connected with the third output end of the first-stage amplifier and grounded through the sixth switch, the second end of the third capacitor is connected with the first end of the fourth capacitor, and the second end of the third capacitor and the first end of the fourth capacitor are connected to a common-mode node through the seventh switch, and the second end of the fourth capacitor is connected with the third input end of the second-stage analog-digital conversion circuit; The first end of the fifth capacitor is connected with the fourth output end of the first stage amplifier, and is grounded through the ninth switch; the second end of the fifth capacitor is connected with the first end of the sixth capacitor, and the second end of the fifth capacitor and the first end of the sixth capacitor are connected to a common mode node through the tenth switch; the second end of the sixth capacitor is connected with the fourth input end of the second stage analog-to-digital conversion circuit; The second end of the fourth capacitor and the second end of the sixth capacitor are used for outputting the second amplified signal.

13. The analog-to-digital converter according to claim 12, wherein: The second stage amplifier further comprises a fifth switch and an eighth switch, the first end of the third capacitor is connected with the third output end of the first stage amplifier through the fifth switch, and the first end of the fifth capacitor is connected with the fourth output end of the first stage amplifier through the eighth switch.

14. The analog-to-digital converter of claim 2, wherein, The second stage amplifier is an active amplifier.

15. The analog-to-digital converter of claim 14, wherein, The input signal is a single-ended signal, and the second stage amplifier comprises a third capacitor, a fourth capacitor, a second amplifier, a sixth switch and an eleventh switch; The first end of the third capacitor is connected with the first stage amplifier and is grounded through the sixth switch; the second end of the third capacitor is connected with the first end of the fourth capacitor, and the second end of the fourth capacitor is connected with the second stage analog-to-digital conversion circuit; The first input end of the second amplifier is connected between the second end of the third capacitor and the first end of the fourth capacitor, the second input end of the second amplifier is connected to a common mode node, and the output end of the second amplifier is connected with the second end of the fourth capacitor; The first end of the eleventh switch is connected between the second end of the third capacitor and the first end of the fourth capacitor, and the second end of the eleventh switch is connected with the second end of the fourth capacitor; The output end of the second amplifier is used for outputting a second amplified signal.

16. The analog-to-digital converter of claim 15, wherein, The second stage amplifier further comprises a fifth switch, and the first end of the third capacitor is connected with the first stage amplifier through the fifth switch.

17. The analog-to-digital converter of claim 14, wherein, The input signal is a differential signal, the first stage amplifier comprises a third output end and a fourth output end, the second stage analog-to-digital conversion circuit comprises a third input end and a fourth input end, and the second stage amplifier comprises a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a second amplifier, a sixth switch, a ninth switch, an eleventh switch and a twelfth switch; The first end of the third capacitor is connected with the third output end of the first stage amplifier and is grounded through the sixth switch; the second end of the third capacitor is connected with the first end of the fourth capacitor, and the second end of the fourth capacitor is connected with the third input end of the second stage analog-to-digital conversion circuit; the first end of the eleventh switch is connected between the second end of the third capacitor and the first end of the fourth capacitor, and the second end of the eleventh switch is connected with the second end of the fourth capacitor; A first end of the fifth capacitor is connected to a fourth output end of the first-stage amplifier and grounded through the ninth switch; a second end of the fifth capacitor is connected to a first end of the sixth capacitor, and a second end of the sixth capacitor is connected to a fourth input end of the second-stage analog-to-digital conversion circuit; a first end of the twelfth switch is connected between the second end of the fifth capacitor and the first end of the sixth capacitor, and a second end of the twelfth switch is connected to the second end of the sixth capacitor; a first input end of the second amplifier is connected between a second end of the third capacitor and a first end of the fourth capacitor, a second input end of the second amplifier is connected between a second end of the fifth capacitor and a first end of the sixth capacitor, a first power supply end of the second amplifier is connected to the second end of the fourth capacitor, and a second power supply end of the second amplifier is connected to the second end of the sixth capacitor; The first power supply end and the second power supply end of the second amplifier are configured to output a second amplified signal.

18. The analog-to-digital converter of claim 17, wherein, The second-stage amplifier further includes a fifth switch and an eighth switch, and a first end of the third capacitor is connected to a third output end of the first-stage amplifier through the fifth switch, and a first end of the fifth capacitor is connected to a fourth output end of the first-stage amplifier through the eighth switch.

19. The analog-to-digital converter of any of claims 2 to 18, wherein, The first-stage analog-to-digital conversion circuit includes: a first capacitor array configured to sample an input signal and output a residual voltage signal, the first-stage amplifier being connected to the first capacitor array; a first comparator connected to the first capacitor array and configured to compare the residual voltage signal and output a first comparison result; and a first logic control circuit connected to the first capacitor array and the first comparator and configured to perform logic control on the first capacitor array based on the first comparison result and output a first digital signal.

20. The analog-to-digital converter of any of claims 2 to 18, wherein, The second-stage analog-to-digital conversion circuit includes: a second capacitor array connected to the second-stage amplifier and configured to sample the second amplified signal; a second comparator connected to the second capacitor array and configured to compare the second amplified signal and output a second comparison result; and a second logic control circuit connected to the second capacitor array and the second comparator and configured to perform logic control on the second capacitor array based on the second comparison result and output a second digital signal.

21. An analog-to-digital converter as claimed in any one of claims 2 to 18, characterized in that Further comprising: an output circuit connected to the first-stage analog-to-digital conversion circuit and the second-stage analog-to-digital conversion circuit and configured to obtain an analog-to-digital conversion result of the input signal based on the first digital signal and the second digital signal.

22. A chip, characterized by The analog-to-digital converter includes any one of claims 1-21.

23. A method of analog-to-digital conversion control, the method comprising: Further comprising: An inter-stage amplifier is arranged between at least two adjacent stages of analog-to-digital conversion circuits of an analog-to-digital converter, the inter-stage amplifier comprising at least two amplifiers in cascade, the at least two amplifiers comprising a first-stage amplifier and a second-stage amplifier, the first-stage amplifier and the second-stage amplifier each being configured to amplify a signal, the first-stage amplifier having a bandwidth greater than that of the second-stage amplifier, and at least one of the first-stage amplifier and the second-stage amplifier being a passive amplifier.

24. The analog-to-digital conversion control method of claim 23, wherein, The adjacent two stages of analog-to-digital conversion circuits comprise a first-stage analog-to-digital conversion circuit and a second-stage analog-to-digital conversion circuit, and the analog-to-digital conversion control method further comprises: controlling the first-stage analog-to-digital conversion circuit to sample an input signal, to analog-to-digital convert the input signal to obtain a first digital signal and a residual voltage signal, and to hold the residual voltage signal; controlling the first-stage amplifier to amplify the residual voltage signal to obtain a first amplified signal; controlling the second-stage amplifier to sequentially sample and amplify the first amplified signal to obtain a second amplified signal; controlling the second-stage analog-to-digital conversion circuit to sequentially sample and analog-to-digital convert the second amplified signal to obtain a second digital signal; and obtaining an analog-to-digital conversion result of the input signal according to the first digital signal and the second digital signal.

25. The analog-to-digital conversion control method according to claim 24, wherein: the second-stage amplifier is an active amplifier, and when controlling the second-stage analog-to-digital conversion circuit to sequentially sample and analog-to-digital convert the second amplified signal, the first-stage analog-to-digital conversion circuit is synchronously controlled to sample and analog-to-digital convert the input signal next time.

26. The analog-to-digital conversion control method according to claim 24, wherein: the second-stage amplifier is a passive amplifier, and when controlling the first-stage analog-to-digital conversion circuit to hold the residual voltage signal, the second-stage analog-to-digital conversion circuit is synchronously controlled to sample the second amplified signal; when controlling the second-stage analog-to-digital conversion circuit to analog-to-digital convert the second amplified signal, the first-stage analog-to-digital conversion circuit is synchronously controlled to sample and analog-to-digital convert the input signal next time.

27. The analog-to-digital conversion control method according to any one of claims 24 to 26, wherein: when controlling the first-stage analog-to-digital conversion circuit to hold the residual voltage signal, the first-stage amplifier is synchronously controlled to amplify the residual voltage signal.

28. The analog-to-digital conversion control method according to claim 27, wherein: when controlling the first-stage amplifier to amplify the residual voltage signal, the second-stage amplifier is synchronously controlled to sample the first amplified signal.

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