Inter-symbol interference compensation circuit and modulator for Sigma-Delta modulator

Abstract

The present invention provides an inter-symbol interference compensation circuit and a modulator for a Sigma-Delta modulator. A current-steering DAC unit circuit receives a positive input terminal voltage and a negative input terminal voltage of an integrator, and generates an inter-symbol interference current through parasitic capacitors Cp and Cn; PMOS transmission tubes Mp3 and Mp4 receive the positive input terminal voltage and the negative input terminal voltage of the integrator, and transmit them to a fully differential common-source operational amplifier circuit; the fully differential common-source operational amplifier circuit detects the voltage difference between the positive input terminal voltage and the negative input terminal voltage transmitted by the PMOS transmission tubes Mp3 and Mp4, amplifies the voltage difference by two times, and then generates a compensation current with the same magnitude and opposite direction as the inter-symbol interference current through capacitors Ccp and Ccn, and feeds it back to the current-steering DAC unit circuit, thereby solving the inter-symbol interference problem of the DAC and improving the signal-to-noise ratio of the continuous-time Sigma-Delta modulator.

Description

Technical Field

[0001] The invention belongs to the technical field of broadband continuous-time Sigma-Delta modulators, and in particular relates to an inter-symbol interference compensation circuit for a Sigma-Delta modulator and a continuous-time Sigma-Delta modulator. Background Art

[0002] Analog-to-digital converters (ADCs) are the link between the real world dominated by analog signals and the powerful digital signal processing field in today's era, and have been widely used. Currently, ADCs are mainly divided into two categories: Nyquist ADCs and Sigma-Delta ADCs. Sigma-Delta ADCs use oversampling and noise shaping techniques, and the sampling frequency is much higher than twice the upper limit of the input signal bandwidth, that is, the Nyquist frequency, thereby achieving a good compromise between speed and accuracy. The basic structure of Sigma-Delta ADC consists of two parts: Sigma-Delta modulator and digital filter. The Sigma-Delta modulator completes the coarse quantization of the sampled signal, and shapes the spectrum of the quantization error to move the low-frequency component outside the modulator bandwidth. In addition, the anti-aliasing filtering function of the continuous-time Sigma-Delta modulator also reduces the requirements for the front-end anti-aliasing filter.

[0003] However, in actual Sigma-Delta modulators, since the DAC has different rise and fall times in different clock cycles, it causes additional delay errors and is directly fed back to the input of the modulator integrator without being shaped by the modulator loop, which seriously affects the performance of the modulator. For time-continuous Sigma-Delta modulators using NRZ DACs, the mismatch between its rise time and fall time will cause the area corresponding to one output code value to differ greatly from half of the area corresponding to two consecutive output code values. Therefore, the error generated in the feedback DAC depends on the modulator output sequence, which causes the modulator signal to be distorted, that is, inter-symbol interference. For example Figure 1 As shown in the figure, in the broadband continuous-time Sigma-Delta modulator, the existing implementation method is to use a return-to-zero (RZ) DAC. Although the rise and fall times of the RZ DAC response are different, the error remains constant within each clock cycle and is independent of the output sequence. The resulting error can be compensated by adjusting the modulator scaling factor. However, the RZ DAC has an increased sensitivity to clock jitter and a higher requirement for integrator linearity, which does not allow the modulator to achieve higher performance.

[0004] In summary, a new inter-symbol interference compensation circuit and a continuous-time Sigma-Delta modulator are urgently needed. Summary of the invention

[0005] In view of the problems existing in the prior art, the present invention provides an inter-symbol interference compensation circuit and a modulator for a Sigma-Delta modulator, which can generate a current opposite to the inter-symbol interference current, so as to solve the inter-symbol interference problem of DAC and improve the signal-to-noise ratio of the continuous-time Sigma-Delta modulator.

[0006] The present invention is achieved through the following technical solutions:

[0007] An inter-symbol interference compensation circuit for a Sigma-Delta modulator includes a current steering DAC unit circuit, PMOS transmission tubes Mp3 and Mp4, a fully differential common source operational amplifier circuit, and capacitors Ccp and Ccn; the capacitance of the capacitor Ccp is equal to the capacitance of the parasitic capacitor Cp in the current steering DAC unit circuit, and the capacitance of the capacitor Ccn is equal to the capacitance of the parasitic capacitor Cn in the current steering DAC unit circuit;

[0008] The current steering DAC unit circuit receives the positive input terminal voltage and the negative input terminal voltage of the integrator under the control of the output signals D and DN of the quantizer, and generates the inter-symbol interference current through the parasitic capacitors Cp and Cn;

[0009] The PMOS transmission tubes Mp3 and Mp4 are used to receive the positive input terminal voltage and the negative input terminal voltage of the integrator under the control of the output signals D and DN of the quantizer, and transmit them to the fully differential common source stage operational amplifier circuit;

[0010] The fully differential common-source operational amplifier circuit is used to detect the voltage difference between the positive input terminal voltage and the negative input terminal voltage transmitted by the PMOS transmission tubes Mp3 and Mp4, and amplify the voltage difference by two times, and then generate a compensation current equal to the inter-code interference current in magnitude and opposite direction through capacitors Ccp and Ccn to feed back to the current steering DAC unit circuit.

[0011] Preferably, the fully differential common-source operational amplifier circuit includes differential input pair transistors Mn4 and Mn5; the source of the PMOS transmission transistor Mp3 receives the negative input terminal of the integrator, the gate is connected to the output signal DN of the 4-bit quantizer Q1, and the drain is connected to the gate of the differential input pair transistor Mn4; the source of the PMOS transmission transistor Mp4 is connected to the positive input terminal Vsp of the integrator, the gate is connected to the output signal D of the 4-bit quantizer Q1, and the drain is connected to the gate of the differential input pair transistor Mn5; the drain of the differential input pair transistor Mn4 is connected to one end of the capacitor Ccp, and the source is connected to the source of the differential input pair transistor Mn5; the drain of the differential input pair transistor Mn5 is connected to one end of the capacitor Ccn.

[0012] Further, the current steering DAC unit circuit includes differential input pair transistors Mn1, Mn2, Mp1 and Mp2, parasitic capacitors Cp and Cn;

[0013] The gate of the differential input pair tube Mn1 is connected to the output signal DN of the 4-bit quantizer Q1, the drain is connected to the positive input terminal of the integrator, the source is connected to the source of the differential input pair tube Mn2, one end of the parasitic capacitor Cn and the other end of the capacitor Ccn, and the other end of the parasitic capacitor Cn is grounded to Vss; the gate of the differential input pair tube Mn2 is connected to the output signal D of the 4-bit quantizer Q1, and the drain is connected to the negative input terminal of the integrator; the gate of the differential input pair tube Mp1 is connected to the output signal D of the 4-bit quantizer Q1, the drain is connected to the positive input terminal of the integrator, the source is connected to the source of the differential input pair tube Mp2, one end of the parasitic capacitor Cp and the other end of the capacitor Ccp, and the other end of the parasitic capacitor Cp is connected to the power supply Vdd; the gate of the differential input pair tube Mp2 is connected to the output signal DN of the 4-bit quantizer Q1, and the drain is connected to the negative input terminal of the integrator.

[0014] Furthermore, it also includes a current source Icellp and a current source Icelln, the source of the differential input pair of tubes Mp1 and Mp2 is connected to the current source Icellp, and the source of the differential input pair of tubes Mn1 and Mn2 is connected to the current source Icelln.

[0015] Furthermore, it also includes a current source Icell; the current input end of the current source Icell is connected to the source of the differential input pair of tubes Mn4 and Mn5, and the current output end is grounded Vss.

[0016] Furthermore, it also includes load resistors R1 and R2, the drain of the differential input pair tube Mn4 is connected to one end of the load resistor R1, and the other end of the resistor R1 is connected to the power supply Vdd; the drain of the differential input pair tube Mn5 is connected to one end of the load resistor R2, and the other end of the resistor R2 is connected to the power supply Vdd.

[0017] A modulator comprises the inter-symbol interference compensation circuit.

[0018] Preferably, the modulator comprises: integrator 1, integrator 2, integrator 3, 4-bit quantizer Q1, non-return-to-zero DAC circuit DAC1, non-return-to-zero DAC circuit DAC2, non-return-to-zero DAC circuit DAC3, loop delay compensation circuit E1, loop delay compensation circuit E2, inter-symbol interference compensation circuit D1, inter-symbol interference compensation circuit D2 and inter-symbol interference compensation circuit D3; inter-symbol interference compensation circuit D1, inter-symbol interference compensation circuit D2 and inter-symbol interference compensation circuit D3 are all the above-mentioned inter-symbol interference compensation circuits;

[0019] The output end of the integrator 1 is connected to the input end of the integrator 2, the output end of the integrator 2 is connected to the input end of the integrator 3 and the output ends of the non-return-to-zero DAC circuit DAC2, the non-return-to-zero DAC circuit DAC3, the inter-symbol interference compensation circuit D2 and the inter-symbol interference compensation circuit D3, the output end of the integrator 3 is connected to the input end of the 4-bit quantizer Q1, the output end of the 4-bit quantizer Q1 is connected to the input end of the loop delay compensation circuit E1, the output end of the loop delay compensation circuit E1 is connected to the input ends of the loop delay compensation circuit E2, the non-return-to-zero DAC circuit DAC1, the non-return-to-zero DAC circuit DAC2, the inter-symbol interference compensation circuit D1 and the inter-symbol interference compensation circuit D2; the output end of the loop delay compensation circuit E2 is connected to the input ends of the non-return-to-zero DAC circuit DAC3 and the inter-symbol interference compensation circuit D3; the output ends of the non-return-to-zero DAC circuit DAC1 and the inter-symbol interference compensation circuit D1 are connected to the input end of the integrator 1.

[0020] Preferably, the integrator 1 comprises integrating resistors R11 and R12, integrating capacitors C11 and C12, tuning resistors Rs11 and Rs12 and an operational amplifier OP1; the output end of the integrating resistor R11 is connected to the positive input end of the operational amplifier OP1, the output end of the integrating resistor R12 is connected to the negative input end of the operational amplifier OP1, the input end of the integrating capacitor C11 is connected to the positive input end of the operational amplifier OP1, the output end of the integrating capacitor C11 is connected to the input end of the tuning resistor Rs11, and the output end of the tuning resistor Rs11 is connected to the negative output end of the operational amplifier OP1; the input end of the integrating capacitor C12 is connected to the negative input end of the operational amplifier OP1, the output end of the integrating capacitor C12 is connected to the input end of the tuning resistor Rs12, and the output end of the tuning resistor Rs12 is connected to the positive output end of the operational amplifier OP1;

[0021] Integrator 2 includes integrating resistors R21 and R22, integrating capacitors C21 and C22, tuning resistors Rs21 and Rs22 and operational amplifier OP2; the input end of integrating resistor R21 is connected to the positive output end of operational amplifier OP1, the output end of integrating resistor R21 is connected to the positive input end of operational amplifier OP2, the input end of integrating resistor R22 is connected to the negative output end of operational amplifier OP1, the output end of integrating resistor R21 is connected to the negative input end of operational amplifier OP2, and the output end of integrating resistor R22 is connected to the negative input end of operational amplifier OP2. The input end of the integrating capacitor C22 is connected to the negative input end of the operational amplifier OP2, the input end of the integrating capacitor C21 is connected to the positive input end of the operational amplifier OP2, the output end of the integrating capacitor C21 is connected to the input end of the tuning resistor Rs21, and the output end of the tuning resistor Rs21 is connected to the negative output end of the operational amplifier OP2; the input end of the integrating capacitor C22 is connected to the negative input end of the operational amplifier OP2, the output end of the integrating capacitor C22 is connected to the input end of the tuning resistor Rs22, and the output end of the tuning resistor Rs22 is connected to the positive output end of the operational amplifier OP2;

[0022] The integrator 3 comprises integrating resistors R31 and R32, integrating capacitors C31 and C32, tuning resistors Rs31 and Rs32 and an operational amplifier OP3; the input end of the integrating resistor R31 is connected to the positive output end of the operational amplifier OP2, the output end of the integrating resistor R31 is connected to the positive input end of the operational amplifier OP3, the input end of the integrating resistor R32 is connected to the negative output end of the operational amplifier OP2, the output end of the integrating resistor R32 is connected to the negative input end of the operational amplifier OP3, the input end of the integrating capacitor C31 is connected to the positive input end of the operational amplifier OP3, the output end of the integrating capacitor C31 is connected to the input end of the tuning resistor Rs31, and the output end of the tuning resistor Rs31 is connected to the negative output end of the operational amplifier OP3; the input end of the integrating capacitor C32 is connected to the negative input end of the operational amplifier OP3, the output end of the integrating capacitor C32 is connected to the input end of the tuning resistor Rs32, and the output end of the tuning resistor Rs32 is connected to the positive output end of the operational amplifier OP3.

[0023] Furthermore, it also includes feedforward resistors Rf1, Rf2 and feedback resistors Rz1 and Rz2; the input end of the feedforward resistor Rf1 is connected to the positive output end of the operational amplifier OP1, and the output end of the feedforward resistor Rf1 is connected to the positive input end of the operational amplifier OP3; the input end of the feedforward resistor Rf2 is connected to the negative output end of the operational amplifier OP1, and the output end of the feedforward resistor Rf1 is connected to the negative input end of the operational amplifier OP3; the input end of the feedback resistor Rz1 is connected to the positive input end of the operational amplifier OP2, and the output end of the feedback resistor Rz1 is connected to the negative input end of the operational amplifier OP3; the input end of the feedback resistor Rz2 is connected to the negative input end of the operational amplifier OP2, and the output end of the feedback resistor Rz2 is connected to the positive output end of the operational amplifier OP3.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] In the present invention, the positive input terminal voltage Vsp and the negative input terminal voltage Vsn of the current steering DAC unit circuit generate offset voltages ΔVsp and ΔVsn due to the non-ideality of the integrator, causing Vcp and Vcn to generate offset voltages ΔVcp=ΔVsp and ΔVcn=ΔVsp, and then generate inter-symbol interference current IISI=Cp[d(-ΔVcp) / dt] through parasitic capacitors Cp and Cn. The present invention controls PMOS transmission tubes Mp3 and Mp4 through output signals D and DN of a quantizer, transmits a voltage signal Vsp of a positive input terminal and a voltage signal Vsn of a negative input terminal of an integrator to a fully differential common source operational amplifier circuit, and the fully differential common source operational amplifier circuit is used to detect a voltage difference between a voltage Vsp of a positive input terminal and a voltage Vsn of a negative input terminal, and amplifies the voltage difference ΔVsp to 2ΔVsp=2ΔVcp, and then generates a compensation current Icp=Ccp[d(ΔVcp-2ΔVcp) / dt] with the same magnitude and opposite direction as the inter-symbol interference current through capacitors Ccp and Ccn, and feeds it back to a current steering type DAC unit circuit, thereby compensating for an inter-symbol interference current IISI=Cp[d(-ΔVcp) / dt] generated by offset voltages ΔVcp and ΔVcn due to the non-ideality of the integrator through parasitic capacitors Cp and Cn. The circuit improves the matching of Icp and IISI by setting Ccp=Cp, Ccn=Cn and increasing the gain-bandwidth product of the fully differential common-source operational amplifier circuit, eliminates the error generated by the feedback DAC, suppresses the signal distortion of the modulator, and improves the signal-to-noise ratio.

[0026] Furthermore, a current source Icellp and a current source Icelln are provided to control the operating current of the differential input pair tubes Mn1 , Mn2 , Mp1 and Mp2 .

[0027] Furthermore, the current source Icell is used to provide an operating current for the fully differential common-source operational amplifier.

[0028] Furthermore, the load resistors R1 and R2 are used to superimpose the current signals generated by the fully differential common-source operational amplifier circuit, convert them into voltage signals, and output them.

[0029] The continuous-time Sigma-Delta modulator of the present invention adopts the inter-symbol interference compensation circuit of the present invention, which can offset the inter-symbol interference current and improve the signal-to-noise ratio of the modulator system.

[0030] Furthermore, due to the limited gain bandwidth of the operational amplifier in the integrator, the unit gain frequency of the operational amplifier is reduced, which changes the zero point and noise transfer function of the modulator system, seriously affecting the signal-to-noise ratio of the modulator. For this reason, the present invention adds tuning resistors Rs11, Rs12, Rs21, Rs22, Rs31 and Rs32 in parallel with the integrating capacitor in the integrator, and by setting appropriate resistance values, the zero point of the integrator system can be offset, thereby optimizing the noise transfer function of the modulator. Compared with the traditional structure (such as Figure 1 ), further improving the signal-to-noise ratio of the modulator system. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a schematic diagram of the circuit structure of the existing continuous-time Sigma-Delta modulator structure and the use of RZ DAC to compensate for inter-symbol interference;

[0032] Figure 2 1 is a schematic diagram of the circuit structure of a continuous-time Sigma-Delta modulator with an inter-symbol interference compensation circuit in an embodiment of the present invention;

[0033] Figure 3 This is the inter-symbol interference compensation circuit in the present invention. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical effect and technical solution of the embodiment of the present invention clearer, the technical solution in the embodiment of the present invention is clearly and completely described below in combination with the drawings in the embodiment of the present invention; it is obvious that the described embodiment is a part of the embodiment of the present invention. Based on the embodiments disclosed in the present invention, other embodiments obtained by ordinary technicians in this field without making creative work should belong to the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be the usual meanings understood by people with general skills in the field to which the present invention belongs. The words "including" and similar words used in this article mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0035] See also Figure 2 According to an embodiment of the present invention, a continuous-time Sigma-Delta modulator with an inter-symbol interference compensation circuit includes three integrators, a 4-bit quantizer Q1, two feedforward resistors Rf1 and Rf2, two feedback resistors Rz1 and Rz2, three non-return-to-zero (NRZ) DAC circuits, two loop delay compensation circuits, and three inter-symbol interference compensation circuits.

[0036] The output end of integrator 1 is connected to the input end of integrator 2, and the output end of integrator 2 is connected to the input end of integrator 3. Each integrator includes its own operational amplifier OP, an integrating resistor, an integrating capacitor and a tuning resistor. Integrator 1 is composed of integrating resistors R11 and R12, integrating capacitors C11 and C12, tuning resistors Rs11 and Rs12 and operational amplifier OP1; the output end of integrating resistor R11 is connected to the positive input end of operational amplifier OP1, the output end of integrating resistor R12 is connected to the negative input end of operational amplifier OP1, the input end of integrating capacitor C11 is connected to the positive input end of operational amplifier OP1, the output end of integrating capacitor C11 is connected to the input end of tuning resistor Rs11, and the output end of tuning resistor Rs11 is connected to the negative output end of operational amplifier OP1; the input end of integrating capacitor C12 is connected to the negative input end of operational amplifier OP1, the output end of integrating capacitor C12 is connected to the input end of tuning resistor Rs12, and the output end of tuning resistor Rs12 is connected to the positive output end of operational amplifier OP1. Similarly, integrator 2 is composed of integrating resistors R21 and R22, integrating capacitors C21 and C22, tuning resistors Rs21 and Rs22 and operational amplifier OP2; the input end of integrating resistor R21 is connected to the positive output end of operational amplifier OP1, the output end of integrating resistor R21 is connected to the positive input end of operational amplifier OP2, the input end of integrating resistor R22 is connected to the negative output end of operational amplifier OP1, the output end of integrating resistor R21 is connected to the negative input end of operational amplifier OP2, and the output end of integrating resistor R22 is connected to the negative input end of operational amplifier OP1. The negative input terminal of the operational amplifier OP2 is connected to the input terminal of the integrating capacitor C21, the positive input terminal of the operational amplifier OP2, the output terminal of the integrating capacitor C21 is connected to the input terminal of the tuning resistor Rs21, and the output terminal of the tuning resistor Rs21 is connected to the negative output terminal of the operational amplifier OP2; the input terminal of the integrating capacitor C22 is connected to the negative input terminal of the operational amplifier OP2, the output terminal of the integrating capacitor C22 is connected to the input terminal of the tuning resistor Rs22, and the output terminal of the tuning resistor Rs22 is connected to the positive output terminal of the operational amplifier OP2. Similarly, the integrator 3 is composed of integrating resistors R31 and R32, integrating capacitors C31 and C32, tuning resistors Rs31 and Rs32 and an operational amplifier OP3; the input end of the integrating resistor R31 is connected to the positive output end of the operational amplifier OP2, the output end of the integrating resistor R31 is connected to the positive input end of the operational amplifier OP3, the input end of the integrating resistor R32 is connected to the negative output end of the operational amplifier OP2, the output end of the integrating resistor R32 is connected to the negative input end of the operational amplifier OP3, the input end of the integrating capacitor C31 is connected to the positive input end of the operational amplifier OP3, the output end of the integrating capacitor C31 is connected to the input end of the tuning resistor Rs31, and the output end of the tuning resistor Rs31 is connected to the negative output end of the operational amplifier OP3; the input end of the integrating capacitor C32 is connected to the negative input end of the operational amplifier OP3, the output end of the integrating capacitor C32 is connected to the input end of the tuning resistor Rs32, and the output end of the tuning resistor Rs32 is connected to the positive output end of the operational amplifier OP3.

[0037] The input end of the integrator 3 is connected to the output ends of the non-return-to-zero (NRZ) DAC circuit DAC2, the non-return-to-zero (NRZ) DAC circuit DAC3, the inter-symbol interference compensation circuit D2 and the inter-symbol interference compensation circuit D3; the output end of the integrator 3 is connected to the input end of the 4-bit quantizer Q1, the output end of the 4-bit quantizer Q1 is connected to the input end of the loop delay compensation circuit E1, the output end of the loop delay compensation circuit E1 is connected to the input ends of the loop delay compensation circuit E2, the non-return-to-zero (NRZ) DAC circuit DAC1, the non-return-to-zero (NRZ) DAC circuit DAC2, the inter-symbol interference compensation circuit D1 and the inter-symbol interference compensation circuit D2; the output end of the loop delay compensation circuit E2 is connected to the input ends of the non-return-to-zero (NRZ) DAC circuit DAC3 and the inter-symbol interference compensation circuit D3; the output ends of the non-return-to-zero (NRZ) DAC circuit DAC3 and the inter-symbol interference compensation circuit D3 are connected to the integrator 2, the non-return-to-zero (NRZ) The output end of the DAC circuit DAC2 and the inter-symbol interference compensation circuit D2 and the input end of the integrator 3 are connected; the output end of the non-return-to-zero (NRZ) DAC circuit DAC1 and the inter-symbol interference compensation circuit D1 are connected to the input end of the integrator 1; the input end of the feed-forward resistor Rf1 is connected to the positive output end of the operational amplifier OP1, and the output end of the feed-forward resistor Rf1 is connected to the positive input end of the operational amplifier OP3; the input end of the feed-forward resistor Rf2 is connected to the negative output end of the operational amplifier OP1, and the output end of the feed-forward resistor Rf1 is connected to the negative input end of the operational amplifier OP3; the input end of the feedback resistor Rz1 is connected to the positive input end of the operational amplifier OP2, and the output end of the feedback resistor Rz1 is connected to the negative input end of the operational amplifier OP3; the input end of the feedback resistor Rz2 is connected to the negative input end of the operational amplifier OP2, and the output end of the feedback resistor Rz2 is connected to the positive output end of the operational amplifier OP3, forming a continuous-time Sigma-Delta modulator loop.

[0038] The 4-bit quantizer Q1 converts the analog signal output by the integrator 3 into a digital signal through quantization. After the digital signal output by the 4-bit quantizer Q1 is delayed by the loop delay compensation circuit E1, the signal of the first path is converted into an analog signal through DAC1 and the inter-symbol interference compensation circuit D1 and fed back to the input end of the integrator 1; the signal of the second path is converted into an analog signal through DAC2 and the inter-symbol interference compensation circuit D2 and fed back to the input end of the integrator 3; the signal of the third path is delayed by the loop delay compensation circuit E2, and converted into an analog signal through DAC3 and the inter-symbol interference compensation circuit D3 and fed back to the input end of the integrator 3. The integrating resistors R11 and R12 are equal, R21 and R22 are equal, R31 and R32 are equal, the integrating capacitors C11, C12, C21, C22, C31 and C32 are all equal, the tuning resistors Rs11 and Rs12 are equal, Rs21 and Rs22 are equal, Rs31 and Rs32 are equal, the feedforward resistors Rf1 and Rf2 are equal, and the feedback resistors Rz1 and Rz2 are equal.

[0039] See also Figure 3 The inter-symbol interference compensation circuit of the present invention comprises a basic current steering type DAC unit circuit composed of differential input pair tubes Mn1, Mn2, Mp1 and Mp2 and parasitic capacitors Cp and Cn, current sources Icellp and Icelln, PMOS transmission tubes Mp3 and Mp4, a fully differential common source stage operational amplifier circuit composed of current source Icell, differential input pair tubes Mn4 and Mn5, load resistors R1 and R2, capacitors Ccp and Ccn, connected to the Sigma-Delta modulator loop. The capacitance Ccp is equal to the capacitance value of the parasitic capacitor Cp in the current steering type DAC unit circuit, and the capacitance Ccn is equal to the capacitance value of the parasitic capacitor Cn in the current steering type DAC unit circuit.

[0040] The gate of the current steering DAC unit circuit Mn1 is connected to the output signal DN of the 4-bit quantizer Q1, the drain is connected to the positive input terminal Vsp of the integrator, the source is connected to the source of the differential input pair tube Mn2, one end of the parasitic capacitor Cn and the current source Icelln, and the current of the integrator is extracted under the control of the output signal DN of the 4-bit quantizer Q1; the gate of Mn2 is connected to the output signal D of the 4-bit quantizer Q1, the drain is connected to the negative input terminal Vsn of the integrator, and the source is connected to the current source Icelln, and the current of the integrator is extracted under the control of the output signal D of the 4-bit quantizer Q1 Extract the current of the integrator; the gate of Mp1 is connected to the output signal D of the 4-bit quantizer Q1, the drain is connected to the positive input terminal Vsp of the integrator, the source is connected to the source of Mp2, one end of the parasitic capacitor Cp and the current source Icellp, and the current of the integrator is extracted under the control of the output signal D of the 4-bit quantizer Q1; the gate of Mp2 is connected to the output signal DN of the 4-bit quantizer Q1, the drain is connected to the negative input terminal Vsn of the integrator, and the source is connected to the current source Icellp, and the current of the integrator is extracted under the control of the output signal DN of the 4-bit quantizer Q1. The current steering DAC unit circuit is used to feed back the output signals D and DN of the 4-bit quantizer Q1 to the input terminals Vsp and Vsn of the integrator.

[0041] One end of the current source Icellp is connected to the power supply Vdd, and the other end is connected to the source of the differential input pair tubes Mp1 and Mp2; one end of the current source Icelln is grounded to Vss, and the other end is connected to the source of the differential input pair tubes Mn1 and Mn2. The current sources Icellp and Icelln are used to control the working current of the corresponding differential input pair tubes Mn1, Mn2, Mp1 and Mp2.

[0042] The source of the PMOS transmission tube Mp3 receives the negative input terminal of the integrator, the gate is connected to the output signal DN of the 4-bit quantizer Q1, and the drain is connected to the gate of the differential input pair tube Mn4; the source of the PMOS transmission tube Mp4 is connected to the positive input terminal Vsp of the integrator, the gate is connected to the output signal D of the 4-bit quantizer Q1, and the drain is connected to the gate of the differential input pair tube Mn5. The PMOS transmission tube Mp3 receives the voltage signal of the negative input terminal Vsn of the integrator, and transmits it to the gate of the differential input pair tube Mn4 under the control of the output signal DN of the 4-bit quantizer Q1; the PMOS transmission tube Mp4 receives the voltage signal of the positive input terminal Vsp of the integrator, and transmits it to the gate of the differential input pair tube Mn5 under the control of the output signal D of the 4-bit quantizer Q1. The PMOS transmission tubes Mp3 and Mp4 are used to transmit the voltage signals of the input terminals Vsp and Vsn of the integrator to the differential input pair tubes Mn4 and Mn5 of the fully differential common source stage operational amplifier.

[0043] The gate of the differential input pair tube Mn4 in the fully differential common source operational amplifier circuit is connected to the drain of the PMOS transmission tube Mp3, the drain of the differential input pair tube Mn4 is connected to the load resistor R1, and the source of the differential input pair tube Mn4 is connected to the drain of the current source Icell; the gate of Mn5 is connected to the drain of the PMOS transmission tube Mp4, the drain of the differential input pair tube Mn5 is connected to the load resistor R2, and the source of the differential input pair tube Mn5 is connected to the drain of the current source Icell; the current input end of the current source Icell is connected to the source of the differential input pair tubes Mn4 and Mn5, and the current output end of the current source Icell is grounded to Vss, which is used to provide the working current of the fully differential common source operational amplifier. The fully differential common source operational amplifier circuit is used to detect the difference between the voltages Vsp and Vsn transmitted by the PMOS transmission tubes Mp3 and Mp4, and amplify the voltage difference by two times, and then generate a compensation current equal to the inter-code interference current and opposite in direction through the capacitors Ccp and Ccn to feedback to the current steering type DAC unit circuit.

[0044] One end of the load resistor R1 is connected to the power supply Vdd, and the other end is connected to the drain of the differential input pair tube Mn4; one end of the load resistor R2 is connected to the power supply Vdd, and the other end is connected to the drain of the differential input pair tube Mn5. Load resistors R1 and R2 are used to superimpose the current signal generated by the fully differential common source operational amplifier circuit, convert it into a voltage signal and output it.

[0045] One end of capacitor Ccp is connected to the sources of Mp1 and Mp2 in the current-steering DAC unit circuit, and the other end is connected to the drain of Mn4 in the fully differential common-source operational amplifier; one end of capacitor Ccn is connected to the sources of Mn1 and Mn2 in the current-steering DAC unit circuit, and the other end is connected to the drain of Mn5 in the fully differential common-source operational amplifier.

[0046] One end of the parasitic capacitor Cp is connected to the source of Mp1 and Mp2 in the current steering DAC unit circuit, and the other end is connected to the power supply Vdd; one end of the parasitic capacitor Cn is connected to the source of Mn1 and Mn2 in the current steering DAC unit circuit, and the other end is grounded Vss. The output signal D of the 4-bit quantizer Q1 is connected to the gates of Mp1, Mn2 and PMOS transmission tube Mp4 in the current steering DAC unit circuit; the output signal DN of the 4-bit quantizer Q1 is connected to the gates of Mn1, Mp2 and PMOS transmission tube Mp3 in the current steering DAC unit circuit. The output signals D and DN of the 4-bit quantizer Q1 are used to control the conduction of the current signals generated by the differential input pair tubes Mn1, Mn2, Mp1 and Mp2 and the PMOS transmission tubes Mp3 and Mp4 in the current steering DAC unit circuit.

[0047] The principle of the present invention is as follows: the present invention first controls PMOS transmission tubes Mp3 and Mp4 through the output signals D and DN of the quantizer, and transmits the voltage signal Vsp of the positive input terminal and the voltage signal Vsn of the negative input terminal of the integrator to the fully differential common source operational amplifier circuit. The fully differential common source operational amplifier circuit is used to detect the difference between the positive input terminal voltage Vsp and the negative input terminal voltage Vsn, and amplify the voltage difference ΔVsp to 2ΔVsp=2ΔVcp, and then generate a compensation current Icp=Ccp[d(ΔVcp-2ΔVcp) / dt] with the same magnitude and opposite direction as the inter-symbol interference current through capacitors Ccp and Ccn, which is fed back to the current steering type DAC unit circuit, thereby compensating for the inter-symbol interference current IISI=Cp[d(-ΔVcp) / dt] generated by the offset voltage ΔVcp and ΔVcn generated by the non-ideality of the integrator through parasitic capacitors Cp and Cn. The circuit improves the matching of Icp and IISI by setting Ccp=Cp, Ccn=Cn and increasing the gain-bandwidth product of the fully differential common-source operational amplifier circuit, thereby eliminating the error generated by the feedback DAC and suppressing the signal distortion of the modulator.

[0048] At the same time, tuning resistors Rs11, Rs12, Rs21, Rs22, Rs31 and Rs32 are added in parallel with the integrating capacitor in the integrator. By setting appropriate resistance values, the zero point of the integrator system can be offset, the noise transfer function of the modulator is optimized, and the signal-to-noise ratio of the modulator system is further improved.

[0049] The present invention studies the existing continuous-time Sigma-Delta modulator technology and proposes an inter-symbol interference delay compensation circuit and a continuous-time Sigma-Delta modulator structure, which eliminates the error generated by the feedback DAC, suppresses the signal distortion of the modulator, and optimizes the noise transfer function of the modulator, further improving the signal-to-noise ratio of the modulator system.

[0050] In summary, the present invention studies the DAC inter-symbol interference problem and the continuous-time Sigma-Delta modulator structure for a continuous-time Sigma-Delta modulator, and discloses an inter-symbol interference delay compensation circuit and a continuous-time Sigma-Delta modulator structure based on the compensation circuit. The inter-symbol interference compensation circuit proposed in the present invention improves the traditional continuous-time Sigma-Delta modulator structure, solves the inter-symbol interference problem, and improves the performance of the continuous-time Sigma-Delta modulator.

[0051] The above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit the same. Although the present invention has been described in detail with reference to the above embodiments, a person skilled in the art can still modify or make equivalent substitutions to the specific implementations of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention are within the scope of protection of the claims of the present invention to be approved.

Claims

1. An inter-symbol interference compensation circuit for a Sigma-Delta modulator, characterized in that: It includes a current steering type DAC unit circuit, PMOS transmission tubes Mp3 and Mp4, a fully differential common source operational amplifier circuit, and capacitors Ccp and Ccn; the capacitance Ccp is equal to the capacitance value of the parasitic capacitance Cp in the current steering type DAC unit circuit, and the capacitance Ccn is equal to the capacitance value of the parasitic capacitance Cn in the current steering type DAC unit circuit; The current steering DAC unit circuit receives the positive input terminal voltage and the negative input terminal voltage of the integrator under the control of the output signals D and DN of the quantizer, and generates the inter-symbol interference current through the parasitic capacitors Cp and Cn; The PMOS transmission tubes Mp3 and Mp4 are used to receive the positive input terminal voltage and the negative input terminal voltage of the integrator under the control of the output signals D and DN of the quantizer, and transmit them to the fully differential common source stage operational amplifier circuit; The fully differential common-source operational amplifier circuit is used to detect the voltage difference between the positive input terminal voltage and the negative input terminal voltage transmitted by the PMOS transmission tubes Mp3 and Mp4, and amplify the voltage difference by two times, and then generate a compensation current equal to the inter-symbol interference current in magnitude and opposite in direction through the capacitors Ccp and Ccn to feed back to the current steering DAC unit circuit; The fully differential common-source operational amplifier circuit includes differential input pair transistors Mn4 and Mn5; the source of the PMOS transmission transistor Mp3 receives the negative input terminal of the integrator, the gate is connected to the output signal DN of the 4-bit quantizer Q1, and the drain is connected to the gate of the differential input pair transistor Mn4; the source of the PMOS transmission transistor Mp4 is connected to the positive input terminal Vsp of the integrator, the gate is connected to the output signal D of the 4-bit quantizer Q1, and the drain is connected to the gate of the differential input pair transistor Mn5; the drain of the differential input pair transistor Mn4 is connected to one end of the capacitor Ccp, and the source is connected to the source of the differential input pair transistor Mn5; the drain of the differential input pair transistor Mn5 is connected to one end of the capacitor Ccn.

2. The inter-symbol interference compensation circuit for Sigma-Delta modulator according to claim 1, characterized in that: The current steering DAC unit circuit includes differential input pair tubes Mn1, Mn2, Mp1 and Mp2, parasitic capacitors Cp and Cn; The gate of the differential input pair tube Mn1 is connected to the output signal DN of the 4-bit quantizer Q1, the drain is connected to the positive input terminal of the integrator, the source is connected to the source of the differential input pair tube Mn2, one end of the parasitic capacitor Cn and the other end of the capacitor Ccn, and the other end of the parasitic capacitor Cn is grounded to Vss; the gate of the differential input pair tube Mn2 is connected to the output signal D of the 4-bit quantizer Q1, and the drain is connected to the negative input terminal of the integrator; the gate of the differential input pair tube Mp1 is connected to the output signal D of the 4-bit quantizer Q1, the drain is connected to the positive input terminal of the integrator, the source is connected to the source of the differential input pair tube Mp2, one end of the parasitic capacitor Cp and the other end of the capacitor Ccp, and the other end of the parasitic capacitor Cp is connected to the power supply Vdd; the gate of the differential input pair tube Mp2 is connected to the output signal DN of the 4-bit quantizer Q1, and the drain is connected to the negative input terminal of the integrator.

3. The inter-symbol interference compensation circuit for Sigma-Delta modulator according to claim 2, characterized in that: It also includes a current source Icellp and a current source Icelln. The source of the differential input pair of tubes Mp1 and Mp2 is connected to the current source Icellp, and the source of the differential input pair of tubes Mn1 and Mn2 is connected to the current source Icelln.

4. The inter-symbol interference compensation circuit for Sigma-Delta modulator according to claim 1, characterized in that: It also includes a current source Icell; the current input end of the current source Icell is connected to the source of the differential input pair of tubes Mn4 and Mn5, and the current output end is grounded to Vss.

5. The inter-symbol interference compensation circuit for Sigma-Delta modulator according to claim 1, characterized in that: It also includes load resistors R1 and R2. The drain of the differential input pair tube Mn4 is connected to one end of the load resistor R1, and the other end of the resistor R1 is connected to the power supply Vdd. The drain of the differential input pair tube Mn5 is connected to one end of the load resistor R2, and the other end of the resistor R2 is connected to the power supply Vdd.

6. A modulator, characterized in that The invention comprises the inter-symbol interference compensation circuit as described in any one of claims 1 to 5.

7. The modulator according to claim 6, characterized in that include: Integrator 1, integrator 2, integrator 3, 4-bit quantizer Q1, non-return-to-zero DAC circuit DAC1, non-return-to-zero DAC circuit DAC2, non-return-to-zero DAC circuit DAC3, loop delay compensation circuit E1, loop delay compensation circuit E2, inter-symbol interference compensation circuit D1, inter-symbol interference compensation circuit D2 and inter-symbol interference compensation circuit D3; inter-symbol interference compensation circuit D1, inter-symbol interference compensation circuit D2 and inter-symbol interference compensation circuit D3 are all inter-symbol interference compensation circuits according to any one of claims 1 to 6; The output end of the integrator 1 is connected to the input end of the integrator 2, the output end of the integrator 2 is connected to the input end of the integrator 3 and the output ends of the non-return-to-zero DAC circuit DAC2, the non-return-to-zero DAC circuit DAC3, the inter-symbol interference compensation circuit D2 and the inter-symbol interference compensation circuit D3, the output end of the integrator 3 is connected to the input end of the 4-bit quantizer Q1, the output end of the 4-bit quantizer Q1 is connected to the input end of the loop delay compensation circuit E1, the output end of the loop delay compensation circuit E1 is connected to the input ends of the loop delay compensation circuit E2, the non-return-to-zero DAC circuit DAC1, the non-return-to-zero DAC circuit DAC2, the inter-symbol interference compensation circuit D1 and the inter-symbol interference compensation circuit D2; the output end of the loop delay compensation circuit E2 is connected to the input ends of the non-return-to-zero DAC circuit DAC3 and the inter-symbol interference compensation circuit D3; the output ends of the non-return-to-zero DAC circuit DAC1 and the inter-symbol interference compensation circuit D1 are connected to the input end of the integrator 1.

8. The modulator according to claim 7, characterized in that The integrator 1 comprises integrating resistors R11 and R12, integrating capacitors C11 and C12, tuning resistors Rs11 and Rs12 and an operational amplifier OP1; the output end of the integrating resistor R11 is connected to the positive input end of the operational amplifier OP1, the output end of the integrating resistor R12 is connected to the negative input end of the operational amplifier OP1, the input end of the integrating capacitor C11 is connected to the positive input end of the operational amplifier OP1, the output end of the integrating capacitor C11 is connected to the input end of the tuning resistor Rs11, and the output end of the tuning resistor Rs11 is connected to the negative output end of the operational amplifier OP1; the input end of the integrating capacitor C12 is connected to the negative input end of the operational amplifier OP1, the output end of the integrating capacitor C12 is connected to the input end of the tuning resistor Rs12, and the output end of the tuning resistor Rs12 is connected to the positive output end of the operational amplifier OP1; Integrator 2 includes integrating resistors R21 and R22, integrating capacitors C21 and C22, tuning resistors Rs21 and Rs22 and operational amplifier OP2; the input end of integrating resistor R21 is connected to the positive output end of operational amplifier OP1, the output end of integrating resistor R21 is connected to the positive input end of operational amplifier OP2, the input end of integrating resistor R22 is connected to the negative output end of operational amplifier OP1, the output end of integrating resistor R21 is connected to the negative input end of operational amplifier OP2, and the output end of integrating resistor R22 is connected to the negative input end of operational amplifier OP2. The input end of the integrating capacitor C22 is connected to the negative input end of the operational amplifier OP2, the input end of the integrating capacitor C21 is connected to the positive input end of the operational amplifier OP2, the output end of the integrating capacitor C21 is connected to the input end of the tuning resistor Rs21, and the output end of the tuning resistor Rs21 is connected to the negative output end of the operational amplifier OP2; the input end of the integrating capacitor C22 is connected to the negative input end of the operational amplifier OP2, the output end of the integrating capacitor C22 is connected to the input end of the tuning resistor Rs22, and the output end of the tuning resistor Rs22 is connected to the positive output end of the operational amplifier OP2; The integrator 3 comprises integrating resistors R31 and R32, integrating capacitors C31 and C32, tuning resistors Rs31 and Rs32 and an operational amplifier OP3; the input end of the integrating resistor R31 is connected to the positive output end of the operational amplifier OP2, the output end of the integrating resistor R31 is connected to the positive input end of the operational amplifier OP3, the input end of the integrating resistor R32 is connected to the negative output end of the operational amplifier OP2, the output end of the integrating resistor R32 is connected to the negative input end of the operational amplifier OP3, the input end of the integrating capacitor C31 is connected to the positive input end of the operational amplifier OP3, the output end of the integrating capacitor C31 is connected to the input end of the tuning resistor Rs31, and the output end of the tuning resistor Rs31 is connected to the negative output end of the operational amplifier OP3; the input end of the integrating capacitor C32 is connected to the negative input end of the operational amplifier OP3, the output end of the integrating capacitor C32 is connected to the input end of the tuning resistor Rs32, and the output end of the tuning resistor Rs32 is connected to the positive output end of the operational amplifier OP3.

9. The modulator according to claim 8, characterized in that It also includes feedforward resistors Rf1, Rf2 and feedback resistors Rz1 and Rz2; the input end of the feedforward resistor Rf1 is connected to the positive output end of the operational amplifier OP1, and the output end of the feedforward resistor Rf1 is connected to the positive input end of the operational amplifier OP3; the input end of the feedforward resistor Rf2 is connected to the negative output end of the operational amplifier OP1, and the output end of the feedforward resistor Rf1 is connected to the negative input end of the operational amplifier OP3; the input end of the feedback resistor Rz1 is connected to the positive input end of the operational amplifier OP2, and the output end of the feedback resistor Rz1 is connected to the negative input end of the operational amplifier OP3; the input end of the feedback resistor Rz2 is connected to the negative input end of the operational amplifier OP2, and the output end of the feedback resistor Rz2 is connected to the positive output end of the operational amplifier OP3.

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