Offset cancellation circuit of current balance circuit

Abstract

The present invention relates to an offset cancellation circuit for a current balance circuit, and its purpose is to eliminate current imbalance caused by offset generated by component mismatch and PVT variations (P: process, V: voltage, T: temperature). The current balance circuit of the present invention includes: a first comparator section that forms a first offset voltage at two input terminals and inputs an offset cancellation voltage to any one of the input terminals; a second comparator section that forms a second offset voltage at two input terminals, inputs the output voltage of the first comparator section to any one of the input terminals, and inputs a reference voltage to the other input terminal; a third comparator section that forms a third offset voltage at two input terminals, inputs the output voltage of the second comparator section to any one of the input terminals, and uses the reference voltage as the other input terminal; and a control section that, during the calibration process, forms and outputs an offset cancellation voltage that increases with time, and outputs the offset cancellation voltage when the offset cancellation voltage is greater than the sum of the first offset voltage, the second offset voltage, and the third offset voltage.

Description

Technical Field

[0001] The present invention relates to an offset cancellation circuit for a current balancing circuit, and aims to eliminate current imbalance caused by offset generated by component mismatch and PVT variations (process, voltage, temperature). Background Art

[0002] A converter is a general term for a device that converts alternating current into direct current or raises or lowers a DC voltage. In particular, a DC-DC converter includes a boost converter that increases the input voltage and a buck converter that decreases the input voltage, and is often used not only in industry but also at home.

[0003] In these converters, switching elements are connected in series between a driving voltage and a reference voltage, and the current output from the node connecting the switching elements is supplied to a load through an inductor. Summary of the Invention

[0004] Technical Problem

[0005] The current output by a multiphase converter corresponds to the sum of the output currents of each phase. When the current output by each phase is evenly distributed, it has high efficiency. However, if the current is concentrated in any one phase, the load is concentrated in the driving circuit, resulting in reduced efficiency. Accordingly, a current balancing circuit is provided to prevent efficiency reduction caused by current concentration.

[0006] However, in the current balancing circuit, due to reasons such as component mismatch and PVT variations (process, voltage, temperature), offset inevitably occurs, and thus current balance may be broken. The present invention aims to solve the current imbalance that occurs as described above.

[0007] The present invention aims to solve the current imbalance that occurs as described above, and the technical problems to be solved by the present invention are not limited to the above technical problems, and other technical problems not mentioned will be clearly understood by those of ordinary skill in the art through the description of the present invention.

[0008] Technical Solution

[0009] The current balance circuit of the present invention includes: a first comparator unit that forms a first offset voltage at two input terminals and inputs an offset cancellation voltage to any one of the input terminals; a second comparator unit that forms a second offset voltage at two input terminals, inputs the output voltage of the first comparator unit to any one of the input terminals, and inputs a reference voltage to the other input terminal; a third comparator unit that forms a third offset voltage at two input terminals, inputs the output voltage of the second comparator unit to any one of the input terminals, and inputs a reference voltage to the other input terminal; and a control unit that, during the calibration process, forms and outputs an offset cancellation voltage that increases with time, and outputs the offset cancellation voltage when the offset cancellation voltage is greater than the sum of the first offset voltage, the second offset voltage, and the third offset voltage.

[0010] According to an embodiment of the present invention, the first comparator unit includes: a transconductance amplifier that forms a first offset voltage at two input terminals and inputs an offset cancellation voltage to any one of the input terminals; a sense resistor connected to the two input terminals; and a switch connected in parallel with the sense resistor, wherein the transconductance amplifier receives a voltage formed by a current flowing through the sense resistor and outputs a corresponding current.

[0011] According to an embodiment of the present invention, during the calibration process, the control unit controls the switch to turn on, and the transconductance amplifier compares the magnitudes of the first offset voltage and the offset cancellation voltage.

[0012] According to an embodiment of the present invention, the second comparator unit is a low-pass filter that includes an operational amplifier and a reactance element connected to a feedback loop of the operational amplifier and calculates the difference between an average current and a channel current.

[0013] According to an embodiment of the present invention, the second comparator unit provides a reference voltage to any one of the input terminals during the calibration process.

[0014] According to an embodiment of the present invention, the third comparator unit outputs a corresponding signal by comparing the magnitudes of the offset Eliminate voltage, the first offset voltage, the second offset voltage, and the third offset voltage.

[0015] According to an embodiment of the present invention, the control unit includes: a counter that is input with a clock pulse and counts the number of input clock pulses; a digital-to-analog converter (DAC) for generating an offset cancellation voltage that increases with time corresponding to the counting result of the counter; and a storage element for storing the counting result of the counter.

[0016] According to an embodiment of the present invention, the controller further includes a multiplexer (MUX). When the offset cancellation voltage is greater than the sum of the first offset voltage, the second offset voltage, and the third offset voltage, the storage element stores the counting result of the counter. When the calibration process is completed, the storage element provides the stored counting result of the counter to the DAC, and the DAC outputs an offset cancellation voltage corresponding to the counting result of the counter.

[0017] According to an embodiment of the present invention, the current balance circuit balances the current of each phase of a multi-phase converter.

[0018] Advantages of the Invention

[0019] According to the present invention, the effect is that the current can be balanced by eliminating the current mismatch of each phase caused by the offset formed in the converter circuit elements.

[0020] The effects of the present invention are not limited to those mentioned above. Other technical problems not mentioned can be clearly understood from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 FIG. schematically shows a multi-phase converter including the current balance circuit of the present invention.

[0022] Figure 2 (a) of FIG. shows a current profile of each phase where imbalance occurs in a multi-phase converter equipped with the current balance circuit of the present invention. Figure 2 (b) of FIG. shows the current in a state where the duty ratio is adjusted. Figure 2 (c) of FIG. shows a state where the current is balanced in all phases of the multi-phase converter.

[0023] Figure 3 (a) of FIG. is an equivalent circuit of any one phase included in the current balance circuit during the calibration process for solving the current imbalance caused by the offset. Figure 3 (b) of FIG. is a simplified equivalent circuit of any one phase of the current balance circuit during the calibration process.

[0024] Figure 4 FIG. is a schematic timing diagram for explaining the operation of the current balance circuit according to the present embodiment during the calibration process. DETAILED DESCRIPTION

[0025] The offset cancellation circuit of the current balance circuit according to an embodiment of the present invention is characterized by including: a first comparator section that forms a first offset voltage at two input terminals and inputs an offset cancellation voltage to any one of the input terminals; a second comparator section that forms a second offset voltage at two input terminals, inputs the output voltage of the first comparator section to any one of the input terminals, and inputs the reference voltage to the other input terminal; a third comparator section that forms a third offset voltage at two input terminals, inputs the output voltage of the second comparator section to any one of the input terminals, and inputs the reference voltage as the other input terminal; and a control section that, during the calibration process, forms and outputs an offset cancellation voltage that increases with time, and outputs the offset cancellation voltage when the offset cancellation voltage is greater than the sum of the first offset voltage, the second offset voltage, and the third offset voltage.

[0026] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Before that, the terms or words used in this specification and claims should not be construed as being limited to their ordinary or dictionary meanings. The inventor, in order to describe his invention in the best way and in accordance with the principle of reasonably defining the concept of terms, interprets his own aspects as meanings and concepts that conform to the technical gist of the present invention. Accordingly, it should be understood that the embodiments described in this specification and the configurations shown in the drawings are only the most preferred embodiments of the present invention and do not represent the entire technical gist of the present invention, and various equivalents and modifications that can replace them may be available when this application is filed.

[0027] Figure 1 FIG. schematically shows a multiphase converter 1 including the current balance circuit of the present invention. Referring to Figure 1 , the multiphase converter includes: a plurality of switching elements (SWa1, Swa2, SWb1, SWb2, SWc1, SWc2) connected in series between a drive voltage (VIN) and a reference voltage; transconductance amplifier sections (100a, 100b, 100c) that output corresponding currents by detecting the currents (I La , I Lb , I Lc ) output from each phase; an arithmetic section (220a, 220b, 220c) that calculates the difference between the low-pass filter 210 and the average current output by averaging the currents output by the transconductance amplifier sections (100a, 100b, 100c) and the currents output by the transconductance amplifier sections (100a, 100b, 100c); and a duty ratio control section (300a, 300b, 300c) that controls the duty ratio by forming gate signals for the plurality of switching elements (SWa1, Swa2, SWb1, SWb2, SWc1, SWc2) included in each phase according to the difference in the currents calculated by the arithmetic section.

[0028] Figure 2 Figure (a) shows the current profiles of the unbalanced phases in the multiphase converter 1 equipped with the current balance circuit of the present invention. Refer to Figure 1 and Figure 2 Figure (a), due to the imbalance, the output of the current (I Lc ) from the c-phase increases. The increased current generates heat, thereby reducing the efficiency of the drive circuit. According to the current balance circuit of the present invention, the transconductance amplifiers (Gma, Gmb, Gmc) detect the current flowing through each phase and provide a signal corresponding to the current to the low-pass filter 210.

[0029] The low-pass filter 210 outputs a current signal (I AVG ) corresponding to the average value of the provided current, and provides it to the arithmetic units (220a, 220b, 220c). The arithmetic units (220a, 220b, 220c) calculate the difference between the signal output by detecting the output current of each phase by the transconductance amplifiers (Gma, Gmb, Gmc) and the average current (I AVG ), and then provide it to the duty controllers (300a, 300b, 300c). The duty controllers (300a, 300b, 300c) receive the calculated difference signals (I DUTYa , I DUTYb , I DUTYc ), and adjust the duty ratio of each phase output by forming the gating signal of each switch. As shown in Figure 2 Figure (b), the current imbalance problem is solved to a certain extent by the duty ratio adjusted in this way.

[0030] However, non-ideal characteristics such as offsets are formed in the components included in each phase of the current balance circuit. Therefore, as shown in Figure 2 Figure (c), it may be difficult to evenly balance the currents (I L1 , I L2 , I L3 ) flowing in all phases.

[0031] Figure 3 Figure (a) is the equivalent circuit of any one phase included in the current balance circuit during the calibration process for solving the current imbalance caused by the offset, Figure 3 Figure (b) is the simplified equivalent circuit of any one phase of the current balance circuit during the calibration process. As an embodiment, the calibration process can be performed when the converter starts driving. Refer to Figure 3 Figure (a) and Figure 3 (b), in the transconductance amplifier section (100a, 100b, 100c) (see Figure 1) A first offset voltage (Vos1) is formed between the two input terminals, and an offset cancellation voltage (Vosc) is input to either of the input terminals. During the calibration process, the transconductance amplifier can be modeled as a first comparator 100 and operate equivalently to a comparator.

[0032] An offset voltage (Vos2) is formed between the two input terminals of the low-pass filter 210 and the arithmetic unit (220a, 220b, 220c, see Figure 1 ). Additionally, during the calibration process, the low-pass filter 210 and the arithmetic unit 220 can be modeled as a second comparator 200 and operate equivalently to a comparator. Further, the duty ratio control unit 300 forms an offset voltage (Vos3) between the two input terminals, can be modeled as a third comparator 300 during the calibration process, and operate equivalently to a comparator.

[0033] Accordingly, the current balance circuit of an embodiment of the present invention includes: a first comparator unit 100 that forms a first offset voltage (Vos1) on two input terminals and inputs the offset cancellation voltage to either of the input terminals; a second comparator unit 200 that forms a second offset voltage (Vos2) between the two input terminals, inputs the output voltage of the first comparator unit 100 to either of the input terminals, and inputs a reference voltage (Vref) to the other input terminal; a third comparator unit 300 that forms a third offset voltage (Vos3) between the two input terminals, inputs the output voltage of the second comparator unit 200 to either of the input terminals, and inputs a reference voltage (Vref) to the other input terminal; and a control unit 400 that, during the calibration process, forms and outputs an offset cancellation voltage that increases with time, and outputs the offset cancellation voltage when the offset cancellation voltage is greater than the sum of the first offset voltage, the second offset voltage, and the third offset voltage.

[0034] Figure 4 is a schematic timing diagram for explaining the operation of the current balance circuit according to this embodiment during the calibration process. Refer to Figure 3 and Figure 4 , if the converter is driven by applying power, the state of the calibration start signal (CALON) changes and the calibration process for offset cancellation starts. In Figure 4 the illustrated embodiment, the calibration start signal (CALON) is exemplified as starting the calibration process in the logic high state. However, in the illustrated embodiment, the calibration start signal (CALON) can be in the logic low state during the calibration process.

[0035] When a calibration start signal (CALON) is provided, clock pulses are provided to a counter. The counter counts the number of input clock pulses and outputs a count result (CAL count). A memory receives and stores the count result output by the counter.

[0036] As the calibration start signal (CALON) remains at a logic high level, a calibration multiplexer (CAL MUX) outputs the count result signal (CAL count) output by the counter to a digital-to-analog converter (DAC). The DAC forms an offset cancellation signal (Vosc) that increases with time corresponding to the provided count result (CAL count) signal and provides it to one input terminal of the first comparator unit 100.

[0037] The first comparator unit 100 can be a transconductance amplifier (Gma, Gmb, Gmc, see Figure 1 ) that detects the current of each phase as described above and outputs a current corresponding to the detection result. Accordingly, a resistor is connected between the two input terminals of the first comparator unit 100, and the resistor forms a corresponding voltage as a current (I L ) of each phase flows through it. However, since the influence of the offset voltage cannot be accurately measured in a state where the resistors are connected, the current (I L ) of each phase is bypassed to a reference voltage by turning on a switch (SW). As an example, the on and off of the switch (SW) can be performed by the calibration start signal (CALON).

[0038] The DAC can form and output a reference voltage (Vref) and provide the reference voltage (Vref) to either one of the input terminals of the second comparator 200 and the third comparator 300 through a multiplexer (MUX) during the calibration process.

[0039] As described above, the DAC receives the count result signal obtained by the counter counting the number of clock pulses and forms and outputs an offset cancellation signal (Vosc) corresponding to the count result signal. Accordingly, the offset cancellation signal (Vosc) increases with time.

[0040] When the magnitude of the offset cancellation signal (Vosc) supplied to the first comparator section 100 is inverted with respect to the sum of the magnitudes of the first offset signal (Vos1), the second offset signal (Vos2), and the third offset signal (Vos3), the output CP_OUT signal of the third comparator 300 changes. As an example, when the magnitude of the first offset voltage (Vos1) formed in the transconductance amplifier 100 is 5 mV, the magnitude of the second offset voltage (Vos2) formed in the low-pass filter 200 is -3 mV, the magnitude of the second offset voltage (Vos2) formed in the duty control section 300 is -3 mV, and the magnitude of the third offset voltage (Vos3) is 2 mV, the CP_OUT signal output by the third comparator changes only when the magnitude of the offset cancellation voltage (Vosc) exceeds 4 mV.

[0041] The Memory detects the change in the CP_OUT signal and stores the count result signal (CAL count) provided by the counter. In the illustrated embodiment, the Memory stores the count result signal (CAL count) before the CP_OUT signal changes. However, in an embodiment not illustrated, the Memory stores the count result signal (CAL count) immediately after the CP_OUT signal changes.

[0042] As an example, after the CP_OUT signal changes, even if the value of the count result signal (CALcount) output by the counter is changed, the Memory does not update the stored value.

[0043] If the counter reaches the maximum countable value, the calibration process ends, and the state of the calibration start signal (CAL_ON) changes. As the calibration process ends, the Memory outputs the stored count result signal (CALcount). The MUX supplies the coefficient result signal output by the Memory to the DAC, and the DAC forms and outputs an offset cancellation signal (Vosc) corresponding to the same provided count result signal (CAL).

[0044] Accordingly, in the present embodiment, when the converter operates after the calibration process, the offset of the elements included in the converter can be eliminated, and the current in each phase of the converter can be balanced with high precision.

[0045] The present invention has been described above in connection with specific embodiments of the present invention, but this is only an example and the present invention is not limited thereto. Those of ordinary skill in the art to which the present invention pertains can make changes or modifications to the described embodiments without departing from the scope of the present invention, and various changes or modifications can be made within the equivalent scope of the technical spirit of the present invention and the claims to be described below.

Claims

1. A current balancing circuit, characterized in that, Comprising: A first comparator section that forms a first offset voltage at two input terminals and inputs an offset cancellation voltage to either input terminal; A second comparator section that forms a second offset voltage at two input terminals, inputs the output voltage of the first comparator section to either input terminal, and inputs a reference voltage to the other input terminal; A third comparator section that forms a third offset voltage at two input terminals, inputs the output voltage of the second comparator section to either input terminal, and inputs a reference voltage as the other input terminal; And A control section that, during a calibration process, forms and outputs an offset cancellation voltage that increases with time, and outputs an offset cancellation voltage when the offset cancellation voltage is greater than the sum of the first offset voltage, the second offset voltage, and the third offset voltage.

2. The current balance circuit according to claim 1, wherein The first comparator section includes: a transconductance amplifier that forms a first offset voltage at the two input terminals and inputs the offset cancellation voltage to one of the input terminals; A sense resistor connected to the two input terminals; and A switch connected in parallel with the sense resistor, wherein the transconductance amplifier receives a voltage formed by a current flowing through the sense resistor and outputs a corresponding current.

3. The current balance circuit according to claim 2, wherein During the calibration process, the control section controls the switch to conduct, and the transconductance amplifier compares the magnitudes of the first offset voltage and the offset cancellation voltage.

4. The current balance circuit according to claim 1, wherein The second comparator section provides the reference voltage to either input terminal during the calibration process.

5. The current balance circuit according to claim 1, wherein The third comparator section outputs a corresponding signal by comparing the magnitudes of the offset cancellation voltage, the first offset voltage, the second offset voltage, and the third offset voltage.

6. The current balance circuit according to claim 1, wherein The control section includes: A counter that is input with a clock pulse and counts the number of input clock pulses; A digital-to-analog converter for generating the offset cancellation voltage, which increases with time corresponding to the counting result of the counter; and A storage element for storing the counting result of the counter.

7. The current balance circuit according to claim 6, wherein The control section further includes a multiplexer, When the offset cancellation voltage is greater than the sum of the first offset voltage, the second offset voltage, and the third offset voltage, the storage element stores the counting result of the counter, When the calibration process is completed, the storage element provides the stored counting result of the counter to the digital-to-analog converter, And the digital-to-analog converter outputs the offset cancellation voltage corresponding to the counting result of the counter.

8. The current balance circuit according to claim 1, wherein The current balance circuit balances the current of each phase of a multiphase converter.

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