Fast Digital Isolators

Abstract

The invention relates to a digital isolator, comprising a logic module (20) for receiving an input signal D and providing a command signal (41, 42) to a sawtooth modulator. A first sawtooth modulator provides a first sawtooth signal at a node A1, the first sawtooth signal comprising a fast rising edge triggered by a rising edge of a control signal followed by a slow falling edge when D equals 1, and comprising a fast falling edge triggered by a rising edge of the control signal followed by a slow rising edge when D equals 0. A second sawtooth modulator provides a second sawtooth signal at a node A2 that is inverted relative to the first sawtooth signal. Isolation capacitors (61, 62) are connected to nodes A1 and A2 and act as an isolation barrier and as part of a high-pass filter together with dipoles Z1 and Z2. Threshold comparators (121, 122) provide output signals S and R. Based on these S and R output signals, the input signal D can be regenerated with reference to ground G1 relative to ground G2 using, for example, an SR logic gate, a low-pass filter or a peak detector.

Description

Technical Field

[0001] The present invention generally relates to the field of capacitively isolated links.

[0002] The present invention relates to the field of capacitive isolation systems for isolating circuits from each other while transmitting digital information data. More specifically, the present invention relates to isolation systems with capacitor-coupled isolation barriers. This is suitable for industrial process control applications, telephony, medical electronics, data communications, for example. Background Art

[0003] Isolators are typically implemented to separate circuits or circuit sections of circuits from each other to avoid, for example but not limited to, undesired effects on other circuits or circuit sections, to minimize the effects of common mode transients (CMT), radiation or electromagnetic interference, and crosstalk between circuits or circuit sections. Capacitive isolation links are also used to minimize the transmission of environmentally introduced interference from one circuit to another or from one section of a circuit to another. Capacitive isolation links are also used for galvanic isolation to isolate high voltages from each other or to isolate low voltage command circuits from high voltage power supply circuits. Capacitive isolation links also allow better integration compared to other systems based on, for example, electromagnetic isolators.

[0004] Capacitive isolation links typically utilize a dielectric to block direct current between isolated circuit sections of a circuit or to block the lowest frequency current between circuit sections while allowing higher frequency data signals to be transmitted. The isolation barrier typically contains one or more capacitors or transformers. For this reason, a commonly used information data shape is a square signal with very fast transients for the signal edge, followed by a maintained information level (no transient information), allowing only the edge changes of the signal to be transmitted through the capacitive barrier. The output signal of a capacitive isolation link is typically delayed relative to the corresponding input. In addition, "jitter" may occur, that is, the delay may vary over time.

[0005] Nevertheless, common mode transients (CMT) may be caused by switching different supply voltages and grounds present in different circuits or circuit sections or due to external interference such as radiation or electromagnetic fields or by other reasons. As a result, high frequency transients may corrupt the data transmission of data signals across the isolation barrier. It is well known that addressing the effects of CMT in digital isolators is a challenge in designing such digital isolators.

[0006] The document SLLA284B (published in January 2009 - revised in August 2018) "Digital Isolator Design Guide" from Texas Instruments discloses a capacitive isolation link device that includes two differential data links: a high-frequency channel (HF), whose bandwidth is typically from 100kbps to 150Mbps; and a low-frequency channel (LF), which covers the range below to DC. In principle, the single-ended input signal entering the HF channel is split into differential signals via an inverter gate at the input. The following capacitor-resistor network distinguishes the signal into small and narrow transients, which are then converted into rail-to-rail differential pulses by two comparators. The comparator output drives a "NOR" gate flip-flop, whose output is fed to an output multiplexer. The decision logic (DCL) of the driven output of the flip-flop measures the duration between signal transients. If the duration between two consecutive transients exceeds a certain time limit (as in the case of low-frequency signals), the DCL forces the output multiplexer to switch from the high-frequency channel to the low-frequency channel. Because low-frequency input signals require excessive values ​​for the internal capacitors, these signals are pulse-width modulated (PWM) at the carrier frequency of the internal oscillator to produce a sufficiently high frequency to pass the capacitive barrier. When modulating the input, a low-pass filter (LPF) is required to remove the high-frequency carrier from the actual data before passing it to the output multiplexer.

[0007] Document US2017 / 0302225A1 discloses a system in which an input circuit includes an on-off keying (OOK) modulator configured to generate a modulated data signal in response to an input data signal and a carrier signal. An output circuit includes a frequency shift keying (FSK) demodulator configured to detect the presence of a carrier signal in a modulated differential data signal and generate a demodulated data signal in response to the presence of the carrier signal.

[0008] Document EP0973305A1 discloses a capacitive isolation barrier system, which uses a sawtooth wave signal as a carrier to generate a pulse width modulation (PWM) signal as an input signal of the capacitive isolation barrier. There are two capacitors between the input circuit and the output circuit, which provide isolation between the input circuit and the output circuit. The square pulse width modulation signal is used as a transmission signal from one side of the isolation barrier to the other side.

[0009] Conventional capacitive links cannot transmit states, but only transients, so that when a single capacitor is used, the system cannot distinguish between parasitics and transitions of the state of the data to be transmitted. Therefore, two capacitors are used to transmit data in a differential manner, which allows the removal of unwanted parasitic noise. But it is risky to transmit the signal directly using only two capacitors. In fact, in the case of erroneous communication due to any of the reasons described previously, the output signal may be in an erroneous state and theoretically may remain in the erroneous state for a long time until some correction can be made, or until the new state to be transmitted is defined. This may cause fatal failures in some applications. For this reason, many designs contain a second pair of capacitors, which are intended to transmit a modulated version of the data signal, rather than the data signal itself. For a modulated square data signal, there is always a state change, so the capacitive link will transmit said state change. In the case of a "false pulse", it will be quickly corrected at the next edge of the modulated signal to avoid a fatal failure.

[0010] However, for this second channel, since the input signal is modulated with a carrier frequency that is either asynchronous or synchronous with the input signal, the modulated signal also needs to be demodulated. This adds latency and / or jitter. Depending on the end application, this may or may not be critical.

[0011] In a capacitive link, a square or sinusoidal signal is applied at the input of the capacitive link. In the case of a sine wave, a specific demodulator is needed, which causes some delay and jitter. This may also require some magnetic components to generate such a waveform. In the case of a square wave, the capacitor will always transmit a rising edge, followed by a constant state, and then a falling edge. The capacitive link is a high-pass filter. These solutions usually require a demodulator in the receiver circuit to extract the envelope of the signal. This involves some time constants, causes additional delay and / or output jitter and additional demodulation or detection circuits, which increases the system size and limits its integration. Summary of the invention

[0012] An object of the present invention is to provide a digital isolator for receiving a digital signal D and for transmitting said signal over an isolation link, the isolation link being a single differential capacitor, said digital isolator having reduced delay and high performance.

[0013] According to a first aspect, the present invention provides a digital isolator for receiving a digital signal D having a high or low state pulse with a duration greater than TD0 with reference to a first ground G1 and providing a corresponding signal to an output node S and an output node R with reference to a second ground G2. The digital isolator comprises

[0014] - a logic module, configured to receive said digital signal D, comprising:

[0015] - a generator for generating a pulse signal CK pls ;

[0016] - a delay generator for generating a digital signal D having a fast rising edge delayed by TD1 after the rising edge of D and a fast falling edge delayed by TD1 ' after the falling edge of D D ;

[0017] and is configured to provide a first command signal and a second command signal,

[0018] a first sawtooth modulator, which is used to receive the first command signal and is configured to provide a first sawtooth signal at a node A1, wherein the first sawtooth signal

[0019] -As long as D=D D ,

[0020] -As long as there is no CK pls The pulse signal appears, if D D = 1, it may have a slow falling edge followed by a low state flat line area. D = 0, it may have a slow rising edge followed by a high state flat line area;

[0021] - In the pulse signal CK pls During the occurrence of D D The value of

[0022] - As long as D=not(D D ),

[0023] -With D D The value of

[0024] -In D D When any conversion of

[0025] -With D D The value of

[0026] a second sawtooth modulator, which is used to receive the second command signal and is configured to provide a second sawtooth signal at node A2, wherein the second sawtooth signal

[0027] -As long as D=D D ,

[0028] -As long as there is no CK pls The pulse signal appears, if D D = 0, it may have a slow falling edge followed by a low state flat line area. D = 1, it may have a slow rising edge followed by a high state flat line area,

[0029] - In the pulse signal CKpls During the occurrence period, there is not(D D ) value;

[0030] - As long as D=not(D D ):

[0031] - has not(D D ) value;

[0032] -In D D When any conversion of:

[0033] - has not(D D ) value;

[0034] - a first capacitive coupling connected to said node A1 and node B1;

[0035] - a first dipole Z1 connected between said node B1 and a bias voltage source referenced to a second ground G2;

[0036] - a second capacitive coupling connected to said node A2 and node B2;

[0037] - a second dipole Z2 connected between said node B2 and said bias voltage source;

[0038] a first threshold comparator having a first input connected to said node B1 and a second input connected to said node B2, generating at an output node S a digital signal having a high state value when its first input exceeds its second input threshold Th1, and generating otherwise a digital signal having a low state value;

[0039] - a second threshold comparator having a first input connected to said node B2 and a second input connected to said node B1, generating at an output node R a digital signal having a high state value when its first input exceeds its second input threshold Th2, and generating otherwise a signal having a low state value.

[0040] The duration of the slow falling edge or rising edge depends on the components of the circuit. If no rising edge or falling edge occurs in the sawtooth signal, a low or high state plateau occurs after the slow falling edge or slow rising edge, respectively. Thresholds Th1 and Th2 are selected so that when the signals at nodes A1 and A2 have a fast rise with a falling transition, pulses appear at nodes S and R.

[0041] The logic module may include a D A low state pulse signal D having a duration TD3 is generated during or after each conversion of pls and / or for the pulse signal CK pls Appearance of "and" Dpls A circuit that generates a signal CTRL that is equal to a logical combination of low state pulses when the signal is high.

[0042] According to an embodiment, the first sawtooth modulator is at node A1.

[0043] -When D=0, D D =0 and CTRL=1, a slow rising edge is generated;

[0044] -When D=0, D D =0 and CTRL=0, a low state flat line area is generated;

[0045] -When D=1, D D =1 and CTRL=1, a slow falling edge is generated;

[0046] -When D=1, D D =1 and CTRL=0, a high state flat line area is generated;

[0047] -When D=0, D D =1 and CTRL=1, a high state flat line area is generated;

[0048] -When D=0, D D =1 and CTRL=0, a high state flat line area is generated;

[0049] -When D=1, D D =0 and CTRL=1, a low state flat line area is generated;

[0050] -When D=1, D D =0 and CTRL=0, a low state flat line area is generated.

[0051] The first capacitive coupling element and / or the second capacitive coupling element may be implemented as one or more capacitors connected in series.

[0052] Said duration TD1 may advantageously be equal to TD1 ′.

[0053] The first command signal may include digital signals SU1, SD1, WU1, and WD1, and the second command signal may include digital signals SU2, SD2, WU2, and WD2,

[0054] -When D=0 and D D =0, or when D = 1 and D D =1 and CTRL=1, or when D=1 and D D =0, SU1 is equal to 1, otherwise SU1 is equal to 0;

[0055] -When D=0 and D D=0 and CTRL=1, or when D=1 and D D =1, or when D = 0 and D D =1, SD1 is equal to 0, otherwise it is equal to 1;

[0056] -When D=0 and D D =0 and CTRL=1, WU1 and WD1 are equal to 0, when D=1 and D D =1 and CTRL=1, WU1 and WD1 are equal to 1, otherwise WU1 and WD1 are equal to 0 or 1;

[0057] -SU2 is equal to not(SD1);

[0058] -SD2 is equal to not(SU1);

[0059] -When D=0 and D D =0 and CTRL=1, WU2 and WD2 are equal to 1, when D=1 and D D When =1 and CTRL=1, WU2 and WD2 are equal to 0, otherwise WU2 and WD2 are equal to 1 or 0.

[0060] The digital isolator may include an SR latch, the signals at output nodes R and S being connected to corresponding inputs of the SR latch.

[0061] The first sawtooth modulator may include

[0062] - a first low-impedance controllable switch LU1, connected between the first power supply voltage V1 and the output node A1, closed when the command signal SU1 is equal to 0, otherwise open;

[0063] - a second low-impedance controllable switch LD1, connected between the node A1 and the first ground G1, closed when the command signal SD1 is equal to 1, otherwise open;

[0064] - a first controllable switch MU1, which is connected in series with the current limiting dipole ILU1 between the first power supply voltage V1 and the node A1, the first controllable switch MU1 being opened when the command signal WU1 is equal to 1, and closed otherwise;

[0065] - a second controllable switch MD1 connected in series with a current limiting dipole ILD1 between the node A1 and the first ground G1, the second controllable switch being closed when the command signal WD1 is equal to 1, and being open otherwise;

[0066] - A capacitor Cp1 between said node A1 and ground G1.

[0067] The components ILU1, ILD1, Cp1 of the first sawtooth modulator may be selected so that the duration of the slow rising edge and / or the slow falling edge of the signal at the node A1 is at least twice, four times or more preferably ten times the duration of the fast rising edge and / or the fast falling edge of the signal at the node A1. The duration of the slow or fast rising edge may be determined as the time required to reach an 80% or equivalent ratio of the power supply voltage. The duration of the slow or fast falling edge may be determined as the time required to drop to a 20% or equivalent ratio of the power supply voltage.

[0068] The second sawtooth modulator may include corresponding identical elements.

[0069] The components ILU2, ILD2, Cp2 of the second sawtooth modulator are selected so that the duration of the slow rising edge and / or the slow falling edge is at least two, four or more preferably ten times the duration of the fast rising edge and / or the fast falling edge at the signal at node A2.

[0070] According to a second aspect, the present invention provides a method for isolating a digital signal D having a high or low state pulse with a duration greater than TD0 with reference to a first ground G1 and providing corresponding possible redundant signals to an output node S and an output node R with reference to a second ground G2, the method using an isolator according to the present invention and the steps claimed for protection.

[0071] The method may comprise the step of feeding said signals at output nodes R and S to corresponding inputs of an SR latch.

[0072] In the context of the present invention, a sawtooth signal may include fast / slow rising / falling edges and a low-high state plateau. The slow rising / falling edges may be straight line segments, curves such as those produced by the charging / discharging of capacitors in resistors, or a series of small upward / downward steps. Digital signals with high / low state values ​​may also be defined as having values ​​of 1 or 0, respectively. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] In the diagram:

[0074] FIG. 1 is a conceptual block diagram of a known edge-based architecture of a digital isolator from document SLLA284A by Texas Instruments Incorporated.

[0075] Fig. 2 is a schematic diagram of a CMOS technology implementation of a known isolation coupler with a capacitive barrier. This figure is Fig. 3 in document EP0973305A1.

[0076] Further aspects of the invention will be explained in more detail by way of example and with reference to the accompanying drawings, in which:

[0077] Figure 3a is a block diagram of an isolator according to the present invention,

[0078] Figure 3b is a block diagram of an isolator according to the present invention, which includes an SR latch;

[0079] Figure 4a Indicates that when the minimum duration TD0 of the low or high state pulse of D is greater than TD1 and TD1' Figure 3a or Figure 3b Typical signal at a specific node of an isolator.

[0080] Figure 4b Indicates that the duration of the low or high state pulse of D can be shorter than TD1 and TD1' Figure 3a or Figure 3b Typical signal at a specific node of an isolator.

[0081] Figure 4c It means that according to the signals D, D D and CK pls Flow chart of the variation in the value of the signal at node A1.

[0082] Figure 5 is an embodiment of a logic module used in a digital isolator according to an embodiment of the present invention,

[0083] Figure 6a and 6b An embodiment of a sawtooth modulator for use in a digital isolator according to an embodiment of the present invention is shown.

[0084] The drawings are neither drawn to scale nor to proportion. DETAILED DESCRIPTION

[0085] Figure 3a A block diagram of a digital isolator 10 according to an embodiment of the present invention is depicted. The digital isolator 10 is configured for receiving a digital signal D with reference to a first ground G1 and for providing corresponding output signals S and R with reference to a second ground G2. The digital isolator 10 comprises a logic module 20 for receiving the digital signal D and for providing a first command signal 41 and a second command signal 42 to a first sawtooth modulator STM1 51 and a second sawtooth modulator STM2 52, respectively. The digital isolator 10 further comprises a differential link 80 comprising a first channel 71 and a second channel 72.

[0086] The first channel 71 includes the first sawtooth modulator 51 for receiving the first command signal 41 and for providing the first sawtooth signal at the node A1. The first sawtooth signal will be described below. The first channel further includes a high-pass filter 91, which includes a first capacitive coupling member 61 represented as a single capacitor 61 and a first dipole 101Z1. The first dipole can advantageously be a resistor. The dipole 101Z1 is grounded through a bias voltage source. The bias voltage source can be short-circuited, i.e., there is no bias voltage. The output signal of the high-pass filter is presented at the node B1. When there may be a high voltage between the input and output of the isolator, it may be useful to use a plurality of capacitors in series so as to split the high voltage between each of the capacitors. The second channel 72 includes corresponding components numbered 52, 42, A2, 92, 62, 102, B2, respectively. The logic module 20 is represented here as a single module, but it can also be implemented in two parts, one for the first channel 71 and one for the second channel 72, provided that the two logic module blocks use the same clock signal block or the signal clock of the two blocks is synchronized. A first threshold comparator 121 having a first input connected to the node B1 and a second input connected to the node B2 generates a logic 1 output S when the difference between the values ​​of its first input exceeds its second input threshold Th1, otherwise generates a logic 0 output, so that only a positive B1-B2 pulse greater than the threshold Th1 will generate a logic 1 pulse at the output S. A second threshold comparator 122 having a first input connected to the node B2 and a second input node B1 connected to the node generates a logic 1 output R when its first input exceeds its second input threshold Th2, otherwise generates a logic 0 output, so that only a positive B2-B1 pulse greater than the threshold Th2 will generate a logic 1 pulse R at the output R.

[0087] Figure 3b A block diagram of a digital isolator 10 according to a preferred embodiment of the present invention is depicted. The signals S and R may be sent to an SR latch to regenerate the input signal D as a signal OUT. Alternatively, the signals S and R may be sent to a low pass filter, a peak detector, or other digital circuit to regenerate the input signal D as a signal OUT.

[0088] Figure 4a Indicates that when the minimum duration TD0 of the low or high state pulse of D is greater than TD1 and TD1' Figure 3a or Figure 3b A typical signal at a specific node of an isolator of FIG. 1 is shown. This is the case when the digital signal is quite slow. An example of a digital signal D is shown in the first line. In an embodiment of the present invention, the signal D DGenerated by the logic module 20, the rising edge of D is delayed by TD1, and the falling edge of D is delayed by TD1'. pls may be generated by logic module 20. According to an exemplary embodiment, except for a brief pulse of a low state value, signal CK pls It also has a high state value of duration TD2. Such a signal can be generated from a regular clock signal using the circuit described below. pls The low state pulses of CK can have a constant interval, but the interval can vary over time. The duration TD2 can be a very short duration and can also vary. This is the pulse signal CK pls The pulse signal CK pls It can have any shape, such as a positive rectangular pulse, a Dirac or a Gaussian pulse. pls It can also be generated by the logic module 20. In addition to the short pulse of the low state value, the signal D pls It also has a high state value of duration TD3, which may overlap or be followed quickly by D D This signal can be obtained by using the circuit described below from D D Signal generation.

[0089] Using the first command signal 41 / the second command signal 42, the first sawtooth modulator and the second sawtooth modulator generate sawtooth signals at nodes A1 and A2, respectively. These signals are filtered by high pass filters 91 and 92, respectively, and represent the filtered signals obtained at nodes B1 and B2. It can be seen that the fast rising / falling edges of the signals at nodes A1 and A2 generate high amplitude positive / negative short pulses at nodes B1 and B2. In contrast, the slow rising / falling edges of the signals at nodes A1 and A2 generate low amplitude long positive / negative pulses at nodes B1 and B2, while the flat line area generates a signal with a value of 0 at nodes B1 and B2. Ideally, the signal at node A2 is a mirror image of the signal at node A1 along a horizontal line at the middle height of the signal at node A1. Threshold comparators 121 and 122 receive the differences B1-B2 and B2-B1, respectively, and generate digital pulses S and R, respectively. These two threshold comparators allow the D pls or CK pls Possible non-interleaved continuous digital pulses are obtained when pulses appear on CK, only on output S when input signal D is set to logic 1, and only on output R when input signal is set to 0. This allows setting the system to the correct mode depending on the channel S or R from which the fast output signal comes. In case of large disturbances at B1 or B2, if erroneous information is generated on output S or output R, the system willpls The maximum time of the two pulses of the 121 / 122 pulses is used to correct itself. When the parasitic can induce a differential voltage large enough to trigger the comparator 121 or 122, it is considered large. In case of moderate parasitics at node B1 or node B2, the system will filter the erroneous information with a high pass filter and will not consider the erroneous information, making the system robust to moderate disturbances on B1 or B2.

[0090] exist Figure 3b In the embodiment of FIG. 5 , these pulses may generate a signal OUT at the output of the SR latch. The signal OUT corresponds to the signal D after a delay TD1 and is isolated therefrom.

[0091] Preferably, duration TD1 is selected to be short duration to minimize the delay between the input and output of the isolator. pls The duration between pulses determines the delay in regenerating the S or R pulse after a parasitic perturbation in the isolator.

[0092] Although the pulse signal CK pls Depicted as being derived from the clock signal CK, but pulses may occur at any rate and with any delay between successive pulses. The rate may vary as required by the application. CK pls The rate of the pulses will govern the rate of the redundant S and R pulses.

[0093] Figure 4b Indicates that the duration of the low or high state pulse of D can be shorter than TD1 and TD1' Figure 3a or Figure 3b A typical signal at a specific node of an isolator. This is the case when the digital signal is quite fast. In this case, the transition of the digital signal D may occur before the delay TD1 or TD1' expires. Figure 4b In the example case, it can be seen that the first downward transition of D occurs before the expiration of the delay TD1. This starts a slow rising edge at node A1. The second downward transition of D occurs after the expiration of the delay TD1. This produces a fast rising edge at node A1, followed by a high state plateau. It can be seen that the resulting signal Out correctly reproduces the digital signal D, with the rising edge delayed by TD1 and the falling edge delayed by TD1'.

[0094] like Figure 4a and Figure 4b As depicted above, the signals at nodes A1 and A2 have fast rising / falling edges, represented by upward or downward arrows when transitioning from a low state plateau to a high state plateau or from a high state plateau to a low state plateau, or when transitioning from a slow edge to a plateau.

[0095] It can be seen from these figures that the first sawtooth wave signal at node A1

[0096] When D = D D = 1, with a slow falling edge, possibly followed by a low state plateau until one of the following occurs:

[0097] - When a fast falling edge of D occurs, the first sawtooth signal has a sharp rising edge followed by a high state flat line area;

[0098] -When the signal CK pls When a low state pulse appears, the first sawtooth signal has a fast rising edge;

[0099] When D = D D = 0, with a slow rising edge, possibly followed by a high state plateau until one of the following occurs:

[0100] - When a fast rising edge of D occurs, the first sawtooth signal has a sharp falling edge, followed by a low state flat line area;

[0101] -When the signal CK pls When a low state pulse appears, the first sawtooth signal has a fast falling edge;

[0102] When D=not(D D )(This corresponds to Figure 4a and Figure 4b The first sawtooth signal is equal to D D .

[0103] It can also be seen from these figures that the second sawtooth signal at node A2

[0104] - when the first sawtooth signal has a fast rising edge, it has a fast falling edge;

[0105] - when the first sawtooth signal has a fast falling edge, it has a fast rising edge;

[0106] - when the first sawtooth signal has a low-state plateau region, it has a high-state plateau region;

[0107] - when the first sawtooth signal has a high-state plateau region, it has a low-state plateau region;

[0108] - when the first sawtooth signal has a slow rising edge, it has a slow falling edge;

[0109] - When the first sawtooth signal has a slow falling edge, it has a slow rising edge.

[0110] Figure 4c It means that according to the signals D, D D and CKpls A flowchart of the change of the value of the signal at node A1. An example process of the flowchart is as follows: D If the result is positive, the pulse signal CK is pls If the result is negative, a slow falling edge is generated at node A1, and we return to the first test. D and CK pls Other loops can follow in the flow chart depending on the value of . A similar flow can be drawn for the signal at node A2.

[0111] Figure 5 is an example of a logic module for use in a digital isolator according to an embodiment of the present invention. The signal CK can be obtained from the regular clock signal CK by using a delay of duration TD2 and a NOR gate (XOR gate) having the received clock signal and the delayed clock signal as inputs. pls In a similar manner, the signal D D Get signal D pls The signal CTRL can be combined with the signal CK in an AND gate. pls and signal D pls To obtain. Signal D, D D and CTRL are inputs to the command logic module 200. The command logic module 200 is configured to generate command signals to the sawtooth modulator. In this embodiment, the first command signal 41 includes four individual signals SD1, SU1, WU1 and WD1. The first sawtooth modulator 51 receives the signals and generates a fast falling edge (strong downward transition) at the node A1 when SD1=1 and SU1=1, a fast rising edge (strong upward transition) when SU1=0 and SD1=0, a slow rising edge (weak upward transition) when SU1=1, SD1=0, WD1=0 and WU1=0, and a slow falling edge (weak downward transition) when SU1=1, SD1=0, WU1=1 and WD1=1.

[0112] The relationship between the second command signal 42 and the command signal 41 is as follows

[0113] WD2=not(WU1)

[0114] WU2=not(WD1)

[0115] SD2=not(SU1)

[0116] SU2=not(SD1)

[0117] The command logic module can be constructed by using logic gates such as AND gates, OR gates, inverters, etc., as shown in the figure, but those skilled in the art will know that the ... D and CTRL to obtain the required command signals. A non-overlapping circuit 210 may be provided to generate the signals SD1, SU1 from the signals SD10, SU10. The non-overlapping circuit will prevent the transient condition of SD1=1 and SU1=0, as this condition would cause a short-term strong short circuit of the power supply V1 to the ground G1. As is well known in the art, the non-overlapping circuit may be obtained by combining simple logic gates. A similar non-overlapping circuit 220 may also be provided between the signals SD20, SU20 and the signals SD2, SU2.

[0118] Figure 6a and 6b 1 and 2 show embodiments of sawtooth modulators 51 and 52 for use in a digital isolator according to an embodiment of the present invention. Figure 6a A general implementation of an ideal switch or a low impedance switch using a sawtooth modulator 51 is presented above. To generate a sawtooth signal at node A1, the first sawtooth modulator 51 shown may include

[0119] - a first low-impedance controllable switch LU1, connected between the first power supply voltage V1 and the output node A1, closed when the command signal SU1 is equal to 0, otherwise open;

[0120] - a second low-impedance controllable switch LD1, connected between the node A1 and the first ground G1, closed when the command signal SD1 is equal to 1, otherwise open;

[0121] - a first controllable switch MU1, which is connected in series with the current limiting dipole ILU1 between the first power supply voltage V1 and the node A1, the first controllable switch MU1 being opened when the command signal WU1 is equal to 1, and closed otherwise;

[0122] - a second controllable switch MD1 connected in series with a current limiting dipole ILD1 between the node A1 and the first ground G1, the second controllable switch being closed when the command signal WD1 is equal to 1, and being open otherwise;

[0123] - A capacitor Cp1 between said node A1 and ground G1.

[0124] The current limiting dipoles ILU1 and ILD1 can be current sources or resistors or a combination thereof or any other current limiting structure. The values ​​of these components and capacitor Cp1 are such that the sawtooth signal preferably reaches at least 80% of V1 or preferably reaches less than 20% of V1 within a slow rising edge or falling edge, respectively. The small dynamic range at the output node A1 results in a poor signal amplitude at the node B1, making it difficult for the comparators 121 and 122 to correctly regenerate the S and R output signals. In a specific embodiment, Cp1 can be a specific capacitor, or a parasitic capacitance due to the technology used, or a combination of capacitors. Parasitic capacitance can be generated by circuit layout, assembly such as bonding or connection, etc.

[0125] To generate a fast rising edge at node A1, SU1 is configured to close the switch LU1 so that capacitor Cp1 is quickly charged to V1 through LU1, while SD1 is configured to open switch LD1, and WU1 and WD1 are preferably configured to open switches MU1 and MD1, respectively.

[0126] To generate a slow rising edge at node A1 , WU1 is set to 0 to close the switch MU1 so that the capacitor Cp1 is charged to V1 through MU1 and ILU1 , while SD1 , SU1 , WD1 are set to open their corresponding switches.

[0127] To generate a fast falling edge of the sawtooth signal, SD1 is set to close the switch LD1 so that the capacitor Cp1 is quickly discharged to the ground G1 through LD1, while SU1 is set to open the switch LU1, and WU1 and WD1 may preferably be set to open the switches MU1 and MD1 respectively.

[0128] To generate a slow falling edge of the sawtooth wave signal, WD1 is set to 1 to close the switch MD1 so that the capacitor Cp1 is discharged to G1 through MD1 and ILD1 , while SD1 , WU1 and SU1 are set to open their corresponding switches.

[0129] Figure 6b The second sawtooth modulator 52 shown above can be constructed in a similar manner to the first sawtooth modulator 51. As is well known to those skilled in the art, the low impedance controllable switches and medium impedance controllable switches used in the present invention can be implemented in various ways, such as with MOSFETs, bipolar or any other kind of transistors or any kind of device that can modulate the conductive channel or any mechanical switch.

[0130] The sawtooth modulators 51 and 52 may be implemented conventionally, for example but not exclusively, in CMOS technology, using transistors or micro-electromechanical switches or any other kind of controlled elements as gates, or logic circuits, such as a microcontroller controlling a fast digital / analog converter.

[0131] Since the differential link includes two inverse logic channels 71 and 72, when a logic signal 1 is sent to the first line of the differential link, a logic signal 0 is sent to the second line of the differential link, and when a logic signal 0 is sent to the first line of the differential link, a logic signal 1 is sent to the second line of the differential link. Therefore, nodes A1 and A2, and correspondingly B1 and B2, will receive signals of complementary logic values.

[0132] In case of injection of unwanted parasitic signals on Node B1 or Node B2, thereby generating erroneous information pulses due to some switching elements or due to ambient electromagnetic noise or any other kind of noise, the system will pls The signal period automatically corrects itself after a maximum time delay. This allows to significantly reduce the time during which the system can provide erroneous information.

[0133] The command logic is summarized in Table I below, where the first three columns show the input signals D, D D and CTRL. The next four columns represent the commands SU1, SD1, WU1 and WD1 provided by the command logic module 200 to the first sawtooth modulator, which are also the negation of the command signals SD2, SU2, WD2 and WU2 provided to the second sawtooth modulator (the symbol / SD2 means the negation of the logic signal SD2). In the table, the arrows represent slow rising / falling edges. The value X means that the corresponding signal can take the value 1 or 0, which is independent for each case.

[0134] Table I

[0135]

[0136] The isolator of the present invention provides improved isolation. According to the present invention, a specific waveform is generated based on the digital input signal so that the output comparator can generate redundant continuous S or R pulses (rather than staggered pulses). Applying these digital outputs S and R directly to the RS flip-flop, one obtains digital redundancy of the input signal. If the first S or R signal is missed, the next occurrence will quickly correct the error and regenerate the output signal. The present invention does not require very high frequency technology and does not require analog low-pass filtering at the output. Everything remains in the digital world, where the output jitter is almost zero.

[0137] The present description provides a method for generating a voltage waveform sufficient to be transmitted across an isolation capacitor. However, other implementations may be used to generate such waveforms, such as but not limited to a microcontroller with a fast digital / analog converter (DAC). The present invention relates to a specific shape of the waveform to be generated so that non-interleaved redundant set and reset pulses can be generated after the output comparator. Basically, the present invention is based on a series of flat line areas, fast voltage transients, or slow voltage transients that produce possible non-interleaved S and R signals at the output.

[0138] The main advantages of the present invention are:

[0139] - No need for very advanced technology

[0140] - Reduced current consumption due to lower internal frequency

[0141] - No analog filtering, resulting in less jitter and low latency.

[0142] - A low frequency clock can be used to adjust the redundancy rate of S and R pulses

[0143] -Compatible with fast digital input

[0144] - Only one differential channel is required for data and redundancy transmission

[0145] -Better EMI due to reduced amount of fast edges.

Claims

1. A digital isolator, comprising: A logic circuit, the logic circuit being configured to: Receiving a first digital signal D; generating a first intermediate signal at a first intermediate node A1; generating a second intermediate signal opposite to the first intermediate signal at a second intermediate node A2; Generate a second digital signal D D , the second digital signal D D Corresponding to the first digital signal D plus a predetermined delay time TD1; Wherein, the logic circuit is referenced to the first ground G1; The logic circuit is further configured to control the first intermediate signal, the second intermediate signal and the second digital signal D in response to the first digital signal D. D , so that: When the first digital signal D is converted from a low state to a high state, the first intermediate signal is converted from a high state to a low state, and remains in the low state for the predetermined delay time TD1; When the second digital signal D D When the first digital signal D is in a high state, the first intermediate signal is converted from a low state to a high state and remains in a high state; When the second digital signal D D When the first digital signal D is in a low state, the first intermediate signal is converted from a high state to a low state. 2 . The digital isolator of claim 1 , further comprising a first isolation capacitor coupled between the first intermediate node A1 and a first input terminal of an output circuit. 3 . The digital isolator of claim 2 , further comprising a second isolation capacitor coupled between the second intermediate node A2 and a second input terminal of the output circuit.

4. The digital isolator according to claim 3, wherein: The first isolation capacitor is configured to transmit the first intermediate signal to the first input terminal of the output circuit, and the second isolation capacitor is configured to transmit the second intermediate signal to the second input terminal of the output circuit.

5. The digital isolator according to claim 4, wherein: The output circuit is referenced to a second ground G2 and is configured to generate an output signal OUT corresponding to the first digital signal D.

6. The digital isolator according to claim 1, wherein: The logic circuit includes a logic module and a clock generation circuit. 7 . The digital isolator of claim 5 , further comprising a first impedance element coupled between the first input terminal of the output circuit and a bias voltage source referenced to the second ground G2 . 8 . The digital isolator of claim 7 , further comprising a first impedance element coupled between the second input terminal of the output circuit and the bias voltage source.

9. The digital isolator according to claim 8, wherein: The output circuit includes a first comparator having a first input node connected to the first isolation capacitor and a second input node connected to the second isolation capacitor.

10. The digital isolator according to claim 9, wherein: The output circuit also includes a second comparator having a third input node connected to the first isolation capacitor and a fourth input node connected to the second isolation capacitor.

11. A circuit operation method, the method comprising: Providing logic circuits; Receiving a first digital signal D by the logic circuit; generating a first intermediate signal at a first intermediate node A1 by the logic circuit; generating, by the logic circuit, a second intermediate signal opposite to the first intermediate signal at a second intermediate node A2; The logic circuit generates a second digital signal D D , the second digital signal D D Corresponding to the first digital signal D plus a predetermined delay time TD1; Wherein, the logic circuit is referenced to the first ground G1; The logic circuit is further configured to control the first intermediate signal, the second intermediate signal and the second digital signal D in response to the first digital signal D. D , so that: When the first digital signal D is converted from a low state to a high state, the first intermediate signal is converted from a high state to a low state, and remains in the low state for the predetermined delay time TD1; When the second digital signal D D When the first digital signal D is in a high state while the first intermediate signal is in a low state, the first intermediate signal is converted from a low state to a high state and remains in a high state; When the second digital signal D D When the first digital signal D is in a low state, the first intermediate signal is converted from a high state to a low state. 12 . The method of claim 11 , further comprising providing a first isolation capacitor coupled between the first intermediate node A1 and a first input terminal of an output circuit.

13. The method of claim 12, further comprising providing a second isolation capacitor coupled between the second intermediate node A2 and a second input of the output circuit.

14. The method according to claim 13, wherein: The first isolation capacitor is configured to transmit the first intermediate signal to the first input terminal of the output circuit, and the second isolation capacitor is configured to transmit the second intermediate signal to the second input terminal of the output circuit.

15. The method according to claim 14, wherein: The output circuit is referenced to a second ground G2 and is configured to generate an output signal OUT corresponding to the first digital signal D.

16. The method of claim 15, further comprising providing a first impedance element coupled between the first input of the output circuit and a bias voltage source referenced to the second ground G2.

17. The method of claim 16, further comprising providing a second impedance element coupled between the second input of the output circuit and the bias voltage source.

18. The method according to claim 17, wherein: The output circuit includes a first comparator having a first input node connected to the first isolation capacitor and a second input node connected to the second isolation capacitor.

19. The method according to claim 18, wherein: The output circuit also includes a second comparator having a third input node connected to the first isolation capacitor and a fourth input node connected to the second isolation capacitor.

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