Neural signal detection circuit for outputting time-difference data or neural data

Abstract

A neural signal detection circuit capable of outputting time-difference data or neural data includes a first time circuit and a second time circuit. The first time circuit is used to store the detection voltage energy of a first period and a second period as the time-difference data. The second time circuit is used to store the detection voltage energy of the second period as the neural data. The neural signal detection circuit is used to output the time-difference data or the neural data in different operating modes.

Description

Technical Field

[0001] The present invention relates to a detection circuit, and more particularly to a neural signal detection circuit capable of selectively outputting a pulse width signal corresponding to time-differential data and / or neural data. Background Art

[0002] With the development of neuroscience, cognitive psychology, and artificial intelligence research, electroencephalogram (EEG) signals have gradually been applied to the fields of medical diagnosis and neurobiology.

[0003] Generally, voltage signals can be collected using electrodes as the electroencephalogram signals.

[0004] Electrodes that can be used to collect voltage signals include dry electrodes and wet electrodes. Compared with using wet electrodes for detection, since using dry electrodes for detection does not require a conductive medium, the complexity of preparing for detection is significantly reduced, and the preparation time can be shortened.

[0005] Since EEG signals are in the millivolt range, how to accurately and quickly obtain clean electroencephalogram signals is a problem. In addition, analyzing and processing the collected voltage signals is another problem. Summary of the Invention

[0006] The present invention provides a neural signal detection circuit capable of outputting time-differential data and / or neural data.

[0007] The present invention provides a neural signal detection circuit including an electrode, a first time circuit, a second time circuit, a first comparator, and a second comparator. The electrode is used to generate a detection voltage. The first time circuit includes a first capacitor having a first end coupled to the electrode. The second time circuit includes a second capacitor having a first end coupled to the electrode. The first comparator includes a first input transistor and a second input transistor. The first input transistor is disposed within the first time circuit and connected to the second end of the first capacitor. The second input transistor is disposed outside the first time circuit and shared with other neural signal detection circuits. The second comparator includes a third input transistor and a fourth input transistor. The third input transistor is disposed within the second time circuit and connected to the second end of the second capacitor. The fourth input transistor is disposed outside the second time circuit and shared with the other neural signal detection circuits.

[0008] The present invention also provides a neural signal detection circuit including an electrode, a first timing circuit, and a second timing circuit. The electrode is used to generate a detection voltage. The first timing circuit includes a first capacitor having a first terminal coupled to the electrode. The second timing circuit includes a second capacitor having a first terminal coupled to the electrode. The second terminal of the first capacitor is coupled to the inverting input terminal of a first comparator, which is configured outside the neural signal detection circuit and shared by the first timing circuit and other neural signal detection circuits. The second terminal of the second capacitor is coupled to the inverting input terminal of a second comparator, which is configured outside the neural signal detection circuit and shared by the second timing circuit and the other neural signal detection circuits.

[0009] The present invention also provides a neural signal detection circuit including a source follower, a first timing circuit, and a second timing circuit. The first timing circuit includes a first capacitor having a first terminal coupled to the source follower. The second timing circuit includes a second capacitor having a first terminal coupled to the source follower. The second terminal of the first capacitor is coupled to the inverting input terminal of a first comparator, which is configured outside the neural signal detection circuit and shared by the first timing circuit and other neural signal detection circuits. The second terminal of the second capacitor is coupled to the inverting input terminal of a second comparator, which is configured outside the neural signal detection circuit and shared by the second timing circuit and the other neural signal detection circuits.

[0010] In the present invention, the electrode is selected from dry electrodes and wet electrodes. In one embodiment, the detection voltage generated by the electrode is first amplified and filtered, and then transferred to the timing circuit.

[0011] In order to make the above and other objects, features, and advantages of the present invention more obvious, the following will be described in detail with reference to the accompanying drawings. In addition, in the description of the present invention, the same components are denoted by the same reference numerals, which are hereby stated in advance. Description of the Drawings

[0012] Figure 1 is a block diagram of the circuit architecture of the neural signal detection circuit according to an embodiment of the present invention;

[0013] Figure 2 is a circuit diagram of the neural signal detection circuit according to an embodiment of the present invention;

[0014] Figure 3 is a circuit diagram of the timing circuit of the neural signal detection circuit according to an embodiment of the present invention;

[0015] Figure 4A is Figure 3 the operation timing diagram of the timing circuit;

[0016] Figure 4B is Figure 2 The operation timing diagram of the neural signal detection circuit;

[0017] Figure 5 is the circuit diagram of the subtraction circuit of the neural signal detection circuit according to an embodiment of the present invention;

[0018] Figure 6 is the circuit diagram of the addition circuit of the neural signal detection circuit according to an embodiment of the present invention;

[0019] Figure 7 is the circuit diagram of the absolute difference circuit of the neural signal detection circuit according to an embodiment of the present invention;

[0020] Figure 8 is the circuit diagram of the recursive operation circuit of the neural signal detection circuit according to an embodiment of the present invention;

[0021] Figure 9 is Figure 8 The operation timing diagram of the recursive operation circuit;

[0022] Figure 10 is the schematic diagram of an application of the neural signal detection circuit according to an embodiment of the present invention;

[0023] Figures 11A to 11C is the flowchart of different modes executed using the neural signal detection circuit according to an embodiment of the present invention;

[0024] Figure 12 is the schematic diagram of outputting time difference data or neural data using the neural signal detection circuit according to an embodiment of the present invention;

[0025] Figure 13 is Figure 12 The signal timing diagram of the neural signal detection circuit;

[0026] Figure 14 is the schematic diagram of performing time difference detection using the detection array of the neural signal detection circuit according to an embodiment of the present invention;

[0027] Figure 15 is the circuit diagram of Variant I of the neural signal detection circuit of the present invention;

[0028] Figure 16 is Figure 15 The signal timing diagram of the neural signal detection circuit;

[0029] Figure 17 is the circuit diagram of Variant II of the neural signal detection circuit of the present invention;

[0030] Figure 18 is the circuit diagram of Variant III of the neural signal detection circuit of the present invention; and

[0031] Figure 19 This is the circuit diagram of Variant IV of the neural signal detection circuit of the present invention.

[0032] Explanation of reference numerals

[0033] 10, 200 Neural signal detection circuit

[0034] 12 Operational circuit

[0035] 14 Judgment circuit

[0036] 2a First time circuit

[0037] 2b Second time circuit

[0038] SWrst Reset transistor

[0039] SWt Transfer transistor

[0040] A First detection signal

[0041] B Second detection signal

[0042] T1, T2 Pulse width Detailed implementation

[0043] The present invention relates to a neural signal detection circuit for performing analog operations on neural signals. Each detection circuit outputs a detection signal with a pulse width corresponding to a detection voltage. The operational circuit performs analog operations on the pulse width signal. After the voltage value after the analog operation is converted into a pulse width signal through a voltage-time conversion circuit, the next analog operation can be performed by the same or other operational circuits. Thus, all data operations can be completed at the analog stage without first converting to digital data.

[0044] Please refer to Figure 1 as shown, which is a block diagram of the circuit architecture of the neural signal detection circuit (sometimes simply referred to as the detection circuit) according to an embodiment of the present invention. The circuit architecture includes a neural signal detection circuit 10 and an operational circuit 12. The neural signal detection circuit 10 is used to output detection signals in different periods. For example Figure 1 signals A and B in represent different detection signals detected in different periods. In the present invention, the detection signals A and B respectively represent the magnitude of the voltage energy detected by the neural signal detection circuit 10 with pulse widths T1 and T2. Among them, when the detected voltage energy is greater, the pulse width of the corresponding detection signal A or B is wider.

[0045] The operational circuit 12 includes any circuit for performing operations between signals. For example, in the description of the present invention Figure 5 the subtraction circuit in Figure 6The addition circuit and Figure 7 the absolute difference circuit will be described, but not limited thereto. In a detection array including a plurality of detection circuits, the arithmetic circuit 12 can be configured within each detection circuit to process the data within the detection circuit, or configured between the detection circuits to process the data between the detection circuits.

[0046] In some embodiments, the circuit architecture may further include a judgment circuit 14. The judgment circuit 14 includes, for example, a comparator, and is used to compare the output result of the arithmetic circuit 12 with a predetermined threshold to judge the operating state of the device applying the circuit architecture of the present invention. For example, the judgment circuit 14 can be used to judge whether the electrode is picked up. The output result of the arithmetic circuit 12 represents the voltage energy change. When the judgment circuit 14 judges that the voltage energy change is greater than or less than the threshold, it is judged that the electrode is picked up. The judgment circuit 14 then outputs a control signal for corresponding control, for example, outputs a voltage signal, etc., but is not limited thereto.

[0047] Please refer to Figure 2 , which is the circuit diagram of the neural signal detection circuit 200 according to an embodiment of the present invention. The neural signal detection circuit 200 is used to output pulse width signals A and B, that is, detection signals. The neural signal detection circuit 200 includes an electrode ED, a transfer transistor SWt, a reset transistor SWrst, a first time circuit 2a, and a second time circuit 2b connected to a node V FD .

[0048] The electrode ED is used to generate a detection voltage. The detection voltage passes through the transfer transistor SWt and is respectively stored in the first time circuit 2a and the second time circuit 2b during different periods (for example, controlled by a control signal TX). In the present invention, in addition to storing the voltage energy detected during different periods, the first time circuit 2a and the second time circuit 2b also convert the stored voltage energy into detection signals A and B with corresponding pulse widths (for example, T1 and T2) respectively for the arithmetic circuit 12 to perform analog operations. The first time circuit 2a and the second time circuit 2b have the same circuit configuration, only the operating periods are different.

[0049] The first time circuit 2a stores the first detection voltage (for example, V Figure 4B shown in SA ) generated by the electrode ED during the first period (for example, T Figure 4B shown in SIG1 [[ID=2⑥]]), and outputs a first detection signal A with a first pulse width T1 according to the first detection voltage V Figure 4B shown in O1 during the operation period (for example, T SIG1 ).

[0050] The second time circuit 2b stores the second detection voltage (for example, VFigure 4B The displayed T SB ) stores the second detection voltage generated by the storage electrode ED (e.g., refer to Figure 4B The displayed V SIG2 ), and during the operation T O1 According to the second detection voltage V SIG2 Output a second detection signal B with a second pulse width T2. It can be understood that the lengths of T1 and T2 in the figure are only illustrative and not intended to limit the present invention.

[0051] The reset transistor SWrst is coupled between the voltage source V DD and the node V FD for resetting the first time circuit 2a during the first period T SA and resetting the second time circuit 2b during the second period T SB

[0052] The transfer transistor SWt is coupled between the electrode ED and the node V FD for transferring the first detection voltage V SA to the first time circuit 2a for storage during the first period T SIG1 and transferring the second detection voltage V SB to the second time circuit 2b for storage during the second period T SIG2 . Thereby, the neural signal detection circuit 200 can be used to store the detection voltage energy in different periods to represent the change of the detected neural signal over time.

[0053] In some embodiments, the first time circuit 2a further includes a first inverter INV1 coupled between the output terminal of the first time circuit 2a and the arithmetic circuit 12 for inverting the first detection signal A; the second time circuit 2b further includes a second inverter INV2 coupled between the output terminal of the second time circuit 2b and the arithmetic circuit 12 for inverting the second detection signal B. In other embodiments, the first inverter INV1 and the second inverter INV2 are disposed in the arithmetic circuit 12 instead of in the first time circuit 2a and the second time circuit 2b.

[0054] Please refer to Figure 3 and Figure 4A simultaneously, Figure 3 is the circuit diagram of the time circuit (e.g., 2a and 2b) of the neural signal detection circuit according to an embodiment of the present invention; Figure 4A is Figure 3 the operation timing diagram of the time circuit 2a / 2b of Figure 2 It must be noted that although Figure 3 ​A single-time circuit outputs a pulse-width signal A or B.

[0055] In the present invention, Figure 3 and Figure 4A are used to Figure 2 describe the operation modes of the time circuits 2a and 2b.

[0056] The time circuits 2a and 2b each include a storage capacitor C, a first transistor SW1, a second transistor SW2, and a third transistor SW3. The storage capacitor and the first to third transistors are respectively denoted by different reference numerals in Figure 2 to distinguish the time circuits to which they belong.

[0057] One end of the storage capacitor C (shown as the first capacitor C1 in the first time circuit 2a and as the second capacitor C2 in the second time circuit 2b) is connected to the reset transistor SWrst. The storage capacitor C is used to store the voltage energy generated by the electrode ED, such as the first detection voltage V SIG1 or the second detection voltage V SIG2 .

[0058] The first transistor SW1 (shown as SWa1 in the first time circuit 2a and as SWb1 in the second time circuit 2b) is coupled between the voltage source V DD and the node V X . It is controlled by the control signal BIAS (shown as BIAS1 in the first time circuit 2a and as BIAS2 in the second time circuit 2b) to convert the stored voltage energy into a detection signal, such as the first detection signal A or the second detection signal B.

[0059] The second transistor SW2 (shown as SWa2 in the first time circuit 2a and as SWb2 in the second time circuit 2b) is coupled between the storage capacitor C and the first transistor SW1 and is controlled by the control signal AZ (shown as AZ1 in the first time circuit 2a and as AZ2 in the second time circuit 2b). During the first period T SA , the second transistor SWb2 is non-conductive to avoid changing the energy stored in the second capacitor C2. During the second period T SB , the second transistor SWa2 is non-conductive to avoid changing the energy stored in the first capacitor C1.

[0060] The third transistor SW3 (shown as SWa3 in the first time circuit 2a and as SWb3 in the second time circuit 2b) is coupled between the second end of the storage capacitor C and the ground voltage.

[0061] Please refer again to Figure 4A, the operation of its display time circuit 2a / 2b includes a reset period, an energy transfer period, an energy storage period, and a transfer pulse period. During the reset period, the control signals BIAS, RESET, and AZ are at a high level to reset the potential on the storage capacitor C, for example, the potential of node V FD is reset to V RESET (e.g., equal to V DD ) and the potential of node V G is reset to V AZ . During the energy transfer period, the control signal RESET changes to a low level. When the control signal TX changes to a high level, the voltage energy V SIG detected by the electrode ED is transferred to node V FD through the transfer transistor SWt, increasing the potential thereon to V RESET +V SIG , where V SIG represents the detected voltage energy. During the energy storage period, the control signal RESET changes back to a high level and the control signals BIAS and AZ change to a low level to store the voltage energy V SIG to node V G , decreasing the potential thereon to V AZ -V SIG . At this time, if the control signal AZ is maintained at a low level to turn off the second transistor SW2, the potential of the storage capacitor C remains approximately unchanged.

[0062] Figure 4A In, the reset period, the energy transfer period, and the energy storage period are collectively used as the energy storage period T SA of the first time circuit 2a or as the energy storage period T SB of the second time circuit 2b. Before the operation of the arithmetic circuit 12 starts, the first time circuit 2a and the second time circuit 2b sequentially store the voltage energy detected by the electrode ED. As Figure 4A shows, after the operation starts and enters the transfer pulse period, the first detected voltage V SIG1 in the first time circuit 2a is only converted into the first detection signal A and the second detected voltage V SIG2 in the second time circuit 2b is only converted into the second detection signal B.

[0063] During the transfer pulse period, the control signal BIAS uses a ramp signal whose voltage level decreases with time. When the control signal BIAS starts to change to a high level (e.g., V BIAS_AZ ), the current I1 flowing through the first transistor SW1 is less than the current I3 flowing through the third transistor SW3, causing the output voltage V Xis at a low level. As the voltage level of the control signal BIAS gradually decreases, the current I1 gradually increases until the current I1 is approximately equal to the current I3, and the output voltage V X changes to a high level, forming a negative pulse width signal. When the output voltage V X passes through the inverter INV, a positive pulse width signal as shown in Figure 4A can be generated, where the pulse width ΔT is positively correlated with the voltage energy V SIG . Thus, the time circuits 2a and 2b of the embodiments of the present invention convert the voltage energy detected by the electrode ED into a time signal for the arithmetic circuit 12 to perform arithmetic operations.

[0064] Please refer to Figure 4B , which is the operating timing diagram of the neural signal detection circuit 200 of Figure 2 . The first time circuit 2a stores the first detection voltage V SA to the first capacitor C1 according to the operating mode of Figure 4A during the first period (such as the energy storage period T SIG1 ). The second time circuit 2b stores the second detection voltage V SB to the second capacitor C2 according to the operating mode of Figure 4A during the second period (such as the energy storage period T SIG2 ). Then, during the first arithmetic period T O1 , the first time circuit 2a uses a ramp signal with a voltage level decreasing over time as the control signal BIAS1 to convert the first detection voltage V SIG1 into the first detection signal A, while the second time circuit 2b uses a ramp signal with a voltage level decreasing over time as the control signal BIAS2 to convert the second detection voltage V SIG2 into the second detection signal B. Preferably, the ramp signals BIAS1 and BIAS2 are substantially in-phase to generate the detection signals A and B substantially simultaneously, but this is not limited thereto. The detection signals A and B can be generated sequentially according to the arithmetic operations performed by the arithmetic circuit 12. The arithmetic circuit 12 then performs numerical calculations on the first detection signal A and the second detection signal B during the first arithmetic period T O1 , such as addition, subtraction, and absolute difference operations exemplified in the present invention, but the present invention is not limited to these operations.

[0065] As shown in Figure 4B , during the first arithmetic period T O1 , the first period T SIG1 storing the first detection voltage V SA is earlier than the second period T SIG2 storing the second detection voltage V SB .

[0066] In one embodiment, during the first arithmetic period TO1 After completion, the second timing circuit 2b continues to store the second detection voltage V SIG2 , and the first timing circuit 2a stores the next first detection voltage V SA ' also according to the operating mode of Figure 4A to the first capacitor C1 during the next energy storage period T SIG1 '. Then, during the second operation period T O2 , the first timing circuit 2a uses a ramp signal with a voltage level decreasing over time as the control signal BIAS1 to convert the first detection voltage V SIG1 ' into the first detection signal A', while the second timing circuit 2b uses a ramp signal with a voltage level decreasing over time as the control signal BIAS2 to convert the second detection voltage V SIG2 into the second detection signal B, which is substantially the same as the signal generated during the first operation period T O1 . The arithmetic circuit 12 then performs a numerical calculation on the first detection signal A' and the second detection signal B during the second operation period T O2 . During the second operation period T O2 , the first period T SIG1 ' for storing the first detection voltage V SA ' is later than the second period T SIG2 for storing the second detection voltage V SB .

[0067] During the next energy storage period, the first detection voltage V SIG1 ' of the first timing circuit 2a is maintained while the second detection voltage of the second timing circuit 2b is updated to V SIG2 '. As shown in Figure 4B , by repeatedly updating the voltage energy stored in the first timing circuit 2a and the second timing circuit 2b, numerical calculations can be performed on signals at different times.

[0068] Please refer to Figure 5As shown, it is the circuit diagram of the subtraction circuit 500 according to an embodiment of the present invention. It has two input terminals respectively coupled to the first time circuit 2a and the second time circuit 2b to receive a first detection signal A with a first pulse width T1 and a second detection signal B with a second pulse width T2 respectively. The subtraction circuit 500 includes an operational capacitor Co and a first operational transistor SWA and a second operational transistor SWB connected in series with each other. Among them, the operational capacitor Co is connected between the first operational transistor SWA and the second operational transistor SWB. The first operational transistor SWA is used as a switch to control the charging time of the operational capacitor Co by a first current Ic according to the first pulse width T1; the second operational transistor SWB is used as a switch to control the discharging time of the operational capacitor Co by a second current Id according to the second pulse width T2, where the first current Ic is approximately equal to the second current Id. Thereby, the subtraction circuit 500 can perform the numerical calculation of A - B. It can be understood that when the subtraction circuit 500 is used to perform the numerical calculation of B - A, the input signals received by the gates of the first operational transistor SWA and the second operational transistor SWB are opposite, which can be achieved, for example, by a switching component or a multiplexer.

[0069] Please refer to Figure 6 As shown, it is the circuit diagram of the addition circuit 600 according to an embodiment of the present invention. It has two input terminals respectively coupled to the first time circuit 2a and the second time circuit 2b to receive a first detection signal A with a first pulse width T1 and a second detection signal B with a second pulse width T2 respectively. The addition circuit 600 includes an operational capacitor Co and a first operational transistor SWA and a second operational transistor SWB connected in parallel with each other. Among them, the operational capacitor Co is connected between the first operational transistor SWA and the second operational transistor SWB. The first operational transistor SWA is used as a switch to control the first charging time of the operational capacitor Co by a first current Ic1 according to the first pulse width T1; the second operational transistor SWB is used as a switch to control the second charging time of the operational capacitor Co by a second current Ic2 according to the second pulse width T2, where the first current Ic1 is approximately equal to the second current Ic2. Thereby, the addition circuit 600 can perform the numerical calculation of A + B.

[0070] Please refer to Figure 7As shown, it is the circuit diagram of the absolute difference circuit 700 according to an embodiment of the present invention. It has two sets of input terminals respectively coupled to the first time circuit 2a and the second time circuit 2b to receive the first detection signals A and Abar with the first pulse width T1 and the second detection signals B and Bbar with the second pulse width T2. Among them, Abar and Bbar can be generated from A and B respectively using inverters, or vice versa. When the first pulse width T1 is greater than the second pulse width T2, the first set of input terminals (including the operational transistors SWA and SWBbar) receive the pulse width signals A and Bbar to control the first charging time of the operational capacitor Co by the first current Ic1. When the first pulse width T1 is less than the second pulse width T2, the second set of input terminals (including the operational transistors SWB and SWAbar) receive the pulse width signals B and Abar to control the second charging time of the operational capacitor Co by the second current Ic2. Thus, the absolute difference circuit 700 can perform the numerical calculation of |A - B|.

[0071] Although Figures 5 to 7 the current source is shown as being implemented by controlling a transistor with the control signal PBIAS, the present invention is not limited thereto. Other current sources can also be used.

[0072] Please refer to Figure 8 , which is the circuit diagram of the recursive operation circuit 800 of the detection circuit according to an embodiment of the present invention. The recursive operation circuit 800 is connected to the operation circuit 12 to control the operation timing of the operation circuit 12 and convert the operation result (i.e., the potential stored in the operation capacitor Co) back into a pulse width signal for the next operation. For example, the pulse width output of the recursive operation circuit 800 is connected to a signal input terminal of the operation circuit 12 as Figures 5 to 7 the signal A or B.

[0073] The recursive operation circuit 800 includes a first recursive transistor SWr1, a second recursive transistor SWr2, and a third recursive transistor SWr3, and their connections are the same as those of Figure 3 the first transistor SW1, the second transistor SW2, and the third transistor SW3.

[0074] Figure 8 In, the circuit within the dashed box 81 can be called a voltage - time conversion circuit, for example, which is used to convert the voltage of the operation capacitor Co into a pulse width signal similar to A and B. Among them, Figure 8 the operation capacitor Co of Figures 5 to 7 is the operation capacitor Co of

[0075] Please also refer to Figure 9 , which is Figure 8The operation timing diagram of the recursive operation circuit 800. Before performing numerical calculations on the first detection signal A and the second detection signal B output by the first time circuit 2a and the second time circuit 2b using the operation capacitor Co, the operation capacitor Co needs to be reset first. During the operation reset, the control signals AZr and BIASr change to the high level, which is used to reset the potential of the operation capacitor Co to V AZ . In this embodiment, the second recursive transistor SWr2 is used as the operation reset transistor to reset the potential of the operation capacitor Co during the operation reset. During the numerical calculation period (for example, the slanted part), the control signal AZr changes to the low level, and the operation result of the operation circuit 12 is stored in the operation capacitor Co to change its potential, where the amplitude of the potential change is related to the operation result. Then, during the energy storage period, the operation capacitor Co continuously maintains the potential after the operation until the start of the next operation, and the voltage-time conversion circuit 81 converts the potential after the operation into a pulse width signal for the operation circuit 12 to perform operations. The operation modes of the energy storage period and the pulse conversion period of the recursive operation circuit 800 are the same as those of Figure 4A the energy storage period and the pulse conversion period of, for example, using a ramp signal to generate a pulse width signal, so it will not be elaborated here.

[0076] In one embodiment, the recursive operation circuit 800 may further include an inverter INV for inverting the output pulse width signal. However, when the operation circuit 12 includes an inverter, the recursive operation circuit 800 does not include the inverter INV.

[0077] In the present invention, Figure 4A the pulse conversion period of and Figure 9 the operation reset period and the numerical calculation period of can be collectively referred to as the operation period To, where Figure 9 the operation of the operation reset period of can be performed simultaneously with or subsequent to the operation of Figure 4A the pulse conversion period of.

[0078] It can be understood that if the recursive operation circuit 800 does not need to perform the next operation, the recursive operation circuit 800 can directly provide (for example, controlled by a switch component) the potential after the calculation of the operation capacitor Co to the judgment circuit 14 for judgment, for example, by comparing with a reference potential through a comparator.

[0079] The present invention refers to Figure 8 the circuit as a recursive operation circuit because the operation result of the operation circuit 12 can pass through the recursive operation circuit 800 for storage and conversion into a pulse width signal multiple times to perform multiple recursive operations. That is, the operation circuit 12 not only calculates the detection result of the electrode ED, but can also perform another operation on its own operation result and the operation results of other detection circuits.

[0080] Thus, by usingFigure 2 The neural signal detection circuit 200 is paired with Figure 8 the recursive operation circuit 800, which can directly perform various operations on neural data at the analog level for various applications. The judgment circuit 14 directly makes various judgments based on the final operation results of the neural signal detection circuit 200 paired with the recursive operation circuit 800. For example, it can perform judgments such as electrode lifting judgment and multi-layer neural network operation to implement the circuit architecture for in-circuit operations.

[0081] For example, referring to Figure 10 as shown, it shows a schematic diagram of the application of the neural signal detection circuit of the present invention in array detection. The detection array includes a plurality of detection circuits arranged in an array. The judgment circuit 14 performs detection based on, for example, 9 adjacent detection circuits, including circuit 0 to circuit 8, where circuit 0 is the middle detection circuit of circuit 1 to circuit 8. In this embodiment, circuit 0 to circuit 8 respectively include Figure 2 the neural signal detection circuit 200 and / or at least one operation circuit 12.

[0082] As described above, circuit 0 to circuit 8 respectively generate the first detection signals A0 to A8 and the second detection signals B0 to B8. The first detection signals A0 to A8 and the second detection signals B0 to B8 of circuit 0 to circuit 8 are subjected to numerical calculation by the subtraction circuit 500 (for example, included in the neural signal detection circuit of circuit 0 to circuit 8, but not limited thereto), and the subtraction results of Y0 to Y8 can be respectively obtained and stored in the corresponding operation capacitor Co (for example Figure 8 the Co of). Among them, Y0 to Y8 represent the time difference operation of the detection signals during different detections of each circuit 0 to circuit 8 to represent the voltage energy change detected by each detection circuit.

[0083] Next, after converting Y0 to Y8 into pulse width signals through the recursive operation circuit 800, through the absolute difference circuit 700, absolute difference numerical calculations are respectively performed on Y0 and Y1, Y0 and Y2,..., Y0 and Y8 to obtain Y01 to Y08. Among them, Y01 to Y08 represent the spatial difference operation between different detection circuits of the detection array, and Y01 to Y08 include the operation results of time and space differences.

[0084] Finally, Y01 to Y08 are totaled by the addition circuit 600. Similarly, Y01 to Y08 are first stored in the corresponding operation capacitor Co, and then converted into pulse width signals by the voltage-time conversion circuit 81 for the addition circuit 600 to perform addition operations.

[0085] In one embodiment, the addition circuit 600 is as Figure 6It is shown that there are two signal input terminals. After performing the addition operation of two of Y01 to Y08 each time, the result is stored and then voltage-time conversion is carried out, and then the addition operation is performed with the next one remaining among Y01 to Y08 until all the addition operations are completed.

[0086] In another embodiment, the addition circuit includes 8 input terminals and uses the pulse widths related to Y01 to Y08 to control the charging time of the respective current sources for the operational capacitors to add Y01 to Y08.

[0087] The judgment circuit 14 receives the addition operation result of the addition circuit 600 and compares the sum with a predetermined threshold value (for example, using a comparator). When the sum of Y01 to Y08 is greater than or equal to the predetermined threshold value, it indicates that a change in the electroencephalogram is detected.

[0088] In another embodiment, the judgment circuit 14 receives the sum of the time differences Y0 to Y8 (for example, Y0 to Y8 are directly output from circuit 0 to circuit 8 to the addition circuit 600). When the sum is greater than or less than the threshold value, it indicates that the electrode is picked up.

[0089] It can be understood that Figure 10 in the electroencephalogram detection or pick-up detection is performed based on the time and spatial brightness changes detected by 9 adjacent detection circuits, but the present invention is not limited thereto. The judgment circuit 14 can perform detection according to the time and spatial voltage changes of an appropriate number of detection circuits, and it can be set according to the detection environment and the size of the detection array.

[0090] Figure 2 In the neural signal detection circuit 200 of the embodiment of the present invention in, according to different control signals, it can operate in different modes, including outputting neural data as shown in Figure 11A , outputting differential data as shown in Figure 11B , and judging whether to output neural data as shown in Figure 11C , where mode III can be regarded as a combination of mode I and mode II.

[0091] Figure 12 In, it is shown that the first time circuit 2a outputs differential data D Figure 4B during the output period (for example, during the period T O1 ), and the second time circuit 2b outputs neural data D diff during the output period. In the next output period (for example, during the period T nueral ), the first time circuit 2a outputs neural data D Figure 4B and the second time circuit 2b outputs differential data D O2 ), and so on, alternating repeatedly. nueral while the second time circuit 2b outputs differential data D diff , and this repeats alternately.

[0092] That is,Figures 11A to 11C The circuit swapping shown in diff refers to the recording and output of differential data D nueral and neural data D

[0093] Figure 12 of the neural signal detection circuit 1200 is the same as Figure 2 except that the control signal is changed to obtain different output signals from the two time circuits. In addition, to label different time circuits, Figure 12 in

[0094] please refer to Figure 13 shown, which is Figure 12 the signal timing diagram of the neural signal detection circuit 1200, which includes a first period and a second period of recording voltage energy, and three signal output periods, including a differential data reading period, a differential check period, and a neural data reading period.

[0095] During the reset detection period of the first period, the electrode ED operates and resets the voltage of node V Figure 13 to V FD and the voltage of node V RESET to V G_R through the configuration of the control signals BIAS_R, RESET, and AZ_R shown in AZ .

[0096] During the energy transfer period of the first period, the voltage energy V Figure 13 is transferred to node V REF through the transfer transistor SWt by the configuration of the control signals BIAS_R, RESET, and AZ_R shown in FD to change the potential thereon to V RESET +V REF .

[0097] During the reset detection period of the second period, the electrode ED operates again and resets the voltage of node V FD to V RESET again. At this time, since the storage capacitor C1 is floating (AZ_R turns to a low level), corresponding to the change in the voltage V FD of node V REF , the voltage of node V G_R simultaneously decreases by V REF to become V AZ -V REF .

[0098] During the energy transfer period of the second period, the voltage energy V NEW is transferred to the node V FD through the transfer transistor SWt, causing the potential thereon to change to V RESET +V NEW , where the meaning of V REF is similar to that of Figure 4B V SIG1 while the meaning of V NEW is similar to that of Figure 4B V SIG2 , except that here both V REF and V NEW are transferred to the node V FD . At this time, since the storage capacitor C1 is still floating, the voltage of the node V G_R changes simultaneously to V AZ +(V NEW -V REF ). That is, the node V G_R records the change in voltage energy (V NEW -V REF ) detected by the electrode ED in the first and second periods.

[0099] Next, by selecting the control signal BIAS_R or BIAS_N, different modes of operation in Figures 11A to 11C can be selected.

[0100] Figure 11A In mode I of NEW , the detected voltage energy V NEW of the second-time circuit 2b is read. Since this detected voltage energy V FD is not differentiated from the voltage energy detected in other periods, it can be considered as the neural data detected by the neural signal detection circuit 1200 in the second period.

[0101] Please refer to NEW again. During the energy transfer period of the second period, the voltage of the node V RESET is formed as V FD -V RESET . During the period of reading neural data, the storage capacitor C2 is floating (AZ_N changes to a low level). When the voltage of the node V FD is reset to V REF , corresponding to the voltage change V G_N of the node V NEW , the voltage of the node V AZ simultaneously decreases by V NEW to form V NEW -V Figure 4AUsing the same method, a ramp signal is used as the control signal BIAS_N to input the first transistor SW1_N to output a pulse width signal Tneural, the length of which corresponds to the voltage energy V NEW of the size. Since it has been described above, it will not be elaborated here. The pulse width signal Tneural can be simulated and operated by other arithmetic circuits as described above or used for other applications by the backend processor.

[0102] In the next period, when the electrode ED is operating, new neural data is recorded in the first time circuit 2a and new differential data is recorded in the second time circuit 2b. Using the same method as Figure 4A described above, a ramp signal is used as the control signal BIAS_R to input the first transistor SW1_R to output a time signal (i.e., a pulse width signal) Tneural as the neural data output by the neural signal detection circuit 1200.

[0103] Figure 11B In mode II of NEW -, the voltage energy difference (V REF ) of the first time circuit 2a is read.

[0104] Please refer to Figure 13 again. During the energy transfer period of the second period, the voltage change of the node V G_R is V AZ +(V NEW -V REF ). During the period of reading the differential data, using a similar method as Figure 4A described above, a ramp signal is used as the control signal BIAS_R to input the first transistor SW1_R to output a time signal Tdiff, the length of which corresponds to the magnitude of the voltage energy difference (V NEW -V REF ). Since it has been described above, it will not be elaborated here.

[0105] It must be noted that during the period of reading the differential data, according to the voltage energy detected by the electrode ED in different periods, the voltage energy difference (V NEW -V REF ) may be positive or negative. In order to be able to output a corresponding pulse width signal (the pulse width has no negative value) when (V NEW -V REF ) is negative, the start of the ramp signal does not start from V AZP , but a voltage offset value Voff is added. Although Figure 13 shows that the pulse width signal Tdiff is proportional to Voff+(V NEW -V REF ), when Voff is a fixed value, the pulse width signal Tdiff is essentially only related to (V NEW-V REF ) is related to

[0106] It must be noted that although Figure 13 it is shown that the ramp control signals BIAS_R and BIAS_N start after the voltage deep, which is used to create the starting point of the ramp signal.

[0107] In the next period, when the electrode ED is operating, the new differential data D diff is recorded in the second time circuit 2b while the new neural data D nueral is recorded in the first time circuit 2a. Using the same method as Figure 4A described, the ramp signal is input as the control signal BIAS_N to the first transistor SW1_N to output the time signal Tdiff as the differential data output by the neural signal detection circuit 1200.

[0108] Figure 11C In mode III of NEW -V REF ), according to the differential signal (V

[0109] Please refer to again Figure 13 as shown, during the differential check period, the voltage V AZP of the control signal BIAS_R is added to and subtracted from the voltage threshold Vth to compare with V AZ +(V NEW -V REF ). When the change amount of (V NEW -V REF ) is greater than Vth, the differential signal D diff will change state, for example, from 1 to 0 or from 0 to 1, indicating that the neural signal detection circuit 1200 detects a voltage energy change between the first period and the second period. Therefore, the subsequent processor reads the neural data recorded in the second time circuit 2b of the neural signal detection circuit 1200 at the node V G_N during the period of reading the neural data.

[0110] If the change amount of (V NEW -V REF ) is not greater than Vth, the voltage value of the node V G_N is not read and the voltage energy is continuously detected in the next period, as Figure 11C shown.

[0111] Similarly, in the next period, when the electrode ED is operating, the storage positions of the differential data and the neural data are swapped. The back-end processor then determines whether the voltage energy change is greater than or equal to the threshold Vth based on the differential signal Ddiff of the second time circuit 2b, so as to decide whether to read the neural data Dnueral from the first time circuit 2a.

[0112] It should be noted that Figure 13 it is not necessary to execute all of the differential data reading period, the differential checking period, and the neural data reading period. At least one of them can be executed according to different applications.

[0113] For example, referring to Figure 14 as shown, when the detection array includes multiple neural signal detection circuits 1200 (or 1500, 1700, 1800, 1900 described later), according to Figure 13 the differential checking shown can confirm whether each neural signal detection circuit 1200 detects a voltage energy change between the first frame and the second frame, that is, to judge whether the signal D diff has a state transition.

[0114] In one implementation, the back-end processor (such as the above-mentioned judgment circuit or the back-end host) tags the neural signal detection circuits 1200 that detect a sufficient voltage energy change. For example Figure 14 it is shown that there are five (marked with arrow symbols) detection circuits in the detection array that detect a voltage energy change, that is, the differential signal D diff has a state transition.

[0115] In another implementation, the back-end processor only reads the neural data (i.e., the pulse width signal) of the neural signal detection circuits 1200 that detect a voltage energy change for updating the neural data stored in the corresponding frame buffer at the back-end. The neural data of the neural signal detection circuits 1200 that do not detect a voltage energy change are not read by the back-end processor.

[0116] It should be noted that the usage methods of the back-end processor for the neural signal detection circuits 1200 that detect a sufficient voltage energy change and their neural data can be determined according to different applications.

[0117] In summary, since the neural signal detection circuit 1200 of the present invention includes two time circuits, after performing reset detection and energy transfer in two different periods, it can record time differential data (or signals) and neural data respectively. By selecting different control signals BIAS_R and BIAS_N (such as using a switch or a multiplexer), different Figures 11A to 11C operation modes can be executed.

[0118] Please refer toFigure 15 As shown, this is Variant 1500 of the neural signal detection circuit according to an embodiment of the present invention. It can also perform Figures 11A to 11C operations in different modes according to different control signals BIAS_R and BIAS_N.

[0119] Figure 15 The difference between the neural signal detection circuit 1500 and Figure 12 the neural signal detection circuit 1200 is that a comparator is used to replace Figure 12 the first transistors SW1_R, SW1_N and the third transistors SW3_R, SW3_N. Figure 15 The circuit in the upper right shows the structure of two comparators and their input signals. The inverting input terminal of comparator CMP1 is connected to the second terminal of the first capacitor C1 and the second transistor SW2_R, and the non-inverting input terminal of comparator CMP1 receives the control signal BIAS_R. The inverting input terminal of comparator CMP2 is connected to the second terminal of the second capacitor C2 and the second transistor SW2_N, and the non-inverting input terminal of comparator CMP2 receives the control signal BIAS_N. Relatively Figure 12 , this embodiment can reduce the influence of current and noise.

[0120] Please refer to Figure 16 as shown, which is Figure 15 the signal timing diagram of the neural signal detection circuit 1500.

[0121] Similarly, during the first period, the electrode ED operates and forms a voltage VRESET + VREF at the node VFD through the Figure 16 configuration of the control signals BIAS_R, RESET and AZ_R shown. During the second period, the electrode ED operates again and forms a voltage VAZ + (VNEW - VREF) at the node VG_R through the Figure 16 configuration of the control signals BIAS_R, RESET and AZ_R shown.

[0122] During the period of reading neural data, the storage capacitor C2 is floating (AZ_N turns to low level). When the voltage of the node VFD is reset to VRESET, corresponding to the voltage change VREF of the node VFD, the voltage of the node VG_N decreases by VNEW at the same time to form VAZ - VNEW. A ramp signal is used as the control signal BIAS_N and input to the comparator CMP2 so that the comparator CMP2 outputs a time signal Tneural.

[0123] During the period of reading differential data, a ramp signal is used as the control signal BIAS_R and input to the comparator CMP1 so that the comparator CMP1 outputs a time signal Tdiff.

[0124] During differential checking, the voltage VAZ is added to and subtracted from the voltage threshold Vth as the control signal BIAS_R for comparison with VAZ+(VNEW-VREF). When the change amount of (VNEW-VREF) is greater than Vth, the differential signal Ddiff will change state.

[0125] Reading differential data, differential checking, and reading neural data are similar to Figure 13 , and the main difference is that the control signals BIAS_R and BIAS_N are different.

[0126] Figure 15 In [reference], all transistors of the comparators CMP1 and CMP2 are arranged within the neural signal detection circuit 1500, thus increasing the area of the neural signal detection circuit 1500.

[0127] Please refer to Figure 17 As shown, it is a modified example 1700 of the neural signal detection circuit according to an embodiment of the present invention. It mainly arranges Figure 15 the first input transistor SWc1 and the third input transistor SWc3 of the comparator within the neural signal detection circuit 1700, and arranges the other transistors of the comparator outside the neural signal detection circuit 1700 and shares them with other neural signal detection circuits. The other neural signal detection circuits are multiple neural signal detection circuits located in the same column as the neural signal detection circuit 1700 (for example Figure 1 the same column of the detection array in [reference]).

[0128] The signal timing diagram of the neural signal detection circuit 1700 is also shown in ​ .

[0129] In this modified example, the neural signal detection circuit 1700 includes an electrode ED, a transfer transistor SWt, a reset transistor SWrst, a first timing circuit 172a, and a second timing circuit 172b.

[0130] The first timing circuit 172a includes a first capacitor (or storage capacitor) C1 and a second transistor SW2_R, and their functions are respectively similar to those of the components C1 and SWa2 in ​ [reference], so they will not be elaborated here. The first capacitor C1 has a first end (for example ​ shown as its left end) coupled to the electrode ED.

[0131] The first timing circuit 172a further includes a first input transistor SWc1, which serves as the inverting input terminal of the first comparator and is connected to the second end of the first capacitor C1 (for example ​showing its right end). The first comparator further includes a second input transistor SWc2, and transistors T1 and T2 are arranged outside the neural signal detection circuit 1700 and shared by the first timing circuit 172a and other neural signal detection circuits. The second input transistor SWc2 serves as the non-inverting input terminal of the first comparator.

[0132] The second timing circuit 172b includes a second capacitor (or storage capacitor) C2 and a second transistor SW2_N, whose functions are the same as those of the components C2 and SWb2 of ​ respectively, so they will not be described in detail here. The second capacitor C2 has a first end (for example ​ showing its left end) coupled to the electrode ED.

[0133] The second timing circuit 172b further includes a third input transistor SWc3, which serves as the inverting input terminal of the second comparator and is connected to the second end of the second capacitor C2 (for example ​ showing its right end). The second comparator further includes a fourth input transistor SWc4, and transistors T3 and T4 are arranged outside the neural signal detection circuit 1700 and shared by the second timing circuit 172b and the other neural signal detection circuits. The fourth input transistor SWc4 serves as the non-inverting input terminal of the second comparator.

[0134] The electrode ED is used to generate a detection voltage, including ​ the VREF and VNEW shown.

[0135] The transfer transistor SWt is connected between the electrode ED, the first end of the first capacitor C1, and the first end of the second capacitor C2. As ​ shown, the transfer transistor SWt is used to transfer the detection voltage (including VREF and VNEW) to the first timing circuit 172a during the first period and the second period (VRESET + VREF and VRESET + VNEW shown at the node VFD respectively) and transfer the detection voltage (including VNEW) to the second timing circuit 172b during the second period (VRESET + VNEW shown at the node VFD).

[0136] The reset transistor SWrst is connected between the transfer transistor SWt, the first end of the first capacitor C1, and the first end of the second capacitor C2. The function of the reset transistor SWt has been described above, so it will not be described in detail.

[0137] The second transistor SW2_R is connected between the first capacitor C1 and the first input transistor SWc1, where the second transistor SW2_R of the first timing circuit 172a is non-conductive during the second period. ​The control signal AZ_R shown is at a low level during the second period. The second transistor SW2_N is connected between the second capacitor C2 and the third input transistor SWc3, where the second transistor SW2_N of the second timing circuit 172b is non-conductive during the first period. ​ The control signal AZ_N shown is at a low level during the first period.

[0138] In this embodiment, the first timing circuit 172a is used to record the voltage energy change of the voltage energy detected by the electrode ED between the first period and the second period, as ​ shown, when the transfer transistor SWt is turned on during the second period, the voltage of the node VG_R changes to VAZ+(VNEW-VREF), where VAZ is the voltage on the node VG_R during the reset period. The second timing circuit 172b is used to record the detected voltage of the electrode ED during the second period, as ​ shown, when the node VFD is reset to the voltage VRESET during the period of reading neural data, the voltage of the node VG_N changes to VAZ-VNEW.

[0139] According to the input signal of the second input transistor SWc2, the neural signal detection circuit 1700 can operate in different modes, as ​ and ​ shown. When the second input transistor SWc2 receives a ramp signal (as shown during the period of reading differential data in ​ ), the first timing circuit 172a outputs a pulse width signal Tdiff corresponding to the voltage energy change (VNEW-VREF). As mentioned above, since (VNEW-VREF) may be negative, a bias value Voff is added to the starting point of the ramp signal.

[0140] When the second input transistor SWc2 sequentially receives the lower threshold voltage VAZ-Vth and the upper threshold voltage VAZ+Vth (as shown during the period of reading check differential in ​ ), it can be confirmed whether the voltage energy change (VNEW-VREF) exceeds the voltage threshold Vth. When VAZ+(VNEW-VREF) does not exceed the range of the upper threshold voltage VAZ+Vth and the lower threshold voltage VAZ-Vth, the output signal Ddiff does not change state, indicating that the neural signal detection circuit 1700 does not detect sufficient energy change; when VAZ+(VNEW-VREF) exceeds the range of the upper threshold voltage VAZ+Vth or the lower threshold voltage VAZ-Vth, the output signal Diff changes state, indicating that the neural signal detection circuit 1700 detects an energy change, and the subsequent processor can perform corresponding operations based on this.

[0141] According to the input signal of the fourth input transistor SWc4, the neural signal detection circuit 1700 can operate in another mode, as​ as shown. When the fourth input transistor SWc4 receives a ramp signal (as shown during the reading of neural data in ​ ), the second timing circuit 172b outputs a pulse width signal Tneural corresponding to the detected voltage energy VNEW. Since the detected voltage energy VNEW does not undergo differential operation and thus does not have negative values, there is no need to add a bias value Voff.

[0142] In one embodiment, the first timing circuit 172a further includes row selection transistors SWrs_R (shown as two) connected between the first timing circuit 172a and the first comparator. The row selection transistors SWrs_R are used to connect the first timing circuit 172a and the first comparator according to the row selection signal RS. The second timing circuit 172b further includes row selection transistors SWrs_N (shown as two) connected between the second timing circuit 172b and the second comparator. The row selection transistors SWrs_N are used to connect the second timing circuit 172b and the second comparator according to the row selection signal RS.

[0143] For the operations of the neural signal detection circuit 1700 not described, reference can be made to ​ as shown.

[0144] Please refer to ​ as shown, which is a modified example 1800 of the neural signal detection circuit according to an embodiment of the present invention. It mainly disposes all of the first comparator and the second comparator outside the neural signal detection circuit 1800 and shares them with other neural signal detection circuits. The other neural signal detection circuits are multiple neural signal detection circuits located in the same column as the neural signal detection circuit 1800 (for example, ​ the same column of the detection array in ​ ).

[0145] The signal timing diagram of the neural signal detection circuit 1800 is also shown in ​ .

[0146] The neural signal detection circuit 1800 includes an electrode ED, a transfer transistor SWt, a reset transistor SWrst, a first timing circuit 182a, and a second timing circuit 182b.

[0147] The first timing circuit 182a includes a first capacitor C1 and a second transistor SW2_R, whose functions are respectively similar to those of the components C1 and SWa2 in ​ , so they will not be elaborated here. The first capacitor C1 has a first end (for example, ​ shown as its left end) coupled to the electrode ED.

[0148] The second end of the first capacitor C1 of the first timing circuit 182a (for example, ​couples to the inverting input terminal of the first comparator CMP1 (showing its right end). The first comparator CMP1 is configured outside the neural signal detection circuit 1800 and is shared by the first timing circuit 182a and the other neural signal detection circuits.

[0149] The second timing circuit 182b includes a second capacitor C2 and a second transistor SW2_N, whose functions are respectively similar to those of the components C2 and SWb2 ​ in, so they will not be elaborated here. The second capacitor C2 has a first terminal (for example ​ showing its left end) coupled to the electrode ED.

[0150] The second terminal of the second capacitor C2 of the second timing circuit 182b (for example ​ showing its right end) couples to the inverting input terminal of the second comparator CMP2. The second comparator CMP2 is configured outside the neural signal detection circuit 1800 and is shared by the second timing circuit 182b and the other neural signal detection circuits.

[0151] The electrode ED is used to generate a detection voltage, including ​ the VREF and VNEW shown.

[0152] The transfer transistor SWt is connected between the electrode ED and the first terminals of the first capacitor C1 and the second capacitor C2. As ​ shown, the transfer transistor SWt is used to transfer voltage energy (including VREF and VNEW) to the first timing circuit 182a (VRESET+VREF and VRESET+VNEW shown at the node VFD respectively) during the first period and the second period and transfer voltage energy (including VNEW) to the second timing circuit 182b (VRESET+VNEW shown at the node VFD) during the second period.

[0153] The reset transistor SWrst is connected between the transfer transistor SWt and the first terminals of the first capacitor C1 and the second capacitor C2. The function of the reset transistor SWt has been described above, so it will not be elaborated again.

[0154] The second transistor SW2_R is connected between the first capacitor C1 and the first comparator CMP1, where the second transistor SW2_R of the first timing circuit 182a is not turned on during the second period, as ​ shown, the control signal AZ_R is at a low level during the second period. The second transistor SW2_N is connected between the second capacitor C2 and the second comparator CMP2, where the second transistor SW2_N of the second timing circuit 182b is not turned on during the first period, ​ shown, the control signal AZ_N is at a low level during the first period.

[0155] In this embodiment, the first timing circuit 182a is used to record the voltage energy change of the voltage energy detected by the electrode ED between the first period and the second period. As ​ shown, when the transfer transistor SWt is turned on during the second period, the voltage on the node VG_R becomes VAZ+(VNEW-VREF), where VAZ is the voltage on the node VG_R during the reset period. The second timing circuit 182b is used to record the detected voltage of the electrode ED during the second period. As ​ shown, when the node VFD is reset to the voltage VRESET during the period of reading neural data, the voltage of the node VG_N becomes VAZ-VNEW.

[0156] According to the input signal of the non-inverting input terminal of the first comparator CMP1, the neural signal detection circuit 1800 can operate in different modes. As ​ shown. For example, when the non-inverting input terminal of the first comparator CMP1 receives a ramp signal (as ​ shown during the period of reading differential data), the first timing circuit 182a outputs a pulse width signal Tdiff corresponding to the voltage energy change (VNEW-VREF). As described above, (VNEW-VREF) may be negative, and the bias value Voff is added to the starting point of the ramp signal.

[0157] When the non-inverting input terminal of the first comparator CMP1 sequentially receives the lower threshold voltage VAZ-Vth and the upper threshold voltage VAZ+Vth (as ​ shown during the period of reading check differential), it can be confirmed whether the voltage energy change (VNEW-VREF) exceeds the voltage threshold Vth. When VAZ+(VNEW-VREF) does not exceed the range of the upper threshold voltage VAZ+Vth and the lower threshold voltage VAZ-Vth, the output signal Ddiff does not change state, indicating that the neural signal detection circuit 1800 does not detect sufficient energy change; when VAZ+(VNEW-VREF) exceeds the upper threshold voltage VAZ+Vth or the lower threshold voltage VAZ-Vth, the output signal Ddiff changes state, indicating that the neural signal detection circuit 1800 detects energy change, and the subsequent processor can perform corresponding operations accordingly.

[0158] It should be noted that the input order of the upper threshold voltage and the lower threshold voltage has no specific limitation.

[0159] According to the input signal of the non-inverting input terminal of the second comparator CMP2, the neural signal detection circuit 1800 can operate in another mode. As ​ shown, when the non-inverting input terminal of the second comparator CMP2 receives a ramp signal (as ​As shown during the reading of neural data, the second timing circuit 182b outputs a pulse width signal Tneural corresponding to the detected voltage energy VNEW. Since the detected voltage energy VNEW does not undergo differential operation and thus does not have negative values, there is no need to add the bias voltage value Voff.

[0160] To buffer the voltage on the first capacitor C1 without loss to the capacitor C3 for storage, the first timing circuit 182a further includes a first source follower SF_R connected between the first capacitor C1, the second transistor SW2_R, and the first comparator CMP1. To buffer the voltage on the second capacitor C2 without loss to the capacitor C4 for storage, the second timing circuit 182b further includes a second source follower SF_N connected between the second capacitor C2, the second transistor SW2_N, and the second comparator CMP2.

[0161] In one embodiment, the first timing circuit 182a further includes a row selection transistor SWrs_R connected between the first source follower SF_R and the first comparator CMP1. The row selection transistor SWrs_R is used to conduct the first source follower SF_R and the first comparator CMP1 according to the row selection signal RS. The second timing circuit 182b further includes a row selection transistor SWrs_N connected between the second source follower SF_N and the second comparator CMP2. The row selection transistor SWrs_N is used to conduct the second source follower SF_N and the second comparator CMP2 according to the row selection signal RS.

[0162] Regarding the operations not described for the neural signal detection circuit 1800, reference can be made to ​ as shown.

[0163] ​ In a modification of [], the first comparator CMP1 and the second comparator CMP2 are arranged outside the neural signal detection circuit 1800 and shared with other neural signal detection circuits. Therefore, ​ During the operation of [], the operations in the first period and the second period are performed within the neural signal detection circuit 1800, while the reading of differential data, differential check, and reading of neural data in the output stage (i.e., conducting the row selection transistor SWrs_R or SWrs_N) are mainly performed outside the neural signal detection circuit 1800.

[0164] Multiple neural signal detection circuits 1800 in a detection circuit column sequentially use the comparator CMP1 or CMP2 to output a time signal or a differential check signal according to the row selection signal RS.

[0165] Please refer to ​ as shown, which is a modification 1900 of the neural signal detection circuit according to an embodiment of the present invention, and it mainly ​In the neural signal detection circuit 1800, a source follower SF is additionally arranged and connected between the transfer transistor SWt and the first capacitor C1 of the first time circuit 192a and the second capacitor C2 of the second time circuit 192b, so as to buffer the voltage on the node VFD losslessly to the first capacitor C1 and the second capacitor C2 to improve the sensitivity and conversion gain of the neural signal detection circuit.

[0166] ​ The rest of it is the same as that in ​ and its operation can also refer to ​ , so it will not be elaborated here.

[0167] ​ In a modification of, the second end of the first capacitor C1 is coupled to the inverting input terminal of the first comparator CMP1, and the first comparator CMP1 is arranged outside the neural signal detection circuit 1900 and shared by the first time circuit 192a and other neural signal detection circuits. The second end of the second capacitor C2 is coupled to the inverting input terminal of the second comparator CMP2, and the second comparator CMP2 is arranged outside the neural signal detection circuit 1900 and shared by the second time circuit 192b and other neural signal detection circuits. The said other neural signal detection circuits are multiple neural signal detection circuits located in the same column as the neural signal detection circuit 1900 (for example ​ the same column of the detection array of

[0168] It should be noted that the operation of the above neural signal detection circuits 1500, 1700, 1800 and 1900 can be applied to each detection circuit of the detection array such as ​ of the detection array.

[0169] It should be noted that since the storage locations of the time difference data and the neural data will be interchanged, in the first cycle, it is also possible that the first time circuit records the neural data and the second time circuit records the time difference data.

[0170] It should be noted that in the description of the present invention, a component being within the neural signal detection circuit means that each detection circuit of the detection array includes such a component, and a component being outside the neural signal detection circuit means that a column of detection circuits of the detection array shares such a component.

[0171] The present invention is also applicable to a retina chip, as long as the sensing component (i.e., the electrode) is replaced by an optical sensing component, for example, the photodiode mentioned in the parent application, and its details have been described in the parent application, so it will not be elaborated here.

[0172] In summary, processing and analyzing electroencephalogram signals is an important task. Therefore, the present invention also provides a neural signal detection circuit that can output a pulse width signal and perform analog operations on neural signals ( ​and ​ 、 ​ and ​ ).

[0173] Although the present invention has been disclosed by the foregoing examples, it is not intended to limit the present invention. Any person having ordinary knowledge and skill in the technical field to which the present invention pertains may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the appended claims.

Claims

1. A neural signal detection circuit, the neural signal detection circuit comprising: An electrode for generating a detection voltage; A first timing circuit, the first timing circuit comprising: A first capacitor having a first terminal coupled to the electrode; A second timing circuit, the second timing circuit comprising: A second capacitor having a first terminal coupled to the electrode; A transfer transistor connected between the electrode and the first terminal of the first capacitor and the first terminal of the second capacitor for transferring the detection voltage to the first timing circuit during a first period and a second period and transferring the detection voltage to the second timing circuit during the second period; A reset transistor connected between the transfer transistor and the first terminal of the first capacitor and the first terminal of the second capacitor; A first comparator, the first comparator comprising: A first input transistor configured within the first timing circuit and connected to a second terminal of the first capacitor, the first input transistor serving as the inverting input terminal of the first comparator; And A second input transistor configured outside the first timing circuit and shared with other neural signal detection circuits, the second input transistor serving as the non-inverting input terminal of the first comparator; and A second comparator, the second comparator comprising: A third input transistor configured within the second timing circuit and connected to a second terminal of the second capacitor, the third input transistor serving as the inverting input terminal of the second comparator; And A fourth input transistor configured outside the second timing circuit and shared with the other neural signal detection circuits, the fourth input transistor serving as the non-inverting input terminal of the second comparator, wherein The first timing circuit further comprises a second transistor connected between the first capacitor and the first input transistor, The second timing circuit further comprises a second transistor connected between the second capacitor and the third input transistor, The first timing circuit is configured to record the voltage energy change of the electrode between the first period and the second period, and The second timing circuit is configured to record the detection voltage of the electrode during the second period.

2. The neural signal detection circuit according to claim 1, wherein The other neural signal detection circuits are a plurality of neural signal detection circuits in the same column of the detection array as the neural signal detection circuit 3. The neural signal detection circuit according to claim 1, wherein The second transistor of the first timing circuit is not conducting during the second period, and the second transistor of the second timing circuit is not conducting during the first period.

4. The nerve signal detection circuit according to claim 1, wherein, The second input transistor is configured to Receive a ramp signal to cause the first timing circuit to output a pulse width signal corresponding to the voltage energy change, or Sequentially receive an upper threshold voltage and a lower threshold voltage to confirm whether the voltage energy change exceeds the upper threshold voltage or the lower threshold voltage.

5. The neural signal detection circuit according to claim 1, wherein the fourth input transistor is configured to receive a ramp signal, so that the second timing circuit outputs a pulse width signal corresponding to the detection voltage.

6. The neural signal detection circuit according to claim 1, further comprising a plurality of row selection transistors connected between the first timing circuit and the first comparator and between the second timing circuit and the second comparator.

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