Silicon photonic structure and manufacturing method thereof and wafer-level system

Abstract

Embodiments of the present invention disclose an apparatus and method for a silicon photonic (SiPh) structure, which includes the integration of the following: an electronic integrated circuit (EIC); a photonic integrated circuit (PIC), which is placed on top of the electronic integrated circuit; two or more polymer waveguides (PWG), which are placed on top of the photonic integrated circuit and are formed by a cladding polymer layer and a core polymer layer; and an integrated fan-out redistribution (InFO RDL) layer, which is placed on top of the two or more polymer waveguides. The operation of the polymer waveguide is based on the refractive index of the cladding polymer and the core polymer. Interlayer optical signal coupling is provided by edge coupling, reflective prisms, and grating coupling. The silicon photonic structure die is implemented at the wafer level system and inter-die signal optical interconnection is provided between the polymer waveguides.

Description

Technical Field

[0001] The embodiments of the present invention relate to a silicon photonic structure and a manufacturing method thereof and a wafer-level system. Background Art

[0002] Fan-out wafer-level packaging can be used to provide a more integrated solution for placing a die (or chip) on a wafer. Fan-out wafer-level packaging is an integrated circuit packaging technology and an enhancement of the standard wafer-level packaging (WLP) solution. Compared with conventional packaging, fan-out wafer-level packaging can provide a smaller package footprint and improved thermal and electrical performance, and can allow a larger number of contacts without increasing the size of the die. In current solutions, WLP technology has evolved to build a package with an integrated fan-out type redistribution layer (InFO RDL) and a die embedded in a wafer material such as an organic laminate or silicon.

[0003] A key part of fan-out is the redistribution layer (RDL). RDL is typically a copper metal connection line or wiring layer that electrically connects one part of the package to another part. RDL relies on pins or solder bumps for connection to a printed circuit board. From a cost and space perspective and due to the performance of the electrical interconnects of the RDL infrastructure within the wafer-level package, solutions based on traditional fan-out redistribution layers may be limited. However, RDL is not very suitable for supporting optical interconnects that provide higher performance than that provided by electrical interconnects. Therefore, a more efficient method is needed to provide optical interconnects within a wafer-level package containing one or optical integrated circuits.

[0004] The information disclosed in this Background section is intended only to provide context for the various embodiments of the present invention described below, and therefore, this Background section may contain information that is not necessarily prior art information (i.e., information known to one of ordinary skill in the art). Therefore, to the extent that the work is described in this Background section, the work of the presently named inventors and aspects of the description that may not otherwise qualify as prior art at the time of filing are neither explicitly nor implicitly admitted to be prior art against the present disclosure. Summary of the invention

[0005] In some embodiments, a silicon photonic structure (SiPh) includes an electronic integrated circuit (EIC), a photonic integrated circuit (PIC), at least one polymer waveguide (PWG), and an integrated fan-out redistribution layer (InFO RDL). The photonic integrated circuit is disposed on top of the electronic integrated circuit. At least one polymer waveguide is disposed on top of the photonic integrated circuit and forms a polymer bridging layer, wherein each of at least one of the polymer waveguides includes a core layer and at least two cladding layers, the core layer includes a first polymer, and at least two of the cladding layers include a second polymer surrounding the core layer. The integrated fan-out redistribution layer is disposed on top of two or more polymer waveguides.

[0006] In some embodiments, a wafer-level system includes a wafer carrier, a plurality of dies, a polymer waveguide, and an integrated fan-out redistribution layer. A plurality of dies are disposed on the wafer carrier, wherein each of the plurality of dies includes at least one photonic integrated circuit and at least one electronic integrated circuit. The polymer waveguide is coupled to the at least one photonic integrated circuit to provide inter-die optical interconnection. An integrated fan-out redistribution layer is disposed on top of each of the plurality of dies. The plurality of dies are bonded to the wafer carrier before the polymer waveguide is formed.

[0007] In some embodiments, a method of fabricating a silicon photonic structure using polymer waveguides includes the following steps: attaching a photonic integrated circuit on top of an electronic integrated circuit using hybrid die bonding to form a photonic / electronic integrated circuit package; forming a polymer waveguide bridging layer including at least one polymer waveguide and placing the polymer waveguide bridging layer on top of the photonic integrated circuit; placing at least one application specific integrated circuit within the photonic / electronic integrated circuit package; and forming an integrated fan-out redistribution layer on top of the polymer waveguide bridging layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] When read in conjunction with the accompanying drawings, the various aspects of the present disclosure are best understood from the following detailed description. It should be noted that the various features are not necessarily drawn to scale. In fact, the size and geometry of the various features may be arbitrarily increased or reduced for clarity of illustration.

[0009] Figure 1A A silicon photonic (SiPh) structure including a photonic integrated circuit (PIC), an electrical integrated circuit (EIC), and a cladding layer is shown according to some embodiments.

[0010] Figure 1B Some embodiments of the present disclosure are shown Figure 1A A SiPh structure having openings for a first set of vias in the cladding layer.

[0011] Figure 1C Some embodiments of the present disclosure are shown Figure 1B A SiPh structure is provided in which a thin copper (Cu) plated layer is formed in a first set of through holes of a cladding polymer layer.

[0012] Figure 1D Some embodiments of the present disclosure are shown Figure 1C A SiPh structure wherein a first set of through-holes are filled with plated copper (Cu) in a capping polymer layer.

[0013] Figure 1E Some embodiments of the present disclosure are shown Figure 1D A SiPh structure in which a core layer is formed on top of a cladding layer.

[0014] Figure 1F Some embodiments of the present disclosure are shown Figure 1E A SiPh structure wherein a second set of through holes are formed in the core layer and a thin plated Cu layer is formed in the openings of the second set of through holes in the core layer.

[0015] Figure 1G Some embodiments of the present disclosure are shown Figure 1F The SiPh structure, in which the repeating Figures 1A to 1D to form a polymer waveguide (PWG).

[0016] Figure 1H According to some embodiments of the present disclosure, Figure 1G SiPh structure where both ASIC and die are integrated and bonded to a glass carrier.

[0017] Figure 2A According to some embodiments of the present disclosure, Figure 1H A SiPH structure in which a PWG bridging layer is formed.

[0018] Figure 2B According to some embodiments of the present disclosure, Figure 2A A SiPh structure is shown in which an integrated fan-out redistribution layer (InFO RDL) is formed on top of a PWG bridge layer.

[0019] Figure 2C to Figure 2D An embodiment of edge coupling according to some embodiments of the present disclosure is shown.

[0020] Figure 2E , Figure 2F , Figure 2G as well as Figure 2H An embodiment of inter-layer coupling according to some embodiments of the present disclosure is shown.

[0021] Fig.2I A reflecting prism according to some embodiments of the present disclosure is shown.

[0022] Figure 3A According to some embodiments of the present disclosure, Figure 2B An embodiment of a SiPh structure in which a fiber interface is supported by an optical lens and a SiPh grating coupler.

[0023] Figure 3B According to some embodiments of the present disclosure, Figure 2B Another embodiment of a SiPh structure in which the fiber interface is supported by an optical lens and a SiPh grating coupler.

[0024] Figure 3C According to some embodiments of the present disclosure, Figure 2B SiPh structure where the optical fiber is coupled to the PWG bridge layer.

[0025] Figure 4A The electronic integrated circuit according to some embodiments of the present disclosure is modified according to Figure 3A SiPh structure.

[0026] Figure 4B The electronic integrated circuit according to some embodiments of the present disclosure is modified according to Figure 3B SiPh structure.

[0027] Figure 4C The electronic integrated circuit according to some embodiments of the present disclosure is modified according to Figure 3C SiPh structure.

[0028] Figure 5 A wafer-level system is shown in which a PWG connects a PIC on a wafer carrier according to some embodiments of the present disclosure.

[0029] Figure 6 A flow chart illustrating an exemplary method of fabricating an exemplary SiPh structure for a photonic / electronic IC package using a polymer waveguide according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0030] Various exemplary embodiments of the present disclosure are described below with reference to the accompanying drawings so that a person of ordinary skill in the art can make and use the present disclosure. As will be apparent to a person of ordinary skill in the art, after reading the present disclosure, various changes or modifications may be made to the examples described herein without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the exemplary embodiments and applications described and shown herein. In addition, the specific order and / or hierarchy of the steps in the method disclosed herein are only exemplary methods. Based on design preferences, the specific order or hierarchy of the steps of the disclosed method or process may be rearranged while remaining within the scope of the present disclosure. Therefore, a person of ordinary skill in the art will understand that the methods and techniques disclosed herein present various steps or actions in a sample order, and unless otherwise explicitly stated, the present disclosure is not limited to the specific order or hierarchy presented. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0031] The following disclosure describes various exemplary embodiments for implementing the different features of the subject matter. The following describes specific examples of components and arrangements to simplify the present disclosure. Of course, these components and arrangements are only examples and are not intended to be restrictive. For example, it should be understood that when an element is referred to as "connected to" another element or "coupled to" another element, it can be directly connected to another element or coupled to another element, or one or more intervening elements may exist. In addition, for ease of description, the spatial relative terms such as "beneath", "below", "lower", "bottom", "underneath", "above", "upper", etc. can be used herein to describe the relationship between an element or feature and another element or feature as shown in the figure. In addition to the orientation depicted in the figure, the spatial relative terms are intended to cover the different orientations of the device in use or operation.

[0032] According to some embodiments, the semiconductor package design includes integrated fan out (InFO), wafer-level system integration technology platform, and high-density redistribution layer (RDL). In some embodiments, through-silicon vias (TSV) are included for high-density interconnect and performance for various applications such as mobile high-performance computing. The InFO platform provides various packaging solutions for 2D and 3D optimized for specific applications.

[0033] Embodiments described herein disclose structures and process flows for integrated photonic-electronic IC packages using polymer waveguides. According to various embodiments, substantially higher communication performance and more compact structures can be achieved in a wafer-level platform using optical interconnects provided by polymer waveguides. These embodiments with polymer waveguides can be compatible with the InFO platform. Additionally, polymer waveguides can support interlayer optical coupling in wafer-level systems. According to various embodiments, technologies for interlayer coupling include concave / convex bumps, grating couplers, and reflective prisms.

[0034] Exemplary embodiments of PIC packages integrated by using polymer waveguides are described herein. The exemplary embodiments discussed herein include the following topics of silicon photonics (SiPh), redistribution layers (RDL), through silicon vias (TSV), photonic integrated circuits (PICs), polymer waveguides, optical refractive index, and lithography. These topics are briefly discussed below.

[0035] Silicon photonics (SiPh) is a combination of silicon integrated circuits and semiconductor lasers. Compared with traditional electronic devices, silicon photonics enables faster data transmission over longer distances. SiPh technology generally uses silicon as a medium for optical signal transmission and can be a material platform for manufacturing photonic integrated circuits (PICs). Silicon can be patterned into photonic components with sub-micron precision. The main advantages of SiPh include the potential to integrate optical devices and electronic devices in the same IC, and its compatibility with existing complementary metal-oxide semiconductor (CMOS) processes in manufacturing.

[0036] Photonic integrated circuits (PICs) or integrated photonic circuits are circuits that are usually integrated with electronic integrated circuits (EICs). PICs can generate optical signals based on input from the EIC, usually in the visible spectrum or near infrared from 850 nanometers to 1650 nanometers. Unlike electronic integrated circuits, which are mainly made of silicon, system photonic integrated circuits have been manufactured from a variety of material systems, including electro-optical crystals such as lithium niobate, silicon dioxide on silicon, silicon on insulator, various polymers, and semiconductor materials used to make semiconductor lasers such as GaAs and InP.

[0037] In integrated circuit design, a via is a small opening in an insulating oxide layer that allows a conductive connection between different layers. Through silicon vias (TSVs) or through chip vias are vertical electrical connections that pass completely through a silicon wafer or die. TSVs are high-performance interconnect technologies used as an alternative to wire-bonded chips and flip chips to produce 3D packages and 3D integrated circuits. Compared to alternatives such as stacked packages, interconnect density and device density can be significantly higher, and the length of the connection can be reduced.

[0038] A redistribution layer (RDL) is an additional metal layer on a chip that makes the input / output pads of an integrated circuit available at other locations on the chip for improved access to the pads when necessary. When an integrated circuit is manufactured, it may have a set of input / output pads that are wire-bonded to the pins of the package. A redistribution layer may be an additional wiring layer on a chip that can be bonded out from different locations on the chip, making chip-to-chip bonding simpler. Another example of using an RDL is for spreading contact points around the die so that solder balls can be applied and the thermal stress of the installation can be spread. As a metal layer, the RDL supports electrical connections between many locations on an integrated circuit (IC) chip.

[0039] According to various embodiments, optically transparent polymer waveguides (PWGs) may be used to interfacing silicon photonic devices to optical fibers. Traditionally, polymer waveguides are processed onto silicon photonic wafers or bonded to chips. Polymer waveguides are typically optically patternable materials that can be fabricated into complex optical routes at a small form factor. A polymer waveguide may include a core layer and a cladding layer. The polymer of the cladding layer will be different from the polymer of the core layer. Based on this difference, the refractive index in the cladding layer may be lower than that of the core layer, so that the optical signal is transmitted in the core layer while being adjacent to the cladding layer (or surrounded by the cladding layer). The cladding layer and the core layer may have a thickness (or width) of 2 microns to 10 microns. In addition, the core layer may be stepped to support multi-mode signal transmission. As discussed herein, "cladding layer" is equivalent to "cladding polymer layer". Similarly, the term "core layer" is equivalent to "core polymer layer".

[0040] In optics, the refractive index of a material (also called refraction index / index of refraction) is a dimensionless number that describes the speed at which light propagates through a material. It is defined as N=c / v, where c is the speed of light in a vacuum and v is the phase velocity of light in the medium. For example, the refractive index of water is 1.333, meaning that light propagates 1.333 times slower in water than in a vacuum. Increasing the refractive index corresponds to decreasing the speed of light in a material. Typical polymers have a refractive index of 1.30 to 1.70, but higher refractive indices are often required for specific applications. Polymer waveguides can be designed based on a refractive index range of 1.3 to 2.0. According to various embodiments, polymers can be modified with different refractive indices to form different cladding / core structures of polymer optical waveguides.

[0041] According to various embodiments, photolithography can be used to pattern the layers of the cladding and core layers of the PWG, pattern the openings of vias, pattern the TSVs and pattern the openings to direct the optical signals to different locations. Using photolithography and photoresist coating, concave / convex topologies can be formed on the cladding polymer layers and the core polymer layers.

[0042] According to some embodiments, Figure 1A A silicon photonic (SiPh) structure 100 is shown, comprising: a photonic integrated circuit (PIC) 102; an electronic integrated circuit (EIC) 104; and a first cladding layer 106A; a plurality of through silicon vias (TSVs) 108; a first metal contact 110 disposed in a first passivation layer 114A; a second metal contact 118 disposed in a second passivation layer 114B; and a third passivation layer 116A disposed in the first passivation layer 114A and surrounding the first metal contact 110; and a fourth passivation layer 116B disposed in the second passivation layer 114B and surrounding the second metal contact 118. Figure 1A As shown in FIG. 1 , the EIC 104 is disposed under the first passivation layer 114A, which in turn is disposed under the PIC 102, which in turn is disposed under the edge coupler 111, which in turn is disposed under the cladding layer 106. Figure 1A , the edge coupler 111 is disposed over the PIC 102 between portions of the second passivation layer 114B, and will be discussed in further detail below.

[0043] According to various embodiments, cladding 106A and cladding 106B may serve as claddings for waveguides, and EIC 104 and PIC 102 may provide electronic and photonic functions, respectively, for an integrated photonic-electronic IC package, as described in further detail below.

[0044] In some embodiments, TSVs 108 have a diameter in the range of 1 micrometer (μm) to 3 micrometers. For example, in some embodiments, each TSV 108 has a diameter of 2 micrometers. Figure 1A Only two TSVs 108, two first metal structures 110, and two second metal structures 118 are shown, but it should be understood that any desired number of TSVs 108, first metal structures 110, and second metal structures 118 may be formed in the PIC 102. Each TSV 108 electrically couples one of the metal structures 110 to one of the metal structures 118. In some embodiments, the TSVs 108, metal structures 110, and metal structures 118 may be formed of gold. The TSVs 108 allow for conductive connections between conductive structures in two or more of the different layers of the SiPh structure 100, such as, but not limited to, the PIC 102, the EIC 104, and the first passivation layer 114A and the second passivation layer 114B. As discussed in further detail below, according to various embodiments, after subsequent process steps, the TSVs 108 may facilitate electrical connections between the EIC 104 and the solder bumps of the SiPh structure 100.

[0045] In some embodiments, the first passivation layer 114A, the second passivation layer 114B, the third passivation layer 116A, and the fourth passivation layer 116B each include a silicon nitride material. In some embodiments, the density of the silicon nitride material in the third passivation layer 116A and the fourth passivation layer 116B is less than the density of the silicon nitride material in the first passivation layer 114A and the second passivation layer 114B. Therefore, by surrounding each of the metal structure 110 and the metal structure 118 with the third passivation layer 116A and the fourth passivation layer 116B, respectively, the mechanical stress adjacent to the metal structure 110 and the metal structure 118 can be released.

[0046] Figure 1B According to some embodiments of the present disclosure, Figure 1A The SiPh structure 110 after performing other processing to form openings in the first cladding layer 106A to provide a first set of vias 112 and vias 113. Photolithography techniques may be used to pattern the openings in the first cladding layer 106A to form vias 112 and vias 113, which expose corresponding metal structures 118 formed in the second passivation layer 114B.

[0047] Figure 1C According to some embodiments of the present disclosure, Figure 1B The SiPh structure 110 is subjected to other processing to form thin layers of metal plating 122 and metal plating 123 in the openings of the through hole 112 and the through hole 113 of the first cladding layer 106A, respectively. In some embodiments, the metal plating 122 and the metal plating 123 include copper (Cu) metal. Figure 1C As shown in FIG. 1 , other processing includes forming a first patterned photoresist (PR) layer 124 on the top surface of the first cladding layer 106A to protect some areas from etching. After etching to expose the vias 112 and 113, a seed layer sputtering is performed to form a thin metal coating on the bottom and side surfaces of the vias 112 and 113. In some embodiments, an ashing process is then performed to remove the residue of the first PR coating 124 from the etched wafer.

[0048] Figure 1D According to some embodiments of the present disclosure, Figure 1C The SiPh structure 130 after performing other processing to completely fill the via 112 and the via 113 with the metal plating material (e.g., copper) in the first cladding layer 106A. During this other processing, the first PR coating layer 124 is removed from the first cladding layer 106A, and then the second PR coating layer is deposited to form a first PR region 126 and a second PR region 127 above the via 112 and the via 113, respectively.

[0049] Figure 1E According to some embodiments of the present disclosure, Figure 1D The SiPh structure 130 of the present invention is subjected to other processing to form the SiPh structure 140 after the core layer 107 is placed on the top of the first cladding layer 106A. As described in further detail below, according to some embodiments, the core layer 107 provides the core layer of the polymer waveguide. In order to support the design of the waveguide, the refractive index of the first cladding layer 106A is lower than the refractive index of the core layer 107. The polymer can be selected for the first cladding layer 106A and the core layer 107 so as to achieve a desired refractive index relationship. In the case where the second PR coating is deposited over the through hole 112 and the through hole 113, the contact between the core layer 107 and the through hole 112 and the through hole 113 is reduced or minimized. In some embodiments, the core polymer and / or the cladding polymer can be modified to change its corresponding refractive index. In some embodiments, the refractive index of each polymer can be modified by doping with metal ions and / or halogen ions or by changing the curing profile (e.g., time, temperature, etc.) of the polymer. Figure 1F According to some embodiments of the present disclosure, Figure 1E The SiPh structure 150 is subjected to other processing to form a second set of vias 152 and vias 153 in the core layer 107, respectively, and to form a thin layer of metal plating layer 142 and metal plating layer 143 in each of the openings of the second set of vias 152 and vias 153. The process includes: (1) depositing a third PR coating layer 145 on top of the core layer 107; (2) etching the PR coating layer 145 above the second set of vias; and then (3) performing seed layer sputtering to coat the openings of the second set of vias 152 and vias 153 with a thin layer of metal layer 142 and metal layer 143.

[0050] Figure 1G According to some embodiments of the present disclosure, Figure 1F The SiPh structure 150 performs other processing to repeat as discussed above Figures 1A to 1D The SiPh structure 160 is formed by the steps of forming a polymer waveguide (PWG) 165. Figure 1G As shown in FIG. Figures 1A to 1DThe second cladding layer 106B and another set of through holes 162 and through holes 163 are formed in the same manner as described for forming the first cladding layer 106A and the through holes 112 and 113. In this way, the PWG 165 is formed of the core layer 107 and the first cladding layer 106A and the second cladding layer 106B, respectively, so that the cladding layer 106A and the cladding layer 106B are adjacent to (or surround) the core layer 107. Hereinafter, the first cladding layer 106A and the second cladding layer 106B may be collectively referred to as the cladding layer 106. Since the refractive index in the cladding layer 106 is smaller than that in the core layer 107, the optical signal is transmitted inside the core layer 107 while being guided by the cladding layer 106. Figure 1G As shown in FIG. 1 , the PWG 165 has a plurality of metal-filled vias 112, 152, 162, 113, 153, 163 that provide electrical connections for electrical signals. Effectively, the vias 112, 152, 162, 113, 153, 163 provide PWG through-holes formed between PWG layers to provide inter-layer electrical connections.

[0051] In some embodiments, the PWG 165 can be designed based on a refractive index range of 1.3 to 2.0 and a thickness (or width) of 2 microns to 10 microns for both the cladding layer 106 and the core layer 107. In some embodiments, the core layer 107 can be stepped to support multi-mode signal transmission. As discussed above, the process steps discussed above form the PWG 165 and a plurality of through holes that provide electrical connections through the PWG 165.

[0052] Figure 1H According to some embodiments of the present disclosure, Figure 1GThe SiPh structure 160 of the embodiment of the present invention performs other processing to integrate the two ASICs 175 and ASIC 176 of the die bonded to the glass carrier 174. The PIC 102 and the EIC 104 are attached together via a hybrid bonding technique to minimize the thickness of the attached ASIC die in order to improve the yield of the SiPh structure 170. However, the thickness of the attached ASIC die can affect the wafer-level yield. In some embodiments, there is an InFO or CoWoS packaging process called "pick and place", in which a machine picks up the die and places it on a carrier, and then starts the RDL formation, molding and other processes. If the die is too thin, the die may break during the pick and place process, so thicker dies can improve the packaging level yield. In addition, in some embodiments, there may be thermal considerations that can affect the die yield based on the thickness of the attached ASIC. Effectively, the attached ASIC is a core computing block of the package. The core computing block can always be turned on under heavy load conditions that generate a lot of heat. For thicker silicon, the die can act as a local "heat sink" for the device layer and can positively affect the yield. In some embodiments, a support filler 172 may be added at the back side of the EIC 104. In some embodiments, the support filler 172 may act as a heat sink structure to dissipate heat energy from the EIC 104. According to various embodiments, the support filler 172 may be Si or Si3N4 or SiO2. In some embodiments, the support filler is made of a translucent material so that optical signals can be transmitted through the support filler 172. In some embodiments, molded / MCG plastic may provide support for the PGW 165 formation.

[0053] like Figure 1H , a plurality (e.g., six) of metal structures 177 and metal structures 178 are disposed on top of ASIC 175 and ASIC 176, respectively. SiPh structure 170 also includes vias 171 and 173 formed in PWG 165. In some embodiments, via 171 is formed by vias 112, 152, and 162 as described above, and via 173 is formed by vias 113, 153, and 163 as described above. Figure 1H There are two other corresponding sets of PWG vias and TSVs on the left side of , which can be formed in the same manner as the corresponding structures described above. The foregoing process steps mount ASIC 175 and ASIC 176 in SiPh structure 170 and bond SiPh structure 170 to glass carrier 174. In some embodiments, additional PWGs can be formed on top of PWG 165.

[0054] Figure 2A According to some embodiments of the present disclosure, Figure 1HThe SiPh structure 170 is subjected to other processing steps to form the PWG bridge layer 202 after the SiPh structure 200. Figure 2A , the PWG bridging layer 202 is formed with a second PWG 205 placed on top of the first PWG 165. Figure 2A , PWG 165 and PWG 205 have several vias. For example, via 204 and via 206 may provide electrical connections from the top of PWG bridge layer 202 to second passivation layer 114B, then to TSV 108, then to first passivation layer 114A, and then to EIC 104. Vias located on top of ASIC 175 and ASIC 176 (e.g., via 207 and via 209) electrically connect ASIC 175 and ASIC 176 to other contact structures (not shown). Collectively, PWG 165 and PWG 205 and their respective vias form PWG bridge layer 202.

[0055] Figure 2B According to some embodiments of the present disclosure, Figure 2A The SiPh structure 200 is subjected to further processing to form an integrated fan-out redistribution layer (InFO RDL) 211 disposed on top of the PWG bridge layer 202. The InFO 211 includes the same polymer as the cladding layer 106. The InFO RDL supports electrical signals and can be used to connect to the two ASICs 175 and 176 or to connect electrical signals through vias. A plurality of conductive bumps 213 that provide electrical connections between the SiPh structure 210 and other conductive structures (e.g., conductive bumps, pads, or other die lines, circuits, etc. (not shown)) are fabricated on top of the InFO RDL 211. The InFO RDL 211 provides electrical connections for the ASICs 175 and 176 via vias (such as vias 207 and vias 209) on top of the PWG bridge layer 202. In some embodiments, after forming the InFO RDL 211, the glass carrier 174 is peeled off from the bottom of the ASIC 175 and ASIC 176 and the fill 172. Thus, the SiPh structure 210 provides coupling for the PIC 102, the EIC 104, the ASIC 175, and the ASIC 176 to allow interconnection between these components. After completing the aforementioned process steps, the SiPh structure 210 represents an exemplary embodiment of a photonic / electronic IC package using a polymer waveguide.

[0056] Figure 2B Also indicated is the location of edge coupler 208 disposed within edge coupler 111, which may provide an interface between the polymer waveguide and the silicon waveguide. Figure 2CFurther discussion of edge coupling. As previously described, the PWG bridging layer 202 includes the PWG 165 and the PWG 205. Within the PWG bridging layer 202, interlayer coupling may be provided, such as Figure 2E , Figure 2F , Figure 2G as well as Figure 2H Discussion.

[0057] Figure 2C FIG. 2 shows an edge coupler 208 according to some embodiments of the present disclosure. Figure 2B , indicating the location of the edge coupler 208 in the SiPh structure 210. Figure 2C , the edge coupler 208 provides coupling between the silicon waveguide 212 and the PWG 214, which may be the PWG 165 as discussed above. The silicon waveguide 212 having a taper 216 protrudes in the PWG 214. With the pointed shape of the silicon waveguide 212, light can be "squeezed" into the PWG 214. Thus, with the edge coupler 208, light can be transmitted from the silicon waveguide 212 to the PWG 214. The edge coupler 208 has the same function as the edge coupler 111.

[0058] Figure 2D An embodiment of a grating coupler 220 according to an alternative embodiment of the present disclosure is shown. The grating coupler 220 couples an optical signal from a silicon waveguide 222 to a core layer 107, i.e., a polymer waveguide. The core layer 107 is surrounded by a cladding layer 106. The grating coupler 220 includes an upper grating structure 226 and a lower grating structure 224, respectively, wherein the direction of the light is changed by the lower grating structure 224 in the silicon waveguide 222, and the light is collected by the upper grating structure 226 in the core layer 107. Figure 2D The direction of light is shown in FIG by dashed line 228. In some embodiments, grating coupler 220 is made of a combination of silicon and polymer materials.

[0059] When comparing edge coupler 208 to grating coupler 220, grating coupler 220 requires less space but has more signal loss than edge coupler 208. Therefore, edge coupling may be preferred in situations where higher performance and less signal loss are important and the design supports the space requirements. The design and selection may be determined by the wavelength of the optical signal. For some embodiments, the wavelength may be 800 nanometers, 1310 nanometers, or 1510 nanometers.

[0060] Figure 2E , Figure 2F , Figure 2G as well as Figure 2HAn embodiment of interlayer coupling within a polymer waveguide according to some embodiments of the present disclosure is shown. The embodiments previously described herein support one layer for optical signal transmission. Using interlayer coupling, optical signals can be transmitted or coupled between several polymer layers.

[0061] Figure 2E The interlayer coupling 230 between the plurality of cladding layers 106A, 106B, 106C and the plurality of core layers 107A and 107B is shown. The polymer layer may form some concave / convex topologies on its surface to facilitate the transmission of optical signals 232 from one PWG layer to another PWG layer. Figure 2E As shown in FIG. 1 , the optical signal 232 propagates through the core layer 107A and is coupled to the core layer 107B via a relatively thin portion of the cladding layer 106B. Figure 2E As further shown in FIG. 1 , the core layer 107B bends and protrudes downward toward the core layer 107A at a relatively thin portion of the cladding layer 106B (thinner than other portions of the cladding layer 106B). The cladding layer 106A and the cladding layer 106C complete the structure of the polymer waveguide, such as Figure 2E shown in.

[0062] Figure 2F A similar embodiment of interlayer coupling 240 between multiple cladding layers 106A, cladding layers 106B, and cladding layers 106C and multiple core layers 107A and 107B is shown. The polymer layer may form some concave / convex topology on the surface to facilitate the transmission of optical signals 242 from one PWG layer to another PWG layer. Figure 2E compared to, Figure 2F Different shape patterns of the cladding and core of a polymer waveguide are shown. The direction of the optical signal 242 is tuned to the shape pattern in the polymer waveguide. Figure 2F , the optical signal 242 propagates through the core layer 107A and is coupled to the core layer 107B via the relatively thin portion of the cladding layer 106B. In this embodiment, a portion of the core layer 107A bends and protrudes upward toward the core layer 107B at the relatively thin portion of the cladding layer 106B. The cladding layer 106A and the cladding layer 106C complete the structure of the polymer waveguide.

[0063] Figure 2GA grating coupler 250 for interlayer coupling within a polymer waveguide is shown in accordance with some embodiments of the present disclosure. As shown, an optical signal 252 propagates through the core layer 107A to a lower grating structure 254 associated with the core layer 107A. Next, the direction of the optical signal 252 is changed and directed through the cladding layer 106B to an upper grating structure 256 in the core layer 107B. The upper grating structure 256 in the core layer 107B collects the optical signal 252 and changes the direction of the optical signal 252 to allow propagation through the core layer 107B. In some embodiments, all elements of the grating coupler 250 are made of a polymer or a cladding polymer or a core polymer. In contrast, in accordance with some embodiments, Figure 2D The grating coupler 220 is made of a combination of silicon and polymer.

[0064] Figure 2H An interlayer coupling structure 260 in a polymer waveguide with a reflective prism is shown. A reflective prism can be formed by locally changing the refractive index in the PWG to reflect light from one layer to another in one direction. The refractive index can be modified by various methods. For example, the modification can be changing the metal or Cu doped inside the polymer, or it can be changing the manufacturing process. In summary, a reflective prism formed by changing the refractive index in at least one of the layers of the cladding layer and the core layer allows an optical signal to be reflected from one PWG layer to another PWG layer.

[0065] like Figure 2H As shown in FIG. 2 , optical signal 262 propagates downward along core layer 107A and is reflected by first prism 264. Optical signal 262 then propagates through cladding layer 106B to core layer 107B, where optical signal 262 is reflected by second prism 266. Optical signal 262 is then directed to propagate downward along core layer 107B. Figure 2H Other coating layers in the embodiment include coating layer 106A and coating layer 106C.

[0066] Fig.2I 2 shows a reflective prism 270 according to some embodiments of the present disclosure. The reflective prism 270 includes a core layer 107 having a funnel shape, wherein the cladding layer 106 is adjacent to (or surrounds) the funnel-shaped core layer 107, and the narrower end of the funnel-shaped core layer 107 protrudes through the cladding layer material. Fig.2I As shown in FIG. 1 , when the funnel-shaped core layer 107 narrows from a first width to a second width narrower than the first width, the cladding layer 106 correspondingly becomes thicker. In some alternative embodiments, the reflective prism may be formed of glass without any polymer layer.

[0067] Figure 3A , Figure 3B as well as Figure 3C Three embodiments of SiPh packaged fiber optic interfaces are shown: (1) Figure 3A——Light propagates through the filler inside the SiPh package; (2) Figure 3B - light propagates through the cladding layer within the PWG bridge layer; and (3) Figure 3C - Optical fiber is directly coupled to the PWG bridge layer. These embodiments are further discussed in the following paragraphs.

[0068] According to some embodiments, Figure 3A The SiPh structure 300 connects the optical package to an external light source. Figure 2B 10 is similar to the SiPh structure 210 of FIG. 10 , in which the fiber interface is supported by optical lens 303A, optical lens 303B, SiPh grating coupler 304A, and SiPh grating coupler 304B. The optical signal is emitted from optical fiber 302A and optical fiber 302B and coupled to optical lens 303A and optical lens 303B, respectively. The optical signal is projected from optical lens 303A and optical lens 303B through several layers of SiPh structure 300 including support filler 172, EIC 104, passivation layer 114, PIC 102, and coupled to SiPh grating coupler 304A and SiPh grating coupler 304B, respectively. SiPh grating coupler 304A and SiPh grating coupler 304B have the same optical structure as described above with respect to FIG. Figure 2D The optical lens 303A and the optical lens 303B are formed of polymer and / or silicon according to various embodiments. In summary, the optical signals from the optical fiber 302A and the optical fiber 302B are coupled to the optical lens 303A and the optical lens 303B, respectively, which guide the corresponding optical signals through the support filler 172, the EIC 104, the PIC 102, and then reach the SiPh grating coupler 304A and the SiPh grating coupler 304B, respectively.

[0069] According to some embodiments, Figure 3B The SiPh structure 320 connects the optical package to an external light source. Figure 2B210, but with the addition of a fiber interface supported by optical lens 323A, optical lens 323B, SiPh grating coupler 324A, and SiPh grating coupler 324B. Optical signals are emitted from optical fiber 322A and optical fiber 322B and are coupled to optical lens 323A and optical lens 323B, respectively. Optical signals are projected from optical lens 323A and optical lens 323B through InFO RDL 211 and PWG bridge layer 202 and are coupled to SiPh grating coupler 324A and SiPh grating coupler 324B, respectively. SiPh grating coupler 324A and SiPh grating coupler 324B have the same optical properties as described above with respect to Figure 2D In summary, the optical fiber is coupled to each of optical lens 323A and optical lens 323B, which directs the optical signal through InFO RDL 211, through polymer bridging layer 202, to SiPh grating coupler 324A and SiPh grating coupler 324B, respectively.

[0070] According to some embodiments, Figure 3C The SiPh structure 340 connects the optical package to an external light source. Figure 2B 165, with the addition of an optical fiber 342 coupled to the PWG bridge layer 202. The optical signal is emitted from the optical fiber 342 and is directly coupled to the PWG bridge layer 202 at a lateral side portion of the PWG bridge layer 202. From the optical fiber 342 to the PWG 165, the optical signal may have active alignment. In some embodiments, a machine may track the optical intensity to ensure that the core of the optical fiber and the core of the PWG are optically aligned. From the PIC 102 to another chip at a lateral side of the package, the optical signal may be coupled from the PWG 165 to the PWG 205 and from the PWG 205 to the PWG 165, and then coupled to the lateral side of the package (e.g., Figure 3C In some embodiments, the SiPh structure 340 may be connected to another chip on the right side of the SiPh structure 340. Figure 2E , Figure 2F , Figure 2G as well as Figure 2H The coupling between PWG 165 and PWG 205 is achieved by the method disclosed in .

[0071] Figure 4A Some embodiments of the present disclosure are shown. Figure 3A The SiPh structure 300 is similar to but modified from the SiPh structure 400 of the electronic integrated circuit. Figure 3A The length of EIC 104, such as Figure 4A175 and ASIC 176. As shown, the EIC 404A and EIC 404B of ASIC 175 and ASIC 176 are shown. Therefore, the size of EIC 404A and EIC 404B can be smaller than PIC 102. As shown, to fill the resulting gap, fill gap 402A and fill gap 402B are disposed adjacent to EIC 404A and EIC 404B, respectively. The length of fill gap 402A and EIC 404A is similar to the length of PIC 102 disposed below fill gap 402A and EIC 404A. The size of fill gap 402B and EIC 404B is similar to the size of PIC 102 on the opposite side of ASIC 175 and ASIC 176. In some embodiments, fill gap 402A and fill gap 402B can be filled with Si / SiO2 / Si3N4 by deposition. In some embodiments, light can more efficiently penetrate fill gap 402A and fill gap 402B than through EIC 404A and EIC 404B. An additional benefit is that since silicon is sensitive to temperature, the filled gaps 402A, 402B can act as a heat sink for the EIC or ASIC.

[0072] Figure 4B Some embodiments of the present disclosure are shown. Figure 3B The SiPh structure 320 is similar to but modified to the SiPh structure 420 of the electronic integrated circuit. The modification is substantially the same as Figure 4A The same modifications are made to the SiPh structure 400 of FIG. 104. The length of the EIC 104 is reduced, as shown by EIC 404A and EIC 404B. Filler gaps 402A and 402B are added adjacent to EIC 404A and EIC 404B, respectively. For this embodiment, the addition of filler gaps 402A and 402B does not affect light penetration, but is beneficial as a heat sink for the EIC or ASIC.

[0073] Figure 4C Some embodiments of the present disclosure are shown. Figure 3C The SiPh structure 340 is similar to but modified from the SiPh structure 440 of the electronic integrated circuit. Figure 3C As discussed, optical fiber 342 is directly coupled to PWG bridge layer 202. PWG bridge layer 202 includes PWG 165 and PWG 205. Electronic integrated circuit modification and according to Figure 4A The modifications made to SiPh structure 400 are substantially the same. The length of EIC 104 is reduced, as shown by EIC 404A and EIC 404B. For this embodiment, the addition of filler gap 402A and filler gap 402B does not affect light penetration, but the addition is beneficial as a heat sink for the EIC or ASIC.

[0074] Figure 5A wafer-level system 500 is shown for connecting a PIC to a wafer carrier using one or more PWGs in accordance with some embodiments of the present disclosure. The method utilizes the same process flow as previously described, except that the chips (or dies) are bonded to the carrier prior to forming the PWGs. According to various embodiments, the carrier may be glass, silicon, metal, polymer, epoxy molding compound, or diamond. As shown, the chips are formed on a wafer (e.g., a 12-inch wafer) to form a system on wafer (SOW). As shown, each square represents a chip having multiple components including a PIC 502 and an EIC 504. Each chip may include different functions based on the design of the PIC and EIC and other design elements. Utilizing a system based on Figure 2B The chips are coupled via PWG 506. As an optical waveguide, PWG 506 provides faster communication, longer transmission distance and more compact structure compared to electrical connection. In terms of space and signal loss issues, a wafer-level system based only on electrical connection may require amplifiers or other components that can avoid the use of PWG.

[0075] Figure 6 Flowchart 600 shows an exemplary method for fabricating an exemplary SiPh structure for photonic / electronic IC packaging using polymer waveguides according to some embodiments of the present disclosure. The exemplary method disclosed below describes a method for fabricating an exemplary SiPh structure for photonic / electronic IC packaging. Figure 2B The process flow steps of the SiPh structure 210 are taken as an example. The exemplary method includes the following steps: Attaching the PIC 102 on top of the EIC 104 using hybrid die bonding. Passivation layer 114A is disposed between PIC 102 and EIC (step 602); TSVs are formed in PIC 102 to allow conductive connections between layers of SiPh structure 210 (e.g., cladding layer 106A and passivation layer 114A) (step 604); a PWG bridge layer 202 is formed by combining two or more PWGs (e.g., PWG 165 and PWG 205), and the two or more PWGs are placed on top of PIC 102 (step 606); vias are formed in PWG bridge layer 202 (step 608); an ASIC is placed in a photonic / electronic IC package (step 610); an InFO RDL 211 is formed on top of PWG bridge layer 202 (step 612); a support fill is attached under the EIC (step 614); and the support fill and ASIC are attached to a carrier, such as a glass carrier (step 616).

[0076] According to various embodiments of the present disclosure, the order of the steps in flowchart 600 may be changed.

[0077] In one exemplary embodiment, a silicon photonic (SiPh) structure is disclosed. This embodiment includes: an electronic integrated circuit (EIC); a photonic integrated circuit (PIC) disposed on top of the EIC; two or more polymer waveguides (PWGs) disposed on top of the PICs and forming a polymer bridge layer, wherein each of the two or more PWGs includes a core layer, the core layer including a first polymer. At least two cladding layers include a second polymer adjacent to the core layer. The SiPh structure also includes an integrated fan-out redistribution layer (InFO RDL) disposed on top of the two or more PWGs. If the refractive index based on the second polymer is less than the refractive index of the first polymer, then the optical signal propagates through the core layer, and at least one of the first polymer and the second polymer may be modified to change its respective refractive index. The layers of the first polymer and the second polymer may be patterned by photolithography to facilitate the implementation of waveguide patterns, via holes, and concave / bump topologies. The SiPh structure includes PWG perforations formed between PWG layers to provide interlayer electrical connections, and through silicon vias (TSVs) that provide electrical connections between SiPh structure layers. The SiPh structure may further include an interlayer optical signal coupler operable to transmit an optical signal from one core layer to another core layer via a cladding layer. The interlayer optical signal coupler may be fabricated with a grating coupler, wherein each grating structure is formed in a core layer and another core layer disposed between a cladding layer. The interlayer optical signal coupler may also be fabricated with a concave / convex topology formed on the surface of a layer of a first polymer and a layer of a second polymer. The interlayer optical signal coupler may also be fabricated with a reflective prism formed by changing the refractive index in at least one of two or more PWGs.

[0078] In some embodiments, the polymers used for the two or more polymer waveguides are designed for a refractive index range of 1.3 to 2.0. In some embodiments, at least one of the first polymer and the second polymer is modified to change its respective refractive index. In some embodiments, the layers of the second polymer and the first polymer are patterned by photolithography to facilitate the implementation of waveguide patterns, through-hole holes, and concave / convex topologies. In some embodiments, the silicon photonic structure further includes polymer waveguide perforations formed between two or more layers of the polymer waveguides to provide interlayer electrical connections. In some embodiments, at least one of the polymer waveguides includes a first polymer waveguide and a second polymer waveguide formed above the first polymer waveguide, and the silicon photonic structure further includes an interlayer optical signal coupler, the interlayer optical signal coupler being operable to transmit an optical signal from a first core layer of the first polymer waveguide to a second core layer of the second polymer waveguide via at least one of the cladding layers. In some embodiments, the interlayer optical signal coupler includes a grating coupler having a first grating structure formed in one core layer and a second grating structure formed in another core layer. In some embodiments, the interlayer optical signal coupler is fabricated with a concave / convex topology formed on the surface of the layer of the first polymer and the layer of the second polymer. In some embodiments, the interlayer optical signal coupler is fabricated with a reflective prism in two or more of the polymer waveguides, wherein the reflective prism is formed by changing the refractive index in at least one of the first polymer waveguide and the second polymer waveguide. In some embodiments, the silicon photonic structure further includes a through silicon via (TSV) providing electrical connection between two or more layers of the silicon photonic structure. In some embodiments, the core layer has a funnel shape, and the cladding layer is adjacent to the funnel-shaped core layer, and the narrower end of the funnel-shaped core layer protrudes through the first cladding layer to provide a reflective prism. In some embodiments, the silicon photonic structure further includes an optical lens and a silicon photonic grating coupler, wherein an optical fiber is coupled to the optical lens that guides the optical signal through the supporting filler, the electronic integrated circuit, and the photonic integrated circuit to the silicon photonic grating coupler. In some embodiments, the silicon photonic structure further comprises an optical lens and a silicon photonic grating coupler, wherein an optical fiber is coupled to the optical lens that guides the optical signal through the integrated fan-out redistribution layer and the polymer bridge layer to the silicon photonic grating coupler. In some embodiments, the optical lens is formed of polymer and silicon. In some embodiments, the silicon photonic structure further comprises an optical fiber coupled to the polymer bridge layer.

[0079] In another embodiment, a wafer-level system includes: a wafer carrier; a plurality of dies disposed on the wafer, wherein each of the plurality of dies includes at least one photonic integrated circuit (PIC) and at least one electronic integrated circuit (EIC); a polymer waveguide coupled to at least one PIC to provide inter-die optical interconnect; and an integrated fan-out redistribution layer (InFO RDL) disposed on top of each of the plurality of dies. The plurality of dies are bonded on the wafer carrier prior to forming the polymer waveguide. The wafer carrier includes glass, silicon, metal, polymer, epoxy molding compound, or diamond.

[0080] In some embodiments, the wafer carrier comprises at least one of glass, silicon, metal, polymer, epoxy molding compound, and diamond.

[0081] In yet another embodiment, a method of manufacturing a SiPh structure using a polymer waveguide may include the following steps: attaching a voice integrated circuit (PIC) on top of an electronic integrated circuit (EIC) using hybrid die bonding, wherein a passive layer 114A is disposed between the PIC 102 and the EIC; forming through silicon vias (TSVs) in the PIC to allow conductive connections between the cladding layer and the passivation layer; forming a polymer waveguide (PWG) bridge layer including two or more PWGs on top of the PIC; forming vias within the PWGs of the PWG bridge layer; placing an ASIC in a photonic / electronic IC package; forming an integrated fan-out redistribution layer (InFO RDL) on top of the PWG bridge layer; attaching a support filler under the EIC; and attaching the support filler and the ASIC to a carrier, such as a glass carrier.

[0082] In yet another embodiment, a method of manufacturing a SiPh structure using polymer waveguides may include the following steps: attaching a photonic integrated circuit (PIC) on top of an electronic integrated circuit (EIC) using hybrid die bonding to form a photonic / electronic integrated circuit (IC) package; forming a polymer waveguide bridging layer including at least one polymer waveguide (PWG) and placing the polymer waveguide bridging layer on top of the photonic integrated circuit; placing at least one application specific integrated circuit within the photonic / electronic integrated circuit package; and forming an integrated fan-out redistribution layer (InFO RDL) on top of the polymer waveguide bridging layer.

[0083] In some embodiments, the method of fabricating a silicon photonic structure using a polymer waveguide further comprises: forming a through hole in the polymer waveguide bridging layer; and forming a through silicon via (TSV) in the photonic integrated circuit to allow conductive connections between silicon photonic structure layers. In some embodiments, the method of fabricating a silicon photonic structure using a polymer waveguide further comprises: forming a support filler below the electronic integrated circuit; and attaching the support filler and the at least one application specific integrated circuit to a carrier.

[0084] The foregoing summarizes the features of several embodiments so that those of ordinary skill in the art may better understand aspects of the present disclosure. Those of ordinary skill in the art will appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those of ordinary skill in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications may be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. A silicon photonic structure, comprising: Electronic integrated circuits; a photonic integrated circuit disposed on top of the electronic integrated circuit; at least one polymer waveguide disposed on top of the photonic integrated circuit and forming a polymer bridging layer, wherein the at least one polymer waveguide comprises a core layer and at least two cladding layers, the core layer comprising a first polymer, and at least two of the cladding layers comprising a second polymer surrounding the core layer; an integrated fan-out redistribution layer disposed on top of the at least one polymer waveguide; at least one optical lens to direct light through the integrated fan-out redistribution layer; as well as A silicon photonic grating coupler comprises a first grating structure and a second grating structure, wherein light from the at least one optical lens is received by the first grating structure of the silicon photonic grating coupler, and the first grating structure of the silicon photonic grating coupler changes the direction of the light so that the light is collected by the second grating structure of the silicon photonic grating coupler to guide the light between the photonic integrated circuit and the at least one polymer waveguide.

2. The silicon photonic structure of claim 1, wherein the polymer used for the at least one polymer waveguide is designed for a refractive index range of 1.3 to 2.

0.

3. The silicon photonic structure of claim 1, wherein at least one of the first polymer and the second polymer is modified to change its respective refractive index.

4. The silicon photonic structure of claim 1, wherein the layers of the second polymer and the first polymer are patterned by photolithography to facilitate implementation of waveguide patterns, via holes, and concave / bump topologies. 5 . The silicon photonic structure of claim 1 , further comprising polymer waveguide vias formed between layers of the polymer waveguide to provide inter-layer electrical connections.

6. The silicon photonic structure according to claim 1, wherein the at least one polymer waveguide comprises a first polymer waveguide and a second polymer waveguide formed above the first polymer waveguide, and the silicon photonic structure further comprises an interlayer optical signal coupler, wherein the interlayer optical signal coupler is operable to transmit an optical signal from a first core layer of the first polymer waveguide to a second core layer of the second polymer waveguide via at least one of the cladding layers.

7. The silicon photonic structure of claim 6, wherein the interlayer optical signal coupler comprises a grating coupler having a first grating structure formed in one core layer and a second grating structure formed in another core layer.

8. The silicon photonic structure of claim 6, wherein the interlayer optical signal coupler is fabricated with a concave / convex topology formed on surfaces of the first polymer and the second polymer.

9. The silicon photonic structure according to claim 6, wherein the interlayer optical signal coupler is fabricated with a reflective prism in two or more than two of the polymer waveguides, wherein the reflective prism is formed by changing the refractive index in at least one of the first polymer waveguide and the second polymer waveguide. 10 . The silicon photonic structure of claim 1 , wherein the silicon photonic structure further comprises a through silicon via (TSV) providing electrical connection between two or more layers of the silicon photonic structure.

11. The silicon photonic structure of claim 1, wherein the core layer has a funnel shape, and the cladding layer is adjacent to the funnel-shaped core layer, and a narrower end of the funnel-shaped core layer protrudes through the cladding layer to provide a reflective prism.

12. The silicon photonic structure of claim 1, wherein an optical fiber is coupled to the at least one optical lens that guides an optical signal through the integrated fan-out redistribution layer and the polymer bridge layer to the silicon photonic grating coupler.

13. The silicon photonic structure of claim 1, wherein the at least one optical lens is formed of a polymer and silicon.

14. The silicon photonic structure of claim 1, wherein the silicon photonic structure further comprises an optical fiber coupled to the polymer bridging layer.

15. A wafer-level system comprising: Wafer carrier; a plurality of dies disposed on the wafer carrier, wherein each of the plurality of dies comprises at least one photonic integrated circuit and at least one electronic integrated circuit; a polymer waveguide coupled to the at least one photonic integrated circuit to provide inter-die optical interconnection; an integrated fan-out redistribution layer disposed on top of each of the plurality of dies, wherein the plurality of dies are bonded to the wafer carrier prior to polymer waveguide formation; at least one optical lens to direct light through the integrated fan-out redistribution layer; as well as A silicon photonic grating coupler comprises a first grating structure and a second grating structure, wherein light from the at least one optical lens is received by the first grating structure of the silicon photonic grating coupler, and the first grating structure of the silicon photonic grating coupler changes the direction of the light so that the light is collected by the second grating structure of the silicon photonic grating coupler to guide the light between the at least one photonic integrated circuit and the polymer waveguide.

16. The wafer level system of claim 15, wherein the wafer carrier comprises at least one of glass, silicon, metal, polymer, epoxy molding compound, and diamond.

17. A method of fabricating a silicon photonic structure using a polymer waveguide, the method comprising: attaching the photonic integrated circuit on top of the electronic integrated circuit using hybrid die bonding to form a photonic / electronic integrated circuit package; forming a polymer waveguide bridging layer comprising at least one polymer waveguide, and placing the polymer waveguide bridging layer on top of the photonic integrated circuit; placing at least one application specific integrated circuit within the photonic / electronic integrated circuit package; and forming an integrated fan-out redistribution layer on top of the polymer waveguide bridging layer, The silicon photonic structure includes at least one optical lens and a silicon photonic grating coupler, wherein the at least one optical lens guides light through the integrated fan-out redistribution layer, and the silicon photonic grating coupler includes a first grating structure and a second grating structure, wherein light from the at least one optical lens is received by the first grating structure of the silicon photonic grating coupler, and the first grating structure of the silicon photonic grating coupler changes the direction of the light so that the light is collected by the second grating structure of the silicon photonic grating coupler to guide the light between the photonic integrated circuit and the at least one polymer waveguide.

18. The method according to claim 17, further comprising: forming a through hole in the polymer waveguide bridging layer; as well as Through silicon vias are formed in the photonic integrated circuit to allow conductive connections between silicon photonic structure layers.

19. The method according to claim 17, further comprising: forming a support filler beneath the electronic integrated circuit; as well as The support filler and the at least one application specific integrated circuit are attached to a carrier.

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