Method for manufacturing semiconductor device, three-dimensional memory, and storage system

Abstract

The application provides a semiconductor device manufacturing method, a three-dimensional memory and a storage system. The semiconductor device manufacturing method comprises the following steps: forming a semiconductor structure, the semiconductor structure comprising a substrate, a stack structure and a first dielectric layer, the stack structure comprising a step structure, a stop layer and a second dielectric layer, the step structure comprising a gate layer and an insulating layer arranged in a stack; forming a first step contact hole in the step region, the first step contact hole penetrating through the first dielectric layer and the second dielectric layer and extending to the stop layer; forming a mask layer on the first dielectric layer; forming a second step contact hole comprising the first step contact hole, the second step contact hole penetrating through the stop layer and extending to each corresponding gate layer; forming a first opening in the first dielectric layer; wherein the second step contact hole and the first opening are formed in the same etching step. By forming the second step contact hole and the first opening in the same etching step, the process steps are reduced and the cost is lowered.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a method for fabricating a semiconductor device, a three-dimensional memory, and a storage system. Background Technology

[0002] In recent years, the development of flash memory has been particularly rapid. The main characteristics of flash memory are its ability to retain stored information for extended periods without power, along with advantages such as high integration, fast access speeds, and ease of erasing and rewriting. Consequently, it has found widespread application in microcomputers, automation control, and many other fields. Against this backdrop, to address the challenges of planar flash memory and to pursue lower production costs per unit storage cell, three-dimensional memory (such as 3D NAND flash) has emerged. Three-dimensional memory forms multiple layers of alternating stacked data storage cells, transforming the planar structure into a three-dimensional structure to improve storage density and integration. 3D memory can support higher storage capacity in a smaller space, resulting in significant cost savings, reduced energy consumption, and substantial performance improvements to fully meet the needs of numerous consumer mobile devices and the most demanding enterprise deployments.

[0003] As the number of stacked layers in 3D memory increases, the fabrication process becomes increasingly complex, leading to decreased yield and reliability. Simultaneously, the number of fabrication steps and the associated costs also increase. Therefore, it is necessary to continuously optimize the fabrication process to reduce the number of steps and lower costs. Summary of the Invention

[0004] The purpose of this invention is to provide a method for fabricating a semiconductor device, a three-dimensional memory, and a storage system, so as to reduce process steps and lower costs.

[0005] To address the aforementioned problems, the present invention provides a method for fabricating a semiconductor device. The method includes: forming a semiconductor structure, the semiconductor structure including a substrate, a stacked structure on the substrate, and a first dielectric layer; the stacked structure including a step region and a storage region distributed laterally parallel to the substrate, and including a step structure, a stop layer, and a second dielectric layer located in the step region; the step structure including a gate layer and an insulating layer stacked in a step-like manner; the stop layer completely covering the step structure; and the second dielectric layer covering the stop layer; forming a first step contact hole in the step region, the first step contact hole penetrating the first dielectric layer and the second dielectric layer and extending to the stop layer; forming a mask layer on the first dielectric layer, the mask layer having a first mask layer opening and a second mask layer opening, the first mask layer opening corresponding to the first step contact hole; forming a second step contact hole including the first step contact hole according to the first mask layer opening, the second step contact hole penetrating the stop layer and extending to corresponding gate layers; and forming a first opening in the first dielectric layer according to the second mask layer opening; wherein the second step contact hole and the first opening are formed in the same etching step.

[0006] The step of forming the semiconductor structure further includes forming a channel structure that penetrates the stacked structure and extends to the substrate. The method for fabricating the semiconductor device also includes:

[0007] A channel contact block is formed in the first opening, and the channel contact block is connected to the channel structure.

[0008] After the first step contact hole is formed in the step area, the process also includes:

[0009] The contact hole of the first step is cleaned.

[0010] The method further includes, after forming the first opening in the first dielectric layer according to the opening in the second mask layer:

[0011] The second step contact hole and the first opening are filled respectively.

[0012] The process includes, before forming a mask layer on the first dielectric layer, the mask layer having a first mask layer opening and a second mask layer opening corresponding to the first step contact hole, further comprising:

[0013] A photomask is provided, having a first photomask opening and a second photomask opening, the first photomask opening corresponding to a first photomask layer opening, and the second photomask opening corresponding to a second photomask layer opening.

[0014] The material of the stop layer includes carbonitrides.

[0015] The carbon content of the stop layer is greater than 5%.

[0016] The stop layer has a thickness greater than 100 nm in the longitudinal direction perpendicular to the substrate.

[0017] To address the aforementioned issues, this application also provides a three-dimensional memory, which includes an array storage structure and peripheral circuitry. The array storage structure comprises a semiconductor device formed by the semiconductor device fabrication method described above.

[0018] To address the aforementioned issues, this application also provides a storage system comprising a controller and a three-dimensional memory. The controller is coupled to the three-dimensional memory and is used to control the storage of data in the three-dimensional memory. The three-dimensional memory includes a semiconductor device formed by the method of fabricating a semiconductor device according to any of the above-mentioned methods.

[0019] The beneficial effects of this invention are as follows: Unlike existing technologies, this invention provides a method for fabricating a semiconductor device, a three-dimensional memory, and a memory system. The method for fabricating the semiconductor device includes: forming a semiconductor structure, the semiconductor structure including a substrate, a stacked structure on the substrate, and a first dielectric layer; the stacked structure including a step region and a memory region distributed laterally parallel to the substrate, and including a step structure, a stop layer, and a second dielectric layer located in the step region; the step structure including a gate layer and an insulating layer stacked in the form of steps; the stop layer completely covering the step structure; and the second dielectric layer covering the stop layer; forming a first step contact hole in the step region, the first step contact hole penetrating the first dielectric layer and the second dielectric layer and extending to the stop layer; forming a mask layer on the first dielectric layer, the mask layer having a first mask layer opening and a second mask layer opening, the first mask layer opening corresponding to the first step contact hole; forming a second step contact hole including the first step contact hole according to the first mask layer opening, the second step contact hole penetrating the stop layer and extending to each corresponding gate layer; and forming a first opening in the first dielectric layer according to the second mask layer opening; wherein the second step contact hole and the first opening are formed in the same etching step. The method of the present invention enables the second step contact hole and the first opening to be formed in the same etching step, thereby reducing both process steps and costs. Attached Figure Description

[0020] The technical solution and other beneficial effects of the present invention will become apparent from the following detailed description of specific embodiments of the invention, in conjunction with the accompanying drawings.

[0021] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0022] Figures 2a to 2e This is a schematic diagram of the structure of each step in the method for fabricating a semiconductor device provided in an embodiment of the present invention.

[0023] Figure 3This is a schematic block diagram of the storage system in an embodiment of the present invention. Detailed Implementation

[0024] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0025] It should be understood that although the terms first, second, etc., may be used herein to describe various components, these components should not be limited to these terms. These terms are used to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of the invention.

[0026] It should be understood that when a component is said to be "on" or "connected" to another component, it can be directly on or connected to the other component, or there may be an inserted component. Other terms used to describe relationships between components should be interpreted in a similar manner.

[0027] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far from the substrate. A layer may extend over the entire lower or upper layer structure, or may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and contact layers (where contacts, interconnects, and one or more dielectric layers are formed).

[0028] As used herein, the term "semiconductor device" refers to a semiconductor device having a vertically oriented array structure on a laterally oriented substrate, such that the array structure extends in a vertical direction relative to the substrate; "vertical" means perpendicular to the direction of the substrate.

[0029] It should be noted that the illustrations provided in the embodiments of the present invention are only schematic representations of the basic concept of the present invention. Although the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components, the form, quantity and proportion of each component can be arbitrarily changed in actual implementation, and the layout of the components may also be more complex.

[0030] Please see Figure 1 This is a schematic flowchart of a semiconductor device fabrication method provided in an embodiment of the present invention. A detailed flowchart is provided below. Figures 2a to 2e The structural diagram may include the following:

[0031] Step S101: Form a semiconductor structure, the semiconductor structure including a substrate 110, a stacked structure 120 located on the substrate 110 and a first dielectric layer 130. The stacked structure 120 includes a step region and a storage region (region A1 and region A2, respectively) distributed in the transverse (X direction) parallel to the substrate 110, and includes a step structure 121, a stop layer 140 and a second dielectric layer 150 located in the step region. The step structure 121 includes a gate layer 1211 and an insulating layer 1212 stacked in the form of steps. The stop layer 140 completely covers the step structure 121, and the second dielectric layer 150 covers the stop layer 140.

[0032] In addition, it should be noted that, Figures 2a to 2e Only structures relevant to the embodiments of the present invention are shown. The semiconductor device of the present invention may further include other components and / or structures for realizing the full functionality of the device.

[0033] Figure 2a The structure formed in step S101 includes: a substrate 110, a stacked structure 120 on the substrate 110, and a first dielectric layer 130. The stacked structure 120 includes a step region and a storage region (regions A1 and A2, respectively) distributed laterally (X-direction) parallel to the substrate 110, a stop layer 140 completely covering the step structure 121, and a second dielectric layer 150 covering the stop layer 140. The step structure 121 includes a gate layer 1211 and an insulating layer 1212 stacked in a step-like manner.

[0034] Specifically, the substrate 110 can be a semiconductor substrate, such as a silicon (Si), germanium (Ge), SiGe substrate, silicon-on-insulator (SOI), or germanium-on-insulator (GOI) substrate. In other embodiments, the semiconductor substrate 110 can also be a substrate 110 comprising other elemental semiconductors or compound semiconductors, and can also be a stacked structure, such as Si / SiGe. Furthermore, one or more film layers can be formed beneath the substrate 110, for example, such as... Figure 2a As shown, a nitride film 111 is formed beneath the substrate 110. One or more nitride films 111 can be formed in a specific region beneath the substrate 110 or over the entire substrate 110 to improve wafer warpage or for other functional requirements. Alternatively, one or more other films can be formed beneath the substrate 110 based on other process requirements, without particular limitation.

[0035] Specifically, the semiconductor structure can be formed as follows: After providing the substrate 110, firstly, a stacked layer (not shown in the figure) including alternating sacrificial layers (not shown in the figure) and insulating layers 1212 can be formed on the substrate 110 by a deposition process. Then, a stacked layer with a step structure 121 can be formed by photolithography, trimming, and etching processes, i.e., sacrificial layers and insulating layers 1212 are formed on the outer side of the stacked layer in a step-like manner. Then, a stop layer 140 completely covering the steps of the step structure 121, a second dielectric layer 150 covering the step structure 121 and the stop layer 140, and a first dielectric layer 130 covering the stacked layer can be formed on the step structure 121 by a deposition process. Finally, the original sacrificial layer can be removed, and a gate layer 1211 can be formed at the location of the original sacrificial layer, thereby forming a structure as shown in the figure. Figure 2a The semiconductor structure shown is used. At this time, a stacked structure 120 is formed, comprising alternately stacked gate layers 1211 and insulating layers 1212. Furthermore, it should be noted that when forming a semiconductor structure as shown... Figure 2a The process of forming the semiconductor structure shown also includes the formation of other structures, such as gate line slits, which are not the focus of this invention and will not be described in detail.

[0036] Step S102: A first step contact hole 171 is formed in the step area. The first step contact hole 171 penetrates the first dielectric layer 130 and the second dielectric layer 150 and extends to the stop layer 140.

[0037] The material of the stop layer 140 includes carbonitrides.

[0038] Figure 2b The structure formed in step S102 includes: a substrate 110, a stacked structure 120 on the substrate 110, and a first dielectric layer 130. The stacked structure 120 includes a stepped structure 121, a stop layer 140 completely covering the stepped structure 121, a second dielectric layer 150 covering the stop layer 140, and a first stepped contact hole 171 located in the second dielectric layer 150. The first stepped contact hole 171 penetrates the second dielectric layer 150 and extends to the stop layer 140.

[0039] Specifically, a first stepped contact hole 171 can be formed in the step region (A1 region) through an etching process, such as dry etching. The first stepped contact hole 171 penetrates the first dielectric layer 130 and the second dielectric layer 150 and extends to the stop layer 140. Generally, the materials of the first dielectric layer 130 and the second dielectric layer 150 are oxides, such as silicon oxide (SiO2). The material of the stop layer 140 may include carbonitrides. Since the materials of the first dielectric layer 130, the second dielectric layer 150, and the stop layer 140 are not the same, when using dry etching to remove the first dielectric layer 130 and the second dielectric layer 150 to form the first stepped contact hole 171, the etching gas can be selected. For example, an etching gas with a low carbon-to-fluorine ratio (C / F ratio of carbon to fluorine in the etching gas), such as carbon tetrafluoride (CF4) or fluoromethane (CH3F), can be selected to ensure that the first dielectric layer 130 and the second dielectric layer 150 are connected. Layer 150 has a higher selectivity than stop layer 140 (e.g., selectivity greater than 1). That is, during etching, the etching speed of the first dielectric layer 130 and the second dielectric layer 150 is faster, while the etching speed of stop layer 140 is slower, or even almost no etching of stop layer 140. In this case, stop layer 140 can act as a stop layer to stop etching, thereby forming a first step contact hole 171 in the step region. The first step contact hole 171 penetrates the first dielectric layer 130 and the second dielectric layer 150 and extends to stop layer 140.

[0040] The carbon content of the stop layer 140 is greater than 5%.

[0041] Specifically, the stacked layer includes alternately stacked sacrificial layers and insulating layers 1212. The insulating layer 1212 separates the multiple sacrificial layers. The insulating layer 1212 can be made of oxides, such as silicon oxide (SiO2), while the sacrificial layers can be made of nitrides, such as silicon nitride (SiN). Since the sacrificial layers are mostly nitrides and the insulating layers are mostly oxides, after forming the nitride layer, a certain thickness of nitride layer can be oxidized to form an oxide layer of a certain thickness. This process is repeated to form a certain number of stacked layers including alternately stacked sacrificial layers and insulating layers 1212. As described above, the original sacrificial layer can be removed, and a gate layer 1211 can be formed at the original sacrificial layer location, thereby forming a... Figure 2a The semiconductor structure shown is illustrated. Generally, thermal phosphoric acid can be used to remove the sacrificial layer in the stacked structure 120. Specifically, thermal phosphoric acid reacts with the sacrificial layer material nitride, thereby removing the sacrificial layer. The stop layer 140 is made of carbon-doped nitride. Since the stop layer 140 contains carbon, phosphoric acid cannot react with the carbon in the stop layer 140, so the stop layer 140 is essentially undamaged during the removal of the sacrificial layer. Preferably, to ensure that the stop layer 140 is not damaged during the removal of the sacrificial layer, the carbon content of the stop layer 140 is greater than 5%.

[0042] The stop layer 140 has a thickness greater than 100 nm in the longitudinal direction (Z direction) perpendicular to the substrate 110.

[0043] Specifically, since the first step contact hole 171 is formed in the step region, and the first step contact hole 171 penetrates the first dielectric layer 130 and the second dielectric layer 150 and extends to the stop layer 140, the stop layer 140 will be damaged during the etching process. In order to ensure that the stop layer 140 is not etched through when the first step contact hole 171 is formed, and then stops on the gate layer 1211 below the stop layer 140, causing electrical failure of the device, preferably, the thickness L1 of the stop layer 140 in the longitudinal direction (Z direction) is greater than 100nm.

[0044] In step S102, after the first step contact hole 171 is formed in the step region, the following is also included:

[0045] The first step contact hole 171 is cleaned.

[0046] Specifically, after forming the first step contact hole 171 in the step region through an etching process, etching residues, such as polymers, may remain on the sidewalls and bottom walls of the first step contact hole 171. Cleaning the first step contact hole 171 removes these residues from its sidewalls and bottom walls, which facilitates subsequent etching processes or other processes. At the same time, it prevents the formation of defects due to these residues, thus avoiding any impact on the electrical performance of the device.

[0047] Step S103: A mask layer 180 is formed on the first dielectric layer 130. The mask layer 180 has a first mask layer opening 1811 and a second mask layer opening 1812. The first mask layer opening 1811 corresponds to the first step contact hole 171.

[0048] Figure 2c The structure formed in step S103 includes: a substrate 110, a stacked structure 120 on the substrate 110, a first dielectric layer 130, and a mask layer 180. The stacked structure 120 includes a step structure 121, a stop layer 140 completely covering the step structure 121, a second dielectric layer 150 covering the stop layer 140, and a first step contact hole 171 located in the second dielectric layer 150. The first step contact hole 171 penetrates the second dielectric layer 150 and extends to the stop layer 140. The mask layer 180 includes a photoresist layer 181 and a hard mask layer 182, and has a first mask layer opening 1811 and a second mask layer opening 1812.

[0049] Specifically, a mask layer 180 can be formed on the first dielectric layer 130, and then a first mask layer opening 1811 and a second mask layer opening 1812 can be formed on the mask layer 180. The first mask layer opening 1811 corresponds to the first stepped contact hole 171 and is used for subsequent etching of the already formed first stepped contact hole 171. The mask layer 180 may consist only of a photoresist layer 181, or it may consist of a photoresist layer 181 and a hard mask layer 182. Generally, during deep hole etching, to protect the layers that do not need to be etched from damage, a photoresist layer 181 and a hard mask layer 182 can be selected as the mask layer 180. Hard mask is an inorganic thin film material generated by chemical vapor deposition (CVD). Its main components are usually titanium nitride (TiN), silicon nitride (SiN), and silicon oxide (SiO2). It is mainly used in photolithography. The pattern on the mask is transferred to the photoresist layer 181 through the photolithography process, thus forming a patterned photoresist layer 181. Then, the pattern of the photoresist can be transferred to the hard mask layer 182 through the etching process. Finally, the pattern is etched and transferred to the film layer to be etched through the hard mask layer 182.

[0050] Furthermore, due to the optical reflection effect on the surface of substrate 110, reflected light and incident light interfere with each other, forming a standing wave effect and multiple exposures within the photoresist. This results in the inability to control the critical dimensions of the pattern, reducing etching accuracy. Preferably, a bottom antireflective coating (BARC) can be added between the photoresist layer 181 and the hard mask layer 182. Its main components are crosslinkable resin, thermo-acid generator, surfactant, and solvent, which can reduce reflection and effectively improve the standing wave effect and multiple exposures.

[0051] Specifically, in step S103, before forming a mask layer 180 on the first dielectric layer 130, the mask layer 180 having a first mask layer opening 1811 and a second mask layer opening 1812 corresponding to the first step contact hole 171, the method further includes:

[0052] A photomask (not shown in the figure) is provided, the photomask having a first photomask opening (not shown in the figure) and a second photomask opening (not shown in the figure), the first photomask opening corresponding to a first photomask layer opening 1811, and the second photomask opening corresponding to a second photomask layer opening 1812.

[0053] Specifically, a pattern on a photomask can be transferred to a mask layer 180 using photolithography to form a first mask layer opening 1811 and a second mask layer opening 1812 on the mask layer 180. A photomask with a first mask layer opening and a second mask layer opening can be provided, where the first mask layer opening corresponds to the first mask layer opening 1811, and the second mask layer opening corresponds to the second mask layer opening 1812. The pattern on the photomask is transferred to the mask layer 180 using photolithography, thereby simultaneously forming the first mask layer opening 1811 and the second mask layer opening 1812 on the mask layer 180. The structure of the photomask used to form the second mask layer opening 1812 can be improved so that the improved photomask can be used to simultaneously form the first mask layer opening 1811 and the second mask layer opening 1812 without adding a new photomask, thus reducing both process steps and costs.

[0054] Step S104: A second step contact hole 170 including a first step contact hole 171 is formed according to the opening 1811 of the first mask layer. The second step contact hole 170 penetrates the stop layer 140 and extends to the corresponding gate layer 1211.

[0055] Figure 2d The structure formed in step S104 includes: a substrate 110, a stacked structure 120 on the substrate 110, a first dielectric layer 130, and a mask layer 180. The stacked structure 120 includes a step structure 121, a stop layer 140 completely covering the step structure 121, a second dielectric layer 150 covering the stop layer 140, and a second step contact hole 170 located in the second dielectric layer 150. The second step contact hole 170 penetrates the second dielectric layer 150 and the stop layer 140 and extends to the corresponding gate layers 1211, including a first step contact hole 171 and an etched hole 172 formed in step S104.

[0056] Specifically, based on the opening 1811 of the first mask layer, a second step contact hole 170 including a first step contact hole 171 can be formed by an etching process. The second step contact hole 170 penetrates the stop layer 140 and extends to the corresponding gate layers 1211. Generally, the material of the gate layer 1211 is a metallic conductive material, such as tungsten (W), while the material of the stop layer 140 can be a material including carbonitrides. Based on the different materials of the stop layer 140 and the gate layer 1211, a suitable etching gas can be selected to make the etching selectivity of the stop layer 140 relative to the gate layer 1211 larger. That is, during etching, the etching speed of the stop layer 140 is faster, while the etching speed of the gate layer 1211 is slower, or even the gate layer 1211 is basically not etched. This achieves the removal of part of the stop layer 140 and its extension to the corresponding gate layers 1211, forming the second step contact hole 170 including the first step contact hole 171.

[0057] Step S105: Based on the second mask layer opening 1812, a first opening 190 is formed in the first dielectric layer 130; wherein, the second step contact hole 170 and the first opening 190 are formed in the same etching step.

[0058] Figure 2d The structure formed in step S105 includes: a substrate 110, a stacked structure 120 on the substrate 110, a first dielectric layer 130, a first opening 190 in the first dielectric layer 130, and a mask layer 180. The stacked structure 120 includes a stepped structure 121, a stop layer 140 completely covering the stepped structure 121, a second dielectric layer 150 covering the stop layer 140, and a second stepped contact hole 170 in the second dielectric layer 150. The second stepped contact hole 170 penetrates the second dielectric layer 150 and the stop layer 140 and extends to the corresponding gate layers 1211, including the first stepped contact hole 171 and an etched hole 172 formed in step S104.

[0059] Specifically, based on the second mask layer opening 1812, a first opening 190 can be formed in the first dielectric layer 130 through an etching process. To achieve the formation of the first opening 190 and the second stepped contact hole 170 in the same etching step, after structural improvements to the mask used to form the second mask layer opening 1812, some parameters in the etching process for forming the first opening 190 also need to be adjusted. Specifically, the depth of the second stepped contact hole 170, including the first stepped contact hole 171, is equal to the thickness L1 of the stop layer 140 in the longitudinal (Z direction). The depth of the first opening 190 is related to the actual required depth of the first opening 190. Generally, the required etching thickness of the stop layer 140 is not the same as the etching depth of the first opening 190. Therefore, some parameters in the etching process for forming the first opening 190 need to be adjusted to ensure that the first opening 190 and the second stepped contact hole 170 are formed in the same etching step. By forming the second step contact hole 170 and the first opening 190 in the same etching step, the goal of reducing both process steps and costs is achieved.

[0060] Specifically, the first opening 190 can be a structure with an opening formed after the second step contact hole 170 is formed and before the second step contact hole 170 is filled. That is, by using the mask and etching process that forms the first opening 190 in subsequent processes, by improving the structure of the mask and adjusting some parameters in the etching process that forms the first opening 190, the second step contact hole 170 and the first opening 190 can be formed in the same etching step, thereby reducing both process steps and costs.

[0061] Specifically, in some embodiments, to save on mask costs, contact holes for the step region and the storage region can be formed in the same etching step using a single mask. However, the biggest challenge with this approach is ensuring that the contact holes formed in the step region are precisely on the corresponding gate layers 1211, rather than etching through the gate layers 1211 and causing leakage between the gate layers 1211 and adjacent gate layers 1211. To address this requirement, embodiments of the present invention form a stop layer 140 (which can be an NDC thin film, the material of which includes carbonitride) that completely covers the step structure 121. This allows a first step contact hole 171 to be formed first, penetrating the second dielectric layer 150 and extending to the stop layer. Then, etching is performed downwards from the bottom of the first step contact hole 171 to form a second step contact hole 170 including the first step contact hole 171. This ensures the communication between the second step contact hole 170 and the corresponding gate layers 1211, thereby improving the device yield and reliability.

[0062] In step S105, after forming the first opening 190 in the first dielectric layer 130 according to the second mask layer opening 1812, the method further includes:

[0063] Step S106: Fill the second step contact hole 170 and the first opening 190 respectively.

[0064] Figure 2e The structure formed in step S106 includes: a substrate 110, a stacked structure 120 on the substrate 110, a first dielectric layer 130, a first opening filler block 191 in the first dielectric layer 130, and a mask layer 180. The stacked structure 120 includes a step structure 121, a stop layer 140 completely covering the step structure 121, a second dielectric layer 150 covering the stop layer 140, and a second step contact block 173 in the second dielectric layer 150. The second step contact block 173 penetrates the second dielectric layer 150 and the stop layer 140 and extends to the corresponding gate layers 1211. The second step contact hole 170 and the first opening 190 can be filled by a deposition process to form the second step contact block 173 and the first opening filler block 191, respectively. Generally, the filler material for the second step contact hole 170 and the first opening 190 is a conductive material, such as tungsten (W).

[0065] The step of forming the semiconductor structure further includes forming a channel structure 160 that extends through the stacked structure 120 and into the substrate 110. The method for fabricating the semiconductor device further includes:

[0066] A channel contact block (i.e., a first opening filling block 191) is formed in the first opening 190, and the channel contact block is connected to the channel structure 160.

[0067] Specifically, as described above, the first opening 190 can be a structure with an opening formed after the second stepped contact hole 170 is formed and before the second stepped contact hole 170 is filled. The first opening 190 can be a channel contact hole located above the channel structure 160. When the first opening 190 serves as a channel contact hole, the step of forming the semiconductor structure should further include forming a through-stacking structure 120 extending towards the substrate 110. Figure 2dThe channel structure 160 is shown. After forming the first opening 190, a channel contact block can also be formed in the first opening 190, and the channel contact block is connected to the channel structure 160. The channel hole structure serves as a data storage unit in the semiconductor device, used to implement data storage functionality. Generally, the channel structure 160 includes a blocking layer, a charge trap layer, and a tunneling layer. Typically, the channel hole contact is located above the channel structure 160, and a conductive plug 161 is formed between the channel hole contact and the channel structure 160. The conductive plug 161 can be made of polysilicon doped with N-type or P-type materials. The mask for forming the first opening 190 is structurally improved so that it is used in the same etching step to form a first mask layer opening 1811 and a second mask layer opening 1812 corresponding to the formation of the second step contact hole 170 and the first opening 190. After structural improvements to the photomask, some parameters in the etching process for forming the channel contact hole are adjusted. For example, when forming the channel contact hole by dry etching, a suitable etching gas can be selected, such as an etching gas with a high carbon-to-fluorine ratio (the ratio of carbon to fluorine elements in the etching gas, C / F), such as perfluoropropane (C3F8). This makes the etching selectivity ratio between the first dielectric layer 130 and the conductive plug 161 greater than 1, and the etching selectivity ratio between the stop layer 140 and the gate layer 1211 greater than 1. That is, the etching speed of the stop layer 140 is faster, and the etching speed of the gate layer 1211 is slower, or even the gate layer 1211 is basically not etched. This removes the stop layer 140 and extends it to the second step contact hole 170 of the corresponding gate layer 1211. Meanwhile, since the etching selectivity ratio between the first dielectric layer 130 and the conductive plug 161 is greater than 1, meaning the etching rate of the first dielectric layer 130 is faster and the etching rate of the conductive plug 161 is slower, or even almost non-etched, the first dielectric layer 130 is removed from the channel contact hole formed above the channel structure 160. Besides selecting a suitable etching gas, other parameters for forming the first opening 190 and the second stepped contact hole 170 can be adjusted according to actual process requirements, thereby enabling the second stepped contact hole 170 and the first opening 190 to be formed in the same etching step, achieving both reduced process steps and lower costs.

[0068] Furthermore, when the first opening 190 is not used as a channel contact hole but as an opening in other process flows, the etching process parameters during the formation of the first opening 190, such as the etching gas and reaction time, can be adjusted to allow the second step contact hole 170 and the first opening 190 to be formed in the same etching step, thereby reducing both process steps and costs. For example, when the first opening 190 is an opening with a certain depth, by selecting a suitable etching gas, the etching selectivity ratio of the stop layer 140 to the gate layer 1211 can be greater than 1, and the etching gas can etch the first dielectric layer 130. When the stop layer 140 is etched away and extends to the gate layer 1211, since the etching gas does not react much with the material of the gate layer 1211, the formed second step contact hole 170 penetrates the stop layer 140 and extends to the corresponding gate layer 1211. Meanwhile, by controlling the reaction time, the first opening 190 can reach a certain depth, thereby enabling the second step contact hole 170 and the first opening 190 to be formed in the same etching step, achieving the goal of reducing both process steps and costs. It is understood that the depth of the first opening 190 should not differ significantly from the thickness of the stop layer 140, to ensure that the gate layer 1211 is not etched through when forming the first opening 190, or that the depth of the first opening is within a specified range when forming the second step contact hole 170.

[0069] This application also provides a three-dimensional memory, which includes an array memory structure and peripheral circuitry, wherein the array memory structure includes a semiconductor device formed by the semiconductor device fabrication method described above.

[0070] Specifically, a 3D NAND Flash memory includes an array storage structure and peripheral circuitry. The semiconductor device fabricated using any of the aforementioned semiconductor device fabrication methods is located within the peripheral circuitry. The array storage structure stores information, while the peripheral circuitry can be located above, below, or around the array storage structure. The peripheral circuitry controls the corresponding array storage structure. Furthermore, this semiconductor device can also be applied to other microelectronic devices, such as non-volatile flash memory (Nor Flash), without specific limitations.

[0071] This application also provides a storage system, which includes a controller and a three-dimensional memory. The controller is coupled to the three-dimensional memory and is used to control the storage of data in the three-dimensional memory. The three-dimensional memory includes a semiconductor device formed by the method of fabricating the semiconductor device described above.

[0072] Specifically, such as Figure 3As shown, the storage system 200 includes a controller 210 and one or more three-dimensional memories 220, wherein each three-dimensional memory 220 includes one or more array storage structures 221 and peripheral circuitry 222. The storage system 200 can communicate with the host 300 via the controller 210, wherein the controller 210 can be connected to one or more three-dimensional memories 220 via channels in the three-dimensional memories 220. Each three-dimensional memory 220 can be managed by the controller 210 via channels in the three-dimensional memory 220.

[0073] Based on the above description, embodiments of the present invention disclose a method for fabricating a semiconductor device, a three-dimensional memory, and a memory system. The method for fabricating the semiconductor device includes: forming a semiconductor structure, the semiconductor structure including a substrate, a stacked structure on the substrate, and a first dielectric layer; the stacked structure including a step region and a memory region distributed laterally parallel to the substrate, and including a step structure, a stop layer, and a second dielectric layer located in the step region; the step structure including a gate layer and an insulating layer stacked in the form of steps; the stop layer completely covering the step structure; and the second dielectric layer covering the stop layer; forming a first step contact hole in the step region, the first step contact hole penetrating the first dielectric layer and the second dielectric layer and extending to the stop layer; forming a mask layer on the first dielectric layer, the mask layer having a first mask layer opening and a second mask layer opening, the first mask layer opening corresponding to the first step contact hole; forming a second step contact hole including the first step contact hole according to the first mask layer opening, the second step contact hole penetrating the stop layer and extending to each corresponding gate layer; and forming a first opening in the first dielectric layer according to the second mask layer opening; wherein the second step contact hole and the first opening are formed in the same etching step. The method of the present invention enables the second step contact hole and the first opening to be formed in the same etching step, thereby reducing both process steps and costs.

[0074] The above description of the embodiments is only for the purpose of helping to understand the technical solutions and core ideas of the present invention; those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method of manufacturing a semiconductor device, characterized by, The method for fabricating the semiconductor device includes: A semiconductor structure is formed, the semiconductor structure including a substrate, a stacked structure on the substrate and a first dielectric layer, the stacked structure including a step region and a storage region distributed laterally parallel to the substrate, and including a step structure, a stop layer and a second dielectric layer located in the step region, the step structure including a gate layer and an insulating layer stacked in the form of steps, the stop layer completely covering the step structure, the second dielectric layer covering the stop layer, and the first dielectric layer covering the stacked structure; A first step contact hole is formed in the step region, the first step contact hole penetrating the first dielectric layer and the second dielectric layer and extending to the stop layer; A mask layer is formed on the first dielectric layer, the mask layer having a first mask layer opening and a second mask layer opening, the first mask layer opening corresponding to the first step contact hole, and the second mask layer opening corresponding to the storage area; A second stepped contact hole, including the first stepped contact hole, is formed according to the opening of the first mask layer. The second stepped contact hole penetrates the stop layer and extends to each of the corresponding gate layers. A first opening is formed in the first dielectric layer based on the opening in the second mask layer; The second step contact hole and the first opening are formed in the same etching step.

2. The method of manufacturing a semiconductor device according to Claim 1, wherein The step of forming the semiconductor structure further includes forming a channel structure that extends through the stacked structure and toward the substrate; the method of fabricating the semiconductor device further includes: A channel contact block is formed in the first opening, and the channel contact block is in communication with the channel structure.

3. The method of manufacturing a semiconductor device according to Claim 1, wherein After the first step contact hole is formed in the step area, the method further includes: The first step contact hole is cleaned.

4. The method of manufacturing a semiconductor device according to Claim 1, wherein After forming the first opening in the first dielectric layer according to the opening in the second mask layer, the method further includes: The second step contact hole and the first opening are filled respectively.

5. The method of manufacturing a semiconductor device according to Claim 1, wherein Before forming a mask layer on the first dielectric layer, the mask layer further includes a first mask layer opening and a second mask layer opening corresponding to the first step contact hole: A photomask is provided, the photomask having a first photomask opening and a second photomask opening, the first photomask opening corresponding to a first photomask layer opening, and the second photomask opening corresponding to a second photomask layer opening.

6. The method of producing a semiconductor device according to Claim 1, wherein The material of the stop layer includes carbonitrides.

7. The method of producing a semiconductor device according to Claim 6, wherein The carbon content of the stop layer is greater than 5%.

8. The method of producing a semiconductor device according to Claim 1, wherein The stop layer has a thickness greater than 100 nm in the longitudinal direction perpendicular to the substrate.

9. A three-dimensional memory, comprising: The three-dimensional memory includes an array memory structure and peripheral circuitry, wherein the array memory structure includes a semiconductor device formed by the method of fabricating a semiconductor device as described in any one of claims 1 to 8.

10. A storage system, characterized by The storage system includes a controller and a three-dimensional memory, the controller being coupled to the three-dimensional memory and used to control the storage of data in the three-dimensional memory, the three-dimensional memory including a semiconductor device formed by a method of fabricating a semiconductor device as described in any one of claims 1 to 8.

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