Phase change memory and preparation method thereof

Abstract

The present application provides a phase change memory and a preparation method thereof, the method comprising: forming a gating layer and a phase change memory layer connected in series with the gating layer; the gating layer comprises a first sublayer and a second sublayer; wherein the element of the first sublayer is selected from at least one gating layer element in a first type of element set, and the element of the second sublayer is selected from at least one gating layer element in a second type of element set; the mobility of each gating layer element in the first type of element set is less than the mobility of each gating layer element in the second type of element set. In the method provided by the present application, a gating layer comprising a first sublayer and a second sublayer is formed, so that the mobility of each element in the first sublayer is less than the mobility of each element in the second sublayer, and the interface effect between the first sublayer and the second sublayer is utilized to alleviate the local phase separation or even crystallization caused by material diffusion, so as to improve the high temperature stability of the gating layer, thereby improving the high temperature stability of the phase change memory.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor manufacturing technology, and in particular, to a phase change memory and a method for preparing the same. Background Art

[0002] Phase-change Random Access Memory (PCRAM) uses the Joule heat generated by electric pulses to convert the storage medium between the crystalline state (low resistance state) and the amorphous state (high resistance state). The resistance difference between the low resistance state and the high resistance state is obvious, thereby realizing the writing and erasing of information. The reading of information is achieved by measuring the change in resistance.

[0003] Among them, the gate is the core component of the phase change memory, and the gate includes a gate layer and electrodes located on the upper and lower sides of the gate layer. The principle of the gate is that when an electrical signal is applied, the gate layer changes from a high resistance state to a low resistance state, and the gate is in an on state; when the electrical signal is removed, the gate layer changes from a low resistance state to a high resistance state, and the gate is in an off state. At present, Ovonic Threshold Switching (OTS) based on amorphous chalcogenide materials is usually used as the gate layer of the phase change memory.

[0004] Therefore, there is still a need to further improve the structure of the gating layer to improve the performance of the bidirectional threshold switch, thereby improving the performance of the phase change memory. Summary of the invention

[0005] In view of this, the embodiments of the present application provide a phase change memory and a method for preparing the same in order to solve at least one technical problem existing in the prior art.

[0006] To achieve the above purpose, the technical solution of this application is implemented as follows:

[0007] In a first aspect, an embodiment of the present application provides a method for preparing a phase change memory, the method comprising:

[0008] forming a gating layer and a phase change memory layer connected in series with the gating layer;

[0009] The gating layer includes a first sublayer and a second sublayer; wherein the elements of the first sublayer are selected from at least one gating layer element in a first type of element set, and the elements of the second sublayer are selected from at least one gating layer element in a second type of element set; the mobility of each gating layer element in the first type of element set is less than the mobility of each gating layer element in the second type of element set.

[0010] In some embodiments, the number of the first sub-layers is greater than the number of the second sub-layers; and the second sub-layer is located between two adjacent first sub-layers.

[0011] In some embodiments, the gating layer also includes a third sublayer; wherein the elements of the third sublayer are selected from at least one gating layer element in the third type of element set; the mobility of each gating layer element in the first type of element set and the mobility of each gating layer element in the third type of element set are both less than the mobility of each gating layer element in the second type of element set.

[0012] In some embodiments, the second sublayer is located between the first sublayer and the third sublayer.

[0013] In some embodiments, the gating layer element includes germanium Ge, antimony Sb, silicon Si, selenium Se, arsenic As, and tellurium Te.

[0014] In a second aspect, an embodiment of the present application provides a phase change memory, the phase change memory comprising: a gating layer and a phase change storage layer connected in series with the gating layer;

[0015] The gating layer includes a first sublayer and a second sublayer; the mobility of each element in the first sublayer is smaller than the mobility of each element in the second sublayer.

[0016] In some embodiments, the first sub-layers and the second sub-layers are alternately stacked.

[0017] In some embodiments, the gating layer further includes a third sublayer; the mobility of each element in the third sublayer is less than the mobility of each element in the second sublayer; and the second sublayer is located between the first sublayer and the third sublayer.

[0018] In some embodiments, the first sub-layer, the second sub-layer and the third sub-layer are alternately stacked.

[0019] In some embodiments, the material of the first sublayer includes at least one element of germanium Ge, antimony Sb, and silicon Si;

[0020] The material of the second sublayer includes at least one element of selenium Se, arsenic As, and tellurium Te.

[0021] The embodiment of the present application provides a phase change memory and a preparation method thereof, the method comprising: forming a gating layer and a phase change memory layer connected in series with the gating layer; the gating layer comprises a first sublayer and a second sublayer; wherein the element of the first sublayer is selected from at least one gating layer element in a first type of element set, and the element of the second sublayer is selected from at least one gating layer element in a second type of element set; the mobility of each gating layer element in the first type of element set is less than the mobility of each gating layer element in the second type of element set. In the preparation method of the phase change memory provided by the embodiment of the present application, a gating layer comprising a first sublayer and a second sublayer is formed, so that the mobility of each element in the first sublayer is less than the mobility of each element in the second sublayer, and the interface effect between the first sublayer and the second sublayer is utilized to alleviate the local phase separation or even crystallization caused by material diffusion, so as to improve the high temperature stability of the gating layer, thereby improving the high temperature stability of the phase change memory, so that the phase change memory has better cycle durability, and thus improves the reliability of the phase change memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram of the structure of a phase change memory provided in an embodiment of the present application;

[0023] Figure 2 A schematic diagram of a process for preparing a phase change memory provided in an embodiment of the present application;

[0024] Figure 3 A schematic cross-sectional structure diagram of a phase change memory provided in an embodiment of the present application;

[0025] Figure 4 A schematic cross-sectional structure diagram of another phase change memory provided in an embodiment of the present application;

[0026] Figure 5 A schematic cross-sectional structure diagram of another phase change memory provided in an embodiment of the present application;

[0027] Figure 6 A schematic cross-sectional structure diagram of a gating layer including a third sub-layer provided in an embodiment of the present application;

[0028] Figure 7 A schematic cross-sectional structure diagram of a gating layer including a fourth sublayer provided in an embodiment of the present application;

[0029] The figure includes: 10, selection layer; 11, first sublayer; 12, second sublayer; 13, third sublayer; 14, fourth sublayer; 20, phase change storage layer; 31, first electrode layer; 32, second electrode layer; 33, third electrode layer; 41a, first first conductive wire; 41b, second first conductive wire; 42a, first second conductive wire; 42b, second second conductive wire; 51, first phase change storage unit; 52, second phase change storage unit. DETAILED DESCRIPTION

[0030] The following will be combined with the embodiments of the present application and the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0031] In the following description, a large number of specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features known in the art are not described; that is, all features of the actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0032] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0033] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present application necessarily has the first element, component, region, layer or part.

[0034] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0035] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0036] In order to thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present application. The preferred embodiments of the present application are described in detail below, but in addition to these detailed descriptions, the present application may also have other implementation methods.

[0037] refer to Figure 1 , Figure 1 This is a schematic diagram of the structure of the phase change memory provided in the embodiment of the present application. Figure 1 As shown, the phase change memory includes, from top to bottom, a first first conductive line 41a, a first phase change memory array, a first second conductive line 42a, a second second conductive line 42b, a second phase change memory array, and a second first conductive line 41b. The first phase change memory array includes a plurality of first phase change memory cells 51 arranged in parallel, and the second phase change memory array includes a plurality of second phase change memory cells 52 arranged in parallel. In order to more clearly illustrate the structure of the phase change memory cells in the phase change memory, Figure 1 Only one first phase-change memory cell and one second phase-change memory cell are shown.

[0038] In some embodiments, the first second conductive line 42a and the second second conductive line 42b may be combined into the same second conductive line in the phase change memory. In other words, one second conductive line may be formed by performing one second conductive line forming process.

[0039] It should be noted that the first plane where the first conductive line is arranged is parallel to the second plane where the second conductive line is arranged. The phase change memory unit is located between the first plane and the second plane, and the phase change memory unit is perpendicular to both the first conductive line and the second conductive line.

[0040] Here, the first first conductive line can be a bit line corresponding to the first phase change memory array, and the second first conductive line can be a bit line corresponding to the second phase change memory array; the first second conductive line can be a word line of the first phase change memory array, and the second second conductive line can be a word line of the second phase change memory array.

[0041] Here, the material of the first conductive line and the second conductive line may include a conductive material. The conductive material includes but is not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped polysilicon, or any combination thereof. The first conductive line and the second conductive line may have the same conductive material or different conductive materials.

[0042] Still refer to Figure 1 The structures of the first phase change memory unit 51 and the second phase change memory unit 52 may be the same. Taking the structure of the first phase change memory unit as an example, the first phase change memory unit 51 includes, from top to bottom, a third electrode layer 33, a phase change memory layer 20, a second electrode layer 32, a gating layer 10, and a first electrode layer 31.

[0043] Still refer to Figure 1 , the first electrode layer 31 is located between the gating layer 10 and the first second conductive line 42a, and the gating layer 10 is located between the first electrode layer 31 and the second electrode layer 32. It should be noted that the first electrode layer 31, the second electrode layer 32 and the third electrode layer 33 represent electrode layers in the phase change memory unit, and the materials included therein may be the same or different, and different reference numerals are only used to distinguish the differences in the positions of the electrode layers, and are not used to describe a specific order or sequence.

[0044] Here, the materials of the first electrode layer, the second electrode layer, and the third electrode layer may include amorphous carbon, such as α-phase carbon. Here, the electrode layer may be used to conduct electrical signals.

[0045] Here, the gating layer is the core component of the phase change memory, and the bidirectional threshold switch (Ovonic Threshold Switching, OTS) based on amorphous chalcogenide materials can be used as the gating layer of the phase change memory. When an electrical signal is applied, the gating layer changes from a high resistance state to a low resistance state, and the bidirectional threshold switch is in the on state; when the electrical signal is removed, the gating layer changes from a low resistance state to a high resistance state, and the bidirectional threshold switch is in the off state.

[0046] In phase change memory, a gating layer based on amorphous sulfur-based materials is often formed by a one-time growth method as a bidirectional threshold switch. This bidirectional threshold switch has many advantages. For example, the gating layer of the sulfur-based compound system can be well compatible with the phase change storage layer of the sulfur-based compound system; sulfur-based compounds have advantages in switching speed compared to other systems due to their own fast low-resistance-high-resistance state transition ability; the process for preparing the gating layer of the sulfur-based compound system is simpler, and the process is compatible with the back-end process of the phase change memory.

[0047] However, after a certain number of switching cycles, the gating layer formed by the one-time growth method may be affected by the Joule heat generated during the read and write operations, and the material of the gating layer may undergo local phase separation or even crystallization, resulting in degradation of the switching characteristics of the bidirectional threshold switch, which in turn affects the reliability of the phase change memory and even causes the phase change memory to fail.

[0048] In view of this, an embodiment of the present application provides a phase change memory and a method for preparing the same. In the method for preparing the phase change memory provided in the embodiment of the present application, a gating layer including a first sublayer and a second sublayer is formed, so that the mobility of each element in the first sublayer is less than the mobility of each element in the second sublayer, and the interface effect between the first sublayer and the second sublayer is utilized to alleviate the local phase separation or even crystallization caused by material diffusion, so as to improve the high temperature stability of the gating layer, thereby improving the high temperature stability of the phase change memory, so that the phase change memory has better cycle durability, and thus improves the reliability of the phase change memory.

[0049] refer to Figure 2 , Figure 2 The flowchart of the method for preparing the phase change memory provided in the embodiment of the present application is shown in FIG. Figure 2 As shown, an embodiment of the present application provides a method for preparing a phase change memory, the method comprising:

[0050] Step S100, forming a gating layer and a phase change storage layer connected in series with the gating layer; the gating layer includes a first sublayer and a second sublayer; wherein the element of the first sublayer is selected from at least one gating layer element in a first type of element set, and the element of the second sublayer is selected from at least one gating layer element in a second type of element set; the mobility of each gating layer element in the first type of element set is less than the mobility of each gating layer element in the second type of element set.

[0051] refer to Figure 3 , Figure 3 The cross-sectional structure diagram of a phase change memory provided in an embodiment of the present application is shown in FIG. Figure 3 As shown, a gating layer 10 and a phase change storage layer 20 connected in series with the gating layer 10 are formed; wherein the gating layer 10 includes a first sublayer 11 and a second sublayer 12; wherein the elements of the first sublayer 11 are selected from at least one gating layer element in a first type of element set, and the elements of the second sublayer 12 are selected from at least one gating layer element in a second type of element set; and the mobility of each gating layer element in the first type of element set is less than the mobility of each gating layer element in the second type of element set.

[0052] Here, mobility refers to the rate of electrical migration. Different mobilities of materials mean that when an electrical signal is applied, the atomic migration rate or diffusion rate of the material is different. Generally, the greater the electronegativity of an element, the greater the mobility. By utilizing the interface effect between sublayers with different mobilities, the local phase separation or even crystallization caused by the diffusion of the gating layer material can be alleviated. In this way, the gating layer can still remain stable after a certain number of switching cycles, so that the phase change memory has better cycle durability, thereby improving the reliability of the phase change memory.

[0053] Here, the gating layer elements can be divided into a first type element set and a second type element set according to the mobility of the elements, wherein the mobility of each gating layer element in the first type element set is less than the mobility of each gating layer element in the second type element set. Further, at least one gating layer element in the first type element set is arbitrarily selected to form a first sublayer, and at least one gating layer element in the second type element set is arbitrarily selected to form a second sublayer.

[0054] Still refer to Figure 3, the mobility of each element in the first sublayer 11 is less than the mobility of each element in the second sublayer 12, the first sublayer 11 is in contact with the second electrode layer 32, and the second sublayer 12 is in contact with the first electrode layer 31. That is to say, the first sublayer with a smaller mobility of the gating layer elements is in contact with the second electrode layer, and the second sublayer with a larger mobility of the gating layer elements is in contact with the first electrode layer. Of course, the first sublayer in the gating layer may also be in contact with the first electrode layer, and the second sublayer in the gating layer may also be in contact with the second electrode layer, that is, the first sublayer with a smaller mobility of the gating layer elements is in contact with the first electrode layer, and the second sublayer with a larger mobility of the gating layer elements is in contact with the second electrode layer.

[0055] In some embodiments, the thicknesses of the first sub-layer and the second sub-layer may be the same or different.

[0056] Here, the thickness of the first sublayer (or, the second sublayer) refers to the size of the first sublayer (or, the second sublayer) in the stacking direction.

[0057] In some embodiments, the gating layer has a thickness ranging from 5 nm to 100 nm.

[0058] In some embodiments, the number of layers of the first sublayer may be greater than or equal to 1, and the number of layers of the second sublayer may be greater than or equal to 1. Figure 3 The gating layer shown includes only one first sublayer and one second sublayer, which does not constitute a limitation on the protection scope of the present application. The embodiment of the present application has no special limitation on the number of the first sublayer and the second sublayer.

[0059] Here, A is used to represent the first sublayer and B is used to represent the second sublayer. Figure 3 The structural arrangement of the gating layer shown can be expressed as AB. If the gating layer includes multiple first sub-layers and multiple second sub-layers, the number of first sub-layers and the number of second sub-layers are the same, the first sub-layers and the second sub-layers are alternately stacked, the materials of the multiple first sub-layers are the same, and the materials of the multiple second sub-layers are the same, then the structural arrangement of the gating layer can be expressed as ABAB...AB, and the gating layer includes multiple repeating units, and the structural arrangement of each repeating unit can be expressed as AB.

[0060] In some embodiments, the number of layers of the first sub-layer and the second sub-layer may be the same or different. For example, the gating layer includes three first sub-layers and two second sub-layers.

[0061] In some embodiments, the gating layer includes at least two of the first sub-layers and at least two of the second sub-layers, and the materials of the first sub-layers may be the same or different, and the materials of the second sub-layers may be the same or different. For example, the gating layer includes three first sub-layers and two second sub-layers, wherein the materials of the three first sub-layers may be the same, and the materials of the two second sub-layers may be the same; or, the materials of the three first sub-layers may be different, and the materials of the two second sub-layers may be different.

[0062] In some embodiments, the first sublayer may be disposed adjacent to the first sublayer and / or the second sublayer. For example, the first sublayer is disposed adjacent to the second sublayer, and the second sublayer is also disposed adjacent to the first sublayer, that is, the first sublayer and the second sublayer are alternately stacked. For another example, a first sublayer may also be disposed adjacent to another first sublayer, and the mobility of the elements forming the two first sublayers may be the same, but the materials forming the two first sublayers are different.

[0063] In the embodiment of the present application, the number of layers of the first sub-layer is greater than the number of layers of the second sub-layer; and the second sub-layer is located between two adjacent first sub-layers.

[0064] refer to Figure 4 , Figure 4 A schematic cross-sectional structure diagram of another phase change memory provided in an embodiment of the present application. Figure 4 As shown, the gating layer 10 includes two first sub-layers 11 and one second sub-layer 12, and the second sub-layer 12 is located between two adjacent first sub-layers 11; the phase change memory also includes a first electrode layer 31 and a second electrode layer 32 respectively arranged on opposite sides of the gating layer 10, and the second electrode layer 32 is located between the gating layer 10 and the phase change memory layer 20; wherein the first electrode layer 31 and the second electrode layer 32 are both arranged adjacent to the first sub-layer 11.

[0065] here, Figure 4 The gating layer 10 shown includes two first sub-layers 11 and one second sub-layer 12 , and the second sub-layer 12 is located between two adjacent first sub-layers 11 .

[0066] It should be noted that the gate layer is driven to undergo a phase change by applying a voltage, generating a process of mutual transition between a high resistance state and a low resistance state, thereby controlling the opening and closing of the bidirectional threshold switch. However, during the cycle of opening and closing the bidirectional threshold switch, the constituent materials of the gate layer may diffuse into the first electrode layer and the second electrode layer.

[0067] Here, the elements of the first sublayer are selected from at least one selection layer element in the first type of element set, and the elements of the second sublayer are selected from at least one selection layer element in the second type of element set, and the mobility of each selection layer element in the first type of element set is less than the mobility of each selection layer element in the second type of element set; the second sublayer with a larger mobility of the selection layer element is arranged between two adjacent first sublayers with a smaller mobility of the selection layer element, that is, the second sublayer with a larger mobility of the selection layer element is located in the middle, and the first sublayer with a smaller mobility of the selection layer element is located on the outside, that is, the first sublayer with a smaller mobility of the selection layer element is in contact with the first electrode layer and the second electrode layer, so that the selection layer element with a larger mobility can be confined to the middle layer of the selection layer, effectively reducing the diffusion of the constituent materials of the selection layer into the first electrode layer and the second electrode layer, which is beneficial to ensuring the stability of the electrode layer and the selection layer, and further ensuring the reliability of the phase change memory.

[0068] In the embodiment of the present application, the first sub-layer and the second sub-layer are alternately stacked.

[0069] Here, the mobility of each element in the first sublayer is less than the mobility of each element in the second sublayer, and the first sublayer and the second sublayer are alternately stacked. In this way, the gating layer includes multiple interfaces of the first sublayer and the second sublayer with different mobilities of the gating layer elements, which can effectively alleviate the local phase separation or even crystallization caused by the outward diffusion of the gating layer elements with greater mobility, thereby improving the high temperature stability of the gating layer.

[0070] refer to Figure 5 , Figure 5 A cross-sectional structural diagram of another phase change memory provided in an embodiment of the present application is provided. To facilitate the description of the structure of the gating layer, Figure 5 The phase change memory layer and the third electrode layer are omitted. Figure 5 As shown, the gating layer 10 includes a plurality of first sub-layers 11 and a plurality of second sub-layers 12 which are alternately stacked; wherein the first electrode layer 31 and the second electrode layer 32 are both arranged adjacent to the first sub-layer 11 .

[0071] In a preferred embodiment of the present application, the mobility of each element in the first sublayer 11 is smaller than the mobility of each element in the second sublayer 12; the first sublayer 11 and the second sublayer 12 are alternately stacked.

[0072] Here, the first sublayer with a smaller mobility of the gating layer elements and the second sublayer with a higher mobility of the gating layer elements are alternately stacked to form a multi-layer stacked gating layer. The gating layer is formed by stacking multiple layers, and the interface effect introduced between the multiple first sublayers and the multiple second sublayers can effectively alleviate the local phase separation or even crystallization caused by material diffusion, which helps to improve the high temperature stability of the gating layer, so that the gating layer has better cycle durability, thereby improving the reliability of the phase change memory.

[0073] In the embodiment of the present application, the gating layer elements include germanium Ge, antimony Sb, silicon Si, selenium Se, arsenic As, and tellurium Te.

[0074] In an embodiment of the present application, the material of the first sublayer includes at least one element of germanium Ge, antimony Sb, and silicon Si; the material of the second sublayer includes at least one element of selenium Se, arsenic As, and tellurium Te.

[0075] Here, the elements of the gating layer are divided into a first element set and a second element set according to the size of the element migration rate; the first element set includes germanium Ge, antimony Sb, silicon Si, and the second element set includes selenium Se, arsenic As, and tellurium Te, wherein the mobility of each gating layer element in the first element set is less than the mobility of each element in the second element set. Of course, the elements included in the materials of the first sublayer and the second sublayer are not limited to the above-mentioned elements, and the materials of the first sublayer and the second sublayer may include any other elements in the periodic table having phase change characteristics.

[0076] In a specific example of the present application, the material of the gating layer is a Ge-Se-Te-As-Si system. The gating layer can be divided into a first sublayer including Ge and Si elements, and a second sublayer including Se, Te and As elements. The first sublayer and the second sublayer are alternately stacked, so that the Se, Te and As elements with a higher electromigration rate can be used as the second sublayer to be confined between the two first sublayers of Ge and Si elements with a lower electromigration rate, and the local phase separation or even crystallization caused by the diffusion of Se, Te or As elements in the gating layer can be delayed, thereby improving the amorphous integrity of the gating layer after multiple switching cycles. For example, the gating layer stacked in multiple layers is annealed at 400°C for 30 minutes, and the integrity of the amorphous structure can still be maintained, thereby ensuring the high temperature stability of the gating layer, so that the gating layer has better cycle durability, and finally obtains better phase change memory performance.

[0077] In addition, the phase change memory provided in the embodiment of the present application includes a gating layer formed by stacking multiple layers. The gating layer formed by stacking multiple layers is less sensitive to size shrinkage, and the electrical parameters variability between devices of different sizes is smaller. In other words, even if the size of the phase change memory is reduced, the electrical performance of the phase change memory using the gating layer can still remain stable.

[0078] In an embodiment of the present application, the gating layer also includes a third sublayer; wherein the elements of the third sublayer are selected from at least one gating layer element in the third type of element set; the mobility of each gating layer element in the first type of element set and the mobility of each gating layer element in the third type of element set are both smaller than the mobility of each gating layer element in the second type of element set.

[0079] refer to Figure 6 , Figure 6 The cross-sectional structure diagram of the gating layer including the third sub-layer provided in the embodiment of the present application. Figure 6 As shown, the gating layer 10 includes a first sublayer 11, a second sublayer 12 and a third sublayer 13, the elements of the first sublayer are selected from at least one gating layer element in the first type element set, the elements of the second sublayer are selected from at least one gating layer element in the second type element set, and the elements of the third sublayer are selected from at least one gating layer element in the third type element set; wherein the mobility of each gating layer element in the first type element set and the mobility of each gating layer element in the third type element set are both smaller than the mobility of each gating layer element in the second type element set.

[0080] Here, the mobility of each gating layer element in the first type element set and the mobility of each gating layer element in the third type element set are both less than the mobility of each gating layer element in the second type element set, which includes two cases. In the first case, the mobility of each gating layer element in the third type element set is less than the mobility of each gating layer element in the first type element set, and the mobility of each gating layer element in the first type element set is less than the mobility of each gating layer element in the second type element set. In the second case, the mobility of each gating layer element in the first type element set is less than the mobility of each gating layer element in the third type element set, and the mobility of each gating layer element in the third type element set is less than the mobility of each gating layer element in the second type element set. In other words, the mobility of each element in the third sub-layer is less than the mobility of each element in the first sub-layer, and the mobility of each element in the first sub-layer is less than the mobility of each element in the second sub-layer; or, the mobility of each element in the first sub-layer is less than the mobility of each element in the third sub-layer, and the mobility of each element in the third sub-layer is less than the mobility of each element in the second sub-layer.

[0081] In the embodiment of the present application, the second sublayer is located between the first sublayer and the third sublayer.

[0082] Here, A is used to represent the first sublayer, B is used to represent the second sublayer, and C is used to represent the third sublayer. Figure 6The structural arrangement of the gating layer shown can be expressed as ABCABC...ABC. If the gating layer includes multiple first sub-layers, multiple second sub-layers and multiple third sub-layers, the number of first sub-layers, the number of second sub-layers and the number of third sub-layers are the same, and the first sub-layers, the second sub-layers and the third sub-layers are alternately stacked. If the materials of the multiple first sub-layers are the same, the materials of the multiple second sub-layers are the same, and the materials of the multiple third sub-layers are the same, then Figure 6 The gating layer shown includes a plurality of repeating units, and the structural arrangement of each repeating unit can be represented as ABC.

[0083] Here, the mobility of each selection layer element in the first type of element set and the mobility of each selection layer element in the third type of element set are both smaller than the mobility of each selection layer element in the second type of element set; the second sublayer with a larger mobility of the selection layer element is arranged between the first sublayer and the third sublayer with a smaller mobility of the selection layer element, that is, the second sublayer with a larger mobility of the selection layer element is located in the middle, and the first sublayer and the third sublayer with a smaller mobility of the selection layer element are located on the outside, that is, the first sublayer and the third sublayer with a smaller mobility of the selection layer element are respectively in contact with the first electrode layer and the second electrode layer, so that the selection layer element with a larger mobility can be confined to the middle layer of the selection layer, effectively reducing the diffusion of the constituent materials of the selection layer into the first electrode layer and the second electrode layer, and the interface effect introduced between the first sublayer, the second sublayer and the third sublayer can effectively alleviate the local phase separation or even crystallization caused by material diffusion, which helps to improve the high temperature stability of the selection layer, so that the selection layer has better cycle durability, thereby improving the reliability of the phase change memory.

[0084] In the embodiment of the present application, the first sub-layer, the second sub-layer and the third sub-layer are alternately stacked.

[0085] Here, the mobility of each element in the first sublayer and the mobility of each element in the third sublayer are both smaller than the mobility of each element in the second sublayer, and the first sublayer, the second sublayer and the third sublayer with different mobilities of the gating layer elements are alternately stacked to form a multi-layer stacked gating layer. The gating layer is formed by a multi-layer stacking method, and the interface effect introduced between the multiple first sublayers, the multiple second sublayers and the multiple third sublayers can effectively alleviate the local phase separation or even crystallization caused by material diffusion, which helps to improve the high temperature stability of the gating layer, so that the gating layer has better cycle durability, thereby improving the reliability of the phase change memory.

[0086] As mentioned earlier, Figure 6 The gating layer shown includes a plurality of repeating units, and the structural arrangement of each repeating unit can be expressed as ABC. Of course, the arrangement of the first sub-layer, the second sub-layer and the third sub-layer in the gating layer is not limited thereto.

[0087] Here, A is still used to represent the first sublayer, B is used to represent the second sublayer, and C is used to represent the third sublayer. If the mobility of each element in the third sublayer is less than the mobility of each element in the first sublayer, the mobility of each element in the first sublayer is less than the mobility of each element in the second sublayer.

[0088] In some embodiments, the number of layers of the first sublayer, the second sublayer and the third sublayer in the gating layer are the same, and the structural arrangement of the gating layer can be expressed as CABCAB...CAB. In this way, the gating layer includes a plurality of repeating units, and the structural arrangement of each repeating unit can be expressed as CAB, and the mobility of the gating layer elements of the repeating unit CAB increases. In this way, the third sublayer and the second sublayer in the gating layer are in contact with the first electrode layer and the second electrode layer, respectively. In the embodiment of the present application, the number of layers of the first sublayer, the second sublayer and the third sublayer may also be different.

[0089] In other embodiments, the number of layers of the first sublayer, the second sublayer and the third sublayer in the gating layer are the same, and the structural arrangement of the gating layer can be expressed as BACBAC...BAC. In this way, the gating layer includes a plurality of repeating units, and the structural arrangement of each repeating unit can be expressed as BAC, and the mobility of the gating layer elements of the repeating unit BAC shows a decreasing law. In this way, the second sublayer and the third sublayer in the gating layer are in contact with the first electrode layer and the second electrode layer, respectively. In the embodiment of the present application, the number of layers of the first sublayer, the second sublayer and the third sublayer may also be different.

[0090] Here, A is still used to represent the first sublayer, B is used to represent the second sublayer, and C is used to represent the third sublayer. If the mobility of each element in the first sublayer is less than the mobility of each element in the third sublayer, the mobility of each element in the third sublayer is less than the mobility of each element in the second sublayer.

[0091] In some embodiments, the number of layers of the first sublayer, the second sublayer, and the third sublayer in the gating layer are the same, and the structural arrangement of the gating layer can be expressed as ACBACB...ACB. In this way, the gating layer includes a plurality of repeating units, and the structural arrangement of each repeating unit can be expressed as ACB, and the mobility of the gating layer elements of the repeating unit ACB increases. In this way, the first sublayer and the second sublayer in the gating layer are in contact with the first electrode layer and the second electrode layer, respectively.

[0092] In other embodiments, the number of layers of the first sublayer, the second sublayer, and the third sublayer in the gating layer are the same, and the structural arrangement of the gating layer can be expressed as BCABCA...BCA. In this way, the gating layer includes multiple repeating units, and the structural arrangement of each repeating unit can be expressed as BCA. The mobility of the gating layer elements of the repeating unit BCA shows a decreasing law. In this way, the first sublayer and the second sublayer in the gating layer are in contact with the first electrode layer and the second electrode layer respectively. In the embodiment of the present application, the number of layers of the first sublayer, the second sublayer, and the third sublayer may also be different.

[0093] In an embodiment of the present application, the gating layer also includes a fourth sublayer; wherein the elements of the fourth sublayer are selected from at least one gating layer element in the fourth category element set; the mobility of each gating layer element in the first category element set, the mobility of each gating layer element in the third category element set and the mobility of each gating layer element in the fourth category element set are all less than the mobility of each gating layer element in the second category element set.

[0094] refer to Figure 7 , Figure 7 The cross-sectional structure diagram of the gating layer including the fourth sub-layer provided in the embodiment of the present application. Figure 7 As shown, the gating layer 10 includes a first sublayer 11, a second sublayer 12, a third sublayer 13 and a fourth sublayer 14, the elements of the first sublayer are selected from at least one gating layer element in the first type element set, the elements of the second sublayer are selected from at least one gating layer element in the second type element set, the elements of the third sublayer are selected from at least one gating layer element in the third type element set, and the elements of the fourth sublayer are selected from at least one gating layer element in the fourth type element set; wherein the mobility of each gating layer element in the first type element set, the mobility of each gating layer element in the third type element set and the mobility of each gating layer element in the fourth type element set are all less than the mobility of each gating layer element in the second type element set.

[0095] Here, there are six cases in which the mobility of each gating layer element in the first type element set, the mobility of each gating layer element in the third type element set, and the mobility of each gating layer element in the fourth type element set are all less than the mobility of each gating layer element in the second type element set. A Respectively represent the mobility of each element in the first sublayer, using V B Denotes the mobility of each element in the second sublayer, using V C Denotes the mobility of each element in the third sublayer, using V D represents the mobility of each element in the fourth sublayer. Then we can list the first case, V D <V C <V A <V B ; In the second case, VC <V D <V A <V B ; In the third case, V C <V A <V D <V B ; In the fourth case, V D <V A <V C <V B ; In the fifth case, V A <V D <V C <V B ; In the sixth case, V A <V C <V D <V B .

[0096] In an embodiment of the present application, the second sublayer is located between the first sublayer and the third sublayer; and / or, the second sublayer is located between the first sublayer and the fourth sublayer; or, the second sublayer is located between the third sublayer and the fourth sublayer.

[0097] Here, A is used to represent the first sublayer, B is used to represent the second sublayer, C is used to represent the third sublayer, and D is used to represent the fourth sublayer. Figure 7 The structural arrangement of the gating layer shown can be expressed as ABCDABCD...ABCD. If the gating layer includes multiple first sub-layers, multiple second sub-layers, multiple third sub-layers and multiple fourth sub-layers, the number of first sub-layers, the number of second sub-layers, the number of third sub-layers and the number of fourth sub-layers are the same. If the materials of the multiple first sub-layers are the same, the materials of the multiple second sub-layers are the same, the materials of the multiple third sub-layers are the same, and the materials of the multiple fourth sub-layers are the same, then Figure 7 The gating layer shown includes a plurality of repeating units, and the structural arrangement of each repeating unit can be represented as ABCD.

[0098] Here, the mobility of each gating layer element in the first element set, the mobility of each gating layer element in the third element set, and the mobility of each gating layer element in the fourth element set are all less than the mobility of each gating layer element in the second element set. The second sublayer with a larger mobility of the gating layer element is arranged between the first sublayer and the third sublayer with a smaller mobility of the gating layer element, that is, the second sublayer with a larger mobility of the gating layer element is located in the middle, and the first sublayer, the third sublayer, and the fourth sublayer with a smaller mobility of the gating layer element are located on the outside, that is, the first sublayer and the fourth sublayer with a smaller mobility of the gating layer element are respectively in contact with the first electrode layer and the second electrode layer, so that the gating layer element with a larger mobility can be confined to the middle layer of the gating layer, effectively reducing the diffusion of the constituent materials of the gating layer into the first electrode layer and the second electrode layer, and the interface effect introduced between the first sublayer, the second sublayer, the third sublayer, and the fourth sublayer can effectively alleviate the local phase separation or even crystallization caused by the diffusion of the material, which is helpful to improve the high temperature stability of the gating layer, so that the gating layer has better cycle durability, thereby improving the reliability of the phase change memory.

[0099] In the embodiment of the present application, the first sublayer, the second sublayer, the third sublayer and the fourth sublayer are alternately stacked.

[0100] Here, the first sublayer, the second sublayer, the third sublayer and the fourth sublayer with different element mobility of the gating layer are alternately stacked to form a multi-layer stacked gating layer. The gating layer is formed by stacking multiple layers, and the interface effect introduced between the multiple first sublayers, multiple second sublayers, multiple third sublayers and multiple fourth sublayers can effectively alleviate the local phase separation or even crystallization caused by material diffusion, which helps to improve the high temperature stability of the gating layer, so that the gating layer has better cycle durability, thereby improving the reliability of the phase change memory.

[0101] As mentioned earlier, Figure 7 The gating layer shown includes a plurality of repeating units, and the structural arrangement of each repeating unit can be expressed as ABCD. Of course, the arrangement of the first sub-layer, the second sub-layer, the third sub-layer and the fourth sub-layer in the gating layer is not limited thereto.

[0102] Here, A is still used to represent the first sublayer, B is used to represent the second sublayer, C is used to represent the third sublayer, and D is used to represent the fourth sublayer. If the mobility of each element in the fourth sublayer is less than the mobility of each element in the third sublayer, the mobility of each element in the third sublayer is less than the mobility of each element in the first sublayer, and the mobility of each element in the first sublayer is less than the mobility of each element in the second sublayer, that is, V D <V C <V A <V B .

[0103] In some embodiments, the number of layers of the first sublayer, the second sublayer, the third sublayer and the fourth sublayer in the gating layer are the same, and the structural arrangement of the gating layer can be expressed as DCABDCAB...DCAB. In this way, the gating layer includes a plurality of repeating units, and the structural arrangement of each repeating unit can be expressed as DCAB, and the mobility of the gating layer elements of the repeating unit DCAB increases. In this way, the fourth sublayer and the second sublayer in the gating layer are in contact with the first electrode layer and the second electrode layer, respectively. In the embodiment of the present application, the number of layers of the first sublayer, the second sublayer, the third sublayer and the fourth sublayer may also be different.

[0104] In other embodiments, the number of layers of the first sublayer, the second sublayer, the third sublayer and the fourth sublayer in the gating layer are the same, and the structural arrangement of the gating layer can be expressed as BACDBACD...BACD. In this way, the gating layer includes multiple repeating units, and the structural arrangement of each repeating unit can be expressed as BACD, and the mobility of the gating layer elements of the repeating unit BACD shows a decreasing law. In this way, the second sublayer and the fourth sublayer in the gating layer are in contact with the first electrode layer and the second electrode layer respectively. In the embodiment of the present application, the number of layers of the first sublayer, the second sublayer, the third sublayer and the fourth sublayer may also be different.

[0105] In the embodiment of the present application, the gate layer and the phase change memory layer can be formed by any one of physical vapor deposition, chemical vapor deposition, and atomic layer deposition. For example, the gate layer can be prepared by magnetron sputtering in the physical vapor deposition method.

[0106] In a specific embodiment of the present application, a gating layer can be prepared using a magnetron sputtering method. The sputtering system includes a chamber for fixing a sputtering target and a substrate. The sputtering target and the substrate are coupled to a power supply and a controller for applying a bias to the device during the sputtering process. The applied bias can be direct current, pulsed direct current, radio frequency, and a combination thereof, and the sputtering process is turned on, off, and regulated by a controller. The sputtering chamber is equipped with a vacuum pump for evacuating the chamber; and the chamber is also equipped with an inlet for an inert gas (e.g., nitrogen or argon) or a reactive gas (e.g., oxygen).

[0107] In a specific example of the present application, the material of the gating layer is a Ge-Se-As-Si system. The gating layer can be divided into a first sublayer including Ge and Si elements, and a second sublayer including Se and As elements, and the first sublayer and the second sublayer are alternately stacked. Specifically, a Ge target, a Si target, a Se target and an As target can be selected and fixed on the sputtering target in the sputtering chamber; the sputtering chamber is evacuated, and argon gas is introduced to adjust the pressure in the sputtering chamber; the power knobs of the Ge target and the Si target are adjusted to co-sputter to form a Ge-Si layer on the substrate, that is, the first sublayer; the power knobs of the Se target and the As target are adjusted to co-sputter to form a Se-As layer on the first sublayer, that is, the second sublayer. Repeat the above steps to obtain the first sublayer and the second sublayer that are alternately stacked.

[0108] The method for preparing a phase change memory provided in an embodiment of the present application forms a gating layer by stacking multiple layers, which facilitates controlling the composition and thickness of different sub-layers.

[0109] In the embodiment of the present application, before forming the gating layer, the method further includes: forming a first electrode layer.

[0110] In the embodiment of the present application, after forming the gating layer and before forming a phase change memory layer connected in series with the gating layer, the method further includes: forming a second electrode layer.

[0111] In the embodiment of the present application, after forming the phase change memory layer connected in series with the gating layer, the method further includes: forming a third electrode layer.

[0112] The present application also provides a phase change memory, still referring to Figure 3 , the phase change memory comprises: a gate 10 and a phase change memory layer 20 connected in series with the gate layer 10;

[0113] The gating layer 10 includes a first sub-layer 11 and a second sub-layer 12 ; the mobility of each element in the first sub-layer 11 is smaller than the mobility of each element in the second sub-layer 12 .

[0114] In the embodiment of the present application, the first sub-layer and the second sub-layer are alternately stacked.

[0115] In an embodiment of the present application, the gating layer further includes a third sublayer; the mobility of each element in the third sublayer is less than the mobility of each element in the second sublayer; and the second sublayer is located between the first sublayer and the third sublayer.

[0116] In the embodiment of the present application, the first sub-layer, the second sub-layer and the third sub-layer are alternately stacked.

[0117] In an embodiment of the present application, the material of the first sublayer includes at least one element selected from the group consisting of germanium Ge, antimony Sb, and silicon Si;

[0118] The material of the second sublayer includes at least one element of selenium Se, arsenic As, and tellurium Te.

[0119] The embodiment of the present application provides a phase change memory and a preparation method thereof, the method comprising: forming a gating layer and a phase change memory layer connected in series with the gating layer; the gating layer comprises a first sublayer and a second sublayer; wherein the element of the first sublayer is selected from at least one gating layer element in a first type of element set, and the element of the second sublayer is selected from at least one gating layer element in a second type of element set; the mobility of each gating layer element in the first type of element set is less than the mobility of each gating layer element in the second type of element set. In the preparation method of the phase change memory provided by the embodiment of the present application, a gating layer comprising a first sublayer and a second sublayer is formed, so that the mobility of each element in the first sublayer is less than the mobility of each element in the second sublayer, and the interface effect between the first sublayer and the second sublayer is utilized to alleviate the local phase separation or even crystallization caused by material diffusion, thereby improving the high temperature stability of the gating layer, thereby improving the high temperature stability of the phase change memory, so that the phase change memory has better cycle durability, and thus improving the reliability of the phase change memory.

[0120] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the size of the sequence number of the above-mentioned processes does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned sequence numbers of the embodiments of the present application are only for description and do not represent the advantages and disadvantages of the embodiments.

[0121] The above description is only a preferred embodiment of the present application, and does not limit the patent scope of the present application. All equivalent structural changes made by using the contents of the present application specification and drawings under the inventive concept of the present application, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A method for preparing a phase change memory, characterized in that: The method comprises: forming a gating layer and a phase change memory layer connected in series with the gating layer; The gating layer comprises a first sublayer and a second sublayer; wherein the element of the first sublayer is selected from at least one gating layer element in a first type of element set, and the element of the second sublayer is selected from at least one gating layer element in a second type of element set; the mobility of each gating layer element in the first type of element set is less than the mobility of each gating layer element in the second type of element set; the electronegativity of each gating layer element in the first type of element set is less than the electronegativity of each gating layer element in the second type of element set; The gating layer also includes a third sublayer; wherein the elements of the third sublayer are selected from at least one gating layer element in the third type of element set; the mobility of each gating layer element in the first type of element set and the mobility of each gating layer element in the third type of element set are both smaller than the mobility of each gating layer element in the second type of element set.

2. The method for preparing a phase change memory according to claim 1, characterized in that: The number of the first sub-layers is greater than the number of the second sub-layers; and the second sub-layer is located between two adjacent first sub-layers.

3. The method for preparing a phase change memory according to claim 1, characterized in that: The second sublayer is located between the first sublayer and the third sublayer.

4. The method for preparing a phase change memory according to claim 1, characterized in that: The gate layer elements include germanium Ge, antimony Sb, silicon Si, selenium Se, arsenic As, and tellurium Te.

5. A phase change memory, characterized in that: The phase change memory comprises: a gating layer and a phase change storage layer connected in series with the gating layer; The gating layer comprises a first sublayer and a second sublayer; the elements of the first sublayer are selected from at least one gating layer element in a first type of element set, and the elements of the second sublayer are selected from at least one gating layer element in a second type of element set; the mobility of each gating layer element in the first type of element set is less than the mobility of each gating layer element in the second type of element set; the electronegativity of each gating layer element in the first type of element set is less than the electronegativity of each gating layer element in the second type of element set; The gating layer further includes a third sublayer; the mobility of each element in the third sublayer is smaller than the mobility of each element in the second sublayer.

6. The phase change memory according to claim 5, characterized in that: The first sub-layers and the second sub-layers are alternately stacked.

7. The phase change memory according to claim 5, characterized in that: The second sublayer is located between the first sublayer and the third sublayer.

8. The phase change memory according to claim 7, characterized in that: The first sub-layer, the second sub-layer and the third sub-layer are alternately stacked.

9. The phase change memory according to claim 5, characterized in that: The material of the first sublayer includes at least one element of germanium Ge, antimony Sb, and silicon Si; The material of the second sublayer includes at least one element of selenium Se, arsenic As, and tellurium Te.

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