Rail-to-rail hysteretic comparison circuit and electronic device

Abstract

The application belongs to the field of rail-to-rail hysteresis comparators, and provides a rail-to-rail hysteresis comparison circuit and electronic equipment. The rail-to-rail hysteresis comparison circuit comprises a rail-to-rail input module, a clamping current comparison module and a hysteresis buffer module. The rail-to-rail input module is used for receiving an input signal and a bias power supply signal, and generating a single-ended signal according to the input signal and the bias power supply signal. The clamping current comparison module is connected to the rail-to-rail input module, used for receiving the single-ended signal and the bias power supply signal, and performing clamping processing on the voltage of the single-ended signal to generate a clamping current signal. The hysteresis buffer module is connected to the clamping current comparison module, used for receiving the clamping current signal, and performing hysteresis buffer processing on the clamping current signal to generate a driving signal. The rail-to-rail input module can normally work when the common-mode range of the input signal is wide, and the clamping current comparison module improves the working speed of the rail-to-rail hysteresis comparison circuit.

Description

Technical Field

[0001] This application belongs to the field of rail-to-rail hysteresis comparators, and particularly relates to a rail-to-rail hysteresis comparator circuit and electronic device. Background Technology

[0002] Low Voltage Differential Signaling (LVDS) enables high-speed transmission of low-swing input signals and provides fast-edge drive output signals, often used to transmit clock signals. Clock drivers are widely used in various computer and communication systems to implement clock distribution and driving functions. Among high-speed differential drive technologies, compared to CML and ECL structures, LVDS inputs have the widest common-mode input range and the lowest output swing, contributing to low power consumption. The advantages are even more pronounced in multi-channel LVDS clock driver chips.

[0003] However, existing rail-to-rail comparators have the problem of not being able to handle LVDS with a wide common-mode range. Summary of the Invention

[0004] The purpose of this application is to provide a rail-to-rail hysteresis comparator circuit and electronic device, which aims to solve the problem that rail-to-rail comparators cannot handle LVDS with a wide common-mode range.

[0005] This application provides a rail-to-rail hysteresis comparison circuit, the rail-to-rail hysteresis circuit comprising:

[0006] A rail-to-rail input module is used to receive an input signal and a bias power supply signal, and generate a single-ended signal based on the input signal and the bias power supply signal.

[0007] The clamping current comparison module is connected to the rail-to-rail input module and is used to receive the single-ended signal and the bias power supply signal, and to perform clamping processing on the voltage of the single-ended signal to generate a clamping current signal.

[0008] The hysteresis buffer module, connected to the clamping current comparison module, is used to receive the clamping current signal and perform hysteresis buffering processing on the clamping current signal to generate a drive signal.

[0009] In one embodiment, the rail-to-rail hysteresis comparison circuit further includes:

[0010] A bias power supply module, connected to the rail-to-rail input module and the clamping current comparison module, is used to provide a bias power signal to the rail-to-rail input module and the clamping current comparison module.

[0011] In one embodiment, the bias power supply module is a common-source cascode current mirror.

[0012] In one embodiment, the rail-to-rail input module includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, and a reference signal receiving NMOS transistor; wherein,

[0013] The control terminal of the first PMOS transistor is connected to the first input terminal of the input signal; the second terminal of the first PMOS transistor is connected to the first terminal of the third PMOS transistor; the first terminal of the first PMOS transistor is connected to the first terminal of the fifth NMOS transistor; the first terminal of the second PMOS transistor is connected to the first terminal of the sixth NMOS transistor; the second terminal of the second PMOS transistor is connected to the first terminal of the third PMOS transistor; the control terminal of the second PMOS transistor is connected to the second input terminal of the input signal; the first terminal of the first NMOS transistor is connected to the second terminal of the seventh PMOS transistor; the second terminal of the first NMOS transistor is connected to the first terminal of the third NMOS transistor; and the control terminal of the first NMOS transistor is connected to the second input terminal of the input signal. The first input terminal is connected to the second terminal of the eighth PMOS transistor, the second terminal of the second NMOS transistor is connected to the first terminal of the third NMOS transistor, the control terminal of the second NMOS transistor is connected to the second input terminal of the input signal, the second terminal of the third NMOS transistor is grounded, the control terminal of the third NMOS transistor is connected to the control terminal of the fourth NMOS transistor, the second terminal of the third PMOS transistor receives the power signal, the control terminal of the third PMOS transistor is connected to the control terminal of the fourth PMOS transistor, the first terminal of the fourth NMOS transistor is connected to the first terminal of the fourth PMOS transistor, the second terminal of the fourth NMOS transistor is grounded, and the second terminal of the fourth PMOS transistor receives the power signal.

[0014] The second terminal of the fifth PMOS transistor receives the power signal. The first terminal of the fifth PMOS transistor is connected to the seventh PMOS transistor. The first terminal of the sixth PMOS transistor is connected to the second terminal of the eighth PMOS transistor. The second terminal of the sixth PMOS transistor receives the power signal. The control terminal of the sixth PMOS transistor and the control terminal of the fifth PMOS transistor are jointly connected to the first terminal of the seventh PMOS transistor, the control terminal of the fifth PMOS transistor, and the control terminal of the sixth PMOS transistor. The control terminals of the seventh PMOS transistor and the eighth PMOS transistor jointly receive the first bias power signal. The second terminal of the seventh PMOS transistor is connected to the fifth PMOS transistor. The first end of the transistor, the second end of the eighth NMOS transistor is connected to the first end of the sixth NMOS transistor, the second end of the fifth NMOS transistor is grounded, the second end of the sixth NMOS transistor is grounded, the first end of the eighth PMOS transistor and the second end of the eighth NMOS transistor are also connected to the clamping current comparison module, the control end of the reference signal receiving NMOS transistor is connected to the control end of the seventh NMOS transistor and the control end of the eighth NMOS transistor, the first end of the reference signal receiving NMOS transistor is connected to the control end of the eighth NMOS transistor and the control end of the seventh NMOS transistor and receives the second bias power supply signal, and the second end of the reference signal receiving NMOS transistor is grounded.

[0015] In one embodiment, the clamping current comparison module includes:

[0016] An inverting unit, connected to the rail-to-rail input module, is used to invert the single-ended signal to generate the clamping current signal.

[0017] A feedback unit, connected to the inverting unit, is used to feed back the clamping current signal from the output of the inverting unit to the input of the inverting unit, so as to clamp the voltage of the single-ended signal.

[0018] In one embodiment, the clamping current comparison module further includes:

[0019] A switching unit is connected to the inverting unit and the feedback unit respectively, and is used to control the connection state between the inverting unit and the power supply, and the connection state between the feedback unit and the power supply according to the switching control signal.

[0020] In one embodiment, the inverting unit includes: a tenth NMOS transistor and a tenth PMOS transistor; wherein,

[0021] The first terminal of the tenth NMOS transistor and the first terminal of the tenth PMOS transistor are connected to the rail-to-rail input module. The second terminal of the tenth PMOS transistor receives the bias power supply signal. The second terminal of the tenth NMOS transistor is grounded. The control terminals of the tenth PMOS transistor and the tenth NMOS transistor are connected to the hysteresis buffer module and the feedback unit.

[0022] In one embodiment, the feedback unit includes: an eleventh PMOS transistor and an eleventh NMOS transistor; wherein,

[0023] The first terminal of the eleventh PMOS transistor and the first terminal of the eleventh NMOS transistor are connected to the inverting unit. The second terminal of the eleventh PMOS transistor receives the power signal, and the second terminal of the eleventh NMOS transistor is grounded. The control terminals of the eleventh PMOS transistor and the eleventh NMOS transistor are connected to the rail-to-rail input module.

[0024] In one embodiment, the hysteresis buffer module includes a twelfth PMOS transistor, a twelfth NMOS transistor, a thirteenth PMOS transistor, a thirteenth NMOS transistor, a fourteenth PMOS transistor, a fourteenth NMOS transistor, a first inverter, and a second inverter; wherein,

[0025] The first terminal of the twelfth PMOS transistor is connected to the second terminal of the thirteenth PMOS transistor. The second terminal of the twelfth PMOS transistor receives a power supply signal. The control terminal of the twelfth PMOS transistor is connected to the clamping current comparison module. The first terminal of the thirteenth PMOS transistor is connected to the first terminal of the thirteenth NMOS transistor. The control terminal of the thirteenth PMOS transistor is connected to the clamping current comparison module. The second terminal of the thirteenth NMOS transistor is connected to the first terminal of the twelfth NMOS transistor. The control terminal of the thirteenth NMOS transistor is connected to the clamping current comparison module. The second terminal of the twelfth NMOS transistor is grounded. The control terminal of the twelfth NMOS transistor is connected to the clamping current comparison module. The first terminal of the twelfth PMOS transistor is also connected to... The second terminal of the thirteenth PMOS transistor is connected to the second terminal of the fourteenth PMOS transistor. The second terminal of the thirteenth NMOS transistor is also connected to the second terminal of the fourteenth NMOS transistor along with the first terminal of the twelfth NMOS transistor. The first terminal of the fourteenth NMOS transistor is grounded. The control terminal of the fourteenth PMOS transistor is connected to the first terminal of the thirteenth PMOS transistor MP13. The first terminal of the fourteenth NMOS transistor is grounded. The input terminal of the first inverter is connected to the first terminal of the thirteenth PMOS transistor. The output terminal of the first inverter is connected to the input terminal of the second inverter. The output terminal of the second inverter outputs the drive signal.

[0026] In another aspect, this application provides an electronic device that includes the rail-to-rail hysteresis comparison circuit described in any of the above embodiments.

[0027] The rail-to-rail hysteresis comparator circuit includes a rail-to-rail input module, a clamping current comparator module, and a hysteresis buffer module. The rail-to-rail input module receives the input signal and bias power supply signal, and generates a single-ended signal based on these signals. The clamping current comparator module, connected to the rail-to-rail input module, receives the single-ended signal and bias power supply signal, clamps the voltage of the single-ended signal, and generates a clamping current signal. The hysteresis buffer module, connected to the clamping current comparator module, receives the clamping current signal, performs hysteresis buffering on the clamping current signal, and generates a drive signal. The rail-to-rail input module can operate normally with a wide common-mode range of the input signal, while the clamping current comparator module improves the operating speed of the rail-to-rail hysteresis comparator circuit. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a functional block diagram of the rail-to-rail hysteresis comparison circuit provided in an embodiment of this application;

[0030] Figure 2 A schematic diagram of the circuit principle of the rail-to-rail input comparison module provided in an embodiment of this application;

[0031] Figure 3 A schematic diagram of the circuit principle of the clamping current comparison module provided in the embodiments of this application;

[0032] Figure 4 This is a schematic diagram of the rail-to-rail hysteresis comparison circuit provided in an embodiment of this application. Detailed Implementation

[0033] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0034] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0035] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0036] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0037] In the field of integrated circuits, LVDS can achieve high-speed transmission of clock drive signals. In high-speed differential drive technology, LVDS has a wide common-mode range and low output swing. However, signals with a wide common-mode range need to be processed by rail-to-rail comparators, and traditional rail-to-rail comparators cannot achieve fast transmission of LVDS signals.

[0038] To address the aforementioned problems, this application provides a rail-to-rail hysteresis comparison circuit in one aspect, see [link to relevant documentation]. Figure 1 As shown, the rail-to-rail hysteresis comparator circuit includes a rail-to-rail input module 100, a clamping current comparator module 200, and a hysteresis buffer module 300. The rail-to-rail input module 100 receives input signals INP and INN and a bias power supply signal Ve, and generates a single-ended signal Vi based on the input signals and the bias power supply signal. The clamping current comparator module 200, connected to the rail-to-rail input module 100, receives the single-ended signal Vi and the bias power supply signal Ve, and performs clamping processing on the voltage of the single-ended signal Vi to generate a clamping current signal Vl. The hysteresis buffer module 300, connected to the clamping current comparator module 200, receives the clamping current signal Vl and performs hysteresis buffering processing on the clamping current signal Vl to generate a drive signal Vc.

[0039] For details, please refer to [link / reference]. Figure 1The rail-to-rail input module 100 receives a first input signal INP and a second input signal INN, wherein the amplitudes of the first input signal INP and the second input signal INN are the same but their phases are opposite. The rail-to-rail input module 100 will operate normally when the common-mode level of the input signal received by the rail-to-rail input module 100 is high, low, or moderate. When the input signal is high and the amplitude is large enough, the rail-to-rail input module 100 converts the first input signal INP and the second input signal INN into a single-ended signal Vi and outputs it to the clamping current comparison module 200. The clamping current comparison module 200 is a simple current comparator. After clamping the single-ended signal, the clamping current comparison module 200 ensures that the current of the single-ended signal Vi of the rail-to-rail input module 100 does not leave the saturation region, thereby reducing the transmission delay of the single-ended signal Vi. The hysteresis buffer module 300 receives the clamping current signal Vl after clamping processing. The hysteresis buffer module 300 provides hysteresis function and enhances the driving capability of the clamping current signal Vl to drive the large parasitic capacitance introduced by the subsequent metal connecting wires, etc.

[0040] In this embodiment, the rail-to-rail input module 100 will operate normally when the common-mode level of the input signal received is high, low, or moderate, thus solving the problem that existing rail-to-rail comparators cannot handle LVDS with a wide common-mode range. If the input signals INP and INN have slight changes near the threshold, the generated drive signal Vc will fluctuate accordingly. The rail-to-rail hysteresis comparator circuit has two threshold voltages. If the input signal changes in one direction, the output drive signal Vc will only change once; if the input signal is between the two threshold voltages, the original waveform of the output drive signal Vc will be maintained. When the rail-to-rail input module 100 receives a change in the state of the ground input signal, the single-ended signal Vi output by the rail-to-rail input module 100 will leave the saturation region. When the state changes again, the single-ended signal Vi needs to recover from the non-saturation region to the saturation region, which results in a long recovery time and limits the maximum operating speed of the rail-to-rail hysteresis comparator circuit. However, by connecting a clamping current comparator module 200 after the rail-to-rail input module 100, the clamping current comparator module 200 clamps the single-ended signal Vi output by the rail-to-rail input module 100, preventing the single-ended signal Vi from leaving the saturation region. This reduces the time for the single-ended signal Vi to recover to the saturation region, reduces the delay, and improves the operating speed of the rail-to-rail hysteresis comparator circuit.

[0041] In one embodiment, see Figure 1 As shown, the rail-to-rail hysteresis comparator circuit also includes a bias power supply module 400, which is connected to the rail-to-rail input module 100 and the clamping current comparator module 200, and is used to provide a bias power supply signal Ve to the rail-to-rail input module 100 and the clamping current comparator module 200.

[0042] In this embodiment, the bias power supply signal Ve provides the rail-to-rail input module 100 with the first bias power supply signal IREF and the second bias power supply signal VB1, and provides the clamping current comparison module 200 with the switch control signals VB2 and VB3.

[0043] In one embodiment, the bias power supply module 400 is a common-source cascode current mirror.

[0044] In this embodiment, the voltages of the two branches of the common-source cascode current mirror are equal, which can eliminate the error caused by the channel length modulation effect and the threshold deviation caused by the drain.

[0045] In one embodiment, the rail-to-rail input module includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, and a reference signal receiving NMOS transistor MNR.

[0046] The control terminal of the first PMOS transistor MP1 is connected to the first input signal terminal. The second terminal of the first PMOS transistor MP1 is connected to the first terminal of the third PMOS transistor MP3. The first terminal of the first PMOS transistor MP1 is connected to the first terminal of the fifth NMOS transistor MN5. The first terminal of the second PMOS transistor MP2 is connected to the first terminal of the sixth NMOS transistor MN6. The second terminal of the second PMOS transistor MP2 is connected to the first terminal of the third PMOS transistor MP3. The control terminal of the second PMOS transistor MP2 is connected to the second input signal terminal. The first terminal of the first NMOS transistor MN1 is connected to the second terminal of the seventh PMOS transistor MP7. The second terminal of the first NMOS transistor MN1 is connected to the first terminal of the third NMOS transistor MN3. The control terminal of the first NMOS transistor MN1 is connected to the first input signal terminal. The first terminal of the second NMOS transistor MN2 is connected to the second terminal of the eighth PMOS transistor MP8. The second terminal of the second NMOS transistor MN2 is connected to the first terminal of the third NMOS transistor MN3. The control terminal of the second NMOS transistor MN2 is connected to the second input terminal of the input signal. The second terminal of the third NMOS transistor MN3 is grounded to GND. The control terminal of the third NMOS transistor MN3 is connected to the control terminal of the fourth NMOS transistor MN4. The second terminal of the third PMOS transistor MP3 receives the power supply signal VDD. The control terminal of the third PMOS transistor MP3 is connected to the control terminal of the fourth PMOS transistor MP4. The first terminal of the fourth NMOS transistor MN4 is connected to the first terminal of the fourth PMOS transistor MP4. The second terminal of the fourth NMOS transistor MN4 is grounded to GND. The second terminal of the fourth PMOS transistor MP4 receives the power supply signal VDD.

[0047] The second terminal of the fifth PMOS transistor MP5 receives the power supply signal VDD. The first terminal of the fifth PMOS transistor MP5 is connected to the seventh PMOS transistor MP7. The first terminal of the sixth PMOS transistor MP6 is connected to the second terminal of the eighth PMOS transistor MP8. The second terminal of the sixth PMOS transistor MP6 receives the power supply signal VDD. The control terminal of the sixth PMOS transistor MP6 and the control terminal of the fifth PMOS transistor MP5 are jointly connected to the first terminal of the seventh PMOS transistor MP7, the control terminal of the fifth NMOS transistor MN5, and the control terminal of the sixth NMOS transistor MN6. The control terminals of the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8 jointly receive the first bias power supply signal IREF. The second terminal of the seventh NMOS transistor MN7 is connected to the fifth NMOS transistor MN5. The first terminal is connected to the second terminal of the eighth NMOS transistor MN8, which is connected to the first terminal of the sixth NMOS transistor MN6. The second terminal of the fifth NMOS transistor MN5 is grounded to GND, and the second terminal of the sixth NMOS transistor MN6 is grounded to GND. The first terminal of the eighth PMOS transistor MP8 and the second terminal of the eighth NMOS transistor MN8 are also connected to the clamping current comparison module 200. The control terminal of the reference signal receiving NMOS transistor MNR is connected to the control terminal of the seventh NMOS transistor MN7 and the control terminal of the eighth NMOS transistor MN8. The first terminal of the reference signal receiving NMOS transistor MNR is connected to the control terminal of the eighth NMOS transistor MN8 and the control terminal of the seventh NMOS transistor MN7 and receives the second bias power supply signal VB1. The second terminal of the reference signal receiving NMOS transistor MNR is grounded to GND.

[0048] Specifically, in this embodiment, the first terminals of the first PMOS transistors MP1 to MP8 can be their drains, the second terminals of the first PMOS transistors MP1 to MP8 can be their sources, and the control terminals of the first PMOS transistors MP1 to MP8 can be their gates. Similarly, the first terminals of the first NMOS transistors MN1 to MP8 can be their drains, the second terminals of the first NMOS transistors MN1 to MP8 can be their sources, and the control terminals of the first NMOS transistors MN1 to MP8 can be their gates.

[0049] When the common-mode levels of input signals INN and INP are high, the first NMOS transistor MN1 and the second NMOS transistor MN2 are turned on, and the rail-to-rail input module 100 works normally. When the common-mode levels of input signals INN and INP are low, the first PMOS transistor MP1 and the second PMOS transistor MP2 are turned on, and the circuit works normally. When the common-mode levels of input signals INN and INP are moderate, the first NMOS transistor MN1, the second NMOS transistor MN2, the first PMOS transistor MP1, and the second PMOS transistor MP2 are all turned on, and the rail-to-rail input module 100 still works normally. Therefore, the rail-to-rail input module 100 can handle input signals with a wide common-mode range.

[0050] When the on-rail input module 100 is working, and the differential signal in the input signal is high and the amplitude is large enough, the input signal INP is high and the input signal INN is low. At this time, the first NMOS transistor MN1 and the second PMOS transistor MP2 are turned on, the second NMOS transistor MN2 and the first PMOS transistor MP1 are turned off, and the current in the third PMOS transistor MP3 flows into the sixth NMOS transistor MN6, while the current in the third NMOS transistor MN3 is entirely provided by MN4.

[0051] Since the first PMOS transistor MP1 is off, the current in the seventh NMOS transistor MN7 is equal to the current in the fifth NMOS transistor. Because the current in the third NMOS transistor MN3 is entirely supplied by the fifth PMOS transistor MP5, the current flowing through MP5 is IP5 = IN3 + IP7 = IN3 + IN5, where IN3 is the current flowing through MN3, IP7 is the current flowing through MP7, and IN5 is the current flowing through MN5. Because the second NMOS transistor MN2 is off, the current flowing through the eighth PMOS transistor is IP8 = IP6 = IP5 = IP3 + IN5, where IP3 is the current flowing through MP3, IP5 is the current flowing through MP5, and IP6 is the current flowing through MP6. Since all of IP3 flows into the sixth NMOS transistor MN6, and the current in the sixth NMOS transistor MN6 remains unchanged, the current flowing through the eighth NMOS transistor MN8 is IN8 = IN6 - IP3, where IN6 is the current flowing through the sixth NMOS transistor MN6 and IP3 is the current flowing through the third PMOS transistor.

[0052] The current value Iout of the single-ended signal Vi output by the rail-to-rail output module 100 is:

[0053] Iout=IP8-IN8=IN3+IN5-(IN6-IP3)=IN3+IN5-IN6+IP3

[0054] In this embodiment, as the level of the single-ended signal Vi output by the rail-to-rail input module 100 increases, the drain voltages of the sixth PMOS transistor MP6 and the eighth PMOS transistor gradually increase and leave the saturation region, while the current flowing through the eighth PMOS transistor MP8 decreases. When IP8 = IN8 = IN6 = IN5, the single-ended signal Vi reaches its highest level, thereby realizing the conversion of the input signals INN and INP to the single-ended signal Vi.

[0055] In one embodiment, combined Figure 3As shown, the clamping current comparison module 200 includes an inverting unit 210 and a feedback unit 220. The inverting unit 210 is connected to the rail-to-rail input module 100 and is used to invert the single-ended signal Vi to generate a clamping current signal Vl. The feedback unit 220 is connected to the inverting unit 210 and is used to feed back the clamping current signal Vi from the output of the inverting unit 210 to the input of the inverting unit 210, thereby clamping the voltage of the single-ended signal Vi.

[0056] In this embodiment, the inverting unit 210 and the feedback unit 220 clamp the single-ended signal Vi output by the rail-to-rail input module 100, so that the single-ended signal Vi no longer leaves the saturation region, reducing the time for the single-ended signal Vi to recover to the saturation region, greatly reducing the transmission delay of the single-ended signal Vi, and improving the operating speed of the rail-to-rail hysteresis comparator circuit.

[0057] In one embodiment, combined Figure 3 As shown, the clamping current comparison module 200 also includes a switching unit 230. The switching unit 230 is connected to the inverting unit 210 and the feedback unit 220 respectively, and is used to control the connection state between the inverting unit 210 and the power supply, and the connection state between the feedback unit 220 and the power supply according to the switching control signals VB2 and VB3.

[0058] For details, see Figure 3 As shown, the switching unit 230 includes a ninth PMOS transistor MP9 and a ninth NMOS transistor MN9. The first terminal of the ninth PMOS transistor MP9 is connected to the second terminals of the tenth PMOS transistor MP10 and the eleventh PMOS transistor MP11. The second terminal of the ninth PMOS transistor MP9 is connected to a power supply and receives a power supply signal VDD. The control terminal of the ninth PMOS transistor receives a first switch control signal VB2. The first terminal of the ninth NMOS transistor MN9 is connected to the second terminals of the tenth NMOS transistor MN10 and the eleventh NMOS transistor MN11. The second terminal of the ninth NMOS transistor MN9 is grounded (GND). The control terminal of the ninth PMOS transistor receives a second switch control signal VB3.

[0059] In this embodiment, the first terminal of the ninth PMOS transistor MP9 and the ninth NMOS transistor MN9 can be their drain, the second terminal of the ninth PMOS transistor MP9 and the ninth NMOS transistor MN9 can be their source, and the control terminal of the ninth PMOS transistor MP9 and the ninth NMOS transistor MN9 can be their gate.

[0060] The ninth NMOS transistor MN9 and the ninth PMOS transistor MN9 are control switches. When the rail-to-rail hysteresis comparator circuit does not require the clamping current comparator module 200 to work, the ninth NMOS transistor MN9 and the ninth PMOS transistor MP9 are turned off, thereby reducing the power consumption of the clamping current comparator module 200.

[0061] In one embodiment, the inverting unit 210 includes a tenth NMOS transistor MN10 and a tenth PMOS transistor MP10. The first terminal of the tenth NMOS transistor MN10 and the first terminal of the tenth PMOS transistor MP10 are connected to the rail-to-rail input module 100. The second terminal of the tenth PMOS transistor MP10 receives the power supply signal VDD, and the second terminal of the tenth NMOS transistor MN10 is grounded to GND. The control terminals of the tenth PMOS transistor MP10 and the tenth NMOS transistor MN10 are connected to the hysteresis buffer module 300 and the feedback unit 220.

[0062] In this embodiment, the first terminal of the tenth PMOS transistor MP10 and the tenth NMOS transistor MN10 can be their drain, the second terminal of the tenth PMOS transistor MP10 and the tenth NMOS transistor MN10 can be their source, and the control terminal of the tenth PMOS transistor MP10 and the tenth NMOS transistor MN10 can be their gate.

[0063] When the single-ended signal Vi is near the equilibrium point of the circuit, the single-ended signal Vi and the clamping current signal Vl satisfy the following:

[0064] Vi-VN10 <Vl<Vi+VP10

[0065] Wherein, VN10 is the threshold voltage of the tenth NMOS transistor MN10, and NP10 is the threshold voltage of the tenth PMOS transistor. At this time, both the tenth NMOS transistor MN10 and the tenth PMOS transistor MP10 are in the off state. The clamping current comparison module 200 is equivalent to an ordinary inverter. When Vi deviates from the balance point, the tenth NMOS transistor MN10 or the tenth PMOS transistor MP10 will be turned on. The current flowing through the tenth NMOS transistor MN10 or the tenth PMOS transistor MP10 will be output to the input terminal of the inverter unit 210, thereby balancing the current of the single-ended signal Vi and stopping the voltage of the single-ended signal Vi from changing continuously, thus realizing the clamping function.

[0066] In one embodiment, see Figure 3 As shown, the feedback unit 220 includes an eleventh PMOS transistor NP11 and an eleventh NMOS transistor MP12. The first terminal of the eleventh PMOS transistor MP11 and the first terminal of the eleventh NMOS transistor MN11 are connected to the inverting unit 210. The second terminal of the eleventh PMOS transistor MP11 receives the power supply signal VDD, and the second terminal of the eleventh NMOS transistor MN11 is grounded to GND. The control terminals of the eleventh PMOS transistor MP11 and the eleventh NMOS transistor MN11 are connected to the rail-to-rail input module 100.

[0067] In this embodiment, the first terminal of the eleventh PMOS transistor MP11 and the eleventh NMOS transistor MN10 can be their drains, the second terminal of the eleventh PMOS transistor MP11 and the eleventh NMOS transistor MN11 can be their sources, and the control terminal of the eleventh PMOS transistor MP11 and the eleventh NMOS transistor MN11 can be their gates.

[0068] The eleventh NMOS transistor MN11 and the eleventh PMOS transistor MP11 provide a channel from the output terminal of the clamp current comparison module 200 to the input terminal of the clamp current comparison module 200, so that the clamp current signal Vl controls the tenth PMOS transistor MP10 and the tenth NMOS transistor MN10.

[0069] In one embodiment, see Figure 4 As shown, the hysteresis buffer module 300 includes a twelfth PMOS transistor MP12, a twelfth NMOS transistor MN13, a thirteenth PMOS transistor MP13, a thirteenth NMOS transistor MN13, a fourteenth PMOS transistor MP14, a fourteenth NMOS transistor MN14, a first inverter G1, and a second inverter G2.

[0070] The first terminal of the twelfth PMOS transistor MP11 is connected to the second terminal of the thirteenth PMOS transistor MP13. The second terminal of the twelfth PMOS transistor MP12 receives the power supply signal VDD. The control terminal of the twelfth PMOS transistor MP12 is connected to the clamping current comparator module 200. The first terminal of the thirteenth PMOS transistor MP13 is connected to the first terminal of the thirteenth NMOS transistor MN13. The control terminal of the thirteenth PMOS transistor MP13 is connected to the clamping current comparator module 200. The second terminal of the thirteenth NMOS transistor MN13 is connected to the first terminal of the twelfth NMOS transistor MN12. The control terminal of the thirteenth NMOS transistor MN13 is connected to the clamping current comparator module 200. The second terminal of the twelfth NMOS transistor MN12 is grounded to GND. The control terminal of the twelfth NMOS transistor MN12 is connected to the clamping current comparator module 200. The first terminal of transistor 12 is connected to the second terminal of transistor 14, which is also connected to the second terminal of transistor 13, which is also connected to the second terminal of transistor 14, which is also connected to the first terminal of transistor MN12, which is also connected to the second terminal of transistor MN14. The first terminal of transistor 14 is grounded. The control terminal of transistor 14 is connected to the first terminal of transistor 13, which is also connected to the first terminal of transistor MN13. The first terminal of transistor MN14 is grounded to GND. The input terminal of inverter G1 is connected to the first terminal of transistor 13, which is also connected to the first terminal of inverter G2. The output terminal of inverter G2 outputs a drive signal Vc.

[0071] In this embodiment, see continue to refer to Figure 4 As shown, the first terminals of the twelfth PMOS transistors MP12 to MP14 and the twelfth NMOS transistors MN12 to MN14 can be their drains, the second terminals of the twelfth PMOS transistors MP12 to MP14 and the twelfth NMOS transistors MN12 to MN14 can be their sources, and the control terminals of the twelfth PMOS transistors MP12 to MP14 and the twelfth NMOS transistors MN12 to MN14 can be their gates.

[0072] The twelfth PMOS transistor MP12, the twelfth NMOS transistor MN13, the thirteenth PMOS transistor MP13, the thirteenth NMOS transistor MN13, the fourteenth PMOS transistor MP14, and the fourteenth NMOS transistor MN14 constitute a Schmitt trigger, providing hysteresis functionality for the rail-to-rail hysteresis comparator. Meanwhile, the first inverter G1 and the second inverter G2 provide buffering functionality for the upcoming drive signal Vc to enhance the drive capability of LVDS.

[0073] In another aspect, this application provides an electronic device that includes the rail-to-rail hysteresis comparison circuit described in any of the above embodiments.

[0074] The rail-to-rail hysteresis comparator circuit includes a rail-to-rail input module, a clamping current comparator module, and a hysteresis buffer module. The rail-to-rail input module receives the input signal and bias power supply signal, and generates a single-ended signal based on these signals. The clamping current comparator module, connected to the rail-to-rail input module, receives the single-ended signal and bias power supply signal, clamps the voltage of the single-ended signal, and generates a clamping current signal. The hysteresis buffer module, connected to the clamping current comparator module, receives the clamping current signal, performs hysteresis buffering on the clamping current signal, and generates a drive signal. The rail-to-rail input module can operate normally with a wide common-mode range of the input signal, while the clamping current comparator module improves the operating speed of the rail-to-rail hysteresis comparator circuit.

[0075] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0076] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A rail-to-rail hysteresis comparator circuit, characterized in that, The rail-to-rail hysteresis comparison circuit includes: A rail-to-rail input module is used to receive an input signal and a bias power supply signal, and generate a single-ended signal based on the input signal and the bias power supply signal. The clamping current comparison module is connected to the rail-to-rail input module and is used to receive the single-ended signal and the bias power supply signal, and to perform clamping processing on the voltage of the single-ended signal to generate a clamping current signal. A hysteresis buffer module, connected to the clamping current comparison module, is used to receive the clamping current signal and perform hysteresis buffering processing on the clamping current signal to generate a drive signal. The rail-to-rail input module includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, and a reference signal receiving NMOS transistor; wherein, The control terminal of the first PMOS transistor is connected to the first input terminal of the input signal; the second terminal of the first PMOS transistor is connected to the first terminal of the third PMOS transistor; the first terminal of the first PMOS transistor is connected to the first terminal of the fifth NMOS transistor; the first terminal of the second PMOS transistor is connected to the first terminal of the sixth NMOS transistor; the second terminal of the second PMOS transistor is connected to the first terminal of the third PMOS transistor; the control terminal of the second PMOS transistor is connected to the second input terminal of the input signal; the first terminal of the first NMOS transistor is connected to the second terminal of the seventh PMOS transistor; the second terminal of the first NMOS transistor is connected to the first terminal of the third NMOS transistor; and the control terminal of the first NMOS transistor is connected to the second input terminal of the input signal. The first input terminal is connected to the second terminal of the eighth PMOS transistor, the second terminal of the second NMOS transistor is connected to the first terminal of the third NMOS transistor, the control terminal of the second NMOS transistor is connected to the second input terminal of the input signal, the second terminal of the third NMOS transistor is grounded, the control terminal of the third NMOS transistor is connected to the control terminal of the fourth NMOS transistor, the second terminal of the third PMOS transistor receives the power signal, the control terminal of the third PMOS transistor is connected to the control terminal of the fourth PMOS transistor, the first terminal of the fourth NMOS transistor is connected to the first terminal of the fourth PMOS transistor, the second terminal of the fourth NMOS transistor is grounded, and the second terminal of the fourth PMOS transistor receives the power signal. The second terminal of the fifth PMOS transistor receives the power signal. The first terminal of the fifth PMOS transistor is connected to the seventh PMOS transistor. The first terminal of the sixth PMOS transistor is connected to the second terminal of the eighth PMOS transistor. The second terminal of the sixth PMOS transistor receives the power signal. The control terminal of the sixth PMOS transistor and the control terminal of the fifth PMOS transistor are jointly connected to the first terminal of the seventh PMOS transistor, the control terminal of the fifth PMOS transistor, and the control terminal of the sixth PMOS transistor. The control terminals of the seventh PMOS transistor and the eighth PMOS transistor jointly receive the first bias power signal. The second terminal of the seventh PMOS transistor is connected to the first terminal of the fifth PMOS transistor. The second terminal of the eighth PMOS transistor is connected to the first terminal of the sixth PMOS transistor. The second terminal of the fifth PMOS transistor is grounded. The second terminal of the sixth NMOS transistor is grounded. The first terminal of the eighth PMOS transistor and the second terminal of the eighth NMOS transistor are also connected to the clamping current comparison module. The control terminal of the reference signal receiving NMOS transistor is connected to the control terminals of the seventh and eighth NMOS transistors. The first terminal of the reference signal receiving NMOS transistor is connected to the control terminals of the eighth and seventh NMOS transistors and receives the second bias power supply signal. The second terminal of the reference signal receiving NMOS transistor is grounded. The input signal includes a first input signal and a second input signal. The first access terminal is used to input the first input signal, and the second access terminal is used to input the second input signal. The amplitudes of the first input signal and the second input signal are the same, and the phases of the first input signal and the second input signal are opposite.

2. The rail-to-rail hysteresis comparison circuit as described in claim 1, characterized in that, Also includes: A bias power supply module, connected to the rail-to-rail input module and the clamping current comparison module, is used to provide a bias power signal to the rail-to-rail input module and the clamping current comparison module.

3. The rail-to-rail hysteresis comparison circuit as described in claim 2, characterized in that, The bias power supply module is a common-source cascode current mirror.

4. The rail-to-rail hysteresis comparison circuit as described in claim 2, characterized in that, The clamping current comparison module includes: An inverting unit, connected to the rail-to-rail input module, is used to invert the single-ended signal to generate the clamping current signal. A feedback unit, connected to the inverting unit, is used to feed back the clamping current signal from the output of the inverting unit to the input of the inverting unit, so as to clamp the voltage of the single-ended signal.

5. The rail-to-rail hysteresis comparison circuit as described in claim 4, characterized in that, The clamping current comparison module further includes: A switching unit is connected to the inverting unit and the feedback unit respectively, and is used to control the connection state between the inverting unit and the power supply, and the connection state between the feedback unit and the power supply according to the switching control signal.

6. The rail-to-rail hysteresis comparison circuit as described in claim 4, characterized in that, The inverting unit includes: a tenth NMOS transistor and a tenth PMOS transistor; wherein... The first terminal of the tenth NMOS transistor and the first terminal of the tenth PMOS transistor are connected to the rail-to-rail input module. The second terminal of the tenth PMOS transistor receives the bias power supply signal. The second terminal of the tenth NMOS transistor is grounded. The control terminals of the tenth PMOS transistor and the tenth NMOS transistor are connected to the hysteresis buffer module and the feedback unit.

7. The rail-to-rail hysteresis comparison circuit as described in claim 4, characterized in that, The feedback unit includes an eleventh PMOS transistor and an eleventh NMOS transistor; wherein... The first terminal of the eleventh PMOS transistor and the first terminal of the eleventh NMOS transistor are connected to the inverting unit. The second terminal of the eleventh PMOS transistor receives the power signal, and the second terminal of the eleventh NMOS transistor is grounded. The control terminals of the eleventh PMOS transistor and the eleventh NMOS transistor are connected to the rail-to-rail input module.

8. The rail-to-rail hysteresis comparison circuit as described in claim 1, characterized in that, The hysteresis buffer module includes a twelfth PMOS transistor, a twelfth NMOS transistor, a thirteenth PMOS transistor, a thirteenth NMOS transistor, a fourteenth PMOS transistor, a fourteenth NMOS transistor, a first inverter, and a second inverter; wherein, The first terminal of the twelfth PMOS transistor is connected to the second terminal of the thirteenth PMOS transistor. The second terminal of the twelfth PMOS transistor receives a power supply signal. The control terminal of the twelfth PMOS transistor is connected to the clamping current comparison module. The first terminal of the thirteenth PMOS transistor is connected to the first terminal of the thirteenth NMOS transistor. The control terminal of the thirteenth PMOS transistor is connected to the clamping current comparison module. The second terminal of the thirteenth NMOS transistor is connected to the first terminal of the twelfth NMOS transistor. The control terminal of the thirteenth NMOS transistor is connected to the clamping current comparison module. The second terminal of the twelfth NMOS transistor is grounded. The control terminal of the twelfth NMOS transistor is connected to... The clamping current comparison module has the first terminal of the twelfth PMOS transistor and the second terminal of the thirteenth PMOS transistor connected together to the second terminal of the fourteenth PMOS transistor. The second terminal of the thirteenth NMOS transistor and the first terminal of the twelfth NMOS transistor are also connected together to the second terminal of the fourteenth NMOS transistor. The control terminal of the fourteenth NMOS transistor is connected to the first terminal of the thirteenth PMOS transistor MP13. The first terminal of the fourteenth NMOS transistor is grounded. The input terminal of the first inverter is connected to the first terminal of the thirteenth PMOS transistor. The output terminal of the first inverter is connected to the input terminal of the second inverter. The output terminal of the second inverter outputs the drive signal.

9. An electronic device, characterized in that, The electronic device includes a rail-to-rail hysteresis comparison circuit as described in any one of claims 1 to 8.

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