Integrated iii-v / silicon optoelectronic devices and methods of manufacturing the same

Abstract

An optoelectronic device. The optoelectronic device comprises: a silicon-on-insulator platform comprising: a silicon waveguide located within a silicon device layer of the platform; a substrate; and an insulator layer located between the substrate and the silicon device layer; and a III-V semiconductor-based device located within a cavity of the silicon-on-insulator platform and comprising a III-V semiconductor-based waveguide coupled to the silicon waveguide; wherein the III-V semiconductor-based device comprises a heater and one or more electrical traces connected to the heater, wherein the one or more electrical traces extend from the III-V semiconductor-based device to respective contact pads on the silicon-on-insulator platform.

Description

Technical Field

[0001] The present invention relates to an integrated III-V / silicon optoelectronic device and a method for manufacturing the same. Background Art

[0002] Hybrid integration of III-V semiconductor-based electro-optical devices (e.g., modulators) with silicon-on-insulator (SOI) platforms offers the advantages of combining the best parts of both material systems.

[0003] However, conventional chip bonding processes typically use flip-chip bonding, in which a III-V semiconductor-based device is inverted and bonded into a cavity on an SOI platform. Devices fabricated using these methods often suffer from high optical coupling losses between the waveguides in the III-V semiconductor-based device and the waveguides in the SOI. Furthermore, due to the difficulty in accurately controlling the alignment of the respective waveguides, the fabrication process has relatively low yield and reliability.

[0004] Therefore, microtransfer printing (MTP) is being considered as an alternative way to integrate III-V semiconductor-based devices with SOI wafers. In these methods, a III-V semiconductor-based device in the form of a device coupon can be printed into a cavity on SOI in the same orientation as it was fabricated, and the alignment between the III-V semiconductor-based waveguide and the SOI waveguide is predetermined in the vertical direction (Z direction). As a result, the alignment requirements are reduced from three dimensions to two dimensions, which can be more easily facilitated.

[0005] It is known that the band gap of III-V semiconductors varies with temperature. As temperature increases, the band gap generally decreases, resulting in a corresponding increase in the operating wavelength (redshift). By varying the operating temperature, the operating wavelength of III-V semiconductor-based electroabsorption modulators (EAMs) can be tuned. For example, for coarse wavelength division modulator (CWDM) applications, the same EAM can be operated at multiple wavelengths (e.g., four or more) by adjusting the operating temperature.

[0006] However, incorporating heaters into III-V semiconductor-based EAMs presents several challenges. First, when using MTP processes, substrate real estate in III-V semiconductor device prototypes is at a premium, and therefore accommodating contact pads for heaters can compromise device performance. Second, heaters can negatively impact the speed and / or bandwidth of EAM operation, for example by interfering with the EAM's electrodes. Finally, the heater's fabrication process is often inconsistent with that of the III-V semiconductor device prototype.

[0007] The present invention aims to solve the above-mentioned problems. Summary of the Invention

[0008] Thus, in a first aspect, embodiments of the present invention provide an optoelectronic device comprising:

[0009] A silicon-on-insulator platform, comprising:

[0010] a silicon waveguide within a silicon device layer of the platform; a substrate; and an insulator layer between the substrate and the silicon device layer; and

[0011] a III-V semiconductor-based device located within a cavity of the silicon-on-insulator platform and comprising a III-V semiconductor-based waveguide coupled to the silicon waveguide;

[0012] The III-V semiconductor based device includes a heater and one or more electrical traces connected to the heater, wherein the one or more electrical traces extend from the III-V semiconductor based device to corresponding contact pads on the silicon-on-insulator platform.

[0013] Such optoelectronic devices benefit from including a heater without suffering from the drawbacks discussed above. Specifically, providing contact pads for the heater on a silicon-on-insulator platform ensures that the speed and / or bandwidth of the III-V semiconductor-based device is not affected by the heater. Furthermore, substrate real estate in the III-V semiconductor device is preserved.

[0014] The optoelectronic device may have any one of the following optional features or any combination of the following optional features to the extent that the following optional features are compatible.

[0015] The one or more electrical traces connected to the heater may be laterally spaced apart from one or more traces electrically connected to one or more electro-optically active components in the III-V semiconductor-based device. This may ensure that the traces of the heater do not interfere with the traces of the one or more electro-optically active components.

[0016] The III-V semiconductor based device may be formed from any one or more of: InP, InGaAsP, AlInGaAs, and InGaNAs.

[0017] The III-V semiconductor based waveguide may be curved, and the heater may be positioned adjacent to the waveguide and have a corresponding curved portion.The heater may be located on an inner region of the curved III-V semiconductor based waveguide.

[0018] The heater may be a doped region of the III-V semiconductor based device.The doped region may be doped with an n-type or p-type doping species.

[0019] The heater may be a metal region on or adjacent to the III-V semiconductor based device.The metal may be selected from the list comprising: titanium, titanium nitride, chromium and nickel.

[0020] The silicon-on-insulator platform may include a thermally isolated cavity at least partially underlying the III-V semiconductor-based device. Such a cavity may help thermally isolate the heater within the III-V semiconductor-based device and thereby improve the efficiency of the heater.

[0021] A portion of the heater closest to the electro-optically active component of the III-V semiconductor-based device may be at least 3 μm away from the electro-optically active component in the III-V semiconductor-based device. This may help ensure uniform heating over the spatial region defining or including the electro-optically active component.

[0022] The III-V semiconductor-based device may include an electroabsorption modulator (EAM). The EAM may be formed by a p-doped region facing an n-doped region across an intrinsic region, thereby forming a pin junction. Application of a voltage to the p-doped and n-doped regions generates an electric field across the pin junction. The absorption profile of the junction for light passing therethrough varies with the applied electric field. The refractive index may also change with the applied electric field.

[0023] In a second aspect, embodiments of the present invention provide a method for manufacturing an optoelectronic device, the method comprising the steps of:

[0024] A silicon-on-insulator platform is provided, the platform comprising:

[0025] a silicon waveguide within a device layer; a substrate; an insulator layer between the substrate and the silicon device layer; and a cavity;

[0026] Providing a III-V semiconductor-based device test piece, the III-V semiconductor-based device test piece comprising a III-V semiconductor-based waveguide and a heater;

[0027] Transferring the III-V semiconductor-based device coupon into the cavity of the silicon-on-insulator platform; and

[0028] The heater is electrically connected to one or more contact pads provided in the silicon-on-insulator platform through one or more traces.

[0029] This manufacturing method avoids any conflict between the heater manufacturing process and the III-V semiconductor based waveguide manufacturing process.

[0030] The method may include, before electrically connecting to the heater, the step of spin-coating a dielectric material into one or more trenches between the device coupon and one or more sidewalls of the cavity of the silicon-on-insulator platform. The method may include, after spin-coating the dielectric material, the step of thermally curing the dielectric material.

[0031] After transferring the III-V semiconductor-based device coupon, the method may include depositing a passivation layer on the exposed upper surface of the III-V semiconductor-based device coupon. The passivation layer improves the durability and reliability of the device. After depositing the passivation layer, the method may include opening a contact window above the heater before electrically connecting the heater to the one or more contact pads via the one or more traces.

[0032] The method may include, before transferring the III-V semiconductor based device coupon, the step of etching a thermally insulating cavity into a bed of the cavity in the silicon-on-insulator platform.

[0033] In a third aspect, embodiments of the present invention provide a method of manufacturing a III-V semiconductor based device test piece, the method comprising the steps of:

[0034] Providing a multi-layer stack of III-V semiconductor layers;

[0035] fabricating one or more III-V semiconductor-based photoactive components from the multilayer stack;

[0036] fabricating a heater in or on one of the III-V semiconductor layers; and

[0037] One or more electrical traces are provided from the heater to the III-V semiconductor based device coupon.

[0038] The method may include the step of providing an antireflection coating around one or more lateral sides of the device coupon. The antireflection coating may serve two purposes: (i) reducing optical losses of light entering a waveguide in the III-V semiconductor-based device coupon; and (ii) helping to protect the lateral sides of the device coupon.

[0039] In a fourth aspect, an embodiment of the present invention provides a method for preparing a silicon-on-insulator platform for a transfer process, wherein the silicon-on-insulator platform includes a device cavity, in which a III-V semiconductor device specimen including a heater can be deposited, the method comprising the following steps: etching one or more insulating cavities into a base bed of the device cavity.

[0040] In a fifth aspect, embodiments of the present invention provide a III-V semiconductor-based device coupon suitable for transfer printing onto a silicon-on-insulator platform, the device coupon comprising:

[0041] III-V semiconductor-based waveguides; and

[0042] Heater.

[0043] The device coupon of the fifth aspect may have any one of the optical features set out with reference to the other aspects of the invention or any combination of the following optional features to the extent they are compatible.

[0044] The device coupon may not include any electrical contacts suitable for wire bonding to the heater, but may instead have one or more electrical pads for connecting to traces.

[0045] In a sixth aspect, embodiments of the present invention provide a silicon-on-insulator platform for use in a transfer process, the silicon-on-insulator platform comprising:

[0046] one or more silicon waveguides; and

[0047] a cavity comprising sidewalls to which the one or more silicon waveguides are optically coupled;

[0048] The cavity includes a heat-insulating cavity formed in its base bed.

[0049] The silicon-on-insulator platform of the sixth aspect may include any one of the optical features set forth with reference to other aspects of the invention or any combination of the following optional features to the extent they are compatible.

[0050] In a seventh aspect, embodiments of the present invention provide an optoelectronic device manufactured according to the method of the second aspect.

[0051] In an eighth aspect, embodiments of the present invention provide a III-V semiconductor based device coupon as fabricated according to the third aspect.

[0052] In a ninth aspect, embodiments of the present invention provide a silicon-on-insulator platform for a transfer process as prepared according to the method of the fourth aspect.

[0053] Other aspects of the present invention provide: a computer program comprising code, which, when run on a computer, causes the computer to perform the method of the second, third or fourth aspect; a computer-readable medium, which stores a computer program comprising code, which, when run on a computer, causes the computer to perform the method of the second, third or fourth aspect; and a computer system programmed to perform the method of the second, third or fourth aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Embodiments of the present invention will now be described by way of example with reference to the accompanying drawings, in which:

[0055] Figure 1 A schematic top view of an optoelectronic device according to an embodiment of the present invention is shown;

[0056] Figure 2A yes Figure 1 A cross-sectional view along line ABCDE;

[0057] Figure 2B yes Figure 1 A cross-sectional view along line ABCDE showing a variant optoelectronic device;

[0058] Figure 2C yes Figure 1 A cross-sectional view along line ABCDE showing a variant optoelectronic device;

[0059] Figure 2D yes Figure 1 A cross-sectional view along line ABCDE showing a variant optoelectronic device;

[0060] Figure 3(i) to Figure 3(xiv) shows various stages of fabrication of a III-V semiconductor based device test piece according to an embodiment of the present invention;

[0061] Figure 4(i) to Figure 4(vi) illustrating various stages of fabrication of a silicon-on-insulator platform according to an embodiment of the present invention;

[0062] Figure 5(i) to Figure 5(x) illustrates various stages of fabrication of an optoelectronic device according to an embodiment of the present invention; and

[0063] Figure 6(i) to Figure 6(iv) Various fabrication processes for III-V semiconductor based device coupons according to embodiments of the present invention are shown. DETAILED DESCRIPTION

[0064] Various aspects and embodiments of the present invention will now be discussed with reference to the accompanying drawings. Other aspects and embodiments will be apparent to those skilled in the art.

[0065] Figure 1 A schematic top view of an optoelectronic device 100 according to an embodiment of the present invention is shown. In the top view, various upper layers (eg, an upper passivation layer) are omitted for clarity.

[0066] In summary, device 100 is formed by a III-V semiconductor-based device coupon 102 located within a cavity 111 defined by a cavity edge 112 on a silicon-on-insulator platform 104. The portion of the cavity not occupied by device coupon 102 (i.e., between device coupon edge 113 and cavity edge 112) is filled with a dielectric material. The device coupon includes a III-V semiconductor-based waveguide, which in this example is "U"-shaped, such that the input and output portions of the waveguide abut the same sidewall of cavity 111.

[0067] A silicon-on-insulator platform 104 includes two silicon waveguides 103 whose ribs taper from a first width adjacent to the edge of the platform 104 through corresponding tapers 105 to a second width adjacent to the cavity 111. The first width is wider than the second width. Each silicon waveguide terminates in a facet 106 at the end closest to the cavity. In this example, the facets are T-bar facets. A corresponding facet 107 is located at each end of the "U"-shaped III-V semiconductor-based waveguide 101.

[0068] As discussed in more detail below, a III-V semiconductor based waveguide comprises two electro-optically active layers: an n-doped layer and a p-doped layer. The n-doped layer is connected to the n-electrode 115 and the p-doped layer is connected to the p-electrode 114, and vice versa.

[0069] The III-V device coupon 102 also includes a heater 108, which is located in proximity to the III-V semiconductor-based waveguide 101. The heater 108 in this example has a curved shape corresponding in curvature to the "U"-shaped waveguide 101. The heater is located on the inside of the curved portion of the "U"-shaped waveguide. Metal traces 110 extend from contact pads on the silicon-on-insulator platform to the III-V semiconductor-based device coupon 102 to contact metal pads 109 for the heater 108. It should be noted that these electrodes are located away from the p-electrode 114 and n-electrode 115 so as not to interfere with the operation of the electro-optically active layer.

[0070] Figure 2A yes Figure 1 The cross-sectional view along line ABCDE shows the structure of the optoelectronic device 100 in more detail. Figure 1A silicon dioxide passivation layer 201 extending from the upper surface of device 100, omitted from the diagram, is shown in this view. The cross-sectional view shows that the cavity in the silicon-on-insulator platform extends through the device layer (upper silicon layer), through the buried oxide layer (BOX), and partially into the silicon substrate (Si_Sub). The exact depth of the cavity is selected so that the optical mode in the III-V semiconductor-based waveguide 101 is aligned with the optical mode in the silicon waveguide 103.

[0071] The cross-sectional view shows that waveguide 101 is formed from a p-doped upper layer, an intrinsic layer 203, and an n-doped lower layer. Of course, the order can be reversed. The p-doped layer is connected to a p-electrode 114, and the n-doped layer is connected to an n-electrode 115. It can also be seen that heater 108 is connected to heater electrode 109 via a trace. The heater in this example is formed from an n-doped region that is electrically isolated from the n-doped region within waveguide 101.

[0072] The cross-sectional view also shows a waveguide taper 105 that tapers from a first optical mode having a first width and height to a second optical mode having a second width and height. Furthermore, details regarding the coupling between the III-V semiconductor waveguide 101 and the silicon waveguide 103 are shown. It should be noted that an anti-reflective coating (ARC) is applied to the lateral sides of the device coupon and one or more sidewalls of the cavity. The remaining space between the device coupon and the cavity is filled with a dielectric, such as benzocyclobutene (BCB), to act as a waveguide bridge.

[0073] Figure 2B yes Figure 1 A cross-sectional view along line ABCDE showing a variant optoelectronic device. Figure 2B Optoelectronic devices and Figure 2A Where features are common to the devices shown, like features are indicated by like reference numerals.

[0074] It should be noted that Figure 2B In the example, heater 205 is configured as a metal region within silicon dioxide portion 201, located between dielectric 202 and an n-doped region. The metal region can be formed from titanium, titanium nitride, chromium, or nickel. The metal region provides greater control over the heater's resistance and can be used to create more targeted heating; for example, a wider metal region can be used for lower resistance heating away from desired locations, while a narrower metal region can be used for higher resistance and greater heating near desired locations.

[0075] Figure 2C yes Figure 1 A cross-sectional view along line ABCDE showing a variant optoelectronic device. Figure 2C Optoelectronic devices and Figure 2A Where features are common to the devices shown, like features are indicated by like reference numerals.

[0076] Figure 2C The devices in Figure 2A The device shown differs in that an insulating cavity 206, preferably containing only air, is positioned beneath a portion of the device specimen. The insulating cavity improves the efficiency of the heater by at least partially thermally isolating the heater and pin bond from the substrate. The insulating cavity can have a shape corresponding to the shape of the heater, i.e., a "U" shape. The insulating cavity can be square or rectangular, or any shape as long as there is sufficient space for the specimen to bond to the cavity without affecting the mechanical reliability of the specimen.

[0077] Figure 2D yes Figure 1 A cross-sectional view along line ABCDE showing a variant optoelectronic device. Figure 2D Optoelectronic devices and Figure 2A Where features are common to the devices shown, like features are indicated by like reference numerals.

[0078] Figure 2D The devices in Figure 2A The device shown differs in that heater 205 is configured as a metal region within silicon dioxide portion 201, located between dielectric 202 and an n-doped region. The metal region can be formed from titanium, titanium nitride, chromium, or nickel. Furthermore, an insulating cavity 206, preferably containing only air, is positioned beneath a portion of the device specimen. The insulating cavity improves heater efficiency by at least partially thermally isolating the heater and pin bond from the substrate.

[0079] Figure 3(i) to Figure 3(xiv) Various stages of fabrication of a III-V semiconductor based device test piece according to an embodiment of the present invention are shown.

[0080] In a first step shown in FIG3( i), a multilayer stack of III-V semiconductor layers is provided. From the top downward, the stack includes: a p-doped layer 301; an intrinsic (undoped) layer 302; an n-doped layer 303; an intrinsic or unintentionally doped indium phosphide (InP) layer 304; a sacrificial layer 305; and an InP substrate. In some examples, each of the p-doped layer 301, the intrinsic layer 302, and the n-doped layer 303 may be formed from multiple sublayers, each having a different composition and / or a different doping concentration. One or more p-doped layers may be formed from InGaAs, InGaAsP, InP, and AlInAs. One or more intrinsic layers may be formed from AlInGaAs multiple quantum wells and InGaAsP spacer layers. One or more n-doped layers may include InP with various doping levels. One or more sacrificial layers may include InGaAs and AlInAs.

[0081] Next, in the step shown in Figure 3(ii), a gold bar or other conductor 307 is deposited on the uppermost surface of the stack to act as a seed for the metallization step that will be performed later. Thereafter, in the step shown in Figure 3(iii), a hard mask 308 is deposited and patterned to define the III-V semiconductor-based waveguides that will be fabricated using the multilayer stack. In this example, the hard mask 308 is approximately 500 nm wide (as measured in the 'y' direction) and is formed of silicon dioxide (SiO2).

[0082] After setting the hard mask 308, an etch is performed. The etch extends completely through the p-doped layer and the intrinsic layer, and may extend partially into the n-doped layer 303. This partial etch is to ensure that the optical mode is completely and strongly confined, and that electrical contact to the n-layer can be provided. This is shown in Figure 3(iv). The overetch into the n-layer may extend into the n-doped layer by about 100 nm. This etch defines the geometry of the III-V semiconductor-based waveguide. After this etch step, the hard mask 308 is removed and a passivation layer 309 is deposited, which in this example is formed by a 300 nm layer of silicon dioxide. The result of this step is shown in Figure 3(v).

[0083] Next, two windows are opened in the passivation layer through the passivation layer to the n-doped layer 303, and gold or other conductors are deposited onto the upper surface of the n-doped layer through the two windows. The result of the steps is shown in Figure 3 (vi). One window provides a heater electrode seed 310 for the heater electrode provided in the subsequent metallization step, and the other window provides an n-electrode seed 311 for the n-electrode provided in the subsequent metallization step. After providing the seeds 310 and 311, an additional passivation layer 312 is provided to surround the upper surface of the seeds, as shown in Figure 3 (vii). In this example, an additional 200 nm of silicon dioxide is provided, resulting in a passivation layer with a thickness of 500 nm (excluding the location of the seeds, which has a thickness of approximately 200 nm).

[0084] Next, in the step shown in Figure 3(viii), the structure is patterned and the heater 108 is etched from the n-doped region. As shown, the width of the heater is at least 3 μm and no more than 10 μm, and is separated from the remaining n-doped region by at least 3 μm and no more than 6 μm. The etching is performed so that the heater is electrically isolated from the n-doped layer 303. The etching is performed so that at least 2 μm and no more than 5 μm of the n-doped layer 303 extends from the now formed waveguide toward the heater 108. This etching also provides an isolation area for the p-electrode 114 (not shown). Typically, the n-doped layer 303 has a sheet resistance between 4 Ω per square and 6 Ω per square, and therefore the specific dimensions of any given heater will depend on the temperature requirements of the EAM in which the heater is manufactured. Such requirements typically include: drive voltage; power consumption; temperature to be reached; and heating time.

[0085] After the heater is provided, in the step shown in Figure 3(ix), further etching is performed to define the III-V semiconductor waveguide facets (the coupling interface between the III-V semiconductor-based waveguide and the silicon waveguide once provided in the silicon-on-insulator platform). Further silicon dioxide is also provided.

[0086] Next, in the step shown in Figure 3(x), a dielectric material 202 (such as benzocyclobutene) is used to refill the previously etched space, except for the waveguide facet etching. A planarization etch is performed after providing the dielectric, and then the device is covered with another layer of silicon dioxide 201. Subsequently, in the step shown in Figure 3(xi), heater vias 313, p-electrode vias 314, and n-electrode vias 315 are opened, thereby exposing the upper surfaces of the heater seed, p-electrode seed, and n-electrode. This allows the subsequent metallization step to be performed, the results of which are shown in Figure 3(xii). The metallization step provides heater electrode 109, p-electrode 114, and n-electrode 115. The heater electrode extends through the silicon dioxide and dielectric to electrically connect to heater 108. Similarly, the p-electrode and n-electrode extend downward to electrically connect to the p-doped region and n-doped region, respectively. The n-electrode is connected to a portion of the n-doped region that is laterally spaced apart from the intrinsic region.

[0087] Following the metallization step, in the step shown in FIG3(xiii), an antireflective coating 316 is provided around the lateral and upper surfaces of the device coupon 102. The antireflective coating is typically formed of silicon nitride (e.g., Si3N4). Following this deposition, the device coupon 102 is patterned and etched to provide a generally rectangular device coupon (as viewed from above). Finally, a photoresist tether 317 is provided over the lateral and upper surfaces of the device coupon and the sacrificial layer is etched away. The device coupon is thus held to the InP substrate solely by the photoresist tether 317, as shown in FIG3(xiv).

[0088] Figure 4(i) to Figure 4(vi) Various stages of fabrication of a silicon-on-insulator platform according to an embodiment of the present invention are shown. In the first step, shown in FIG4(i), a silicon-on-insulator (SOI) wafer is provided. The SOI wafer comprises a silicon substrate 401 (Si-Sub), on top of which is a buried oxide layer (typically SiO2) 402 (BOX). On top of the buried oxide is an SOI layer 403, also referred to as the device layer. The buried oxide layer is approximately 400 nm high, as measured from the top surface of the substrate to the top surface of the buried oxide layer. The device layer is approximately 3000 nm or 3 μm high, as measured from the top surface of the BOX layer 402 to the top surface of the SOI layer 403.

[0089] Next, in the step shown in FIG4(ii), an etch mask 404 is placed over a portion of the device layer 403. The exposed device layer is then etched to provide a tapered cavity 405. The tapered cavity has a depth of approximately 1200 nm, leaving an 1800 nm high SOI portion. This etch thus provides the waveguide taper 105 discussed above, from a 3 μm silicon waveguide to a 1.8 μm silicon waveguide.

[0090] Another etch mask 404 is then applied, and the device cavity 406 is subsequently etched, as shown in FIG4(iii). The depth of the device cavity is selected so that the optical mode of the 1.8 μm silicon waveguide is vertically aligned with the optical mode of the III-V semiconductor-based waveguide to be bonded to the bed of the device cavity. The surface roughness of the bed of the cavity should be less than 1 nm. The surface roughness is typically measured by atomic force microscopy and can be defined as the surface roughness parameter R a 、R z or R MAX The measurement area is typically about 10 μm x 10 μm.

[0091] After the device cavity 406 is provided, an antireflection coating is provided on the sidewalls of the device cavity facing the III-V semiconductor-based waveguide (i.e., the 1.8 μm silicon waveguide facet) in the device specimen 102. The antireflection coating is typically formed of silicon nitride (e.g., Si3N4) and is approximately 180 nm wide.

[0092] Optionally, in the step shown in FIG4(v), an insulating cavity 206 can be etched into a portion of the device cavity bed. Further optionally, an adhesive layer 407 can be provided in a step that can be performed in addition to or instead of etching the insulating cavity. This is shown in FIG4(vi). The adhesive layer can be a spin-on dielectric, such as BCB or Intervia (available from Kayaku Advanced Materials). The adhesive layer, if provided, can have a thickness of at least 30 nm and no greater than 100 nm.

[0093] Figure 5(i) to Figure 5(x) Various stages of fabrication of an optoelectronic device according to an embodiment of the present invention are shown. Figure 5(i) to Figure 5(x) The steps shown are along the Figures 2A to 2D 5(i) , a stamp 501 (preferably formed of an elastomer) is attached to the photoresist 317 covering the upper surface of the device coupon 102. The device coupon 102 is then released from the InP substrate. Next, as shown in FIG5(ii), the device coupon 102 is printed into the device cavity 406 of the silicon-on-insulator platform 104. In this step, x and z alignment (i.e., lateral alignment) occurs, so that the III-V semiconductor-based waveguide is aligned with the silicon waveguide in the silicon-on-insulator platform 104.

[0094] The stamp is then removed, as shown in FIG5(iii), with the device coupon 102 remaining within the cavity 406. Next, the photoresist tether 317 is removed (e.g., by dry etching), and the device coupon is bonded to the device cavity 406. This bonding can be performed, for example, by annealing the coupon and platform combination at a temperature of at least 280°C and not more than 300°C for at least 1 hour and not more than 15 hours. The result of this step is shown in FIG5(iv). FIG5(v) shows a variation in which an optional thermal insulation cavity 206 has been etched into the bed of the device cavity.

[0095] Once the device coupon 102 is bonded to the silicon-on-insulator platform 104, the dielectric 202 is spin-coated and thermally cured. In one example, the thermal cure is performed at approximately 280°C for approximately 60 minutes in nitrogen (N2). The result of this step is shown in FIG5(vi). The dielectric 202 acts as a bridge between the one or more silicon waveguides 103 and the III-V semiconductor-based waveguide 101. Next, the dielectric extending above the uppermost surface of the device coupon 102 is etched back. This is shown in FIG5(vii).

[0096] Next, a silicon dioxide layer 201 is deposited over the upper surface of the test piece and platform. This layer has a thickness of approximately 500 nm and serves to passivate the fabricated optoelectronic device. The result of this step is shown in Figure 5(viii). After depositing the silicon dioxide layer 201, three openings are made: a heater contact opening 502; a p-electrode opening 503; and an n-electrode opening 504. A wire bonding or metallization process is then performed, as shown in Figure 5(x), to provide metal traces and pads 110 for the heater on the silicon-on-insulator platform, as well as a p-electrode 114 and an n-electrode 115.

[0097] Figure 6(i) to Figure 6(iv) Various fabrication processes for device samples based on III-V semiconductors according to embodiments of the present invention are shown. Figures 3(i) to 3(v) 6(i) . In this step, an n-electrode seed metal 311 is provided on the upper surface of the n-doped layer 303 through a window in the silicon dioxide layer 312 .

[0098] Next, in the step shown in Figure 6(ii), additional silicon dioxide is provided over the structure. Thus, except for the region containing the seed metal 311 (approximately 200 nm thick), there is a 500 nm thick SiO2 layer over the structure. Thereafter, in one or more steps not shown, an isolation region is etched for the p-electrode. Subsequently, in the step shown in Figure 6(iii), a heater 205 is deposited over a portion of the silicon dioxide layer 312. The heater has a width of at least 3 μm and not more than 10 μm and is positioned at least 3 μm and not more than 6 μm from the closest portion of the III-V semiconductor-based waveguide. The heater has a thickness of at least 150 nm and not more than 350 nm (as measured from the uppermost surface of the silicon dioxide layer adjacent to the heater to the uppermost surface of the heater). As previously discussed, the heater can be formed of titanium, titanium nitride, chromium or nickel. After the heater is provided, in the step shown in Figure 6(iv), additional silicon dioxide is provided to encapsulate the heater. Additionally, waveguide facet etching is performed. After this step, the process is as shown in Figure 6(iii). Figure 3(x) to Figure 3(xiv) Continue as shown.

[0099] Although the present invention has been described in conjunction with the exemplary embodiments described above, many equivalent modifications and variations will be apparent to those skilled in the art upon presentation of this disclosure. Therefore, the exemplary embodiments of the present invention set forth above are to be considered illustrative rather than restrictive. Various changes may be made to the described embodiments without departing from the spirit and scope of the present invention.

[0100] Feature List

[0101] 100 Optoelectronic Devices

[0102] 101 Waveguides based on III-V semiconductors

[0103] 102 III-V device specimens

[0104] 103 Silicon Waveguide

[0105] 104 Silicon-on-Insulator Platform

[0106] 105 Silicon waveguide tapered section

[0107] 106 silicon waveguide facets

[0108] 107 III-V waveguide facets

[0109] 108 Heater

[0110] 109 Metal pad / heater electrode

[0111] 110 Metal Traces and Pads on SOI

[0112] 111 SOI cavity filled with dielectric material

[0113] 112 SOI cavity edge

[0114] 113 III-V device specimen edge

[0115] 114 P III-V semiconductor device electrodes

[0116] 115 N III-V semiconductor device electrodes

[0117] 201 Silica

[0118] 202 Dielectric Materials

[0119] 203 Intrinsic Zone

[0120] 204 Anti-reflective coating

[0121] 205 Heater

[0122] 206 Insulated Cavity

[0123] 301 P-doped layer

[0124] 302 intrinsic layer

[0125] 303 N-doped layer

[0126] 304 UIID indium phosphide (InP) layer

[0127] 305 Sacrificial Layer

[0128] 306 Indium Phosphide (InP) substrate

[0129] 307 Seed Gold Metal Deposition

[0130] 308 silicon dioxide hard mask

[0131] 309 300 nm silicon dioxide layer

[0132] 310 Heater Seed Metal Deposition

[0133] 311 N-electrode seed metal deposition

[0134] 312 500 nm silicon dioxide layer

[0135] 313 Heater through hole

[0136] 314 P electrode through hole

[0137] 315 N electrode through hole

[0138] 316 Anti-reflective coatings and protective layers

[0139] 317 Photoresist Tether

[0140] 401 silicon substrate

[0141] 402 buried oxide layer

[0142] 403 silicon device layer

[0143] 404 Etching Mask

[0144] 405 tapered cavity

[0145] 406 device cavity

[0146] 407 adhesive layer

[0147] 501 Impression

[0148] 502 Heater contact opening

[0149] 503 P electrode opening

[0150] 504 N electrode opening

Claims

1. An optoelectronic device comprising: A silicon-on-insulator platform, comprising: a silicon waveguide within a silicon device layer of the platform; a substrate; and an insulator layer between the substrate and the silicon device layer; and a III-V semiconductor-based device coupon located within a cavity of the silicon-on-insulator platform and comprising a III-V semiconductor-based waveguide coupled to the silicon waveguide, wherein the III-V semiconductor-based waveguide comprises an n-doped layer and a p-doped layer and is curved such that input and output portions of the III-V semiconductor-based waveguide abut a same sidewall of the cavity; The device test piece based on III-V semiconductor includes a heater positioned adjacent to, along an inner region of, and 3 μm to 6 μm from the curved III-V semiconductor-based waveguide; one or more electrical traces connected to the heater, wherein the one or more electrical traces extend from the III-V semiconductor based device coupon to corresponding contact pads on the silicon-on-insulator platform; an n-electrode connected to the n-doped layer, and a p-electrode connected to the p-doped layer, and wherein the one or more traces connected to the heater are distal to the n-electrode and the p-electrode and laterally spaced apart from one or more traces electrically connected to one or more electro-optically active components in the III-V semiconductor based device. 2 . The optoelectronic device of claim 1 , wherein the heater is a doped region of the III-V semiconductor based device. The optoelectronic device of claim 2 , wherein the doped region is doped with an n-type dopant species. 4 . The optoelectronic device of claim 1 , wherein the heater is a metal region on or adjacent to the III-V semiconductor based device.

5. The optoelectronic device of claim 4, wherein the metal is selected from the list consisting of titanium, titanium nitride, chromium, and nickel. 6 . The optoelectronic device of claim 1 , wherein the silicon-on-insulator platform comprises a further cavity at least partially underlying the III-V semiconductor based device.

7. A method for manufacturing the optoelectronic device according to claim 1, comprising the following steps: Providing the silicon-on-insulator platform and the device test piece based on III-V semiconductor; Transferring the III-V semiconductor-based device specimen into the cavity of the silicon-on-insulator platform; as well as The heater is electrically connected to one or more contact pads disposed in the silicon-on-insulator platform through the one or more traces.

8. The method according to claim 7, further comprising the following steps before electrically connecting the heater: A dielectric material is spin-coated into one or more trenches between the device coupon and one or more sidewalls of the cavity of the silicon-on-insulator platform.

9. The method of claim 8, wherein the method comprises the following steps after spin coating the dielectric material: The dielectric material is thermally cured.

10. The method according to any one of claims 7 to 9, further comprising the following steps after transferring the III-V semiconductor-based device specimen: A passivation layer is deposited over the exposed upper surface of the III-V semiconductor based device coupon.

11. The method according to claim 10, further comprising the following steps after depositing the passivation layer: A contact window is opened over the heater before electrically connecting the heater to the one or more contact pads through the one or more traces.

12. The method according to any one of claims 7 to 8, wherein the method comprises the following steps before transferring the III-V semiconductor based device specimen: An insulating cavity is etched into a bed of the cavity in the silicon-on-insulator platform.

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