Solid-state imaging device and imaging apparatus

Abstract

A solid-state imaging device according to the present disclosure is provided with a plurality of first photoelectric conversion elements, a plurality of second photoelectric conversion elements, a plurality of current-voltage conversion circuits (320, 320A), and a plurality of address event detection circuits (231, 231A). The plurality of first photoelectric conversion elements are arranged side by side in a first region. The plurality of second photoelectric conversion elements are arranged side by side in a second region adjacent to the first region. The plurality of current-voltage conversion circuits (320, 320A) respectively convert currents output from the plurality of first photoelectric conversion elements and the plurality of second photoelectric conversion elements into voltages. The plurality of address event detection circuits (231, 231A) respectively detect changes in the voltages output from the plurality of current-voltage conversion circuits (320, 320A). At least one of the current-voltage conversion circuit (320A) and / or the address event detection circuit (231A) connected to the second photoelectric conversion element suppresses output of a signal based on the current output from the second photoelectric conversion element.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a solid-state imaging device and an imaging apparatus. BACKGROUND

[0002] In recent years, an asynchronous solid-state imaging device has been proposed in which an address event detection circuit is provided for each pixel, and the address event detection circuit detects, for each pixel address, a light amount of the pixel exceeding a threshold value as an address event in real time (see, for example, Patent Literature 1).

[0003] LIST OF CITATIONS

[0004] PATENT LITERATURE

[0005] Patent Literature 1: Japanese Patent Application Publication No. 2016-533140 SUMMARY

[0006] PROBLEMS TO BE SOLVED BY THE INVENTION

[0007] However, in the above-described related art, it is difficult to improve the quality of a signal output from an effective pixel in an asynchronous solid-state imaging device.

[0008] In view of this, the present disclosure proposes a solid-state imaging device and an imaging apparatus capable of improving the quality of a signal output from an effective pixel.

[0009] SOLUTION TO PROBLEM

[0010] The present disclosure provides a solid-state imaging device. The solid-state imaging device includes a plurality of first photoelectric conversion elements, a plurality of second photoelectric conversion elements, a plurality of current-voltage conversion circuits, and a plurality of address event detection circuits. The plurality of first photoelectric conversion elements are arranged side by side in a first region. The plurality of second photoelectric conversion elements are arranged side by side in a second region adjacent to the first region. The plurality of current-voltage conversion circuits respectively convert a current output from the plurality of first photoelectric conversion elements and the plurality of second photoelectric conversion elements into a voltage. The plurality of address event detection circuits respectively detect a change in the voltage output from the plurality of current-voltage conversion circuits. At least one of the current-voltage conversion circuit and the address event detection circuit connected to the second photoelectric conversion element suppresses output of a signal based on the current output from the second photoelectric conversion element. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 is a block diagram showing a configuration example of an imaging apparatus according to an embodiment of the present disclosure.

[0012] Figure 2 is an explanatory diagram showing a laminate structure of a solid-state imaging device according to an embodiment of the present disclosure.

[0013] Figure 3is an explanatory diagram illustrating a planar configuration of a light-receiving substrate according to an embodiment of the present disclosure.

[0014] Figure 4 is an explanatory diagram illustrating a planar configuration of a circuit board according to an embodiment of the present disclosure.

[0015] Figure 5 is an explanatory diagram illustrating a configuration of an effective pixel according to an embodiment of the present disclosure.

[0016] Figure 6 A circuit configuration of an effective pixel according to an embodiment of the present disclosure is shown.

[0017] Figure 7 is an explanatory diagram illustrating a configuration of an effective pixel according to an embodiment of the present disclosure.

[0018] Figure 8 A cross-sectional configuration of a solid-state imaging device according to an embodiment of the present disclosure is shown.

[0019] Figure 9 A planar configuration of a solid-state imaging device according to an embodiment of the present disclosure is shown.

[0020] Figure 10 A circuit configuration of an effective pixel and a dummy pixel according to an embodiment of the present disclosure is shown.

[0021] Figure 11 A cross-sectional configuration of a solid-state imaging device of Modification Example 1 according to an embodiment of the present disclosure is shown.

[0022] Figure 12 A planar configuration of a solid-state imaging device of Modification Example 2 according to an embodiment of the present disclosure is shown.

[0023] Figure 13 A planar configuration of a solid-state imaging device of Modification Example 3 according to an embodiment of the present disclosure is shown.

[0024] Figure 14 A planar configuration of a solid-state imaging device of Modification Example 4 according to an embodiment of the present disclosure is shown.

[0025] Figure 15 A circuit configuration of an effective pixel of Modification Example 5 according to an embodiment of the present disclosure is shown.

[0026] Figure 16 is a block diagram illustrating a second configuration example of an address event detection unit.

[0027] Figure 17 is a block diagram illustrating a configuration example of an imaging device according to the second configuration example (i.e., an imaging device of a scanning method) serving as an imaging device in an imaging system to which the technology according to the present disclosure is applied.

[0028] Figure 18 is a schematic diagram illustrating a configuration example of a distance measurement system according to an embodiment of the present disclosure.

[0029] Figure 19 is a block diagram illustrating an example of a circuit configuration. DETAILED DESCRIPTION

[0030] Hereinafter, each embodiment of the present disclosure will be described in detail with reference to the drawings. Note that in each of the following embodiments, the same portions will be denoted by the same reference signs, and overlapping descriptions will be omitted.

[0031] Conventionally, a synchronous solid-state imaging element that captures image data (frame) in synchronization with a synchronization signal such as a vertical synchronization signal has been used for an imaging device and the like. This ordinary synchronous solid-state imaging element can acquire image data only at each cycle of the synchronization signal (for example, 1 / 60 seconds). Therefore, in a case where such processing is required in the fields of transportation, robots, and others, it is difficult to perform a more high-speed processing.

[0032] In view of this, an asynchronous solid-state imaging element is proposed in which an address event detection circuit that detects, for each pixel address, a light amount of its pixel exceeding a threshold as an address event in real time is provided per pixel. In this solid-state imaging element, a photodiode and a plurality of transistors for detecting an address event are arranged per pixel.

[0033] However, in the above-described related art, a power supply voltage to be supplied to an effective pixel fluctuates because there is a potential change in a region other than an effective pixel region. Therefore, in some cases, the address event detection circuit fails. That is, in the above-described related art, it is difficult to improve the quality of a signal output from the effective pixel.

[0034] Therefore, it is desirable to realize a technology capable of solving the above-described problems and improving the quality of a signal output from an effective pixel.

[0035] [Configuration of imaging device]

[0036] First, a configuration of an imaging device 100 according to an embodiment will be described with reference to Figure 1 The configuration of the imaging device 100 according to the embodiment will be described. Figure 1 is a block diagram illustrating a configuration example of the imaging device 100 according to an embodiment of the present disclosure.

[0037] The imaging device 100 according to the embodiment includes an imaging lens 110, a solid-state imaging element 200, a recording unit 120, and a control unit 130. The imaging device 100 is assumed to be a camera mounted on a wearable device, a vehicle-mounted camera, or the like.

[0038] The imaging lens 110 is an example of an optical system, and captures incident light from an object to form an image on an imaging surface of the solid-state imaging device 200.

[0039] The solid-state imaging device 200 is also referred to as a dynamic vision sensor (DVS), and detects, as an address event, an absolute value of a change amount of luminance exceeding a threshold value for each of a plurality of pixels. The address event includes, for example, an on event indicating that an increase amount of luminance exceeds an upper limit threshold value, and an off event indicating that a decrease amount of luminance is lower than a lower limit threshold value that is smaller than the upper limit threshold value.

[0040] Then, the solid-state imaging device 200 generates, for each pixel, a detection signal indicating a detection result of the address event. Each detection signal includes an on event detection signal V CH (see Figure 6 ) indicating whether or not the on event is present, and an off event detection signal V CL (see Figure 6 ) indicating whether or not the off event is present.

[0041] The solid-state imaging device 200 performs predetermined signal processing, such as image recognition processing, on image data including the detection signals, and outputs the processed data to the recording unit 120 via the signal line 209.

[0042] The recording unit 120 records data output from the solid-state imaging device 200. The control unit 130 controls the solid-state imaging device 200 to cause the solid-state imaging device 200 to capture image data.

[0043] [Configuration of solid-state imaging device]

[0044] Next, a configuration of the solid-state imaging device 200 according to the embodiment will be described with reference to Figures 2 to 10 . Figure 2 is an explanatory diagram illustrating a laminated structure of the solid-state imaging device 200 according to the embodiment of the present disclosure.

[0045] The solid-state imaging device 200 according to the embodiment includes a circuit board 202 and a light-receiving substrate 201 laminated on the circuit board 202. The light-receiving substrate 201 and the circuit board 202 are electrically connected via a connection portion such as a via, Cu-Cu bonding, or a bump.

[0046] Figure 3 is an explanatory diagram illustrating a planar configuration of the light-receiving substrate 201 according to the embodiment of the present disclosure. As Figure 3 indicated, the light-receiving substrate 201 includes a light-receiving unit 210, a via arrangement portion 221, and a via arrangement portion 222.

[0047] In the light-receiving unit 210, a plurality of light-receiving circuits 211 are arranged in a two-dimensional lattice pattern. Each of the light-receiving circuits 211 photoelectrically converts incident light to generate a photoelectric current, performs current-voltage conversion on the photoelectric current, and outputs a voltage signal. A pixel address including a row address and a column address is assigned to each of the light-receiving circuits 211.

[0048] The through-holes connected to the circuit board 202 (see Figure 4 ) are arranged in the through-hole arrangement portion 221 and the through-hole arrangement portion 222.

[0049] Figure 4 is an explanatory diagram illustrating a planar configuration of the circuit board 202 according to an embodiment of the present disclosure. As Figure 4 indicated, the circuit board 202 includes an address event detection unit 230, a signal processing circuit 240, a row drive circuit 251, a column drive circuit 252, a through-hole arrangement portion 261, and a through-hole arrangement portion 262.

[0050] In the address event detection unit 230, a plurality of address event detection circuits 231 are arranged in a two-dimensional lattice pattern. Each of the address event detection circuits 231 quantizes a voltage signal supplied from the light-receiving circuit 211 and outputs the quantized voltage signal as a detection signal.

[0051] A pixel address is assigned to each of the address event detection circuits 231 and electrically connected to the light-receiving circuit 211 having the same address. Further, in the embodiment, the light-receiving circuit 211 and the address event detection circuit 231 having the same address are arranged at the same position in a plan view.

[0052] The signal processing circuit 240 performs predetermined signal processing on the detection signals from the address event detection unit 230. For example, the signal processing circuit 240 arranges the detection signals in a two-dimensional lattice pattern as pixel signals and acquires image data having 2-bit information for each pixel. Then, the signal processing circuit 240 performs signal processing such as image recognition processing on the acquired image data.

[0053] The row drive circuit 251 selects a row address and causes the address event detection unit 230 to output a detection signal corresponding to the selected row address. The column drive circuit 252 selects a column address and causes the address event detection unit 230 to output a detection signal corresponding to the selected column address. The through-holes connected to the light-receiving substrate 201 (see Figure 3 ) are arranged in the through-hole arrangement portion 261 and the through-hole arrangement portion 262.

[0054] Figure 5 is an explanatory diagram illustrating a configuration of an effective pixel 310 according to an embodiment of the present disclosure. As Figure 5As shown, each effective pixel 310 includes a light-receiving circuit 211 in the light-receiving substrate 201 and an address event detection circuit 231 in the circuit board 202 to which the same pixel address is respectively assigned.

[0055] As described above, the plurality of light-receiving circuits 211 and the plurality of address event detection circuits 231 are arranged in a two-dimensional grid pattern on the light-receiving substrate 201 and the circuit board 202. Further, each light-receiving circuit 211 and each address event detection circuit 231 having the same address are disposed at the same position in a plan view.

[0056] That is, in the solid-state imaging device 200 according to the embodiment, the effective pixel 310 including the pair of light-receiving circuit 211 and address event detection circuit 231 is arranged in a two-dimensional grid pattern. Then, the pair of light-receiving circuit 211 and address event detection circuit 231 are electrically connected at the bonding portion 203 via a connection portion such as a via, a Cu-Cu bonding, or a bump.

[0057] Figure 6 A circuit configuration of the effective pixel 310 according to the embodiment of the present disclosure is shown. As shown, the effective pixel 310 includes a photodiode 311, a current-voltage conversion circuit 320, a buffer 330, a subtracter 340, a quantizer 350, and a transmission circuit 360. Figure 6

[0058] In the unit of the effective pixel 310, in the embodiment of the present disclosure, the photodiode 311 and the N-type transistors 321 and 322 of the current-voltage conversion circuit 320 are included in the light-receiving circuit 211. Further, in the unit of the effective pixel 310, the buffer 330, the subtracter 340, the quantizer 350, and the transmission circuit 360 are included in the address event detection circuit 231.

[0059] That is, in the embodiment of the present disclosure, the effective pixel 310 includes the photodiode 311, the current-voltage conversion circuit 320, and the address event detection circuit 231.

[0060] The photodiode 311 photoelectrically converts incident light to generate a photoelectric current. Then, the photodiode 311 supplies the generated photoelectric current to the current-voltage conversion circuit 320.

[0061] The current-voltage conversion circuit 320 converts the photoelectric current from the photodiode 311 into a logarithmic voltage signal thereof. Then, the current-voltage conversion circuit 320 supplies the converted voltage signal to the buffer 330.

[0062] ​The buffer 330 corrects the voltage signal transmitted from the current-voltage conversion circuit 320 and outputs the corrected signal to the subtracter 340. In the active pixel 310 according to the embodiment, the buffer 330 can increase a driving force for driving a later stage, and can ensure isolation of noise caused by switching operation in the later stage.

[0063] The subtracter 340 obtains an amount of change of the corrected signal transmitted from the buffer 330 through subtraction processing. Then, the subtracter 340 provides the obtained amount of change as a differential signal to the quantizer 350.

[0064] The quantizer 350 compares the differential signal with a predetermined threshold, and thereby converts (i.e., quantizes) the analog differential signal into a digital detection signal. The quantizer 350 according to the embodiment compares the differential signal with both an upper threshold and a lower threshold, and provides the comparison result as a 2-bit detection signal to the transmission circuit 360.

[0065] The transmission circuit 360 transmits the detection signal to the signal processing circuit 240 in response to a column drive signal provided from the column drive circuit 252.

[0066] A specific circuit configuration of each unit will be described below. The current-voltage conversion circuit 320 includes an N-type transistor 321, an N-type transistor 322, and a P-type transistor 323. The N-type transistor 321, the N-type transistor 322, and the P-type transistor 323 are, for example, metal oxide semiconductor (MOS) transistors.

[0067] The source of the N-type transistor 321 is connected to the cathode of the photodiode 311, and its drain is connected to a terminal of a power supply voltage VDD. The anode of the photodiode 311 is connected to a terminal of a ground potential. The P-type transistor 323 and the N-type transistor 322 are connected in series between the terminal of the power supply voltage VDD and the terminal of the ground potential in this order.

[0068] A connection point between the P-type transistor 323 and the N-type transistor 322 is connected to the gate of the N-type transistor 321 and an input terminal of the buffer 330. A connection point between the N-type transistor 321 and the photodiode 311 is connected to the gate of the N-type transistor 322. A predetermined bias voltage V blog is applied to the gate of the P-type transistor 323.

[0069] Then, the N-type transistor 321 converts the photo current generated by the photodiode 311 into a voltage between the gate and the source, and the N-type transistor 322 amplifies the voltage between the gate having a potential corresponding to the photo current and the source having the ground potential, and outputs the amplified voltage from the drain.

[0070] Further, the P-type transistor 323 amplifies the voltage between the gate and the source based on the bias voltage Vblo A constant current of g is supplied to the N-type transistor 322. With this configuration, the current-voltage conversion circuit 320 converts the photoelectric current from the photodiode 311 into a voltage signal.

[0071] Note that in the solid-state imaging device 200 according to the embodiment, the photodiode 311, the N-type transistor 321, and the N-type transistor 322 are arranged on the light-receiving substrate 201, and the circuit after the P-type transistor 323 is arranged on the circuit board 202.

[0072] Figure 7 is an explanatory diagram illustrating a configuration of the effective pixel 310 according to the embodiment of the present disclosure. As Figure 7 indicated, the photodiode 311 is embedded in the P-well region of the light-receiving substrate 201, thereby forming a back gate of the N-type transistor 321 and a back gate of the N-type transistor 322.

[0073] A power supply voltage VDD is supplied to the drain of the N-type transistor 321, and the potential of the P-well region (i.e., the anode of the photodiode 311) and the potential of the source of the N-type transistor 322 are ground potentials. Further, the P-well regions of the adjacent effective pixels 310 are separated by a pixel separation portion 410 (see Figure 8 ) formed in a portion indicated by a single-dotted line.

[0074] Description returns Figure 6 . The buffer 330 includes a P-type transistor 331 and a P-type transistor 332. The P-type transistor 331 and the P-type transistor 332 are, for example, MOS transistors.

[0075] The P-type transistor 331 and the P-type transistor 332 are connected in series between a terminal of the power supply voltage VDD and a terminal of the ground potential in this order. A predetermined bias voltage V bsf is applied to the gate of the P-type transistor 331. The gate of the P-type transistor 332 is connected to the output terminal of the current-voltage conversion circuit 320.

[0076] With this configuration, the buffer 330 outputs the corrected voltage signal from the connection point between the P-type transistor 331 and the P-type transistor 332 to the subtracter 340.

[0077] The subtracter 340 includes a capacitor 341, a P-type transistor 342, a capacitor 343, a P-type transistor 344, and an N-type transistor 345. The P-type transistor 342, the P-type transistor 344, and the N-type transistor 345 are, for example, MOS transistors.

[0078] The P-type transistor 344 and the N-type transistor 345 are connected in series between a terminal of the power supply voltage VDD and a terminal of a reference potential in this order. A predetermined bias voltage Vba is applied to the gate of the N-type transistor 345.

[0079] In a case where the gate of the P-type transistor 344 serves as an input terminal and a connection point between the P-type transistor 344 and the N-type transistor 345 serves as an output terminal, the P-type transistor 344 and the N-type transistor 345 serve as an inverter which inverts and outputs an input signal.

[0080] One end of the capacitor 341 is connected to the output terminal of the buffer 330, and the other end thereof is connected to the input terminal of the inverter (i.e., the gate of the P-type transistor 344). One end of the capacitor 343 is connected to the input terminal of the inverter, and the other end thereof is connected to the output terminal of the inverter (i.e., the connection point between the P-type transistor 344 and the N-type transistor 345).

[0081] The P-type transistor 342 turns off and on a path connecting both ends of the capacitor 343 in response to a row drive signal output from the row drive circuit 251.

[0082] When the P-type transistor 342 is turned on, a voltage signal V init is input to the buffer 330 side of the capacitor 341, and the opposite terminal thereof serves as a virtual ground terminal. For the sake of convenience, it is assumed that the potential of the virtual ground terminal is zero.

[0083] At this time, the charge Q init accumulated in the capacitor 341 is represented by the following expression (1), where the capacitance of the capacitor 341 is denoted by C1. On the other hand, the capacitor 343 is short-circuited at both ends, and thus the accumulated charge is zero.

[0084] Q init = C1 x V init ...(1)

[0085] Next, consider a case where the P-type transistor 342 is turned off and the voltage of the buffer 330 side of the capacitor 341 becomes V after . The charge Q after accumulated in the capacitor 341 is represented by the following expression (2).

[0086] Q after = C1 x V after ...(2)

[0087] Meanwhile, the charge Q2 accumulated in the capacitor 343 is represented by the following expression (3), where the capacitance of the capacitor 343 is denoted by C2 and the output voltage thereof is denoted by V out .

[0088] Q2 = -C2 x V out ...(3)

[0089] At this time, the total charge amount in the capacitors 341 and 343 does not change, and thus the following expression (4) holds.

[0090] Q init = Q after + Q2...(4)

[0091] Then, when the expressions (1) to (3) are substituted into the above expression (4), and the expression after substitution is transformed, the following expression (5) is obtained.

[0092] V out = -(C1 / C2) x (V after - V init )...(5)

[0093] The above expression (5) shows the operation of subtracting the voltage signal, and the gain of the result of the subtraction is C1 / C2. It is generally desirable to maximize the gain, and thus it is preferable to design the capacitance C1 to be large and the capacitance C2 to be small. Meanwhile, when the capacitance C2 is too small, the kTC noise increases, and the noise characteristics can deteriorate. Thus, the reduction of the capacitance C2 is limited within a range in which the noise is tolerable.

[0094] Further, the subtracter 340 is installed in each effective pixel 310, and thus the capacitance C1 and the capacitance C2 are limited in area. In view of the above points, for example, the capacitance C1 is set to a value of 20 to 200 femto Farad (fF), and the capacitance C2 is set to a value of 1 to 20 femto Farad (fF).

[0095] The quantizer 350 includes a P-type transistor 351, an N-type transistor 352, a P-type transistor 353, and an N-type transistor 354. The P-type transistor 351, the N-type transistor 352, the P-type transistor 353, and the N-type transistor 354 are, for example, MOS transistors.

[0096] The P-type transistor 351 and the N-type transistor 352 are connected in series between a terminal of a power supply voltage VDD and a terminal of a ground potential, in that order. The P-type transistor 353 and the N-type transistor 354 are connected in series between a terminal of the power supply voltage VDD and a terminal of a reference potential, in that order.

[0097] Further, a gate of the P-type transistor 351 and a gate of the P-type transistor 353 are connected to an output terminal of the subtracter 340. A bias voltage V bon indicating an upper limit threshold value is applied to a gate of the N-type transistor 352, and a bias voltage V boff indicating a lower limit threshold value is applied to a gate of the N-type transistor 354.

[0098] The connection point between the P-type transistor 351 and the N-type transistor 352 is connected to the transmission circuit 360. In the quantizer 350, the voltage at the connection point is output as an on-event detection signal V CH to the transmission circuit 360.

[0099] The connection point between the P-type transistor 353 and the N-type transistor 354 is connected to the transmission circuit 360. In the quantizer 350, the voltage at the connection point is output as an off-event detection signal V CL .

[0100] With this configuration, the quantizer 350 outputs a high-level on-event detection signal V CH in a case where the difference signal exceeds the upper limit threshold value, and outputs a low-level off-event detection signal V CL in a case where the difference signal is lower than the lower limit threshold value. That is, the solid-state imaging element 200 according to the embodiment can simultaneously detect whether both of the on-event and the off-event are present.

[0101] Figure 8 A cross-sectional configuration of the solid-state imaging element 200 according to the embodiment of the present disclosure is shown, and a cross-sectional structure of a peripheral portion of the solid-state imaging element 200 is mainly shown. As Figure 8 shown, the solid-state imaging element 200 includes an effective pixel region R1, a dummy pixel region R2, a power supply region R3, and a pad region R4. The effective pixel region R1 is an example of a first region, and the dummy pixel region R2 is an example of a second region.

[0102] The effective pixel region R1 is a region in which the light-receiving unit 210 and the address-event detection unit 230 are provided by lamination thereof. In the effective pixel region R1, a plurality of effective pixels 310 are arranged in a two-dimensional lattice pattern.

[0103] As Figure 9 shown, the dummy pixel region R2 is a region provided to surround four sides of the effective pixel region R1. Figure 9 A planar configuration of the solid-state imaging element 200 according to the embodiment of the present disclosure is shown.

[0104] Further, as Figure 8 shown, a plurality of dummy pixels 310A are arranged side by side in the dummy pixel region R2. The dummy pixel 310A has the same basic configuration as the effective pixel 310, but does not output a signal to the outside. Details of the dummy pixel 310A will be described later.

[0105] Because, in the solid-state imaging device 200 according to the embodiment, the dummy pixel region R2 is formed so as to surround four sides of the effective pixel region R1, it is possible to ensure regularity of processing from the center to the edge of the effective pixel region R1. Therefore, according to the embodiment, it is possible to improve the manufacturing yield of the solid-state imaging device 200.

[0106] As shown in Figure 9 , the power supply region R3 is a region provided so as to surround four sides of the dummy pixel region R2. The power supply region R3 includes a ground wiring 421 to which a ground potential (GND) is applied from the outside, a power supply wiring 422 to which a power supply voltage VDD is applied from the outside, and a power supply wiring 423 to which a substrate voltage VSS having the same potential as the power supply voltage VDD is applied from the outside. SUB The ground wiring 421 and the power supply wirings 422 and 423 are formed, for example, in a ring shape around the dummy pixel region R2.

[0107] The ground wiring 421 supplies the ground potential to the plurality of effective pixels 310 and the like. The power supply wiring 422 supplies the power supply voltage VDD to the plurality of effective pixels 310 and the like. The power supply wiring 423 supplies the substrate voltage VSS having the same potential as the power supply voltage VDD to a portion other than the effective pixel region R1 or the dummy pixel region R2 of the solid-state imaging device 200. SUB

[0108] In the solid-state imaging device 200 according to the embodiment, the power supply wiring 423 is provided separately from the power supply wiring 422, and thus even in a case where the power supply voltage VDD fluctuates, for example, when the effective pixel 310 operates, it is possible to supply the stable substrate voltage VSS to the peripheral portion of the solid-state imaging device 200. Therefore, according to the embodiment, it is possible to stably operate the solid-state imaging device 200. SUB

[0109] Description returns Figure 8 . The pad region R4 is a region provided so as to surround the power supply region R3, and includes a contact hole 424 and a bonding pad 425. The contact hole 424 is formed from the surface of the light-receiving substrate 201 on the light incident side to the middle of the circuit board 202 along the thickness direction of the light-receiving substrate 201 and the circuit board 202.

[0110] The bonding pad 425 is provided at the bottom of the contact hole 424. In the embodiment, a wire or the like is bonded to the bonding pad 425 via the contact hole 424, and thus the recording unit 120 (see Figure 1 ) or the control unit 130 (see Figure 1 ) is electrically connected to each unit of the solid-state imaging device 200.

[0111] Reference will be made to Figure 8 ​​The configuration of each of the effective pixels 310 arranged in the effective pixel region R1 will be further described. The solid-state imaging device 200 is formed by laminating the light-receiving substrate 201 and the circuit board 202, and the bonding portion 203 is provided at the interface between the light-receiving substrate 201 and the circuit board 202.

[0112] The light-receiving substrate 201 includes a semiconductor layer 201a and an insulating layer 201b. The semiconductor layer 201a is made of a semiconductor material such as silicon. In the semiconductor layer 201a, a photodiode 311, an N-type transistor 321 (see Figure 7 ), an N-type transistor 322 (see Figure 7 ), and the like are formed in each of the effective pixels 310 and the dummy pixels 310A.

[0113] Further, in the semiconductor layer 201a, a pixel separation portion 410 is formed to separate the adjacent effective pixels 310 or the dummy pixels 310A from each other. The pixel separation portion 410 electrically and optically separates the adjacent effective pixels 310 or the dummy pixels 310A from each other.

[0114] For example, the pixel separation portion 410 is formed to individually surround the effective pixels 310 or the dummy pixels 310A, and penetrates the semiconductor layer 201a.

[0115] A planarization film 411 is formed on the surface of the semiconductor layer 201a on the light-incident side, and an on-chip lens 412 is formed on the surface of the planarization film 411 on the light-incident side. The planarization film 411 planarizes the surface on which the on-chip lens 412 is mounted.

[0116] For example, the on-chip lens 412 is individually provided in the effective pixels 310 and the dummy pixels 310A, converges incident light, and guides the incident light to the effective pixels 310 and the dummy pixels 310A.

[0117] The insulating layer 201b is made of an insulating material such as silicon oxide (SiOx), silicon nitride (SiN), or silicon oxynitride (SiON), and is provided on the surface of the semiconductor layer 201a opposite to the surface on the light-incident side.

[0118] Further, a wiring portion 401 including a wiring layer, a via, and the like is formed in the insulating layer 201b. The wiring portion 401 is electrically connected to the photodiode 311, the N-type transistor 321, and the N-type transistor 322 provided in the semiconductor layer 201a by Figure 6 the wiring configuration.

[0119] The wiring portion 401 is electrically connected to the first pad 403 via a via hole 402. The first pad 403 is provided to be exposed on a surface of the circuit board 202 opposite to the surface thereof which is the interface with the light-receiving substrate 201, and is made of copper or a copper alloy.

[0120] The circuit board 202 has an insulating layer 202a at the interface with the light-receiving substrate 201. The insulating layer 202a is made of an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0121] Further, the insulating layer 202a includes a second pad 404. The second pad 404 is provided to be exposed on a surface of the circuit board 202 which is the interface with the light-receiving substrate 201, and is made of copper or a copper alloy.

[0122] The second pad 404 is electrically connected to a wiring portion 406 via a via hole 405. The wiring portion 406 is electrically connected to a gate of the P-type transistor 332 (see Figure 6 ) and a source of the P-type transistor 323 (see Figure 6 ). Further, in the embodiment, the first pad 403 and the second pad 404 are directly joined by Cu-Cu joining.

[0123] Figure 10 The circuit configuration of the effective pixel 310 and the dummy pixel 310A according to the embodiment of the present disclosure is shown.

[0124] As described above, in each effective pixel 310 arranged in the effective pixel region R1, a photoelectric current generated by the photodiode 311 is converted into a voltage signal by the current-voltage conversion circuit 320, and the voltage signal is output to the address event detection circuit 231. The photodiode 311 arranged in the effective pixel region R1 is an example of the first photoelectric conversion element.

[0125] On the other hand, in each dummy pixel 310A arranged in the dummy pixel region R2, output of an address event detection signal (a turn-on event detection signal V CH and an off event detection signal V CL ) based on a photoelectric current generated by the photodiode 311A is suppressed. The photodiode 311A arranged in the dummy pixel region R2 is an example of the second photoelectric conversion element.

[0126] For example, as shown in Figure 10 , in the current-voltage conversion circuit 320A belonging to the dummy pixel 310A, all the terminals of the N-type transistor 321A and the N-type transistor 322A are short-circuited, and the potential of each terminal is fixed to the power supply voltage VDD.

[0127] Here, the N-type transistor 321A of the current-voltage conversion circuit 320A is a transistor corresponding to the N-type transistor 321 of the current-voltage conversion circuit 320. Further, the N-type transistor 322A of the current-voltage conversion circuit 320A is a transistor corresponding to the N-type transistor 322 of the current-voltage conversion circuit 320.

[0128] Further, each terminal of the N-type transistors 321A and 322A is short-circuited by a metal wiring formed in the first layer in the insulating layer 201b, for example, as shown in Figure 8

[0129] As described above, because the potential of each terminal of the N-type transistors 321A and 322A is fixed, the current-voltage conversion circuit 320A belonging to the dummy pixel 310A can suppress output of the address event detection signal based on the photoelectric current supplied from the photodiode 311A.

[0130] Further, because output of the address event detection signal from the dummy pixel 310A is suppressed in the embodiment, fluctuation of the power supply voltage VDD due to operation of the dummy pixel 310A can be suppressed.

[0131] Therefore, fluctuation of the power supply voltage VDD supplied to the quantizer 350 (see Figure 6 ) of the effective pixel 310 is suppressed, so it is possible to suppress malfunction of the quantizer 350 due to fluctuation of the power supply voltage VDD and suppress output of an erroneous address event detection signal.

[0132] Therefore, according to the embodiment, it is possible to improve the quality of the address event detection signal output from the effective pixel 310.

[0133] Note that, in the embodiment, the means for fixing the potential of the current-voltage conversion circuit 320A belonging to the dummy pixel 310A is not limited to supplying the power supply voltage VDD to each terminal of the N-type transistors 321A and 322A.

[0134] For example, it is also possible to fix the potential of the current-voltage conversion circuit 320A by supplying a prescribed voltage from an external power supply (not shown) to each terminal of the N-type transistors 321A and 322A.

[0135] Likewise by this configuration, fluctuation of the power supply voltage VDD supplied to the quantizer 350 of the effective pixel 310 is suppressed, so it is possible to suppress malfunction of the quantizer 350 due to fluctuation of the power supply voltage VDD and suppress output of an erroneous address event detection signal.

[0136] Therefore, according to the embodiment, it is possible to improve the quality of the address event detection signal output from the effective pixel 310.

[0137] ​Further, in the embodiment, the means for suppressing the output of the address event detection signal based on the photocurrent supplied from the photodiode 311A is not limited to fixing the potential of the current-voltage conversion circuit 320A.

[0138] For example, by fixing the potential of the address event detection circuit 231A belonging to the dummy pixel 310A, it is possible to suppress the output of the address event detection signal based on the photocurrent supplied from the photodiode 311A.

[0139] Also by this configuration, fluctuation of the power supply voltage VDD supplied to the quantizer 350 of the active pixel 310 is suppressed, so it is possible to suppress malfunction of the quantizer 350 due to fluctuation of the power supply voltage VDD, and to suppress output of an erroneous address event detection signal.

[0140] Therefore, according to the embodiment, it is possible to improve the quality of the address event detection signal output from the active pixel 310.

[0141] Further, in the embodiment, it is possible to suppress the output of the address event detection signal based on the photocurrent supplied from the photodiode 311A by fixing both the potential of the current-voltage conversion circuit 320A and the potential of the address event detection circuit 231A.

[0142] Further, in the embodiment, it is possible to suppress the output of the address event detection signal based on the photocurrent supplied from the photodiode 311A by means other than fixing the potential of the current-voltage conversion circuit 320A or the address event detection circuit 231A.

[0143] Further, in the embodiment, the potential of the power supply region R3 can be fixed. For example, in the embodiment, as shown in FIG. 4B, the potential of the power supply region R3 can be fixed by electrically connecting the semiconductor layer 201a located in the power supply region R3 and the ground wiring 421. Figure 8

[0144] Then, in the embodiment, when the potential of the power supply region R3 is fixed, fluctuation of the potential of the power supply wiring 422 located in the power supply region R3 (i.e., the power supply voltage VDD) can be suppressed.

[0145] Therefore, fluctuation of the power supply voltage VDD supplied to the quantizer 350 of the active pixel 310 is suppressed, so it is possible to suppress malfunction of the quantizer 350 due to fluctuation of the power supply voltage VDD, and to suppress output of an erroneous address event detection signal.

[0146] Therefore, according to the embodiment, it is possible to improve the quality of the address event detection signal output from the active pixel 310. Note that the potential of the power supply region R3 is not limited to being fixed to the ground potential, and can be fixed by a power supply voltage, an external power supply, or the like.​

[0147] Furthermore, in the embodiment, the interior of the power supply region R3 is preferably not separated by the pixel separation portion 410. That is, in the embodiment, the power supply region R3 is preferably electrically integrated.

[0148] Therefore, the potential of the entire power supply region R3 can be easily fixed. Thus, according to the embodiment, potential fluctuations in the power supply wiring 422 located in the power supply region R3 can be easily suppressed.

[0149] [Various modification examples]

[0150] Next, we will refer to Figures 11 to 15 Various examples of modifications to the implementation methods are described. Figure 11 The diagram illustrates a cross-sectional configuration of a solid-state imaging element 200 according to a modified example 1 of an embodiment of the present disclosure, which corresponds to the embodiment. Figure 8 .

[0151] like Figure 11 As shown, the N-type transistor 321A is disposed in the pseudo pixel 310A (see Figure 10 ) and 322A (see ) Figure 10 Each terminal can be short-circuited by metal wiring formed in the second layer of the insulating layer 201b.

[0152] Figure 12 A planar configuration of a solid-state imaging element 200 according to a modified example 2 of an embodiment of the present disclosure is shown, which corresponds to the embodiment of Figure 9 .like Figure 12 As shown, in modified example 2, the pseudo-pixel region R2 is set to surround the four sides of the effective pixel region R1, and the power supply region R3 is set to surround the three sides of the pseudo-pixel region R2.

[0153] Figure 13 A planar configuration of a solid-state imaging element 200 according to a modified example 3 of an embodiment of the present disclosure is shown. Figure 13 As shown, in modified example 3, the pseudo-pixel region R2 is set to surround the four sides of the effective pixel region R1, and the power supply region R3 is set along both sides of the pseudo-pixel region R2.

[0154] Figure 14 A planar configuration of a solid-state imaging element 200 according to a modified example 4 of an embodiment of the present disclosure is shown. Figure 14 As shown, in modified example 4, the pseudo-pixel region R2 is set to surround the four sides of the effective pixel region R1, and the power supply region R3 is set along one side of the pseudo-pixel region R2.

[0155] Figure 15A circuit configuration of the effective pixel 310 of Modification Example 5 according to the embodiment of the present disclosure is shown, and a quantifier 350 that detects whether or not either of the selected turn-on event and turn-off event is present is shown.

[0156] The quantifier 350 according to Modification Example 5 includes a P-type transistor 351, an N-type transistor 352, and a switch 355. The P-type transistor 351 and the N-type transistor 352 are connected in series between a terminal of a power supply voltage VDD and a terminal of a ground potential in this order.

[0157] Further, a gate of the P-type transistor 351 is connected to an output terminal of the subtracter 340. A gate of the N-type transistor 352 is connected to the switch 355.

[0158] Then, the control unit 130 turns on or off the switch 355, and thereby applies a bias voltage V bon or a bias voltage V boff indicative of the lower limit threshold to the gate of the N-type transistor 352. A connection point 356 between the P-type transistor 351 and the N-type transistor 352 is connected to a transfer circuit 360.

[0159] Then, in a case where the bias voltage V bon is applied to the gate of the N-type transistor 352, in the quantifier 350 according to Modification Example 5, a voltage of the connection point 356 is output as a turn-on event detection signal V CH to the transfer circuit 360.

[0160] Meanwhile, in a case where the bias voltage V boff is applied to the gate of the N-type transistor 352, in the quantifier 350 according to Modification Example 5, a voltage of the connection point 356 is output as a turn-off event detection signal V CL to the transfer circuit 360.

[0161] With this configuration, in a case where the control unit 130 selects the turn-on event and the differential signal exceeds the upper limit threshold, the quantifier 350 according to Modification Example 5 outputs a high-level turn-on event detection signal V CH .

[0162] Meanwhile, in a case where the control unit 130 selects the turn-off event and the differential signal is lower than the lower limit threshold, the quantifier 350 according to Modification Example 5 outputs a low-level turn-off event detection signal V CL .

[0163] For example, in the solid-state imaging device 200 according to Modification Example 5, in response to a command from the control unit 130 or the like to turn on a light source (not shown), the control unit 130 selects the turn-on event and thus can effectively output the turn-on event detection signal V CH.

[0164] Further, in the solid-state imaging device 200 according to the modified example 5, in order to turn off the light source (not shown) in response to a command from the control unit 130 or the like, the control unit 130 selects the turn-off event and thus can effectively output the turn-off event detection signal V CL .

[0165] In the above-described modified example 5, the number of transistors included in the quantizer 350 can be reduced. This makes it possible to reduce the chip area of the solid-state imaging device 200 and also reduce the power consumption of the solid-state imaging device 200.

[0166] [Effects]

[0167] The solid-state imaging device 200 according to the embodiment includes a plurality of first photoelectric conversion elements (photodiodes 311), a plurality of second photoelectric conversion elements (photodiodes 311A), a plurality of current-voltage conversion circuits 320 and 320A, and a plurality of address event detection circuits 231 and 231A. The plurality of first photoelectric conversion elements (photodiodes 311) are arranged side by side in a first region (effective pixel region R1). The plurality of second photoelectric conversion elements (photodiodes 311A) are arranged side by side in a second region (dummy pixel region R2) adjacent to the first region (effective pixel region R1). The plurality of current-voltage conversion circuits 320 and 320A respectively convert a current output from the plurality of first photoelectric conversion elements (photodiodes 311) and the plurality of second photoelectric conversion elements (photodiodes 311A) into a voltage. The plurality of address event detection circuits 231 and 231A respectively detect a change in the voltage output from the plurality of current-voltage conversion circuits 320 and 320A. At least one of the current-voltage conversion circuit 320A and the address event detection circuit 231A connected to the second photoelectric conversion element (photodiode 311A) suppresses output of a signal based on a current output from the second photoelectric conversion element.

[0168] Therefore, it is possible to improve the quality of the address event detection signal output from the effective pixel 310.

[0169] Further, in the solid-state imaging device 200 according to the embodiment, the second region (dummy pixel region R2) is provided so as to surround the first region (effective pixel region R1).

[0170] Therefore, it is possible to improve the manufacturing yield of the solid-state imaging device 200.

[0171] Further, in the solid-state imaging device 200 according to the embodiment, the internal potential of at least one of the current-voltage conversion circuit 320A and the address event detection circuit 231A connected to the second photoelectric conversion element (photodiode 311A) is fixed.

[0172] Accordingly, it is possible to suppress output of the address event detection signal based on the photocurrent output from the photodiode 311A.

[0173] Further, in the solid-state imaging device 200 according to the embodiment, the internal potential of at least one of the current-voltage conversion circuit 320A connected to the second photoelectric conversion element (photodiode 311A) and the address event detection circuit 231A is fixed by an external voltage.

[0174] Accordingly, it is possible to suppress output of the address event detection signal based on the photocurrent output from the photodiode 311A.

[0175] Further, in the solid-state imaging device 200 according to the embodiment, the internal potential of at least one of the current-voltage conversion circuit 320A connected to the second photoelectric conversion element (photodiode 311A) and the address event detection circuit 231A is fixed by an external voltage.

[0176] Accordingly, it is possible to suppress output of the address event detection signal based on the photocurrent output from the photodiode 311A.

[0177] Further, the solid-state imaging device 200 according to the embodiment further includes a power supply region R3 provided outside the second region (dummy pixel region R2) and having a power supply wiring 422 and 423 and a ground wiring 421.

[0178] Accordingly, it is possible to improve the quality of the address event detection signal output from the effective pixel 310.

[0179] Further, in the solid-state imaging device 200 according to the embodiment, the internal potential of the power supply region R3 is fixed.

[0180] Accordingly, it is possible to suppress fluctuation in the potential of the power supply wiring 422 (i.e., the power supply voltage VDD) located in the power supply region R3.

[0181] Further, in the solid-state imaging device 200 according to the embodiment, the power supply region R3 is electrically integrated.

[0182] Accordingly, it is possible to easily suppress fluctuation in the potential of the power supply wiring 422 located in the power supply region R3.

[0183] [Second Configuration Example of Address Event Detection Unit]

[0184] Figure 16 is a block diagram illustrating a second configuration example of the address event detection unit 1000. As in the first configuration example, the address event detection unit 1000 includes the current-voltage conversion circuit 320A connected to the second photoelectric conversion element (photodiode 311A).Figure 16 As shown, the address event detection unit 1000 according to this configuration example includes not only the current-voltage conversion unit 1331, the buffer 1332, the subtracter 1333, the quantizer 1334, and the transmission unit 1335 but also a storage unit 1336 and a control unit 1337.

[0185] The storage unit 1336 is provided between the quantizer 1334 and the transmission unit 1335 and accumulates the output of the quantizer 1334 (i.e., the comparison result of the comparator 1334a) based on a sampling signal supplied from the control unit 1337. The storage unit 1336 can be a sampling circuit such as a switch, a resistor, or a capacitor, or can be a digital storage circuit such as a latch or a flip-flop.

[0186] The control unit 1337 supplies a predetermined threshold voltage Vth to the inverting (-) input terminal of the comparator 1334a. The threshold voltage Vth supplied from the control unit 1337 to the comparator 1334a can have different voltage values in a time-division manner. For example, the control unit 1337 supplies, at different timings, a threshold voltage corresponding to a turn-on event indicating that the amount of change in the photoelectric current exceeds an upper limit threshold value and a threshold voltage corresponding to a turn-off event indicating that the amount of change in the photoelectric current is below a lower limit threshold value, and thus one comparator 1334a can detect multiple types of address events.

[0187] For example, the storage unit 1336 can accumulate the comparison result of the comparator 1334a using the threshold voltage corresponding to a turn-on event in a period in which the threshold voltage corresponding to a turn-off event is supplied from the control unit 1337 to the inverting (-) input terminal of the comparator 1334a. Note that the storage unit 1336 can be inside the pixel 2030 (see FIG. 27) or outside the pixel 2030. Furthermore, the storage unit 1336 is not an essential component of the address event detection unit 1000. That is, the storage unit 1336 can not be provided. Figure 17

[0188] [Imaging device (scanning method) according to second configuration example]

[0189] The imaging device 100 according to the above-described first configuration example is an asynchronous imaging device that reads events by an asynchronous reading method. However, the event reading method is not limited to the asynchronous reading method and can be a synchronous reading method. An imaging device that applies the synchronous reading method is an imaging device of a scanning method that is the same as a normal imaging device that performs imaging at a predetermined frame rate.

[0190] Figure 17 is a block diagram showing an example of a configuration of an imaging device according to a second configuration example (i.e., an imaging device of a scanning method) that serves as the imaging device 2000 in the imaging system that applies the technology according to the present disclosure. ​

[0191] As Figure 17 shown, an imaging device 2000 according to a second configuration example of the imaging device used in the present disclosure includes a pixel array unit 2021, a drive unit 2022, a signal processing unit 2025, a read region selection unit 2027, and a signal generation unit 2028.

[0192] The pixel array unit 2021 includes a plurality of pixels 2030. The plurality of pixels 2030 outputs an output signal in response to a selection signal output of the read region selection unit 2027. The plurality of pixels 2030 can also each have a quantizer comparator in the pixel. The plurality of pixels 2030 outputs an output signal corresponding to a change amount of light intensity. The plurality of pixels 2030 can be arranged in a matrix two-dimensionally, as Figure 17 shown.

[0193] The drive unit 2022 drives each of the plurality of pixels 2030 to output a pixel signal generated in each of the pixels 2030 to the signal processing unit 2025. Note that the drive unit 2022 and the signal processing unit 2025 are circuit units for acquiring grayscale information. Therefore, in a case where only event information is acquired, the drive unit 2022 and the signal processing unit 2025 can not be provided.

[0194] The read region selection unit 2027 selects some of the plurality of pixels 2030 included in the pixel array unit 2021. Specifically, the read region selection unit 2027 determines a selection region in response to a request from each of the pixels 2030 of the pixel array unit 2021. For example, the read region selection unit 2027 selects any one or a plurality of rows included in a two-dimensional matrix structure corresponding to the pixel array unit 2021. The read region selection unit 2027 sequentially selects one or a plurality of rows according to a predetermined period. Further, the read region selection unit 2027 can determine a selection region in response to a request from each of the pixels 2030 of the pixel array unit 2021.

[0195] Based on the output signal of the pixel selected by the read region selection unit 2027, the signal generation unit 2028 generates an event signal corresponding to an active pixel in which an event is detected among the selected pixels. The event is an event of a change in light intensity. The active pixel is a pixel in which a change amount of light intensity corresponding to the output signal exceeds or falls below a predetermined threshold value. For example, the signal generation unit 2028 compares the output signal of the pixel with a reference signal, detects an active pixel outputting the output signal in a case where the output signal is greater than or less than the reference signal, and generates an event signal corresponding to the active pixel.

[0196] The signal generation unit 2028 may, for example, include a column selection circuit that arbitrates signals that enter the signal generation unit 2028. Further, the signal generation unit 2028 can output not only information about an active pixel in which an event has been detected but also information about an inactive pixel in which an event has not been detected.

[0197] The address information and the timestamp information of the active pixel in which an event has been detected are output from the signal generation unit 2028 through the output line 2015 (for example, (X, Y, T)). However, the data output from the signal generation unit 2028 can not only be the address information and the timestamp information but also information in a frame format (for example, (0, 0, 1, 0,...)).

[0198] [Distance measurement system]

[0199] The distance measurement system according to the embodiment of the present disclosure is a system for measuring a distance to an object by using a structured light technique. Further, the distance measurement system according to the embodiment of the present disclosure can also be used as a system for acquiring a three-dimensional (3D) image, and in this case, the distance measurement system can be referred to as a three-dimensional image acquisition system. In the structured light method, distance measurement is performed by recognizing the coordinates of a point image and from which light source (so-called point light source) the point image is projected by pattern matching.

[0200] Figure 18 is a schematic diagram illustrating a configuration example of the distance measurement system according to the embodiment of the present disclosure, and Figure 19 is a block diagram illustrating an example of a circuit configuration.

[0201] The distance measurement system 3000 according to the present embodiment includes a surface emitting semiconductor laser (for example, a vertical cavity surface emitting laser (VCSEL)) 3010 as a light source unit, and includes an event detection sensor 3020 called a DVS as a light receiving unit. The vertical cavity surface emitting laser (VCSEL) 3010 projects light of a predetermined pattern onto an object. The distance measurement system 3000 according to the present embodiment includes not only the vertical cavity surface emitting laser 3010 and the event detection sensor 3020 but also a system control unit 3030, a light source drive unit 3040, a sensor control unit 3050, a light source side optical system 3060, and a camera side optical system 3070.

[0202] The system control unit 3030 includes, for example, a processor (CPU), drives the vertical cavity surface emitting laser 3010 via the light source drive unit 3040, and drives the event detection sensor 3020 via the sensor control unit 3050. More specifically, the system control unit 3030 synchronously controls the vertical cavity surface emitting laser 3010 and the event detection sensor 3020.

[0203] In the distance measurement system 3000 having the above configuration according to the present embodiment, the light of the predetermined pattern emitted from the vertical cavity surface emitting laser 3010 is projected onto the object (measurement target) 3100 by the light source side optical system 3060. The projected light is reflected by the object 3100. Then, the light reflected by the object 3100 is incident on the event detection sensor 3020 by the camera side optical system 3070. The event detection sensor 3020 receives the light reflected by the object 3100, and detects a change in luminance of a pixel exceeding a predetermined threshold as an event. The event information detected by the event detection sensor 3020 is supplied to the application processor 3200 outside the distance measurement system 3000. The application processor 3200 performs predetermined processing on the event information detected by the event detection sensor 3020.

[0204] In the foregoing, the embodiments of the present disclosure have been described. However, the technical scope of the present disclosure is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the present disclosure. Further, components of different embodiments and modification examples can be combined as appropriate.

[0205] Further, the effects described in the present specification are merely illustrative and restrictive. In addition, additional effects can be obtained.

[0206] Note that the present technology can also have the following configurations. (1)

[0208] A solid-state imaging device includes:

[0209] a plurality of first photoelectric conversion elements arranged side by side in a first region;

[0210] a plurality of second photoelectric conversion elements arranged side by side in a second region adjacent to the first region;

[0211] a plurality of current-voltage conversion circuits that respectively convert currents output from the plurality of first photoelectric conversion elements and the plurality of second photoelectric conversion elements into voltages; and

[0212] a plurality of address event detection circuits that respectively detect changes in the voltages output from the plurality of current-voltage conversion circuits; wherein

[0213] at least one of the current-voltage conversion circuit and the address event detection circuit connected to the second photoelectric conversion element suppresses output of a signal based on the current output from the second photoelectric conversion element. (2)

[0215] The solid-state imaging device according to (1), wherein

[0216] the second region is disposed so as to surround the first region. (3)

[0218] The solid-state imaging device according to (1) or (2), wherein

[0219] An internal potential of at least one of the current-voltage conversion circuit connected to the second photoelectric conversion element and the address event detection circuit is fixed. (4)

[0221] The solid-state imaging device according to (3), wherein

[0222] The current-voltage conversion circuit connected to the second photoelectric conversion element includes a plurality of transistors; and

[0223] The internal potential of the current-voltage conversion circuit connected to the second photoelectric conversion element is fixed by short-circuiting the plurality of transistors. (5)

[0225] The solid-state imaging device according to (3), wherein

[0226] An internal potential of at least one of the current-voltage conversion circuit connected to the second photoelectric conversion element and the address event detection circuit is fixed by an external voltage. (6)

[0228] The solid-state imaging device according to any one of (1) to (5), further comprising:

[0229] A power supply region provided outside the second region and having a power supply wiring and a ground wiring. (7)

[0231] The solid-state imaging device according to (6), wherein

[0232] An internal potential of the power supply region is fixed. (8)

[0234] The solid-state imaging device according to (6) or (7), wherein

[0235] The power supply region is electrically integrated. (9)

[0237] An imaging apparatus comprising:

[0238] a solid-state imaging device;

[0239] an optical system that captures incident light from an object and forms an image on an imaging surface of the solid-state imaging device; and

[0240] a control unit that controls the solid-state imaging device; wherein

[0241] The solid-state imaging device comprises:

[0242] a plurality of first photoelectric conversion elements arranged side by side in a first region;

[0243] a plurality of second photoelectric conversion elements arranged side by side in a second region adjacent to the first region;

[0244] a plurality of current-voltage conversion circuits that respectively convert currents output from the plurality of first photoelectric conversion elements and the plurality of second photoelectric conversion elements into voltages; and

[0245] a plurality of address event detection circuits that respectively detect changes in the voltages output from the plurality of current-voltage conversion circuits; and

[0246] at least one of the current-voltage conversion circuit and the address event detection circuit suppresses output of a signal based on the current output from the plurality of second photoelectric conversion elements. (10)

[0248] The imaging device according to (9), wherein

[0249] the second region is provided so as to surround the first region. (11)

[0251] The imaging device according to (9) or (10), wherein

[0252] an internal potential of at least one of the current-voltage conversion circuit and the address event detection circuit connected to the second photoelectric conversion element is fixed. (12)

[0254] The imaging device according to (11), wherein

[0255] the current-voltage conversion circuit connected to the second photoelectric conversion element includes a plurality of transistors; and

[0256] the internal potential of the current-voltage conversion circuit connected to the second photoelectric conversion element is fixed by short-circuiting the plurality of transistors. (13)

[0258] The imaging device according to (11), wherein

[0259] the internal potential of at least one of the current-voltage conversion circuit and the address event detection circuit connected to the second photoelectric conversion element is fixed by an external voltage. (14)

[0261] The imaging device according to any one of (9) to (13), further comprising:

[0262] a power supply region provided outside the second region and having a power supply wiring and a ground wiring. (15)

[0264] The imaging device according to (14), wherein

[0265] The internal potential of the power supply region is fixed. (16)

[0267] The imaging device according to (14) or (15), wherein

[0268] The power supply region is electrically integrated.

[0269] Reference mark list

[0270] 100 Imaging device

[0271] 110 Imaging lens (example of optical system)

[0272] 130 Control unit

[0273] 200 Solid-state imaging element

[0274] 231, 231A Address event detection circuit

[0275] 310 Effective pixel

[0276] 310A Dummy pixel

[0277] 311 Photodiode (example of first photoelectric conversion element)

[0278] 311A Photodiode (example of second photoelectric conversion element)

[0279] 320, 320A Current-voltage conversion circuit

[0280] 421 Ground wiring

[0281] 422, 423 Power supply wiring

[0282] R1 Effective pixel region (example of first region)

[0283] R2 Dummy pixel region (example of second region)

[0284] R3 Power supply region

Claims

1. A solid-state imaging device comprising: a plurality of first photoelectric conversion elements arranged side by side in a first region; a plurality of second photoelectric conversion elements arranged side by side in a second region adjacent to the first region; a plurality of current-voltage conversion circuits that respectively convert currents output from the plurality of first photoelectric conversion elements and the plurality of second photoelectric conversion elements into voltages; and a plurality of address event detection circuits that respectively detect changes in the voltages output from the plurality of current-voltage conversion circuits, wherein at least one of the current-voltage conversion circuit and the address event detection circuit connected to the second photoelectric conversion element suppresses output of a signal based on the current output from the second photoelectric conversion element, wherein an internal potential of at least one of the current-voltage conversion circuit and the address event detection circuit connected to the second photoelectric conversion element is fixed, wherein the current-voltage conversion circuit connected to the second photoelectric conversion element includes a plurality of transistors, and wherein the internal potential of the current-voltage conversion circuit connected to the second photoelectric conversion element is fixed by short-circuiting the plurality of transistors.

2. The solid-state imaging device according to claim 1, wherein the second region is provided so as to surround the first region.

3. The solid-state imaging device according to claim 1, further comprising: a power supply region provided outside the second region and having a power supply wiring and a ground wiring.

4. The solid-state imaging device according to claim 3, wherein an internal potential of the power supply region is fixed.

5. The solid-state imaging device according to claim 3, wherein the power supply region is electrically integrated.

6. An imaging apparatus comprising: a solid-state imaging device; an optical system that captures incident light from an object and forms an image on an imaging surface of the solid-state imaging device; and a control unit that controls the solid-state imaging device; wherein the solid-state imaging device comprises: a plurality of first photoelectric conversion elements arranged side by side in a first region; a plurality of second photoelectric conversion elements arranged side by side in a second region adjacent to the first region; a plurality of current-voltage conversion circuits that respectively convert currents output from the plurality of first photoelectric conversion elements and the plurality of second photoelectric conversion elements into voltages; and a plurality of address event detection circuits that respectively detect changes in the voltages output from the plurality of current-voltage conversion circuits, wherein at least one of the current-voltage conversion circuit and the address event detection circuit connected to the second photoelectric conversion element suppresses output of a signal based on the current output from the second photoelectric conversion element, wherein an internal potential of at least one of the current-voltage conversion circuit and the address event detection circuit connected to the second photoelectric conversion element is fixed, wherein the current-voltage conversion circuit connected to the second photoelectric conversion element includes a plurality of transistors, and wherein the internal potential of the current-voltage conversion circuit connected to the second photoelectric conversion element is fixed by short-circuiting the plurality of transistors. ​ ​

Images