Instruction processing method, device, chip, board, equipment and storage medium

Abstract

The present disclosure provides an instruction processing method, apparatus, chip, board, device and storage medium, wherein the method comprises: obtaining a target loop instruction; the target loop instruction comprises multiple layers of nested loop instructions; based on the instruction creation parameters of the target loop instruction, determining a plurality of loop instructions to be reconstructed in the target loop instruction; wherein the instruction creation parameters comprise instruction requirement characteristics under at least one dimension; creating a first target instruction based on the plurality of loop instructions to be reconstructed; the first target instruction is used to describe the loop calculation process of the plurality of loop instructions to be reconstructed; and modifying the instructions in the target loop instruction associated with the plurality of loop instructions to be reconstructed based on the first target instruction to obtain a second target instruction.

Description

Technical Field

[0001] The present disclosure relates to the technical field of computers, and in particular, to an instruction processing method, apparatus, chip, board, device and storage medium. Background Art

[0002] Computer instructions are instructions and commands that direct the work of a machine. The process of executing instructions arranged in a certain order is the working process of the computer. The working process of instruction execution mainly includes access to storage space, calculation of data, and control-related instructions. For a computer program, computer instructions contain control instructions and calculation instructions. Among them, if the number of control instructions is large, it will affect the execution efficiency of the computer program, thereby affecting the execution efficiency of the processor. Summary of the invention

[0003] The embodiments of the present disclosure at least provide an instruction processing method, apparatus, chip, board, device and storage medium.

[0004] In a first aspect, an embodiment of the present disclosure provides an instruction processing method, characterized in that it is applied to a processor, comprising:

[0005] Obtaining a target loop instruction; wherein the target loop instruction includes multiple layers of nested loop instructions;

[0006] Based on the instruction creation parameters of the target cycle instruction, determining a plurality of cycle instructions to be rebuilt in the target cycle instruction; wherein the instruction creation parameters include instruction requirement characteristics under at least one dimension;

[0007] Creating a first target instruction based on the plurality of loop instructions to be rebuilt; the first target instruction is used to describe the loop calculation process of the plurality of loop instructions to be rebuilt;

[0008] The instructions in the target loop instruction associated with the plurality of loop instructions to be rebuilt are modified based on the first target instruction to obtain a second target instruction.

[0009] In an optional implementation manner, the modifying, based on the first target instruction, the instruction in the target loop instruction associated with the plurality of loop instructions to be rebuilt to obtain the second target instruction includes:

[0010] Determining a target loop body of a first loop instruction in the target loop instruction; the first loop instruction is a loop instruction of a layer above the loop instruction with the highest level among the plurality of loop instructions to be reconstructed;

[0011] A target loop body in the target loop instruction is modified based on the first target instruction, and the second target instruction is obtained after the modification.

[0012] In an optional implementation manner, the instruction creation parameter is an instruction indication identifier; and the instruction creation parameter based on the target loop instruction determines a plurality of loop instructions to be rebuilt in the target loop instruction, including:

[0013] Obtaining instruction contents of each layer of loop instructions in the target loop instruction;

[0014] Determine, based on the instruction content, a plurality of loop instructions carrying the instruction indication identifier in the loop instructions of each layer;

[0015] Loop instructions that meet the creation requirement among the multiple loop instructions are determined as the multiple loop instructions to be rebuilt.

[0016] In an optional implementation manner, the instruction creation parameter is an instruction requirement parameter; and the instruction creation parameter based on the target cycle instruction, determining a plurality of cycle instructions to be rebuilt in the target cycle instruction, comprises:

[0017] Obtaining instruction requirement parameters; wherein the instruction requirement parameters include at least one of the following: instruction complexity, instruction execution efficiency, and instruction execution repeatability;

[0018] The plurality of loop instructions to be reconstructed are determined based on a plurality of second loop instructions in the target loop instructions that match the instruction requirement parameter.

[0019] In an optional implementation manner, determining the plurality of loop instructions to be reconstructed based on the plurality of second loop instructions in the target loop instruction that match the instruction requirement parameter comprises:

[0020] Determining instruction dimension information based on the instruction requirement parameter; wherein the instruction dimension information is used to indicate the number of loop layers of the loop instruction to be reconstructed in the target loop instruction;

[0021] The plurality of loop instructions to be reconstructed are determined based on a plurality of second loop instructions in the target loop instruction that match the instruction dimension information.

[0022] In an optional implementation, the method further includes: obtaining a first calculation type of the plurality of loop instructions to be reconstructed, and obtaining a second calculation type of each second loop instruction;

[0023] The determining of the multiple loop instructions to be reconstructed based on the multiple second loop instructions in the target loop instructions that match the instruction requirement parameters includes: determining a multiple third loop instructions matching the first calculation type in the multiple second loop instructions based on the second calculation type, and determining the multiple loop instructions to be reconstructed based on the multiple third loop instructions, wherein the multiple third loop instructions are loop instructions of adjacent levels in the multiple second loop instructions.

[0024] In an optional implementation manner, the creating a first target instruction based on the multiple loop instructions to be rebuilt includes:

[0025] Determine address information and loop information based on the multiple loop instructions to be rebuilt, wherein the address information is used to indicate a storage address of data for executing each loop instruction to be rebuilt, and the loop information is used to indicate the number of loop layers of the multiple loop instructions to be rebuilt and / or the number of loops of each loop instruction to be rebuilt;

[0026] The first target instruction is created based on the address information and the loop information.

[0027] In an optional embodiment, the loop information includes: first loop information and / or second loop information, and the address information includes: data starting address and address stepping information, wherein the first loop information is used to indicate the number of loop layers of the multiple loop instructions to be reconstructed, and the second loop information is used to indicate the number of loops of each loop instruction to be reconstructed; the data starting address is used to indicate the storage address of the starting data for executing the first target instruction, and the address stepping information is used to indicate the address change information of the storage address of the data of each loop instruction to be reconstructed during each execution.

[0028] In a second aspect, the present disclosure also provides an instruction processing device, including:

[0029] An acquisition unit, used for acquiring a target loop instruction; the target loop instruction includes multiple layers of nested loop instructions;

[0030] A determination unit, configured to determine a plurality of to-be-reconstructed loop instructions in the target loop instruction based on an instruction creation parameter of the target loop instruction; wherein the instruction creation parameter includes an instruction requirement feature under at least one dimension;

[0031] A creating unit, configured to create a first target instruction based on the plurality of loop instructions to be rebuilt; the first target instruction is used to describe a loop calculation process of the plurality of loop instructions to be rebuilt;

[0032] The modification unit is used to modify the instructions in the target loop instruction associated with the multiple loop instructions to be rebuilt based on the first target instruction to obtain a second target instruction.

[0033] In a third aspect, an embodiment of the present disclosure further provides a chip, comprising: a processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, the processor and the memory communicate via a bus, and when the machine-readable instructions are executed by the processor, the steps of the above-mentioned first aspect, or any possible implementation of the first aspect are performed.

[0034] In a fourth aspect, an embodiment of the present disclosure further provides a board, comprising: a packaging structure encapsulating at least one chip as described in the third aspect.

[0035] In a fifth aspect, an embodiment of the present disclosure further provides a computer device, comprising the chip as described in the third aspect, or the board as described in the fourth aspect.

[0036] In a sixth aspect, an embodiment of the present disclosure further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned first aspect, or any possible implementation of the first aspect are executed.

[0037] The disclosed embodiments provide an instruction processing method, apparatus, chip, board, device and storage medium. In the disclosed embodiments, a target loop instruction in a program can be first obtained, and multiple loop instructions to be reconstructed in the target loop instruction can be determined based on the instruction creation parameters of the target loop instruction. Next, a first target instruction can be created based on the multiple loop instructions to be reconstructed, and instructions associated with the multiple loop instructions to be reconstructed in the target loop instruction can be modified based on the first target instruction to obtain a second target instruction, thereby simplifying the instructions associated with the multiple loop instructions to be reconstructed and reducing the number of loop instructions that are non-computational instructions, which is equivalent to increasing the proportion of core computing instructions in the program, thereby improving the execution efficiency of the processor on the program.

[0038] In order to make the above-mentioned objectives, features and advantages of the present disclosure more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following is a brief introduction to the drawings required for use in the embodiments. The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and are used together with the specification to illustrate the technical solutions of the present disclosure. It should be understood that the following drawings only illustrate certain embodiments of the present disclosure and should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can also be obtained based on these drawings without creative work.

[0040] Figure 1 A flowchart of an instruction processing method provided by an embodiment of the present disclosure is shown;

[0041] Figure 2 A flowchart of determining a plurality of to-be-reconstructed loop instructions in a target loop instruction based on instruction creation parameters of a target loop instruction provided by an embodiment of the present disclosure is shown;

[0042] Figure 3 A flowchart of creating a first target instruction based on multiple loop instructions to be rebuilt provided by an embodiment of the present disclosure is shown;

[0043] Figure 4 A flowchart of modifying instructions associated with a plurality of to-be-reconstructed loop instructions in a target loop instruction based on a first target instruction to obtain a second target instruction is shown in an embodiment of the present disclosure;

[0044] Figure 5 A schematic diagram of an instruction processing device provided by an embodiment of the present disclosure is shown;

[0045] Figure 6 A schematic diagram of a chip provided by an embodiment of the present disclosure is shown;

[0046] Figure 7 A schematic diagram of a board provided by an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical scheme and advantages of the embodiments of the present disclosure clearer, the technical scheme in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments. The components of the embodiments of the present disclosure generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the drawings is not intended to limit the scope of the present disclosure for protection, but merely represents the selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present disclosure.

[0048] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0049] The term "and / or" herein only describes an association relationship, indicating that three relationships may exist. For example, A and / or B may represent the following three situations: A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "at least one" herein represents any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C may represent including any one or more elements selected from the set consisting of A, B, and C.

[0050] Computer instructions are instructions and commands that direct the work of a machine. The process of executing instructions arranged in a certain order is the working process of the computer. The working process of instruction execution mainly includes access to storage space, calculation of data, and control-related instructions. Research has found that for a computer program, computer instructions contain control instructions and calculation instructions. Among them, if the number of control instructions is large, it will affect the execution efficiency of the computer program, thereby affecting the execution efficiency of the processor.

[0051] Computer instructions include core computing instructions and a large number of non-computing instructions. For example, loop instructions include computing instructions and loop control instructions (i.e., the non-computing instructions mentioned above), wherein the loop control instructions are used to control the execution process of each layer of loop instructions in the loop instructions. During the execution of the loop instructions, a large number of non-computing instructions will occupy more instruction cycles, thereby affecting the execution efficiency of the loop instructions.

[0052] In the related technical solution, the instruction distribution unit can send multiple instructions to the computing unit of the processor within one instruction cycle. However, the hardware structure of this technical solution is relatively complex and is not suitable for AI processor scenarios with high energy efficiency requirements.

[0053] Based on the above research, the present disclosure provides an instruction processing method, device, chip, board, equipment and storage medium. In an embodiment of the present disclosure, a target loop instruction can be first obtained, and multiple loop instructions to be reconstructed in the target loop instruction can be determined based on the instruction creation parameters of the target loop instruction; next, a first target instruction can be created based on the multiple loop instructions to be reconstructed, and the instructions associated with the multiple loop instructions to be reconstructed in the target loop instruction can be modified based on the first target instruction to obtain a second target instruction. In the above implementation, by reconstructing multiple loop instructions to be reconstructed into the first target instruction, the instruction dimension of the target loop instruction can be reduced, and the number of control instructions in the target loop instruction can be reduced, thereby increasing the proportion of calculation instructions in the target loop instruction for the instruction cycle, and improving the execution efficiency of the processor on the program.

[0054] To facilitate understanding of this embodiment, a method for processing instructions disclosed in an embodiment of the present disclosure is first introduced in detail. The execution subject of the method for processing instructions provided in the embodiment of the present disclosure is generally a computer device with certain computing capabilities. In some possible implementations, the method for processing instructions can be implemented by a processor calling a computer-readable instruction stored in a memory.

[0055] See also Figure 1 FIG. 1 is a flowchart of an instruction processing method provided by an embodiment of the present disclosure, wherein the method includes steps S101 to S107, wherein:

[0056] S101: Acquire a target loop instruction; the target loop instruction includes multiple layers of nested loop instructions.

[0057] In the embodiment of the present disclosure, the target loop instruction may include multiple loop instructions, wherein the multiple loop instructions may be the above-mentioned multi-layer nested loop instructions. The target loop instruction is introduced below by taking a 4-layer nested loop instruction (fdim0, fdim1, wdim0, wdim1) as an example, wherein the loop instruction wdim1 is nested inside wdim0, the loop instruction wdim0 is nested inside the loop instruction fdim1, and the loop instruction fdim1 is nested inside the loop instruction fdim0. The specific instruction content of the 4-layer nested loop instruction may be the following:

[0058]

[0059] Among them, the for loop instruction in the 7th line of the program (denoted as for4) is the above-mentioned loop instruction wdim1, the for loop instruction in the 5th line of the program (denoted as for3) is the above-mentioned loop instruction wdim0, the for loop instruction in the 3rd line of the program (denoted as for2) is the above-mentioned loop instruction fdim1, and the for loop instruction in the 1st line of the program (denoted as for1) is the above-mentioned loop instruction fdim0.

[0060] The above 4-layer nested loop instructions can be understood as loop instructions for performing convolution calculations on a two-dimensional feature map and a two-dimensional convolution kernel.

[0061] Here, the specific instruction patterns for each loop instruction from for1 to for4 can be the following patterns:

[0062] for(initialization expression statement, conditional judgment statement, control condition statement)

[0063] {

[0064] Loop body statement;

[0065] }

[0066] At this time, taking for4 as an example, in for(m = 0, m < kernel_w, m++), m = 0 is the "initialization expression statement", "m < kernel_w" is the "conditional judgment statement", and "m++" is the "control condition statement"; "macc(fmp, weight, res)" is the "loop body statement". That is to say, the initialization expression statement, conditional judgment statement, and control condition statement can be understood as the control-type instructions described above, and the loop body statement can be understood as the calculation-type instructions described above. When the number of control-type instructions is large, it will occupy more instruction cycles, thereby reducing the execution efficiency of the processor.

[0067] S103: Determine multiple loop instructions to be reconstructed in the target loop instruction based on the instruction creation parameters of the target loop instruction; wherein, the instruction creation parameters include instruction requirement characteristics in at least one dimension.

[0068] Here, the instruction creation parameters set by the user for the target loop instruction can be obtained, and then, among the multiple loop instructions included in the target loop instruction, the loop instructions that match the instruction creation parameters are determined as the multiple loop instructions to be reconstructed. Among them, different instruction creation parameters can be set for different target loop instructions.

[0069] The instruction creation parameters may include at least one instruction requirement feature, and one or more instruction requirement features in the at least one instruction requirement feature may correspond to a dimension, wherein the dimension of the instruction requirement feature is used to indicate the feature type of the instruction requirement feature. Based on this, the instruction creation parameters may include instruction requirement features belonging to multiple feature types.

[0070] In the embodiments of the present disclosure, the feature types may be identification features and parameter features. For example, for identification features, the instruction creation parameter may be an instruction indication identifier; for parameter features, the instruction creation parameter may be an instruction requirement parameter, wherein the instruction indication identifier is used to indicate the loop instruction to be reconstructed in the target loop instruction, and the instruction requirement parameter is used to indicate the instruction index requirement of the reconstructed loop instruction, wherein the reconstructed loop instruction may be the second target instruction in the following steps.

[0071] In an optional implementation, the instruction indication mark may be a mark carried in the instruction content of the loop instruction, and the instruction indication mark is used to indicate whether the loop instruction is a loop instruction to be rebuilt.

[0072] In an optional embodiment, the above-mentioned instruction requirement parameters may include at least one of the following parameters: instruction complexity, instruction execution efficiency, and instruction execution repeatability; in addition, other requirement parameters that can be used to indicate the instruction index requirements of the reconstructed loop instruction may also be included. The present disclosure does not make specific limitations on this, which is subject to what can be implemented.

[0073] Here, the instruction complexity can be used to indicate the instruction dimension of the second target instruction. The instruction execution efficiency can be used to indicate the number of instruction cycles occupied by the second target instruction; or, to indicate the number of instruction cycles occupied by the control instructions (or calculation instructions) in the second target instruction. The instruction execution repeatability can be used to indicate the maximum number of cycles of each loop instruction in the second target instruction.

[0074] In the disclosed embodiment, the multiple loop instructions to be reconstructed may be all loop instructions in the target loop instruction, or may be part of the loop instructions in the target loop instruction; and the multiple loop instructions to be reconstructed include at least multiple layers of loop instructions continuously nested in the target loop instruction.

[0075] S105: Creating a first target instruction based on the multiple loop instructions to be rebuilt; the first target instruction is used to describe the loop calculation process of the multiple loop instructions to be rebuilt.

[0076] Here, the first target instruction may be a single coarse-grained instruction, wherein the single coarse-grained instruction can be used to describe the loop calculation process of multiple loop instructions to be rebuilt. In the disclosed embodiment, by creating multiple loop instructions to be rebuilt as a single coarse-grained instruction, the number of control instructions in the target loop instruction can be reduced, for example, the number of control instructions in each loop instruction to be rebuilt can be reduced.

[0077] For the single coarse-grained instruction, the instruction distribution unit can send the single coarse-grained instruction to the computing unit of the processor through an instruction cycle. After the computing unit of the processor obtains the single coarse-grained instruction, it can execute the loop calculation process of the above-mentioned multiple loop instructions to be reconstructed based on the single coarse-grained instruction.

[0078] Through the above processing method, the proportion of control instructions in the target loop instructions to the instruction cycle can be effectively reduced, thereby increasing the proportion of calculation instructions in the target loop instructions to the instruction cycle, thereby improving the processor's execution efficiency of computer programs.

[0079] In an embodiment of the present disclosure, at least one first target instruction can be created based on the loop instruction to be rebuilt. Here, a first target instruction can be created based on multiple layers of loop instructions continuously nested in multiple loop instructions to be rebuilt. The present disclosure does not specifically limit the number of first target instructions to be created.

[0080] For example, assume that the target loop instruction includes the following multi-layer nested loop instructions: for1-for2-for3-for4-for5-for6-for7-for8, where assume that the multiple loop instructions to be reconstructed are for6-for7-for8 and for2-for3-for4, then a first target instruction can be created based on for2-for3-for4, and another first target instruction can be created based on for6-for7-for8.

[0081] S107: Modify the instructions in the target loop instruction that are associated with the multiple loop instructions to be rebuilt based on the first target instruction to obtain a second target instruction.

[0082] In specific implementation, instructions in the target loop instructions that are associated with the multiple loop instructions to be reconstructed may be determined, and the associated instructions may be replaced with the above-mentioned coarse-grained instructions, thereby obtaining the reconstructed loop instructions, namely, the second target instructions.

[0083] Following the above four-layer nested loop instructions, assuming that the loop instructions to be reconstructed in the four-layer nested loop instructions are for3 and for4, then the instructions associated with for3 and for4 in the four-layer nested loop instructions are the instructions corresponding to the program in lines 4-8 in the above computer program. At this time, the instructions corresponding to the program in lines 4-8 can be replaced with the first target instruction, thereby obtaining the second target instruction. If the first target instruction is represented as: tmacc (the instruction content of the first target instruction).

[0084] Based on this, the above 4-layer nested loop instructions can be described as:

[0085]

[0086] Here, the instruction content of the first target instruction is used to indicate the storage address of the data required to be used in the process of executing the coarse-grained instruction, and is used to indicate the loop control parameters of multiple loop instructions to be reconstructed (i.e., for3 and for4). The loop control parameters are parameters used to control the loop state of for3 and for4.

[0087] In the disclosed embodiment, the target loop instruction can be first obtained, and multiple loop instructions to be reconstructed in the target loop instruction can be determined based on the instruction creation parameters of the target loop instruction; next, a first target instruction can be created based on the multiple loop instructions to be reconstructed, and the instructions associated with the multiple loop instructions to be reconstructed in the target loop instruction can be modified based on the first target instruction to obtain a second target instruction. In the above implementation, by reconstructing multiple loop instructions to be reconstructed into the first target instruction, the instruction dimension of the target loop instruction can be reduced, and the number of control instructions in the target loop instruction can be reduced, thereby increasing the proportion of computational instructions in the target loop instruction for the instruction cycle, and improving the execution efficiency of the processor on the program.

[0088] In an optional implementation, when the instruction creation parameter is an instruction indication identifier, the above step S103, based on the instruction creation parameter of the target loop instruction, determines a plurality of loop instructions to be rebuilt in the target loop instruction, specifically including the following process:

[0089] S11, obtaining the instruction content of each layer of loop instructions in the target loop instruction;

[0090] S12, determining, based on the instruction content, a plurality of loop instructions carrying the instruction indication identifier in the loop instructions of each layer;

[0091] S13: Determine loop instructions that meet the creation requirement among the multiple loop instructions as the multiple loop instructions to be rebuilt.

[0092] In an embodiment of the present disclosure, the above instruction creation parameter may be an instruction indication identifier预先 set by a programmer in a computer program for loop instructions at a specified level in a target loop instruction. Here, the instruction indication identifier may be set in the instruction content of the corresponding loop instruction.

[0093] For example, for the for3 in the above 4-level nested loop instruction: for(l = 0, l < kernel_h, l++), an instruction indication identifier Q may be set in the instruction content. At this time, the instruction content of the loop instruction for3 may be described as: for(l = 0, l < kernel_h, l++, Q). Among them, when multiple loop instructions carry the instruction indication identifier Q, the loop instruction may be determined as a loop instruction to be reconstructed.

[0094] In specific implementation, the instruction content of each loop instruction in the target loop instruction may be traversed, and the corresponding instruction indication identifier may be searched from the instruction content of each loop instruction, so as to determine the loop instruction carrying the instruction indication identifier according to the search result.

[0095] Among the multiple loop instructions found to carry the instruction indication identifier, the loop instructions that meet the creation requirements are determined as multiple loop instructions to be reconstructed. The creation requirements are described in the following cases.

[0096] Case 1: The creation requirement is an instruction continuity requirement.

[0097] In this case, the adjacent nested loop instructions among the multiple loop instructions carrying the instruction indication identifier may be determined as multiple loop instructions to be reconstructed.

[0098] Case 2: The creation requirement is a requirement determined based on the identification content of the instruction indication identifier.

[0099] For the above instruction indication identifier, different identification contents may be set. For example, the identification content may be 1 or 0. Continuing with the above example, when Q = 1, it may indicate that for3 is a loop instruction to be reconstructed, and when Q = 0, it may indicate that for3 is not a loop instruction to be reconstructed.

[0100] In this case, the loop instructions with the identification content of the instruction indication identifier being 1 may be determined as multiple loop instructions to be reconstructed. Further, the adjacent nested loop instructions with the identification content of the instruction indication identifier being 1 may be determined as multiple loop instructions to be reconstructed.

[0101] In the above implementation manner, by setting an instruction indication identifier in the instruction content of the loop instruction and identifying multiple loop instructions to be reconstructed according to the instruction indication identifier, it is possible to flexibly set the loop instructions to be reconstructed in each layer of the loop instructions of the target loop instruction, thereby meeting the setting requirements of the programmer.

[0102] In an optional implementation, the above instruction creation parameters are instruction requirement parameters, such as Figure 2 The flowchart of step S103 is shown, wherein, based on the instruction creation parameter of the target loop instruction, a plurality of loop instructions to be rebuilt in the target loop instruction are determined, specifically including the following process:

[0103] S21: Obtain instruction requirement parameters; wherein the instruction requirement parameters include at least one of the following: instruction complexity, instruction execution efficiency, and instruction execution repeatability.

[0104] Here, in the case where the feature type of the instruction requirement feature contained in the above instruction creation parameters is a parameter-type feature, the above instruction creation parameters may be instruction requirement parameters. The instruction requirement parameters may be used to indicate the instruction index requirements of the following second target instruction, wherein the instruction index requirements are used to indicate the performance requirements of the instruction execution of the second target instruction in the corresponding instruction execution scenario. The instruction requirement parameters may include at least one of the following: instruction complexity, instruction execution efficiency, and instruction execution repeatability. The above instruction requirement parameters will be introduced below.

[0105] Parameter 1: instruction complexity.

[0106] The instruction complexity can be used to indicate the instruction dimension of the above-mentioned second target instruction, wherein the instruction dimension can be used to indicate the number of levels of loop instructions contained in the second target instruction; or, the instruction complexity can also be used to indicate the number of instructions contained in the instruction content of the second target instruction (for example, the number of control instructions).

[0107] Following the above four-layer nested loop instruction, if the instruction complexity is used to indicate that the number of levels of the loop instruction of the second target instruction is 2, then the second target loop instruction can be described as:

[0108]

[0109] Parameter 2: instruction execution efficiency.

[0110] The instruction execution efficiency may be used to indicate the number of instruction cycles occupied by the second target instruction; or, to indicate the number of instruction cycles occupied by control instructions (or computing instructions) in the second target instruction.

[0111] Here, during the execution of an instruction, the number of instruction cycles occupied will affect the execution efficiency of the instruction. The more instruction cycles occupied, the lower the execution efficiency of the instruction, and the fewer instruction cycles occupied, the higher the execution efficiency of the instruction.

[0112] In the embodiment of the present disclosure, a mapping relationship between instruction execution efficiency and instruction cycle can be pre-established. The mapping relationship contains multiple data, each of which can be expressed in the following format: instruction execution efficiency A-number of instruction cycles B, wherein the mapping relationship is used to indicate that when the instruction execution efficiency of the second target instruction is A, the number of instruction cycles occupied by the second target instruction is B. The instruction execution efficiency A can be a specific value or a numerical range, and similarly, the number of instruction cycles B can also be a specific value or a numerical range. The present disclosure does not make specific limitations on this, and it is subject to what can be implemented.

[0113] Parameter three: instruction execution repeatability.

[0114] The instruction execution repeatability can be used to indicate the maximum number of loops of each loop instruction in the second target instruction, wherein the maximum number of loops can be understood as the number of loops of each loop instruction in each loop process.

[0115] Here, during the execution of the instruction, the number of execution times of each loop instruction will affect the execution efficiency of the instruction. The more times the loop instruction is executed, the lower the execution efficiency of the instruction, and the fewer times the loop instruction is executed, the higher the execution efficiency of the instruction.

[0116] In the embodiment of the present disclosure, loop instructions having a loop number greater than the maximum loop number may be selected from among the multi-layer nested loop instructions, and then the loop instructions to be reconstructed may be determined from among the determined loop instructions.

[0117] Through this processing method, loop instructions with a large number of loops in multi-layer nested loop instructions can be reconstructed into a single coarse-grained instruction, thereby obtaining a second target instruction with a loop number that meets the requirement, thereby improving instruction execution efficiency.

[0118] S22: Determine the plurality of loop instructions to be reconstructed based on the plurality of second loop instructions in the target loop instruction that match the instruction requirement parameter.

[0119] In the embodiment of the present disclosure, after the instruction requirement parameter is obtained, multiple second loop instructions matching the instruction requirement parameter can be determined in the target loop instruction. In specific implementation, instruction dimension information corresponding to the instruction requirement parameter can be determined, and then loop instructions of corresponding dimensions are determined as multiple second loop instructions in the target loop instruction based on the instruction dimension information.

[0120] In an optional implementation, the above step S22, determining the multiple loop instructions to be reconstructed based on the multiple second loop instructions in the target loop instruction that match the instruction requirement parameter, specifically includes the following process:

[0121] (1) determining instruction dimension information based on the instruction requirement parameter; wherein the instruction dimension information is used to indicate the number of loop layers of the loop instruction to be reconstructed in the target loop instruction;

[0122] (2) Determine the multiple loop instructions to be reconstructed based on multiple second loop instructions in the target loop instruction that match the instruction dimension information.

[0123] In the embodiment of the present disclosure, each instruction requirement parameter can determine an instruction dimension information; or all instruction requirement parameters can determine an instruction dimension information; or some instruction requirement parameters can determine an instruction dimension information. The following will introduce the instruction dimension information determination process in detail according to different situations.

[0124] Case 1:

[0125] In this case, instruction dimension information may be determined based on all instruction requirement parameters, and then the loop instruction to be reconstructed may be determined based on the instruction dimension information.

[0126] In a specific implementation, the instruction parameters of the target loop instruction can be obtained, wherein the instruction parameters of the target loop instruction include at least one of the following: the number of instructions of multiple loop instructions contained in the target loop instruction, the number of loops of each loop instruction, the amount of calculation of each loop instruction, and the number of control instructions and calculation instructions in the target loop instruction. Then, the instruction parameters and instruction requirement parameters of the target loop instruction are input into the deep neural network model for processing, so as to predict an instruction dimension information according to the deep neural network model.

[0127] In the disclosed embodiment, the deep neural network model can determine matching instruction dimension information based on the instruction parameters and instruction requirement parameters of the target loop instruction, so that the second target instruction obtained after reconstruction can meet the above instruction requirement parameters.

[0128] Here, the training process of the deep neural network model can be described as follows:

[0129] First, a training sample is generated, wherein the training sample includes input data and data labels, the input data may be a training instruction parameter, and the data label may be label dimension information corresponding to the training instruction parameter.

[0130] Then, the training samples are input into the initial deep neural network model for training. During the training process, the predicted data can be obtained based on the input data; then, the loss function is determined based on the predicted data and the data label, and then the model parameters of the initial deep neural network model are adjusted based on the loss function, so as to obtain a deep neural network model that meets the training requirements.

[0131] Case 2:

[0132] In this case, a piece of instruction dimension information can be determined based on each instruction creation parameter, and then a final piece of instruction dimension information can be determined based on all the instruction dimension information, so as to determine multiple loop instructions to be reconstructed according to the final instruction dimension information. For example, the maximum instruction dimension information in all the instruction dimension information can be determined as the final instruction dimension information, so as to determine multiple loop instructions to be reconstructed according to the maximum instruction dimension information.

[0133] First: The instruction requirement parameter is the instruction complexity.

[0134] From the above description, it can be known that the instruction complexity can be used to indicate the number of levels M1 of loop instructions included in the second target instruction. At this time, the number of levels M2 of loop instructions included in the target loop instruction can be determined, and the instruction dimension information A1 can be determined based on the difference between the number of levels M2 and the number of levels M1.

[0135] Second: The instruction requirement parameter is the instruction execution efficiency.

[0136] From the above description, it can be seen that the instruction execution efficiency can be used to indicate the number of instruction cycles occupied by the above-mentioned second target instruction; or, to indicate the number of instruction cycles occupied by control instructions (or calculation instructions) in the second target instruction.

[0137] In specific implementation, the number of instruction cycles matching the execution efficiency of the instruction can be determined based on the above mapping relationship, recorded as B1. At this time, the number of instruction cycles occupied by the target cycle instruction can be obtained, recorded as B2, and then based on the number of instruction cycles B2 and the number of instruction cycles B1, the instruction dimension information A2 is determined.

[0138] Here, the difference between the instruction cycle number B2 and the instruction cycle number B1 may be determined, and the instruction dimension information A2 may be determined based on the difference.

[0139] In specific implementation, the number C of instruction cycles occupied by each loop instruction in each layer of nested loop instructions can be first determined; then, the number of loop layers of multiple consecutive loop instructions whose total number is greater than or equal to the above difference can be determined from multiple numbers C, thereby determining the instruction dimension information A2 based on the number of loop layers.

[0140] Third: The instruction requirement parameter is the instruction execution repeatability.

[0141] When the instruction execution repeatability is used to indicate the maximum number of loops of each loop instruction in the second target instruction, loop instructions in the target loop instruction whose loop number is greater than the maximum number of loops can be determined, and the number of determined loop instructions is determined as instruction dimension information A3.

[0142] After determining the above-mentioned instruction dimension information A1, instruction dimension information A2 and instruction dimension information A3, the maximum instruction dimension information among the instruction dimension information A1, instruction dimension information A2 and instruction dimension information A3 can be determined as the final instruction dimension information.

[0143] After the instruction dimension information is determined in the manner described above, a plurality of second loop instructions matching the instruction dimension information may be determined in the target loop instruction.

[0144] Here, starting from the innermost loop instruction in the target loop instruction, the loop instructions of multiple consecutive levels can be determined as multiple second loop instructions, wherein the number of levels of the multiple consecutive levels is the instruction dimension information. Afterwards, multiple loop instructions to be reconstructed can be determined from the multiple second loop instructions, for example, the multiple second loop instructions can be determined as multiple loop instructions to be reconstructed.

[0145] For example, assume that the target loop instruction includes the following multi-layer nested loop instructions: for1-for2-for3-for4-for5-for6-for7-for8. If it is determined that the above instruction dimension information A1=3, instruction dimension information A2=2, and instruction dimension information A3=3. At this time, it can be determined that the maximum instruction dimension information 3 is determined as the final instruction dimension information. At this time, starting from the innermost loop instruction (i.e., for8) in the target loop instruction, loop instructions of multiple consecutive levels can be determined as multiple second loop instructions, for example, for6-for7-for8 can be determined as multiple second loop instructions.

[0146] In the above-mentioned implementation mode, by determining a plurality of loop instructions to be reconstructed in a target loop instruction through instruction requirement parameters, it is possible to automatically match a plurality of second loop instructions that meet the requirements in the target loop instruction as loop instructions to be reconstructed according to user requirements, thereby being able to meet the user's various instruction requirements, thereby improving the applicable scenarios of the technical solution disclosed herein.

[0147] In an optional embodiment, the above Figure 2 Based on the illustrated embodiment, the technical solution provided by the present disclosure also includes the following steps:

[0148] A preset first calculation type is obtained, and a second calculation type of each second loop instruction is obtained.

[0149] Based on this, the above S22, based on the multiple second loop instructions in the target loop instruction that match the instruction requirement parameter, determines the multiple loop instructions to be reconstructed, and specifically also includes the following steps:

[0150] Based on the second calculation type, a third loop instruction matching the first calculation type is determined from among the plurality of second loop instructions, and the plurality of loop instructions to be reconstructed are determined based on the third loop instruction.

[0151] In the disclosed embodiment, each loop instruction in the target loop instruction includes a corresponding calculation type, wherein the calculation type is used to indicate the type of corresponding calculation performed by the corresponding loop instruction on the corresponding operand, for example, a multiplication operation, an addition operation, a convolution operation, and the like. Here, a pre-set calculation type, i.e., a first calculation type, can be obtained, and the calculation type of each second loop instruction can be obtained to obtain a second calculation type. Here, the first calculation type can be a calculation type pre-set by a programmer.

[0152] Next, the second calculation type and the first calculation type may be matched to determine a second calculation type that is the same as the first calculation type, and a second loop instruction determined by the same second calculation type may be determined as a third loop instruction.

[0153] In a case where the number of first calculation types is one, a second calculation type that is the same as the first calculation type may be determined.

[0154] In the case that there are multiple first calculation types, a second calculation type that is the same as any first calculation type may be determined, and a second loop instruction determined by the same second calculation type may be determined as a third loop instruction.

[0155] Here, the first calculation type can be understood as a type preset by a programmer, and the number of the first calculation type can be multiple, and the first calculation type can indicate a loop instruction that can be reconstructed in multiple second loop instructions. Therefore, by matching the second calculation type with the first calculation type, the loop instruction that can be reconstructed can be determined in multiple second loop instructions.

[0156] In the case where there are multiple first calculation types, it is also possible to determine the first calculation type specified by the user among the multiple first calculation types, and then determine the second calculation type that is the same as the specified first calculation type, and determine the second loop instruction determined by the same second calculation type as the third loop instruction.

[0157] Afterwards, multiple loop instructions to be reconstructed can be determined based on the third loop instruction. For example, when there are multiple third loop instructions, the third loop instructions at adjacent levels among the multiple third loop instructions can be determined as the multiple loop instructions to be reconstructed.

[0158] Continuing with the above example, for the above four-layer nested loop instructions (fdim0, fdim1, wdim0, wdim1), it is assumed that the four-layer nested loop instructions are loop instructions for performing convolution calculations on a two-dimensional feature map and a two-dimensional convolution kernel.

[0159] Assume that the second loop instructions determined in the 4-layer nested loop instructions (fdim0, fdim1, wdim0, wdim1) are wdim0 and wdim1. If the first calculation type is convolution calculation, and the second calculation type of the second loop instruction is convolution calculation, then the second loop instructions wdim0 and wdim1 can be determined as the third loop instructions, and the third loop instructions are determined as multiple calculation instructions to be reconstructed.

[0160] In the above implementation, after determining a plurality of second loop instructions, a third loop instruction that meets the type requirement can be screened out from the plurality of second loop instructions based on the calculation type, and a plurality of loop instructions to be reconstructed can be determined based on the third loop instruction. Through this processing method, a refined screening of target loop instructions can be achieved, thereby screening out loop instructions that better meet user needs.

[0161] In an optional embodiment, if Figure 3 As shown, the above step S105 creates a first target instruction based on the multiple loop instructions to be rebuilt, and specifically includes the following steps:

[0162] S1051: Determine address information and loop information based on the multiple loop instructions to be rebuilt, wherein the address information is used to indicate the storage address of data for executing each loop instruction to be rebuilt, and the loop information is used to indicate the number of loop layers of the multiple loop instructions to be rebuilt and / or the number of loops of each loop instruction to be rebuilt.

[0163] In an embodiment of the present disclosure, the loop information includes: first loop information and / or second loop information, and the address information includes: a data starting address and an address stepping information, wherein the first loop information is used to indicate the number of loop layers of the multiple loop instructions to be reconstructed, and the second loop information is used to indicate the number of loops of each loop instruction to be reconstructed; the data starting address is used to indicate the storage address of the starting data for executing the first target instruction, and the address stepping information is used to indicate the address change information of the storage address of the data of each loop instruction to be reconstructed during each execution.

[0164] Specifically, the data start address can be represented as addr, the address step information can be represented as step, the first loop information can be represented as dim, and the second loop information can be represented as the number of loops of each layer of the loop instructions. For example, if the multiple loop instructions to be rebuilt are wdim0 and wdim1 in the above four layers of nested loop instructions, then the second loop information can be represented as: kernel_h and kernel_w, where kernel_h represents the number of loops of the outer loop wdim0, and kernel_w represents the number of loops of the inner loop wdim1 during each execution of the outer loop wdim0.

[0165] S1052: Create the first target instruction based on the address information and the loop information.

[0166] Here, the instruction content of the first target instruction may be determined based on the address information and loop information, wherein the instruction content of the first target instruction includes at least one instruction for indicating the address information and loop information.

[0167] Here, taking the above-mentioned tmacc (the instruction content of the first target instruction) as an example, the instruction content of the first target instruction may include the statement "addr, dim=n, size=a1,a1,...an, step", therefore, the first target instruction can be expressed as tmacc(addr, dim=n, size=a1,a1,...an, step), wherein the instructions addr and step are used to indicate the above-mentioned address information, and the instructions dim=n and size=a1,a1,...an are used to indicate the above-mentioned loop information.

[0168] If the target loop instruction is a 4-layer nested loop instruction (fdim0, fdim1, wdim0, wdim1), and the multiple loop instructions to be rebuilt are wdim0 and wdim1, then the first target instruction can be expressed as:

[0169] tmacc(addr,dim=2,size=kernel_hxkernel_w,step).

[0170] Specifically, addr in tmacc is used to indicate the storage address of the starting data for executing the first target instruction, and step is used to indicate the address change information of the storage address of the data of each loop instruction to be rebuilt during each execution. dim can be used to indicate the number of loop layers of the multiple loop instructions to be rebuilt, and size can be used to indicate the number of loops of each loop instruction to be rebuilt.

[0171] In the above implementation, reconstructing multiple loop instructions to be reconstructed into the first target instruction in the manner described above can reduce the instruction dimension of the target loop instruction and reduce the number of control instructions in the target loop instruction, thereby increasing the proportion of computing instructions in the target loop instruction to the instruction cycle and improving the processor's execution efficiency of the program.

[0172] In an optional embodiment, if Figure 4 As shown, the above step S107 modifies the instructions in the target loop instruction associated with the multiple loop instructions to be rebuilt based on the first target instruction to obtain the second target instruction, which specifically includes the following steps:

[0173] S1071: Determine a target loop body of a first loop instruction in the target loop instructions; the first loop instruction is a loop instruction of a layer above the loop instruction with the highest layer among the multiple loop instructions to be reconstructed.

[0174] S1072: Modify the target loop body in the target loop instruction based on the first target instruction, and obtain the second target instruction after modification.

[0175] In the embodiment of the present disclosure, since the loop instructions in the target loop instruction are nested in multiple layers, the loop instructions to be rebuilt in the target loop instruction are also nested in multiple layers.

[0176] Here, first, the highest-level loop instruction among the multiple loop instructions to be reconstructed can be determined, and then the upper-level loop instruction of the highest-level loop instruction can be determined, and the upper-level loop instruction can be determined as the first loop instruction.

[0177] In the embodiment of the present disclosure, the target loop body of the first loop instruction includes loop instructions of other levels (eg, the loop instruction to be rebuilt) nested inside the first loop instruction.

[0178] Here, it is assumed that the target loop instruction is the above-mentioned 4-layer nested loop instruction (fdim0, fdim1, wdim0, wdim1), wherein the target loop instruction includes the following content:

[0179]

[0180]

[0181] Among them, the for loop instruction (denoted as for4) in the 7th line of the program is the above-mentioned loop instruction wdim1, the for loop instruction (denoted as for3) in the 5th line of the program is the above-mentioned loop instruction wdim0, the for loop instruction (denoted as for2) in the 3rd line of the program is the above-mentioned loop instruction fdim1, and the for loop instruction (denoted as for1) in the 1st line of the program is the above-mentioned loop instruction fdim0.

[0182] Assuming that the multiple loop instructions to be reconstructed are the loop instruction wdim0 and the loop instruction wdim1, the first loop instruction may be the loop instruction fdim1, and the target loop body of the first loop instruction may be the content corresponding to the 4th to 8th lines, that is, the following content:

[0183]

[0184] After determining the target loop body, the target loop body in the target loop instruction can be modified based on the first target instruction to obtain the second target instruction. Here, taking the first target instruction tmacc(addr, dim=2, size=kernel_hxkernel_w, step) as an example, the instructions associated with the target loop body in the target loop instruction can be replaced with the first target instruction to obtain the second target instruction. For example, the instructions corresponding to lines 4-8 above can be replaced with the first target instruction tmacc(addr, dim=2, size=kernel_hxkernel_w, step) to obtain the following second target instruction.

[0185]

[0186]

[0187] In the above implementation, the instruction dimension of the target loop instruction can be reduced, and the number of control instructions in the target loop instruction can be reduced, thereby increasing the proportion of calculation instructions in the target loop instruction to the instruction cycle and improving the execution efficiency of the processor on the program.

[0188] In summary, in the disclosed embodiment, the target loop instruction can be first obtained, and multiple loop instructions to be reconstructed in the target loop instruction can be determined based on the instruction creation parameters of the target loop instruction; next, a first target instruction can be created based on the multiple loop instructions to be reconstructed, and the instructions associated with the multiple loop instructions to be reconstructed in the target loop instruction can be modified based on the first target instruction to obtain a second target instruction. In the above implementation, by reconstructing multiple loop instructions to be reconstructed into the first target instruction, the instruction dimension of the target loop instruction can be reduced, and the number of control instructions in the target loop instruction can be reduced, thereby increasing the proportion of computational instructions in the target loop instruction for the instruction cycle, and improving the processor's execution efficiency of the program.

[0189] Those skilled in the art will appreciate that, in the above method of specific implementation, the order in which the steps are written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of the steps should be determined by their functions and possible internal logic.

[0190] Based on the same inventive concept, an instruction processing device corresponding to the instruction processing method is also provided in the embodiment of the present disclosure. Since the principle of solving the problem by the device in the embodiment of the present disclosure is similar to the above-mentioned instruction processing method in the embodiment of the present disclosure, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be repeated.

[0191] Reference Figure 5 FIG. 1 is a schematic diagram of an instruction processing device provided by an embodiment of the present disclosure, wherein the device comprises: an acquisition unit 51, a determination unit 52, a creation unit 53, and a modification unit 54; wherein:

[0192] An acquisition unit 51 is used to acquire a target loop instruction; the target loop instruction includes multiple layers of nested loop instructions;

[0193] A determining unit 52 is configured to determine a plurality of loop instructions to be reconstructed in the target loop instruction based on an instruction creation parameter of the target loop instruction; wherein the instruction creation parameter includes an instruction requirement feature under at least one dimension;

[0194] A creating unit 53, configured to create a first target instruction based on the plurality of loop instructions to be reconstructed; the first target instruction is used to describe a loop calculation process of the plurality of loop instructions to be reconstructed;

[0195] The modifying unit 54 is configured to modify the instructions in the target loop instruction that are associated with the plurality of loop instructions to be reconstructed based on the first target instruction to obtain a second target instruction.

[0196] In the disclosed embodiment, first, a target loop instruction in a program can be obtained, and based on the instruction creation parameters of the target loop instruction, multiple loop instructions to be reconstructed in the target loop instruction can be determined. Next, a first target instruction can be created based on the multiple loop instructions to be reconstructed, and based on the first target instruction, instructions associated with the multiple loop instructions to be reconstructed in the target loop instruction can be modified to obtain a second target instruction, thereby simplifying the instructions associated with the multiple loop instructions to be reconstructed and reducing the number of loop instructions that are non-computational instructions, which is equivalent to increasing the proportion of core computing instructions in the program, thereby improving the processor's execution efficiency of the program.

[0197] In a possible implementation manner, the modification unit 54 is further configured to:

[0198] Determining a target loop body of a first loop instruction in the target loop instruction; the first loop instruction is a loop instruction of a layer above the loop instruction with the highest level among the plurality of loop instructions to be reconstructed;

[0199] A target loop body in the target loop instruction is modified based on the first target instruction, and the second target instruction is obtained after the modification.

[0200] In a possible implementation manner, the instruction creation parameter is an instruction indication identifier, and the determination unit 52 is further configured to:

[0201] Obtaining instruction contents of each layer of loop instructions in the target loop instruction;

[0202] Determine, based on the instruction content, a plurality of loop instructions carrying the instruction indication identifier in the loop instructions of each layer;

[0203] Loop instructions that meet the creation requirement among the multiple loop instructions are determined as the multiple loop instructions to be rebuilt.

[0204] In a possible implementation manner, the instruction creation parameter is an instruction requirement parameter, and the determination unit 52 is further configured to:

[0205] Obtaining instruction requirement parameters; wherein the instruction requirement parameters include at least one of the following: instruction complexity, instruction execution efficiency, and instruction execution repeatability;

[0206] The plurality of loop instructions to be reconstructed are determined based on a plurality of second loop instructions in the target loop instructions that match the instruction requirement parameter.

[0207] In a possible implementation manner, the instruction creation parameter is an instruction requirement parameter, and the determination unit 52 is further configured to:

[0208] Determining instruction dimension information based on the instruction requirement parameter; wherein the instruction dimension information is used to indicate the number of loop layers of the loop instruction to be reconstructed in the target loop instruction;

[0209] The plurality of loop instructions to be reconstructed are determined based on a plurality of second loop instructions in the target loop instruction that match the instruction dimension information.

[0210] In a possible implementation manner, the device is further used to: obtain a preset first calculation type, and obtain a second calculation type of each second loop instruction;

[0211] The determination unit 52 is further used to: determine a plurality of third loop instructions matching the first calculation type among the plurality of second loop instructions based on the second calculation type, and determine the plurality of loop instructions to be reconstructed based on the plurality of third loop instructions, wherein the plurality of third loop instructions are loop instructions of adjacent levels among the plurality of second loop instructions.

[0212] In a possible implementation manner, the creating unit 53 is further configured to:

[0213] Determine address information and loop information based on the multiple loop instructions to be rebuilt, wherein the address information is used to indicate a storage address of data for executing each loop instruction to be rebuilt, and the loop information is used to indicate the number of loop layers of the multiple loop instructions to be rebuilt and / or the number of loops of each loop instruction to be rebuilt;

[0214] The first target instruction is created based on the address information and the loop information.

[0215] In a possible implementation, the loop information includes: first loop information and / or second loop information, and the address information includes: a data starting address and address stepping information, wherein the first loop information is used to indicate the number of loop layers of the multiple loop instructions to be reconstructed, and the second loop information is used to indicate the number of loops of each loop instruction to be reconstructed; the data starting address is used to indicate the storage address of the starting data for executing the first target instruction, and the address stepping information is used to indicate the address change information of the storage address of the data of each loop instruction to be reconstructed during each execution.

[0216] For descriptions of the processing flow of each unit in the device and the interaction flow between each unit, reference may be made to the relevant descriptions in the above method embodiments, which will not be described in detail here.

[0217] Corresponds to Figure 1 The instruction processing method in the present disclosure also provides a chip 600, such as Figure 6 FIG. 6 is a schematic diagram of the structure of a chip 600 provided in an embodiment of the present disclosure, including:

[0218] Processor 61, memory 62, and bus 63; memory 62 is used to store execution instructions, the processor 61 and the memory 62 communicate through bus 63, so that the processor 61 executes the following instructions:

[0219] Obtaining a target loop instruction; wherein the target loop instruction includes multiple layers of nested loop instructions;

[0220] Based on the instruction creation parameters of the target cycle instruction, determining a plurality of cycle instructions to be rebuilt in the target cycle instruction; wherein the instruction creation parameters include instruction requirement characteristics under at least one dimension;

[0221] Creating a first target instruction based on the plurality of loop instructions to be rebuilt; the first target instruction is used to describe the loop calculation process of the plurality of loop instructions to be rebuilt;

[0222] The instructions in the target loop instruction associated with the plurality of loop instructions to be rebuilt are modified based on the first target instruction to obtain a second target instruction.

[0223] The present disclosure also provides a board, which includes a packaging structure encapsulating at least one of the above chips. Figure 7 , which provides an exemplary board card, the board card includes the chip 600 and may also include other components, including but not limited to: a storage device 702 and an interface device 704.

[0224] The memory device is connected to the chip in the chip package structure via a bus for storing data. The memory device may include multiple groups of memory cells 706, such as DDR SDRAM (Double Data Rate SDRAM), etc. Each group of memory cells is connected to the chip via a bus.

[0225] The interface device is electrically connected to the chip in the chip packaging structure. The interface device is used to realize data transmission between the chip and an external device 708 (e.g., a terminal, a server, a camera, etc.). In one embodiment, the interface device may include a PCIE interface, or a network interface, or other interface, which is not limited by the present disclosure.

[0226] The embodiment of the present disclosure further provides a computer device, including the chip 600 as described above or the board as described above.

[0227] The present disclosure also provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the steps of the instruction processing method described in the above method embodiment are executed. The storage medium may be a volatile or non-volatile computer-readable storage medium.

[0228] The embodiments of the present disclosure also provide a computer program product, which carries a program code. The instructions included in the program code can be used to execute the steps of the instruction processing method described in the above method embodiment. For details, please refer to the above method embodiment, which will not be repeated here.

[0229] The computer program product may be implemented in hardware, software or a combination thereof. In one optional embodiment, the computer program product is implemented as a computer storage medium. In another optional embodiment, the computer program product is implemented as a software product, such as a software development kit (SDK).

[0230] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, the specific working process of the system and device described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here. In the several embodiments provided in the present disclosure, it should be understood that the disclosed system, device and method can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of the device or unit can be electrical, mechanical or other forms.

[0231] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0232] In addition, each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0233] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present disclosure, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present disclosure. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0234] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present disclosure, which are used to illustrate the technical solutions of the present disclosure, rather than to limit them. The protection scope of the present disclosure is not limited thereto. Although the present disclosure is described in detail with reference to the above-described embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-described embodiments within the technical scope disclosed in the present disclosure, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure, and should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A command processing method, characterized in that: Applicable to processors, including: Obtaining a target loop instruction; wherein the target loop instruction includes multiple layers of nested loop instructions; Based on the instruction creation parameters of the target cycle instruction, determining a plurality of cycle instructions to be rebuilt in the target cycle instruction; wherein the instruction creation parameters include instruction requirement characteristics under at least one dimension; Determine address information and loop information based on the multiple loop instructions to be rebuilt, wherein the address information is used to indicate a storage address of data for executing each loop instruction to be rebuilt, and the loop information is used to indicate the number of loop layers of the multiple loop instructions to be rebuilt and / or the number of loops of each loop instruction to be rebuilt; Creating a first target instruction based on the address information and the loop information; the first target instruction is used to describe the loop calculation process of the plurality of loop instructions to be rebuilt; Determining a target loop body of a first loop instruction in the target loop instruction; the first loop instruction is a loop instruction of a layer above the loop instruction with the highest level among the plurality of loop instructions to be reconstructed; A target loop body in the target loop instruction is modified based on the first target instruction to obtain a second target instruction after the modification.

2. The method according to claim 1, characterized in that The instruction creation parameter is an instruction indication identifier; the instruction creation parameter based on the target loop instruction determines a plurality of loop instructions to be rebuilt in the target loop instruction, including: Obtaining instruction contents of each layer of loop instructions in the target loop instruction; Determine, based on the instruction content, a plurality of loop instructions carrying the instruction indication identifier in the loop instructions of each layer; Loop instructions that meet the creation requirement among the multiple loop instructions are determined as the multiple loop instructions to be rebuilt.

3. The method according to claim 1, characterized in that: The instruction creation parameter is an instruction requirement parameter; the instruction creation parameter based on the target cycle instruction determines a plurality of cycle instructions to be rebuilt in the target cycle instruction, including: Obtaining instruction requirement parameters; wherein the instruction requirement parameters include at least one of the following: instruction complexity, instruction execution efficiency, and instruction execution repeatability; The plurality of loop instructions to be reconstructed are determined based on a plurality of second loop instructions in the target loop instructions that match the instruction requirement parameter.

4. The method according to claim 3, characterized in that The determining the plurality of loop instructions to be reconstructed based on the plurality of second loop instructions in the target loop instruction that match the instruction requirement parameter comprises: Determining instruction dimension information based on the instruction requirement parameter; wherein the instruction dimension information is used to indicate the number of loop layers of the loop instruction to be reconstructed in the target loop instruction; The plurality of loop instructions to be reconstructed are determined based on a plurality of second loop instructions in the target loop instruction that match the instruction dimension information.

5. The method according to claim 3 or 4, characterized in that: The method further comprises: obtaining a preset first calculation type, and obtaining a second calculation type of each second loop instruction; The determining of the multiple loop instructions to be reconstructed based on the multiple second loop instructions in the target loop instruction that match the instruction requirement parameter includes: based on the second calculation type, determining a third loop instruction matching the first calculation type in the multiple second loop instructions, and determining the multiple loop instructions to be reconstructed based on the third loop instruction.

6. The method according to claim 1, characterized in that The loop information includes: first loop information and / or second loop information, and the address information includes: a data starting address and address stepping information, wherein the first loop information is used to indicate the number of loop layers of the multiple loop instructions to be rebuilt, and the second loop information is used to indicate the number of loops of each loop instruction to be rebuilt; the data starting address is used to indicate the storage address of the starting data for executing the first target instruction, and the address stepping information is used to indicate the address change information of the storage address of the data of each loop instruction to be rebuilt during each execution.

7. An instruction processing device, characterized in that: include: An acquisition unit, used for acquiring a target cycle instruction; The target loop instruction includes multiple layers of nested loop instructions; A determination unit, configured to determine a plurality of to-be-reconstructed loop instructions in the target loop instruction based on an instruction creation parameter of the target loop instruction; wherein the instruction creation parameter includes an instruction requirement feature under at least one dimension; A creating unit, configured to determine address information and loop information based on the plurality of loop instructions to be rebuilt, wherein the address information is used to indicate a storage address of data for executing each loop instruction to be rebuilt, and the loop information is used to indicate the number of loop layers of the plurality of loop instructions to be rebuilt and / or the number of loops of each loop instruction to be rebuilt; and to create a first target instruction based on the address information and the loop information; the first target instruction is used to describe a loop calculation process of the plurality of loop instructions to be rebuilt; A modification unit is used to determine a target loop body of a first loop instruction in the target loop instruction; the first loop instruction is a loop instruction on a layer above the loop instruction with the highest level among the multiple loop instructions to be reconstructed; based on the first target instruction, the target loop body in the target loop instruction is modified to obtain a second target instruction after the modification.

8. A chip, characterized in that: include: A processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, the processor and the memory communicate via a bus, and when the machine-readable instructions are executed by the processor, the steps of the instruction processing method according to any one of claims 1 to 6 are performed.

9. A board, characterized in that: include: A packaging structure encapsulating at least one chip as claimed in claim 8.

10. A computer device, characterized in that: Comprising the chip as claimed in claim 8, or the board as claimed in claim 9.

11. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the instruction processing method according to any one of claims 1 to 6 are executed.

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