Method, apparatus, computer device, and storage medium for reading flash memory data

Abstract

The present application relates to a method, apparatus, computer device, storage medium, and computer program product for reading flash memory data. The method includes: a central processing unit reads instruction data from a first sector of a target flash memory; if the instruction data indicates to read target data from a second sector of the target flash memory, a first control signal and a first address signal are sent to a flash memory reading controller; the flash memory reading controller determines the category of the target data and determines the flash memory address of the target data; in the case where the flash memory reading controller determines that the category of the target data is non-instruction data and the flash memory address of the target data is within a preset encrypted address range, the flash memory reading controller obtains the flash memory address corresponding to the instruction data; in the case where the flash memory reading controller determines that the flash memory address corresponding to the instruction data is not within the preset encrypted address range, the flash memory reading controller returns a read failure response message to the central processing unit. The security of reading flash memory data is improved.

Description

Technical Field

[0001] The present application relates to the technical field of chip circuit design, and particularly to a method, apparatus, computer device, and storage medium for reading flash memory data. Background Art

[0002] With the development of information security technology, a method for reading flash memory data has emerged. This technology can prohibit external access to flash memory data, thereby improving the security of flash memory data reading.

[0003] The traditional method for reading flash memory data is to preset a prohibition of debugging functions and a prohibition of reading flash memory data through a preset static random access memory, thereby prohibiting external access to flash memory data.

[0004] However, the current method for reading flash memory data only prohibits external access to flash memory data, and allows data reading between different sectors inside the flash memory. If the data in sector A of the flash memory needs to be kept confidential, but there is a program in sector B of the flash memory that can read the data in sector A, then the central processing unit can read the data in sector A when executing this program. Therefore, the security of flash memory data is relatively low. Summary of the Invention

[0005] Based on this, in view of the above technical problems, it is necessary to provide a method, apparatus, computer device, computer-readable storage medium, and computer program product for reading flash memory data that can improve the security of flash memory data by prohibiting cross-sector reading of flash memory data.

[0006] In a first aspect, the present application provides a method for reading flash memory data. The method includes:

[0007] The central processing unit reads instruction data from the first sector of the target flash memory; when the instruction data indicates reading target data in the second sector of the target flash memory, a first control signal and a first address signal are sent to the flash memory reading controller through the bus controller;

[0008] The flash memory reading controller determines the category of the target data according to the first control signal, and determines the flash memory address of the target data according to the first address signal;

[0009] When the flash memory reading controller determines that the category of the target data is non-instruction data and the flash memory address of the target data is within a preset encrypted address range, the flash memory reading controller obtains the flash memory address corresponding to the instruction data;

[0010] In the case that the flash memory read controller determines that the flash memory address corresponding to the instruction data is not within the preset encrypted address range, the flash memory read controller returns a read failure response message to the central processing unit.

[0011] In one embodiment, after the central processing unit reads instruction data from the first sector of the target flash memory, it further includes:

[0012] The central processing unit sends a second control signal and a second address signal to the instruction address register;

[0013] The instruction address register determines that the category of the flash memory data corresponding to the second control signal is the instruction data according to the second control signal;

[0014] The instruction address register determines the flash memory address corresponding to the instruction data according to the second address signal, and stores the flash memory address corresponding to the instruction data in the instruction address register.

[0015] In one embodiment, the method further includes:

[0016] The central processing unit generates a bus write according to the preset encrypted address range, and sends the bus write to the encryption control register;

[0017] The encryption control register determines the encrypted address range of the target flash memory according to the bus write;

[0018] The encryption control register generates and sends a start encrypted address configuration signal and an end encrypted address configuration signal to the flash memory read controller according to the encrypted address range of the target flash memory;

[0019] The flash memory read controller configures the encrypted address range of the target flash memory according to the start encrypted address configuration signal and the end encrypted address configuration signal.

[0020] In one embodiment, the method further includes:

[0021] The instruction address register determines a stored address signal according to the currently stored address, and sends the stored address signal to the flash memory read controller;

[0022] The flash memory read controller determines the flash memory address corresponding to the instruction data according to the stored address signal.

[0023] In one embodiment, the method further includes:

[0024] When the flash memory read controller determines that the category of the target data is instruction data, the flash memory read controller returns the target data to the central processing unit.

[0025] In one embodiment, the method further includes:

[0026] When the flash memory read controller determines that the category of the target data is non-instruction data and the flash memory address of the target data is not within the preset encrypted address range, the flash memory read controller returns the target data to the central processing unit.

[0027] In one embodiment, the method further includes:

[0028] When the flash memory read controller determines that the flash memory address corresponding to the instruction data is within the preset encrypted address range, the flash memory read controller returns the target data to the central processing unit.

[0029] In one embodiment, the flash memory read controller returning the target data to the central processing unit includes:

[0030] The flash memory read controller sends a bus read to the target flash memory;

[0031] The target flash memory determines the target data according to the bus read and returns the target data to the flash memory read controller;

[0032] The flash memory read controller returns the target data to the central processing unit.

[0033] In a second aspect, the present application further provides a flash memory data reading system. The flash memory data reading system includes a central processing unit, a bus controller, a flash memory read controller, and a target flash memory; the flash memory read controller is respectively connected to the central processing unit and the target flash memory through a bus; the bus controller is connected to the flash memory read controller through a branch line; wherein:

[0034] The central processing unit is configured to read instruction data from the first sector of the target flash memory;

[0035] The bus controller is configured to, when the instruction data indicates to read target data in the second sector of the target flash memory, the central processing unit sends a first control signal and a first address signal to the flash memory read controller through the bus controller;

[0036] The flash memory read controller is configured to determine the category of the target data according to the first control signal and determine the flash memory address of the target data according to the first address signal;

[0037] The flash memory read controller is further configured to, when determining that the category of the target data is non-instruction data and the flash memory address of the target data is within a preset encrypted address range, obtain the flash memory address corresponding to the instruction data;

[0038] The flash memory read controller is further configured to, when determining that the flash memory address corresponding to the instruction data is not within the preset encrypted address range, return a read failure response message to the central processing unit.

[0039] In one embodiment, the system further includes an instruction address register, where:

[0040] The central processing unit is configured to send a second control signal and a second address signal to the instruction address register;

[0041] The instruction address register is configured to determine, according to the second control signal, that the category of the flash memory data corresponding to the second control signal is the instruction data;

[0042] The instruction address register is further configured to determine, according to the second address signal, the flash memory address corresponding to the instruction data, and store the flash memory address corresponding to the instruction data in the instruction address register.

[0043] In one embodiment, the system further includes an encryption control register, where:

[0044] The central processing unit is configured to generate a bus write according to the preset encrypted address range, and send the bus write to the encryption control register;

[0045] The encryption control register is configured to determine the encrypted address range of the target flash memory according to the bus write;

[0046] The encryption control register is further configured to generate and send a start encrypted address configuration signal and an end encrypted address configuration signal to the flash memory read controller according to the encrypted address range of the target flash memory;

[0047] The flash memory read controller is configured to configure the encrypted address range of the target flash memory according to the start encrypted address configuration signal and the end encrypted address configuration signal.

[0048] In one embodiment, the system further includes an instruction address register, where:

[0049] The instruction address register is configured to determine a stored address signal according to the currently stored address, and send the stored address signal to the flash memory read controller;

[0050] The flash memory read controller is used to determine the flash memory address corresponding to the instruction data according to the register address signal.

[0051] In one embodiment, the flash memory read controller is further used to:

[0052] When the flash memory read controller determines that the category of the target data is instruction data, return the target data to the central processing unit.

[0053] In one embodiment, the flash memory read controller is further used to:

[0054] When the flash memory read controller determines that the category of the target data is non-instruction data and the flash memory address of the target data is not within the preset encrypted address range, return the target data to the central processing unit.

[0055] In one embodiment, the flash memory read controller is further used to:

[0056] When the flash memory read controller determines that the flash memory address corresponding to the instruction data is within the preset encrypted address range, return the target data to the central processing unit.

[0057] In one embodiment, the system further includes:

[0058] The flash memory read controller is used to send a bus read to the target flash memory;

[0059] The target flash memory is used to determine the target data according to the bus read and return the target data to the flash memory read controller;

[0060] The flash memory read controller is further used to return the target data to the central processing unit.

[0061] In a third aspect, the present application further provides a computer device. The computer device includes a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, the steps described in the first aspect are implemented.

[0062] In a fourth aspect, the present application further provides a computer-readable storage medium. The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps described in the first aspect are implemented.

[0063] In a fifth aspect, the present application further provides a computer program product. The computer program product includes a computer program, and when the computer program is executed by a processor, the steps described in the first aspect are implemented.

[0064] The above-mentioned method, apparatus, computer device, storage medium, and computer program product for reading flash memory data read instruction data from the first sector of the target flash memory through the central processing unit; when the instruction data indicates to read target data from the second sector of the target flash memory, a first control signal and a first address signal are sent to the flash memory reading controller through the bus controller; the flash memory reading controller determines the category of the target data according to the first control signal and determines the flash memory address of the target data according to the first address signal; when the flash memory reading controller determines that the category of the target data is non-instruction data and the flash memory address of the target data is within a preset encrypted address range, the flash memory reading controller obtains the flash memory address corresponding to the instruction data; when the flash memory reading controller determines that the flash memory address corresponding to the instruction data is not within the preset encrypted address range, the flash memory reading controller returns a read failure response message to the central processing unit. That is to say, if the data in sector A of the flash memory needs to be kept confidential and there is a program in sector B of the flash memory that can read the data in sector A, then this technical solution can encrypt the address of sector A without encrypting sector B. When the central processing unit reads the program in sector B, the flash memory reading controller will return a read failure response message to the central processing unit, thereby prohibiting the central processing unit from reading the flash memory data and improving the security of the flash memory data. Brief Description of the Drawings

[0065] Figure 1 It is an application environment diagram of the method for reading flash memory data in an embodiment;

[0066] Figure 2 It is a schematic flowchart of the method for reading flash memory data in an embodiment;

[0067] Figure 3 It is an application environment diagram of the method for reading flash memory data in another embodiment;

[0068] Figure 4 It is a schematic flowchart of the method for configuring the encrypted address range in another embodiment;

[0069] Figure 5 It is an internal structure diagram of a computer device in an embodiment. Detailed Embodiments

[0070] In order to make the objectives, technical solutions, and advantages of the present application clearer and more understandable, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0071] The flash memory data reading method provided by the embodiments of the present application can be applied to a terminal, a server, or a system including a terminal and a server, and is implemented through the interaction between the terminal and the server. This embodiment takes the application of this method to a flash memory data reading system as an example for illustration. For example, Figure 1 As shown, the flash memory data reading system includes a central processing unit (CPU) 102, a bus controller 104, a flash memory reading controller 106, and a target flash memory (Flash EEPROM Memory, FLASH) 108. The central processing unit 102 is connected to the bus controller 104 and the flash memory reading controller 106 through the bus respectively. The bus controller 104 is connected to the flash memory reading controller 106 through branch lines. The flash memory reading controller 106 is connected to the target flash memory 108 through the bus. Among them, the bus includes an address bus, a control bus, and a read signal bus. The branch lines include address branch lines, control branch lines, and read signal branch lines.

[0072] The central processing unit 102 reads instruction data from the first sector of the target flash memory 108 through the bus. When the instruction data indicates to read the target data in the second sector of the target flash memory 108, it sends a first bus read to the bus controller 104 through the bus. Then, the bus controller 104 analyzes and obtains the address of the target data, the category of the target data, and the operation category according to the first bus read, and the operation category is read. The bus controller 104 generates a first address signal according to the address of the target data, generates a first control signal according to the category of the target data, and generates a first read signal according to the read operation of the central processing unit. The bus controller 104 sends the first address signal to the flash memory reading controller 106 through the address line, sends the first control signal to the flash memory reading controller 106 through the first control line, and sends the first read signal to the flash memory reading controller 106 through the second control line. The flash memory reading controller 106 analyzes the first address signal to obtain the address of the target data, and analyzes the first control signal to obtain the category of the target data. The flash memory reading control 106 identifies the category of the target data and determines whether the category of the target data is non-instruction data. When the category of the target data is non-instruction data, the flash memory reading controller 106 identifies the address of the target data and determines whether the address of the target data is within a preset encrypted address. When the address of the target data is within the preset encrypted address, the flash memory reading controller 106 identifies the flash memory address corresponding to the instruction data and determines whether the flash memory address corresponding to the instruction data is within the preset encrypted address. When the flash memory address corresponding to the instruction data is not within the preset encrypted address, the flash memory reading controller 106 returns a read failure response message to the central processing unit 102 through the bus. Optionally, the read failure response message can be a preset value, such as 0, etc., or randomly generated data.

[0073] In one embodiment, as Figure 2 shown, a method for reading flash memory data is provided. Taking the flash memory data reading system in Figure 1 as an example for illustration, the method includes the following steps:

[0074] Step 202, the central processing unit reads instruction data from the first sector of the target flash memory; when the instruction data indicates to read the target data in the second sector of the target flash memory, a first control signal and a first address signal are sent to the flash memory reading controller through the bus controller.

[0075] Among them, the flash memory data is the data stored in the target flash memory 108. The categories of the flash memory data include instruction data and non-instruction data. The target data is the flash memory data that the instruction data indicates the central processing unit to read.

[0076] In the embodiment of the present application, the central processing unit 102 reads instruction data from the first sector of the target flash memory 108 and parses the read instruction data. When the central processing unit 102 parses the instruction data and obtains that the content indicated by the instruction data is the memory data to be read. Among them, the memory data is the data stored in the memory. Optionally, the memory can be the target flash memory 108 or a static random access memory (Static Random-Access Memory, SRAM). When the central processing unit 102 recognizes that the read memory data contains the target data in the second sector of the target flash memory 108, the central processing unit 102 sends a first bus read to the bus controller 104. The bus controller 104 parses the first bus read and filters out the information related to the target data. The bus controller 104 generates a first control signal and a first address signal based on the information related to the target data, and sends the first control signal and the first address signal to the flash memory reading controller 106. Among them, the first bus read includes a first control bus signal, a first address bus signal, and a first read bus signal. The information related to the target data includes the category of the target data, the flash memory address of the target data, and the operation category of the target data.

[0077] Specifically, the central processing unit 102 generates a first address bus signal according to the memory address of the memory data, generates a first control bus signal according to the data category of the memory data, and generates a first read bus signal according to the operation on the memory data being a read operation. The central processing unit 102 sends the first address bus signal, the first control bus signal, and the first read bus signal to the bus controller 104. The bus controller 104 analyzes the first address bus signal to obtain the memory address corresponding to the memory data. The bus controller 104 screens the memory address corresponding to the memory data according to the preset address range of the target flash memory to obtain the flash memory address corresponding to the target data. The bus controller 104 analyzes the first control bus signal to obtain the data category corresponding to the memory data. The bus controller 104 screens the memory data according to the flash memory address corresponding to the target data to obtain the target data, and further obtains the data category corresponding to the target data; analyzes the first read bus signal to obtain that the operation category on the memory data is a read operation, and further obtains that the operation category on the target data is also a read operation. The bus controller 104 generates a first address signal corresponding to the flash memory address corresponding to the target data, a first control signal corresponding to the data category corresponding to the target data, and a first read signal corresponding to the read operation respectively according to the flash memory address corresponding to the target data, the data category corresponding to the target data, and the read operation. The bus controller 104 sends the first address signal, the first control signal, and the first read signal to the flash memory reading controller 106.

[0078] Step 204, the flash memory reading controller determines the category of the target data according to the first control signal and determines the flash memory address of the target data according to the first address signal.

[0079] Among them, the category of the target data includes non-instruction data and instruction data.

[0080] In the embodiment of the present application, the flash memory reading controller 106 analyzes the first control signal to obtain the data category corresponding to the target data, analyzes the first address signal to obtain the flash memory address corresponding to the target data, and analyzes the first read signal to obtain that the operation category on the target data is a read operation.

[0081] Step 206, when the flash memory reading controller determines that the category of the target data is non-instruction data and the flash memory address of the target data is within the preset encrypted address range, the flash memory reading controller obtains the flash memory address corresponding to the instruction data.

[0082] In an embodiment of the present application, when the flash memory read controller 106 identifies that the category of the target data is non-instruction data, the flash memory read controller 106 determines whether the flash address of the target data is within the range of the preset encrypted address according to the preset range of the encrypted address. When the flash memory read controller 106 identifies that the flash address of the target data is within the range of the preset encrypted address, the flash memory read controller parses the registered address signal to obtain the flash address corresponding to the instruction data. The flash memory read controller 106 determines whether the flash address corresponding to the instruction data is within the range of the preset encrypted address according to the flash address corresponding to the instruction data. Among them, the registered address signal is generated by the instruction address register according to the currently registered address and sent to the flash memory read controller 106.

[0083] Step 208, when the flash memory read controller determines that the flash address corresponding to the instruction data is not within the range of the preset encrypted address, the flash memory read controller returns a read failure response message to the central processing unit.

[0084] In an embodiment of the present application, when the flash memory read controller 106 identifies that the flash address corresponding to the instruction data is not within the range of the preset encrypted address, the flash memory read controller 106 returns a read failure response message to the central processing unit. Among them, the read failure response message can be a preset value or data randomly generated by the flash memory read controller 106.

[0085] In the above method for reading flash data, the bus controller 104 filters out the information related to the target data and sends the target data information to the flash memory read controller 106. The flash memory read controller 106 sequentially identifies the category of the target data, the flash address of the target data, and the flash address corresponding to the instruction data. When it is determined that the category of the target data is non-instruction data, the flash address of the target data is within the range of the preset encrypted address, and the flash address corresponding to the instruction data is not within the range of the preset encrypted address, the flash memory read controller 106 returns a read failure response message to the central processing unit 102. It can be understood that returning the read failure response message is equivalent to the central processing unit 102 being unable to read the real data, which is equivalent to a read failure, that is, equivalent to the flash memory read controller 106 prohibiting the central processing unit 102 from reading the non-instruction data in the target flash memory 108. Then, when the data in sector A of the flash memory needs to be kept confidential and there is a program in sector B of the flash memory that can read the data in sector A, the technical solution can encrypt the address of sector A without encrypting sector B. Then, when the central processing unit 102 reads the program in sector B, the flash memory read controller 106 will return a read failure response message to the central processing unit 102, which is equivalent to prohibiting the central processing unit 102 from reading the flash data, thereby improving the security of the flash data.

[0086] In one embodiment, after the central processing unit reads instruction data from the first sector of the target flash memory, the following steps are further included:

[0087] The central processing unit sends a second control signal and a second address signal to the instruction address register; the instruction address register determines, according to the second control signal, that the category of the flash memory data corresponding to the second control signal is instruction data; the instruction address register determines, according to the second address signal, the flash memory address corresponding to the instruction data, and stores the flash memory address corresponding to the instruction data in the instruction address register.

[0088] This embodiment can also be applied to a Figure 3 flash memory data reading system as shown in the figure. The flash memory data reading system includes a central processing unit 102, a bus controller 104, a flash memory reading controller 106, a target flash memory 108, an instruction address register 302, and an encryption control register 304. The central processing unit 102 is respectively connected to the bus controller 104, the flash memory reading controller 106, and the encryption control register 304 through a bus. The bus controller 104 is respectively connected to the flash memory reading controller 106 and the instruction address register 302 through branch lines. The flash memory reading controller 106 is connected to the target flash memory 108 through a bus. The instruction address register 302 is address-connected to the flash memory reading controller 106 through an address branch line. The encryption control register 304 is connected to the flash memory reading controller 106 through an address branch line.

[0089] In the embodiment of the present application, the central processing unit 102 identifies the instruction data to obtain the category corresponding to the instruction data, the flash address of the instruction data, and the operation category. Among them, the category corresponding to the instruction data is the instruction data, and the operation category is the read operation. The central processing unit 102 generates a second control bus signal according to the category of the instruction data, generates a second address bus signal according to the flash address of the instruction data, and generates a second read bus signal according to the read operation of the central processing unit. Among them, the second bus read includes the second control bus signal, the second address bus signal, and the second read bus signal. The central processing unit 102 sends the second bus read to the bus controller 104 through the bus, and the bus controller 104 parses the second bus read to obtain the category of the instruction data, the flash address of the instruction data, and the operation category. The bus controller 104 generates a second control signal corresponding to the category of the instruction data, a second address signal corresponding to the flash address of the instruction data, and a second read signal corresponding to the operation category respectively according to the category of the instruction data, the flash address of the instruction data, and the operation category, and sends the second control signal, the second address signal, and the second read signal to the instruction address register 302. The instruction address register 302 parses the second control signal to obtain that the category corresponding to the instruction data is the instruction data. When the instruction address register 302 identifies that the category corresponding to the instruction data is the instruction data, the instruction address register 302 parses the second address signal to obtain the flash address corresponding to the instruction data, and stores the flash address corresponding to the instruction data in the instruction address register 302. Among them, the instruction address register 302 only stores one address. It can be understood that if the instruction address register 302 has stored address 1, and now the instruction address register 302 stores address 2 in the instruction address register 302, address 1 will be overwritten by address 2. Then, the address currently stored in the instruction address register 302 is only address 2.

[0090] In this embodiment, the instruction address register 302 parses the second control signal, the second address signal, and the second read signal to obtain that the category of the flash data corresponding to the instruction data is the instruction data, the flash address corresponding to the instruction data, and the operation category is the read operation. When the instruction address register 302 determines that the category of the flash data corresponding to the instruction data is the instruction data, the instruction address register 302 stores the flash address corresponding to the instruction data in the instruction address register 302. Therefore, the update of the flash address of the instruction data in the instruction address register 302 can be realized.

[0091] In one embodiment, as Figure 4 shown, the method further includes:

[0092] Step 402, the central processing unit generates a bus write according to a preset encrypted address range and sends the bus write to the encryption control register.

[0093] In an embodiment of the present application, the central processing unit 102 generates a bus write according to a preset encrypted address range and sends the bus write to the encryption control register 304. The bus write includes a write bus signal, a start encrypted address configuration bus signal, and an end encrypted address configuration bus signal. It can be understood that if the addresses in the preset encrypted address range are consecutive addresses, then only a pair of start encrypted address configuration bus signals and end encrypted address configuration bus signals need to be sent. If the addresses in the preset encrypted address range are non-consecutive addresses, then the central processing unit 102 identifies multiple consecutive addresses in the preset encrypted address range and respectively generates corresponding start encrypted address configuration bus signals and end encrypted address configuration bus signals. For example, assume that the preset encrypted address range is sector A and sector C in the target flash memory, where the addresses of sector A and sector C are non-consecutive, and the addresses within each sector are consecutive. Then, the central processing unit 102 generates a pair of start encrypted address configuration signals 1 and end encrypted address configuration signals 1 according to the flash memory addresses in sector A; and generates a pair of start encrypted address configuration signals 2 and end encrypted address configuration signals 2 according to the flash memory addresses in sector C.

[0094] Step 404: The encryption control register determines the encrypted address range of the target flash memory according to the bus write.

[0095] In an embodiment of the present application, the encryption control register 304 parses the write bus signal to obtain that the operation type is write; parses the start encrypted address configuration bus signal to obtain the start address corresponding to the encrypted address range of the target flash memory; and parses the end encrypted address configuration bus signal to obtain the end address corresponding to the encrypted address range of the target flash memory.

[0096] Step 406: The encryption control register generates and sends a start encrypted address configuration signal and an end encrypted address configuration signal to the flash memory read controller according to the encrypted address range of the target flash memory.

[0097] In an embodiment of the present application, the encryption control register 304 generates a start encrypted address configuration signal according to the start address corresponding to the encrypted address range of the target flash memory; generates an end encrypted address configuration signal according to the end address corresponding to the encrypted address range of the target flash memory; and generates a write signal according to the operation type being write. The encryption control register 304 sends the start encrypted address configuration signal, the end encrypted address configuration signal, and the write signal to the flash memory read controller 106.

[0098] Step 408: The flash memory read controller configures the encrypted address range of the target flash memory according to the start encrypted address configuration signal and the end encrypted address configuration signal.

[0099] The flash memory read controller 106 parses the write signal to determine that the operation type is a write operation; configures the start encryption address signal to obtain the start address corresponding to the encrypted address range of the target flash memory; configures the end encryption address signal to obtain the end address corresponding to the encrypted address range of the target flash memory. The flash memory read controller 106 configures the range of the encrypted address of the target flash memory according to the start address and the end address.

[0100] In this embodiment, through the preset encrypted address, the flash memory read controller 106 configures the encrypted address of the target flash memory. In this way, the flash memory read controller 106 can determine whether the address of the read flash memory data or the address of the read instruction data is within the encrypted address range according to the encrypted address range of the target flash memory, and further determine whether the central processing unit is executing an instruction that is not within the encrypted address range and the function of the instruction is to read the flash memory data within the encrypted address range. When it is determined that the central processing unit is executing an instruction that is not within the encrypted address range and the function of the instruction is to read the flash memory data within the encrypted address range, the flash memory read controller returns a read failure response message to the central processing unit, thus improving the security of the flash memory data.

[0101] In one embodiment, the method further includes:

[0102] The instruction address register determines the register address signal according to the currently stored address and sends the register address signal to the flash memory read controller; the flash memory read controller determines the flash address corresponding to the instruction data according to the register address signal.

[0103] In the embodiment of the present application, the instruction address register 302 generates a stored address signal according to the currently stored address, and sends the stored address signal to the flash memory read controller 106. The flash memory read controller 106 parses the stored address signal to obtain the flash memory address corresponding to the instruction data. Specifically, when the central processing unit 102 reads the instruction data from the first sector of the target flash memory 108, the instruction address register 302 stores the flash memory address corresponding to the instruction data in the instruction address register 302. When the central processing unit 102 parses the instruction data and obtains that the instruction data indicates to read the target data in the second sector of the target flash memory 108, the bus controller 104 sends a first control signal, a first address signal, and a first read signal to the instruction address register 302 and the flash memory read controller 106 respectively. The instruction address register 302 parses the first read signal to determine that the operation type is a read operation; parses the first control signal to obtain that the category of the target data is non-instruction data. When the instruction address register 302 determines that the category of the target data is non-instruction data, the instruction address register 302 does not update the stored address. It can be understood that after the above two working processes, the currently stored address in the instruction address register 302 is the address corresponding to the instruction data.

[0104] In this embodiment, the instruction address register 302 is used to identify whether the type of data is instruction data. Only when the data is instruction data, the flash memory address corresponding to the data is stored in the instruction address register 302. And the address signal corresponding to the currently stored address in the instruction address register 302 is sent to the flash memory read controller 106, so that the flash memory read controller obtains the currently stored address in the instruction address register 302. It can be understood that since the instruction address register 302 only stores the address of the instruction data, the currently stored address obtained by the flash memory read controller is also the address of the instruction data, thus providing the address of the instruction data for the flash memory read controller.

[0105] In one embodiment, the method further includes:

[0106] When the flash memory read controller determines that the category of the target data is instruction data, the flash memory read controller returns the target data to the central processing unit.

[0107] In the embodiment of the present application, when the flash memory read controller 106 identifies that the category of the target data is instruction data, the flash memory read controller 106 sends a third bus read to the target flash memory 108. The target flash memory 108 parses the third bus read to obtain the flash memory address corresponding to the target data, and obtains the target data according to the flash memory address corresponding to the target data. The target flash memory 108 sends the target data to the flash memory read controller 106. The flash memory read controller 106 sends the target data to the central processing unit 102.

[0108] In this embodiment, the flash memory read controller 106 determines whether to return the target data to the central processing unit 102 by judging the category of the target data. When the flash memory read controller 106 determines that the category of the target data is instruction data, the flash memory read controller 106 returns the target data to the central processing unit 102. That is to say, when the central processing unit 102 reads the target data in the target flash memory 108 as an instruction, the central processing unit 102 can read the target data. That is to say, the central processing unit 102 can execute the instruction data in any sector of the target flash memory, while the central processing unit 102 may not be able to read the non-instruction data in any sector of the target flash memory, thereby improving the security of flash memory data reading.

[0109] In one embodiment, the method further includes:

[0110] When the flash memory read controller determines that the category of the target data is non-instruction data and the flash memory address of the target data is not within a preset encrypted address range, the flash memory read controller returns the target data to the central processing unit.

[0111] In the embodiment of the present application, when the flash memory read controller 106 identifies that the category of the target data is non-instruction data and determines that the flash memory address of the target data is within a preset encrypted address range, the flash memory read controller 106 sends a third bus read to the target flash memory 108. The target flash memory 108 parses the third bus read to obtain the flash memory address corresponding to the target data, and obtains the target data according to the flash memory address corresponding to the target data. The target flash memory 108 sends the target data to the flash memory read controller 106. The flash memory read controller 106 sends the target data to the central processing unit 102.

[0112] In this embodiment, when the category of the target data is non-instruction data, the flash memory read controller 106 determines whether to return the target data to the central processing unit 102 by judging whether the flash memory address of the target data is within a preset encrypted address range. Only when the flash memory address of the target data is not within a preset encrypted address range, the flash memory read controller 106 returns the target data to the central processing unit 102. That is to say, the central processing unit 102 can read non-instruction data that is not within the preset encrypted address range, while non-instruction data within the preset encrypted address range may not be able to be read, thereby improving the security of flash memory data.

[0113] In one embodiment, the method further includes:

[0114] When the flash memory read controller determines that the flash memory address corresponding to the instruction data is within a preset encrypted address range, the flash memory read controller returns the target data to the central processing unit.

[0115] In an embodiment of the present application, when the category of the target data is non-instruction data, the flash address of the target data is within a preset encrypted address range, and the flash address corresponding to the instruction data is also within the preset encrypted address range, the flash read controller 106 sends a third bus read to the target flash 108. The target flash 108 parses the third bus read to obtain the flash address corresponding to the target data, and obtains the target data according to the flash address corresponding to the target data. The target flash 108 sends the target data to the flash read controller 106. The flash read controller 106 sends the target data to the central processing unit 102.

[0116] In the embodiment, when the target data is non-instruction data, the flash address of the target data is an encrypted address, and the flash address of the instruction data for reading the target data is also an encrypted address, the flash read controller 106 returns the target data to the central processing unit. That is to say, when the central processing unit 102 reads the instruction data in the target flash 108, and the instruction data indicating the read target data and the instruction data are both within the encrypted address range, the central processing unit can read the target data. Therefore, if the address of sector A of the target flash is within the preset encrypted address range, instruction data 1 is stored in sector A, and the function of instruction data 1 is to read non-instruction data 1 in sector A, then the central processing unit can read non-instruction data 1. Therefore, the practicability of this solution is high.

[0117] In one embodiment, the flash read controller returns the target data to the central processing unit, including:

[0118] The flash read controller sends a bus read to the target flash; the target flash determines the target data according to the bus read and returns the target data to the flash read controller; the flash read controller returns the target data to the central processing unit.

[0119] Among them, the bus read (the same signal as the above-mentioned third bus read, and also uniformly referred to as the third bus read below for the sake of consistent description) includes a target data address signal and a target data read signal.

[0120] In an embodiment of the present application, the flash memory read controller 106 generates a target data address signal according to the flash memory address corresponding to the target data, and generates a target data read signal according to the read operation. The flash memory read controller 106 sends the target data address signal and the target data read signal to the target flash memory 108. The target flash memory 108 parses the target data address signal to obtain the flash memory address corresponding to the target data, and parses the target data read signal to obtain the read operation. The target flash memory 108 reads the target data according to the flash memory address corresponding to the target data, and sends the target data to the flash memory read controller 106. When the flash memory read controller 106 receives the target data, the flash memory read controller 106 sends the target data to the central processing unit 102.

[0121] In this embodiment, when the target flash memory 108 receives the third bus read sent by the flash memory read controller 106, the target flash memory 108 sends the target data to the flash memory read controller 106, and then the flash memory read controller 106 returns the target data to the central processing unit 102. Therefore, only when the flash memory read controller 106 sends the third bus read to the target flash memory 108 can the central processing unit read the target data, improving the security of the flash memory data.

[0122] It should be understood that although the steps in the flowcharts involved in the above embodiments are shown in sequence according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear indication in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least a part of other steps or steps or stages in other steps.

[0123] Based on the same inventive concept, an embodiment of the present application also provides a flash memory data reading system for implementing the flash memory data reading method involved above. The implementation solution provided by this system to solve the problem is similar to the implementation solution described in the above method. Therefore, the specific limitations in one or more embodiments of the flash memory data reading system provided below can refer to the limitations on the flash memory data reading method in the above text, and will not be repeated here.

[0124] In one embodiment, as Figure 1As shown, the flash memory data reading system includes a central processing unit 102, a bus controller 104, a flash memory reading controller 106, and a target flash memory 108. The central processing unit 102 is connected to the bus controller 104 and the flash memory reading controller 106 through a bus respectively. The bus controller 104 is connected to the flash memory reading controller 106 through a branch line. The flash memory reading controller 106 is connected to the target flash memory 108 through a bus. Among them:

[0125] The central processing unit 102 is configured to read instruction data from the first sector of the target flash memory 108.

[0126] The bus controller 104 is configured to, when the instruction data indicates to read target data from the second sector of the target flash memory 108, the central processing unit 102 sends a first control signal and a first address signal to the flash memory reading controller 106 through the bus controller 104.

[0127] The flash memory reading controller 106 is configured to determine the category of the target data according to the first control signal and determine the flash memory address of the target data according to the first address signal.

[0128] The flash memory reading controller 106 is further configured to, when it is determined that the category of the target data is central processing unit 102 data and the flash memory address of the target data is within a preset encrypted address range, obtain the flash memory address corresponding to the instruction data.

[0129] The flash memory reading controller 106 is further configured to, when it is determined that the flash memory address corresponding to the instruction data is not within the preset encrypted address range, return a read failure response message to the central processing unit 102.

[0130] In one embodiment, as Figure 3 shown, the flash memory data reading system further includes an instruction address register 302 and an instruction address register 304. Among them:

[0131] The central processing unit 102 is configured to send a second control signal and a second address signal to the instruction address register 302.

[0132] The instruction address register 302 is configured to determine that the category of the flash memory data corresponding to the second control signal is instruction data according to the second control signal.

[0133] The instruction address register 302 is further configured to determine the flash memory address corresponding to the instruction data according to the second address signal and store the flash memory address corresponding to the instruction data in the instruction address register 302.

[0134] In one embodiment, the system further includes an instruction address register 304. Among them:

[0135] The central processing unit 102 is configured to generate a bus write according to a preset encrypted address range and send the bus write to the instruction address register 304;

[0136] The instruction address register 304 is configured to determine the encrypted address range of the target flash memory 108 according to the bus write;

[0137] The instruction address register 304 is further configured to generate and send a start encrypted address configuration signal and an end encrypted address configuration signal to the flash memory read controller 106 according to the encrypted address range of the target flash memory 108;

[0138] The flash memory read controller 106 is configured to configure the encrypted address range of the target flash memory 108 according to the start encrypted address configuration signal and the end encrypted address configuration signal.

[0139] In one embodiment, the system further includes an instruction address register 302, wherein:

[0140] The instruction address register 302 is configured to determine a stored address signal according to the currently stored address and send the stored address signal to the flash memory read controller 106;

[0141] The flash memory read controller 106 is configured to determine the flash memory address corresponding to the instruction data according to the stored address signal.

[0142] In one embodiment, the flash memory read controller 106 is further configured to:

[0143] When the flash memory read controller 106 determines that the category of the target data is instruction data, return the target data to the central processing unit 102.

[0144] In one embodiment, the flash memory read controller 106 is further configured to:

[0145] When the flash memory read controller 106 determines that the category of the target data is central processing unit 102 data and the flash memory address of the target data is not within the preset encrypted address range, return the target data to the central processing unit 102.

[0146] In one embodiment, the flash memory read controller 106 is further configured to:

[0147] When the flash memory read controller 106 determines that the flash memory address corresponding to the instruction data is within the preset encrypted address range, return the target data to the central processing unit 102.

[0148] In one embodiment, the system further includes:

[0149] The flash memory read controller 106 is configured to send a bus read to the target flash memory 108;

[0150] The target flash memory 108 is configured to determine target data according to a bus read and return the target data to the flash memory reading controller 106;

[0151] The flash memory reading controller 106 is further configured to return the target data to the central processing unit 102.

[0152] Each module in the above flash memory data reading system can be implemented in whole or in part by software, hardware, or a combination thereof. Each of the above modules can be embedded in or independent of a processor in a computer device in the form of hardware, or stored in a memory in the computer device in the form of software, so that the processor can call and execute the operations corresponding to each of the above modules.

[0153] In one embodiment, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as Figure 5 shown. The computer device includes a processor, a memory, a communication interface, a display screen, and an input device connected through a system bus. Among them, the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The communication interface of the computer device is configured to communicate with an external terminal in a wired or wireless manner. The wireless manner can be implemented through WIFI, a mobile cellular network, NFC (Near Field Communication), or other technologies. The computer program, when executed by the processor, implements a flash memory data reading method. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen. The input device of the computer device can be a touch layer covering the display screen, or a button, a trackball, or a touchpad provided on the housing of the computer device, or an external keyboard, a touchpad, or a mouse, etc.

[0154] Those skilled in the art can understand that Figure 5 the structure shown in

[0155] In one embodiment, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as Figure 5As shown in the figure. The computer device includes a processor, a memory, a communication interface, a display screen, and an input device connected via a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner. The wireless manner can be implemented through WIFI, a mobile cellular network, NFC (Near Field Communication), or other technologies. When the computer program is executed by the processor, it implements a method for detecting malicious code. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen. The input device of the computer device can be a touch layer covering the display screen, or a button, a trackball, or a touchpad provided on the housing of the computer device, or an external keyboard, touchpad, or mouse, etc.

[0156] Those skilled in the art can understand that Figure 5 the structure shown in the figure is only a block diagram of some structures related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0157] In one embodiment, a computer device is provided, including a memory and a processor. A computer program is stored in the memory. When the processor executes the computer program, the steps in the above method embodiments are implemented.

[0158] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by the processor, the steps in the above method embodiments are implemented.

[0159] In one embodiment, a computer program product is provided, including a computer program. When the computer program is executed by the processor, the steps in the above method embodiments are implemented.

[0160] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in the present application are all information and data that have been authorized by the user or fully authorized by all parties.

[0161] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, database, or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memories. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The databases involved in the embodiments provided in the present application can include at least one of relational databases and non-relational databases. Non-relational databases can include distributed databases based on blockchain, etc., and are not limited thereto. The processors involved in the embodiments provided in the present application can be general-purpose processors, central processors, graphics processors, digital signal processors, programmable logic devices, data processing logics based on quantum computing, etc., and are not limited thereto.

[0162] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0163] The above-described embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the patent scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A method for reading flash memory data, characterized in that, The method is applied to a flash memory data reading system, which includes a central processing unit, a bus controller, a flash memory reading controller, and a target flash memory; the method includes: The central processing unit reads instruction data from a first sector of the target flash memory; when the instruction data indicates to read target data from a second sector of the target flash memory, a first control signal and a first address signal are sent to the flash memory reading controller through the bus controller; The flash memory reading controller determines the category of the target data according to the first control signal, and determines the flash memory address of the target data according to the first address signal; When the flash memory reading controller determines that the category of the target data is non-instruction data and the flash memory address of the target data is within a preset encrypted address range, the flash memory reading controller obtains the flash memory address corresponding to the instruction data; When the flash memory reading controller determines that the flash memory address corresponding to the instruction data is not within the preset encrypted address range, the flash memory reading controller returns a read failure response message to the central processing unit.

2. The method according to claim 1, wherein After the central processing unit reads the instruction data from the first sector of the target flash memory, it further includes: The central processing unit sends a second control signal and a second address signal to an instruction address register; The instruction address register determines that the category of the flash memory data corresponding to the second control signal is the instruction data according to the second control signal; The instruction address register determines the flash memory address corresponding to the instruction data according to the second address signal, and stores the flash memory address corresponding to the instruction data in the instruction address register.

3. The method according to claim 1, characterized in that, The method further includes: The central processing unit generates a bus write according to the preset encrypted address range, and sends the bus write to an encryption control register; The encryption control register determines the encrypted address range of the target flash memory according to the bus write; The encryption control register generates and sends a start encrypted address configuration signal and an end encrypted address configuration signal to the flash memory reading controller according to the encrypted address range of the target flash memory; The flash memory reading controller configures the encrypted address range of the target flash memory according to the start encrypted address configuration signal and the end encrypted address configuration signal.

4. The method according to claim 1 or 2, characterized in that, The method further includes: The instruction address register determines a stored address signal according to the currently stored address, and sends the stored address signal to the flash memory reading controller; The flash memory reading controller determines the flash memory address corresponding to the instruction data according to the stored address signal.

5. The method according to claim 1, wherein The method further includes: When the flash memory reading controller determines that the category of the target data is instruction data, the flash memory reading controller returns the target data to the central processing unit.

6. The method according to claim 1, wherein The method further includes: When the flash memory read controller determines that the category of the target data is non-instruction data and the flash memory address of the target data is not within the preset encrypted address range, the flash memory read controller returns the target data to the central processing unit.

7. The method according to claim 1, wherein The method further includes: When the flash memory read controller determines that the flash memory address corresponding to the instruction data is within the preset encrypted address range, the flash memory read controller returns the target data to the central processing unit.

8. The method according to any one of claims 5 to 7, characterized in that The flash memory read controller returning the target data to the central processing unit includes: The flash memory read controller sends a bus read to the target flash memory; The target flash memory determines the target data according to the bus read and returns the target data to the flash memory read controller; The flash memory read controller returns the target data to the central processing unit.

9. A flash memory data reading system, characterized in that, The flash memory data reading system includes a central processing unit, a bus controller, a flash memory read controller, and a target flash memory; the central processing unit is respectively connected to the bus controller and the flash memory read controller through a bus, the bus controller is connected to the flash memory read controller through a branch line, and the flash memory read controller is connected to the target flash memory through a bus; wherein: The central processing unit is configured to read instruction data from the first sector of the target flash memory; The bus controller is configured to, when the instruction data indicates to read target data in the second sector of the target flash memory, the central processing unit sends a first control signal and a first address signal to the flash memory read controller through the bus controller; The flash memory read controller is configured to determine the category of the target data according to the first control signal and determine the flash memory address of the target data according to the first address signal; The flash memory read controller is further configured to, when determining that the category of the target data is non-instruction data and the flash memory address of the target data is within the preset encrypted address range, obtain the flash memory address corresponding to the instruction data; The flash memory read controller is further configured to, when determining that the flash memory address corresponding to the instruction data is not within the preset encrypted address range, return a read failure response message to the central processing unit.

10. A computer device, comprising a memory and a processor, the memory storing a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 8.

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